2 * OMAP L3 Interconnect error handling driver header
4 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #ifndef __OMAP_L3_NOC_H
18 #define __OMAP_L3_NOC_H
20 #define MAX_L3_MODULES 3
21 #define MAX_CLKDM_TARGETS 31
23 #define CLEAR_STDERR_LOG (1 << 31)
24 #define CUSTOM_ERROR 0x2
25 #define STANDARD_ERROR 0x0
26 #define INBAND_ERROR 0x0
27 #define L3_APPLICATION_ERROR 0x0
28 #define L3_DEBUG_ERROR 0x1
30 /* L3 TARG register offsets */
31 #define L3_TARG_STDERRLOG_MAIN 0x48
32 #define L3_TARG_STDERRLOG_HDR 0x4c
33 #define L3_TARG_STDERRLOG_MSTADDR 0x50
34 #define L3_TARG_STDERRLOG_INFO 0x58
35 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
36 #define L3_TARG_STDERRLOG_CINFO_INFO 0x64
37 #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
38 #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c
39 #define L3_FLAGMUX_REGERR0 0xc
40 #define L3_FLAGMUX_MASK0 0x8
42 #define L3_TARGET_NOT_SUPPORTED NULL
44 #define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
46 static const char * const l3_transaction_type[] = {
51 /* 1 0 0 */ "Read Link",
52 /* 1 0 1 */ "Write Non-Posted",
53 /* 1 1 0 */ "Write Conditional",
54 /* 1 1 1 */ "Write Broadcast",
58 * struct l3_masters_data - L3 Master information
59 * @id: ID of the L3 Master
62 struct l3_masters_data {
68 * struct l3_target_data - L3 Target information
69 * @offset: Offset from base for L3 Target
72 * Target information is organized indexed by bit field definitions.
74 struct l3_target_data {
80 * struct l3_flagmux_data - Flag Mux information
81 * @offset: offset from base for flagmux register
82 * @l3_targ: array indexed by flagmux index (bit offset) pointing to the
83 * target data. unsupported ones are marked with
84 * L3_TARGET_NOT_SUPPORTED
85 * @num_targ_data: number of entries in target data
86 * @mask_app_bits: ignore these from raw application irq status
87 * @mask_dbg_bits: ignore these from raw debug irq status
89 struct l3_flagmux_data {
91 struct l3_target_data *l3_targ;
99 * struct omap_l3 - Description of data relevant for L3 bus.
100 * @dev: device representing the bus (populated runtime)
101 * @l3_base: base addresses of modules (populated runtime if 0)
102 * if set to L3_BASE_IS_SUBMODULE, then uses previous
103 * module index as the base address
104 * @l3_flag_mux: array containing flag mux data per module
105 * offset from corresponding module base indexed per
107 * @num_modules: number of clock domains / modules.
108 * @l3_masters: array pointing to master data containing name and register
109 * offset for the master.
110 * @num_master: number of masters
111 * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
112 * @debug_irq: irq number of the debug interrupt (populated runtime)
113 * @app_irq: irq number of the application interrupt (populated runtime)
118 void __iomem *l3_base[MAX_L3_MODULES];
119 struct l3_flagmux_data **l3_flagmux;
122 struct l3_masters_data *l3_masters;
130 static struct l3_target_data omap_l3_target_data_clk1[] = {
135 {0x600, "CLK2PWRDISC",},
137 {0x900, "L4WAKEUP",},
140 static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
142 .l3_targ = omap_l3_target_data_clk1,
143 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
147 static struct l3_target_data omap_l3_target_data_clk2[] = {
148 {0x500, "CORTEXM3",},
156 {0x100, "GPMCsERROR",},
160 {0x1100, "PWRDISCCLK1",},
171 static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
173 .l3_targ = omap_l3_target_data_clk2,
174 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
178 static struct l3_target_data omap4_l3_target_data_clk3[] = {
179 {0x0100, "DEBUGSS",},
182 static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
184 .l3_targ = omap4_l3_target_data_clk3,
185 .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
188 static struct l3_masters_data omap_l3_masters[] = {
196 { 0x12, "FaceDetect"},
211 { 0x30, "USBHOSTHS"},
216 static struct l3_flagmux_data *omap4_l3_flagmux[] = {
217 &omap_l3_flagmux_clk1,
218 &omap_l3_flagmux_clk2,
219 &omap4_l3_flagmux_clk3,
222 static const struct omap_l3 omap4_l3_data = {
223 .l3_flagmux = omap4_l3_flagmux,
224 .num_modules = ARRAY_SIZE(omap4_l3_flagmux),
225 .l3_masters = omap_l3_masters,
226 .num_masters = ARRAY_SIZE(omap_l3_masters),
227 /* The 6 MSBs of register field used to distinguish initiator */
228 .mst_addr_mask = 0xFC,
232 static struct l3_target_data omap5_l3_target_data_clk3[] = {
233 {0x0100, "L3INSTR",},
234 {0x0300, "DEBUGSS",},
238 static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
240 .l3_targ = omap5_l3_target_data_clk3,
241 .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
244 static struct l3_flagmux_data *omap5_l3_flagmux[] = {
245 &omap_l3_flagmux_clk1,
246 &omap_l3_flagmux_clk2,
247 &omap5_l3_flagmux_clk3,
250 static const struct omap_l3 omap5_l3_data = {
251 .l3_flagmux = omap5_l3_flagmux,
252 .num_modules = ARRAY_SIZE(omap5_l3_flagmux),
253 .l3_masters = omap_l3_masters,
254 .num_masters = ARRAY_SIZE(omap_l3_masters),
255 /* The 6 MSBs of register field used to distinguish initiator */
256 .mst_addr_mask = 0x7E0,
260 static struct l3_target_data dra_l3_target_data_clk1[] = {
263 {0x0600, "DSP2_SDMA",},
267 {0x0300, "DSP1_SDMA",},
274 {0x1600, "IVA_CONFIG",},
275 {0x1800, "IVA_SL2IF",},
277 {0x1d00, "L4_WKUP",},
283 {0x2000, "TPCC_EDMA",},
284 {0x2e00, "TPTC1_EDMA",},
285 {0x2b00, "TPTC2_EDMA",},
287 {0x2500, "L4_PER2_P3",},
288 {0x0e00, "L4_PER3_P3",},
295 static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
297 .l3_targ = dra_l3_target_data_clk1,
298 .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1),
301 static struct l3_target_data dra_l3_target_data_clk2[] = {
303 {0x800000, "HOST CLK2",},
304 {0xdead, L3_TARGET_NOT_SUPPORTED,},
307 {0xdead, L3_TARGET_NOT_SUPPORTED,},
308 {0x2100, "L4_PER1_P3",},
309 {0x1c00, "L4_PER1_P1",},
310 {0x1f00, "L4_PER1_P2",},
311 {0x2300, "L4_PER2_P1",},
312 {0x2400, "L4_PER2_P2",},
313 {0x2600, "L4_PER3_P1",},
314 {0x2700, "L4_PER3_P2",},
319 {0x0f00, "OCMC_RAM1",},
320 {0x1700, "OCMC_RAM2",},
321 {0x1900, "OCMC_RAM3",},
322 {0x1e00, "OCMC_ROM",},
326 static struct l3_flagmux_data dra_l3_flagmux_clk2 = {
328 .l3_targ = dra_l3_target_data_clk2,
329 .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2),
332 static struct l3_target_data dra_l3_target_data_clk3[] = {
333 {0x0100, "L3_INSTR"},
334 {0x0300, "DEBUGSS_CT_TBR"},
338 static struct l3_flagmux_data dra_l3_flagmux_clk3 = {
340 .l3_targ = dra_l3_target_data_clk3,
341 .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3),
344 static struct l3_masters_data dra_l3_masters[] = {
347 { 0x5, "IEEE1500_2_OCP" },
348 { 0x8, "DSP1_MDMA" },
351 { 0xB, "DSP2_MDMA" },
359 { 0x14, "PRUSS1 PRU1" },
360 { 0x15, "PRUSS1 PRU2" },
361 { 0x16, "PRUSS2 PRU1" },
362 { 0x17, "PRUSS2 PRU2" },
367 { 0x1C, "TC1_EDMA" },
368 { 0x1D, "TC2_EDMA" },
383 { 0x2E, "USB2_ULPI_SS1" },
384 { 0x2F, "USB2_ULPI_SS2" },
394 static struct l3_flagmux_data *dra_l3_flagmux[] = {
395 &dra_l3_flagmux_clk1,
396 &dra_l3_flagmux_clk2,
397 &dra_l3_flagmux_clk3,
400 static const struct omap_l3 dra_l3_data = {
401 .l3_base = { [1] = L3_BASE_IS_SUBMODULE },
402 .l3_flagmux = dra_l3_flagmux,
403 .num_modules = ARRAY_SIZE(dra_l3_flagmux),
404 .l3_masters = dra_l3_masters,
405 .num_masters = ARRAY_SIZE(dra_l3_masters),
406 /* The 6 MSBs of register field used to distinguish initiator */
407 .mst_addr_mask = 0xFC,
411 static struct l3_target_data am4372_l3_target_data_200f[] = {
420 {0xdead, L3_TARGET_NOT_SUPPORTED,},
425 {0x300, "MPUSS_L2_RAM",},
429 static struct l3_flagmux_data am4372_l3_flagmux_200f = {
431 .l3_targ = am4372_l3_target_data_200f,
432 .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f),
435 static struct l3_target_data am4372_l3_target_data_100s[] = {
436 {0x100, "L4_PER_0",},
437 {0x200, "L4_PER_1",},
438 {0x300, "L4_PER_2",},
439 {0x400, "L4_PER_3",},
445 {0xdead, L3_TARGET_NOT_SUPPORTED,},
448 {0xA00, "MAG_CARD",},
451 static struct l3_flagmux_data am4372_l3_flagmux_100s = {
453 .l3_targ = am4372_l3_target_data_100s,
454 .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s),
457 static struct l3_masters_data am4372_l3_masters[] = {
458 { 0x0, "M1 (128-bit)"},
459 { 0x1, "M2 (64-bit)"},
464 { 0x14, "Wakeup Processor"},
465 { 0x18, "TPTC0 Read"},
466 { 0x19, "TPTC0 Write"},
467 { 0x1A, "TPTC1 Read"},
468 { 0x1B, "TPTC1 Write"},
469 { 0x1C, "TPTC2 Read"},
470 { 0x1D, "TPTC2 Write"},
472 { 0x21, "OCP WP Traffic Probe"},
473 { 0x22, "OCP WP DMA Profiling"},
474 { 0x23, "OCP WP Event Trace"},
476 { 0x28, "Crypto DMA RD"},
477 { 0x29, "Crypto DMA WR"},
487 static struct l3_flagmux_data *am4372_l3_flagmux[] = {
488 &am4372_l3_flagmux_200f,
489 &am4372_l3_flagmux_100s,
492 static const struct omap_l3 am4372_l3_data = {
493 .l3_flagmux = am4372_l3_flagmux,
494 .num_modules = ARRAY_SIZE(am4372_l3_flagmux),
495 .l3_masters = am4372_l3_masters,
496 .num_masters = ARRAY_SIZE(am4372_l3_masters),
497 /* All 6 bits of register field used to distinguish initiator */
498 .mst_addr_mask = 0x3F,
501 #endif /* __OMAP_L3_NOC_H */