drivers/block/rsxx/rsxx_priv.h

   1 /*
   2 * Filename: rsxx_priv.h
   3 *
   4 *
   5 * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
   6 *       Philip Kelleher <pjk1939@linux.vnet.ibm.com>
   7 *
   8 * (C) Copyright 2013 IBM Corporation
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of the
  13 * License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful, but
  16 * WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18 * General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software Foundation,
  22 * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23 */
  24
  25 #ifndef __RSXX_PRIV_H__
  26 #define __RSXX_PRIV_H__
  27
  28 #include <linux/version.h>
  29 #include <linux/semaphore.h>
  30
  31 #include <linux/fs.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/mutex.h>
  34 #include <linux/pci.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/sysfs.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/bio.h>
  39 #include <linux/vmalloc.h>
  40 #include <linux/timer.h>
  41 #include <linux/ioctl.h>
  42
  43 #include "rsxx.h"
  44 #include "rsxx_cfg.h"
  45
  46 struct proc_cmd;
  47
  48 #define PCI_VENDOR_ID_TMS_IBM           0x15B6
  49 #define PCI_DEVICE_ID_RS70_FLASH        0x0019
  50 #define PCI_DEVICE_ID_RS70D_FLASH       0x001A
  51 #define PCI_DEVICE_ID_RS80_FLASH        0x001C
  52 #define PCI_DEVICE_ID_RS81_FLASH        0x001E
  53
  54 #define RS70_PCI_REV_SUPPORTED  4
  55
  56 #define DRIVER_NAME "rsxx"
  57 #define DRIVER_VERSION "3.7"
  58
  59 /* Block size is 4096 */
  60 #define RSXX_HW_BLK_SHIFT               12
  61 #define RSXX_HW_BLK_SIZE                (1 << RSXX_HW_BLK_SHIFT)
  62 #define RSXX_HW_BLK_MASK                (RSXX_HW_BLK_SIZE - 1)
  63
  64 #define MAX_CREG_DATA8  32
  65 #define LOG_BUF_SIZE8   128
  66
  67 #define RSXX_MAX_OUTSTANDING_CMDS       255
  68 #define RSXX_CS_IDX_MASK                0xff
  69
  70 #define RSXX_MAX_TARGETS        8
  71
  72 struct dma_tracker_list;
  73
  74 /* DMA Command/Status Buffer structure */
  75 struct rsxx_cs_buffer {
  76         dma_addr_t      dma_addr;
  77         void            *buf;
  78         u32             idx;
  79 };
  80
  81 struct rsxx_dma_stats {
  82         u32 crc_errors;
  83         u32 hard_errors;
  84         u32 soft_errors;
  85         u32 writes_issued;
  86         u32 writes_failed;
  87         u32 reads_issued;
  88         u32 reads_failed;
  89         u32 reads_retried;
  90         u32 discards_issued;
  91         u32 discards_failed;
  92         u32 done_rescheduled;
  93         u32 issue_rescheduled;
  94         u32 sw_q_depth;         /* Number of DMAs on the SW queue. */
  95         atomic_t hw_q_depth;    /* Number of DMAs queued to HW. */
  96 };
  97
  98 struct rsxx_dma_ctrl {
  99         struct rsxx_cardinfo            *card;
 100         int                             id;
 101         void                            __iomem *regmap;
 102         struct rsxx_cs_buffer           status;
 103         struct rsxx_cs_buffer           cmd;
 104         u16                             e_cnt;
 105         spinlock_t                      queue_lock;
 106         struct list_head                queue;
 107         struct workqueue_struct         *issue_wq;
 108         struct work_struct              issue_dma_work;
 109         struct workqueue_struct         *done_wq;
 110         struct work_struct              dma_done_work;
 111         struct timer_list               activity_timer;
 112         struct dma_tracker_list         *trackers;
 113         struct rsxx_dma_stats           stats;
 114 };
 115
 116 struct rsxx_cardinfo {
 117         struct pci_dev          *dev;
 118         unsigned int            halt;
 119
 120         void                    __iomem *regmap;
 121         spinlock_t              irq_lock;
 122         unsigned int            isr_mask;
 123         unsigned int            ier_mask;
 124
 125         struct rsxx_card_cfg    config;
 126         int                     config_valid;
 127
 128         /* Embedded CPU Communication */
 129         struct {
 130                 spinlock_t              lock;
 131                 bool                    active;
 132                 struct creg_cmd         *active_cmd;
 133                 struct work_struct      done_work;
 134                 struct list_head        queue;
 135                 unsigned int            q_depth;
 136                 /* Cache the creg status to prevent ioreads */
 137                 struct {
 138                         u32             stat;
 139                         u32             failed_cancel_timer;
 140                         u32             creg_timeout;
 141                 } creg_stats;
 142                 struct timer_list       cmd_timer;
 143                 struct mutex            reset_lock;
 144                 int                     reset;
 145         } creg_ctrl;
 146
 147         struct {
 148                 char tmp[MAX_CREG_DATA8];
 149                 char buf[LOG_BUF_SIZE8]; /* terminated */
 150                 int buf_len;
 151         } log;
 152
 153         struct work_struct      event_work;
 154         unsigned int            state;
 155         u64                     size8;
 156
 157         /* Lock the device attach/detach function */
 158         struct mutex            dev_lock;
 159
 160         /* Block Device Variables */
 161         bool                    bdev_attached;
 162         int                     disk_id;
 163         int                     major;
 164         struct request_queue    *queue;
 165         struct gendisk          *gendisk;
 166         struct {
 167                 /* Used to convert a byte address to a device address. */
 168                 u64 lower_mask;
 169                 u64 upper_shift;
 170                 u64 upper_mask;
 171                 u64 target_mask;
 172                 u64 target_shift;
 173         } _stripe;
 174         unsigned int            dma_fault;
 175
 176         int                     scrub_hard;
 177
 178         int                     n_targets;
 179         struct rsxx_dma_ctrl    *ctrl;
 180 };
 181
 182 enum rsxx_pci_regmap {
 183         HWID            = 0x00, /* Hardware Identification Register */
 184         SCRATCH         = 0x04, /* Scratch/Debug Register */
 185         RESET           = 0x08, /* Reset Register */
 186         ISR             = 0x10, /* Interrupt Status Register */
 187         IER             = 0x14, /* Interrupt Enable Register */
 188         IPR             = 0x18, /* Interrupt Poll Register */
 189         CB_ADD_LO       = 0x20, /* Command Host Buffer Address [31:0] */
 190         CB_ADD_HI       = 0x24, /* Command Host Buffer Address [63:32]*/
 191         HW_CMD_IDX      = 0x28, /* Hardware Processed Command Index */
 192         SW_CMD_IDX      = 0x2C, /* Software Processed Command Index */
 193         SB_ADD_LO       = 0x30, /* Status Host Buffer Address [31:0] */
 194         SB_ADD_HI       = 0x34, /* Status Host Buffer Address [63:32] */
 195         HW_STATUS_CNT   = 0x38, /* Hardware Status Counter */
 196         SW_STATUS_CNT   = 0x3C, /* Deprecated */
 197         CREG_CMD        = 0x40, /* CPU Command Register */
 198         CREG_ADD        = 0x44, /* CPU Address Register */
 199         CREG_CNT        = 0x48, /* CPU Count Register */
 200         CREG_STAT       = 0x4C, /* CPU Status Register */
 201         CREG_DATA0      = 0x50, /* CPU Data Registers */
 202         CREG_DATA1      = 0x54,
 203         CREG_DATA2      = 0x58,
 204         CREG_DATA3      = 0x5C,
 205         CREG_DATA4      = 0x60,
 206         CREG_DATA5      = 0x64,
 207         CREG_DATA6      = 0x68,
 208         CREG_DATA7      = 0x6c,
 209         INTR_COAL       = 0x70, /* Interrupt Coalescing Register */
 210         HW_ERROR        = 0x74, /* Card Error Register */
 211         PCI_DEBUG0      = 0x78, /* PCI Debug Registers */
 212         PCI_DEBUG1      = 0x7C,
 213         PCI_DEBUG2      = 0x80,
 214         PCI_DEBUG3      = 0x84,
 215         PCI_DEBUG4      = 0x88,
 216         PCI_DEBUG5      = 0x8C,
 217         PCI_DEBUG6      = 0x90,
 218         PCI_DEBUG7      = 0x94,
 219         PCI_POWER_THROTTLE = 0x98,
 220         PERF_CTRL       = 0x9c,
 221         PERF_TIMER_LO   = 0xa0,
 222         PERF_TIMER_HI   = 0xa4,
 223         PERF_RD512_LO   = 0xa8,
 224         PERF_RD512_HI   = 0xac,
 225         PERF_WR512_LO   = 0xb0,
 226         PERF_WR512_HI   = 0xb4,
 227 };
 228
 229 enum rsxx_intr {
 230         CR_INTR_DMA0    = 0x00000001,
 231         CR_INTR_CREG    = 0x00000002,
 232         CR_INTR_DMA1    = 0x00000004,
 233         CR_INTR_EVENT   = 0x00000008,
 234         CR_INTR_DMA2    = 0x00000010,
 235         CR_INTR_DMA3    = 0x00000020,
 236         CR_INTR_DMA4    = 0x00000040,
 237         CR_INTR_DMA5    = 0x00000080,
 238         CR_INTR_DMA6    = 0x00000100,
 239         CR_INTR_DMA7    = 0x00000200,
 240         CR_INTR_DMA_ALL = 0x000003f5,
 241         CR_INTR_ALL     = 0xffffffff,
 242 };
 243
 244 static inline int CR_INTR_DMA(int N)
 245 {
 246         static const unsigned int _CR_INTR_DMA[] = {
 247                 CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
 248                 CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
 249         };
 250         return _CR_INTR_DMA[N];
 251 }
 252 enum rsxx_pci_reset {
 253         DMA_QUEUE_RESET         = 0x00000001,
 254 };
 255
 256 enum rsxx_pci_revision {
 257         RSXX_DISCARD_SUPPORT = 2,
 258 };
 259
 260 enum rsxx_creg_cmd {
 261         CREG_CMD_TAG_MASK       = 0x0000FF00,
 262         CREG_OP_WRITE           = 0x000000C0,
 263         CREG_OP_READ            = 0x000000E0,
 264 };
 265
 266 enum rsxx_creg_addr {
 267         CREG_ADD_CARD_CMD               = 0x80001000,
 268         CREG_ADD_CARD_STATE             = 0x80001004,
 269         CREG_ADD_CARD_SIZE              = 0x8000100c,
 270         CREG_ADD_CAPABILITIES           = 0x80001050,
 271         CREG_ADD_LOG                    = 0x80002000,
 272         CREG_ADD_NUM_TARGETS            = 0x80003000,
 273         CREG_ADD_CONFIG                 = 0xB0000000,
 274 };
 275
 276 enum rsxx_creg_card_cmd {
 277         CARD_CMD_STARTUP                = 1,
 278         CARD_CMD_SHUTDOWN               = 2,
 279         CARD_CMD_LOW_LEVEL_FORMAT       = 3,
 280         CARD_CMD_FPGA_RECONFIG_BR       = 4,
 281         CARD_CMD_FPGA_RECONFIG_MAIN     = 5,
 282         CARD_CMD_BACKUP                 = 6,
 283         CARD_CMD_RESET                  = 7,
 284         CARD_CMD_deprecated             = 8,
 285         CARD_CMD_UNINITIALIZE           = 9,
 286         CARD_CMD_DSTROY_EMERGENCY       = 10,
 287         CARD_CMD_DSTROY_NORMAL          = 11,
 288         CARD_CMD_DSTROY_EXTENDED        = 12,
 289         CARD_CMD_DSTROY_ABORT           = 13,
 290 };
 291
 292 enum rsxx_card_state {
 293         CARD_STATE_SHUTDOWN             = 0x00000001,
 294         CARD_STATE_STARTING             = 0x00000002,
 295         CARD_STATE_FORMATTING           = 0x00000004,
 296         CARD_STATE_UNINITIALIZED        = 0x00000008,
 297         CARD_STATE_GOOD                 = 0x00000010,
 298         CARD_STATE_SHUTTING_DOWN        = 0x00000020,
 299         CARD_STATE_FAULT                = 0x00000040,
 300         CARD_STATE_RD_ONLY_FAULT        = 0x00000080,
 301         CARD_STATE_DSTROYING            = 0x00000100,
 302 };
 303
 304 enum rsxx_led {
 305         LED_DEFAULT     = 0x0,
 306         LED_IDENTIFY    = 0x1,
 307         LED_SOAK        = 0x2,
 308 };
 309
 310 enum rsxx_creg_flash_lock {
 311         CREG_FLASH_LOCK         = 1,
 312         CREG_FLASH_UNLOCK       = 2,
 313 };
 314
 315 enum rsxx_card_capabilities {
 316         CARD_CAP_SUBPAGE_WRITES = 0x00000080,
 317 };
 318
 319 enum rsxx_creg_stat {
 320         CREG_STAT_STATUS_MASK   = 0x00000003,
 321         CREG_STAT_SUCCESS       = 0x1,
 322         CREG_STAT_ERROR         = 0x2,
 323         CREG_STAT_CHAR_PENDING  = 0x00000004, /* Character I/O pending bit */
 324         CREG_STAT_LOG_PENDING   = 0x00000008, /* HW log message pending bit */
 325         CREG_STAT_TAG_MASK      = 0x0000ff00,
 326 };
 327
 328 static inline unsigned int CREG_DATA(int N)
 329 {
 330         return CREG_DATA0 + (N << 2);
 331 }
 332
 333 /*----------------- Convenient Log Wrappers -------------------*/
 334 #define CARD_TO_DEV(__CARD)     (&(__CARD)->dev->dev)
 335
 336 /***** config.c *****/
 337 int rsxx_load_config(struct rsxx_cardinfo *card);
 338
 339 /***** core.c *****/
 340 void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 341 void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 342 void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
 343                                  unsigned int intr);
 344 void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
 345                                   unsigned int intr);
 346
 347 /***** dev.c *****/
 348 int rsxx_attach_dev(struct rsxx_cardinfo *card);
 349 void rsxx_detach_dev(struct rsxx_cardinfo *card);
 350 int rsxx_setup_dev(struct rsxx_cardinfo *card);
 351 void rsxx_destroy_dev(struct rsxx_cardinfo *card);
 352 int rsxx_dev_init(void);
 353 void rsxx_dev_cleanup(void);
 354
 355 /***** dma.c ****/
 356 typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
 357                                 void *cb_data,
 358                                 unsigned int status);
 359 int rsxx_dma_setup(struct rsxx_cardinfo *card);
 360 void rsxx_dma_destroy(struct rsxx_cardinfo *card);
 361 int rsxx_dma_init(void);
 362 void rsxx_dma_cleanup(void);
 363 int rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
 364                            struct bio *bio,
 365                            atomic_t *n_dmas,
 366                            rsxx_dma_cb cb,
 367                            void *cb_data);
 368
 369 /***** cregs.c *****/
 370 int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
 371                         unsigned int size8,
 372                         void *data,
 373                         int byte_stream);
 374 int rsxx_creg_read(struct rsxx_cardinfo *card,
 375                        u32 addr,
 376                        unsigned int size8,
 377                        void *data,
 378                        int byte_stream);
 379 int rsxx_read_hw_log(struct rsxx_cardinfo *card);
 380 int rsxx_get_card_state(struct rsxx_cardinfo *card,
 381                             unsigned int *state);
 382 int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
 383 int rsxx_get_num_targets(struct rsxx_cardinfo *card,
 384                              unsigned int *n_targets);
 385 int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
 386                                    u32 *capabilities);
 387 int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
 388 int rsxx_creg_setup(struct rsxx_cardinfo *card);
 389 void rsxx_creg_destroy(struct rsxx_cardinfo *card);
 390 int rsxx_creg_init(void);
 391 void rsxx_creg_cleanup(void);
 392
 393 int rsxx_reg_access(struct rsxx_cardinfo *card,
 394                         struct rsxx_reg_access __user *ucmd,
 395                         int read);
 396
 397
 398
 399 #endif /* __DRIVERS_BLOCK_RSXX_H__ */