4 #include <linux/genhd.h>
5 #include <linux/mutex.h>
11 #define MAX_PART (1 << NWD_SHIFT)
15 #define IO_NEEDS_RETRY 3
22 typedef struct ctlr_info ctlr_info_t;
24 struct access_method {
25 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
26 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
27 unsigned long (*fifo_full)(ctlr_info_t *h);
28 bool (*intr_pending)(ctlr_info_t *h);
29 unsigned long (*command_completed)(ctlr_info_t *h);
31 typedef struct _drive_info_struct
33 unsigned char LunID[8];
35 struct request_queue *queue;
41 int raid_level; /* set to -1 to indicate that
42 * the drive is not in use/configured
44 int busy_configuring; /* This is set when a drive is being removed
45 * to prevent it from being opened or it's
46 * queue from being started.
49 __u8 serial_no[16]; /* from inquiry page 0x83,
50 * not necc. null terminated.
52 char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
53 char model[MODEL_LEN + 1]; /* SCSI model string */
54 char rev[REV_LEN + 1]; /* SCSI revision string */
55 char device_initialized; /* indicates whether dev is initialized */
63 char firm_ver[4]; /* Firmware version */
68 int nr_cmds; /* Number of commands allowed on this controller */
69 CfgTable_struct __iomem *cfgtable;
70 int interrupts_enabled;
73 int commands_outstanding;
74 int max_outstanding; /* Debug */
77 int usage_count; /* number of opens all all minor devices */
78 /* Need space for temp sg list
79 * number of scatter/gathers supported
80 * number of scatter/gathers in chained block
82 struct scatterlist **scatter_list;
85 int max_cmd_sgentries;
86 SGDescriptor_struct **cmd_sg_list;
88 # define PERF_MODE_INT 0
89 # define DOORBELL_INT 1
90 # define SIMPLE_MODE_INT 2
91 # define MEMQ_MODE_INT 3
93 unsigned int msix_vector;
94 unsigned int msi_vector;
95 int cciss_max_sectors;
98 BYTE cciss_read_capacity;
100 /* information about each logical volume */
101 drive_info_struct *drv[CISS_MAX_LUN];
103 struct access_method access;
105 /* queue and queue Info */
106 struct hlist_head reqQ;
107 struct hlist_head cmpQ;
109 unsigned int maxQsinceinit;
113 /* pointers to command and error info pool */
114 CommandList_struct *cmd_pool;
115 dma_addr_t cmd_pool_dhandle;
116 ErrorInfo_struct *errinfo_pool;
117 dma_addr_t errinfo_pool_dhandle;
118 unsigned long *cmd_pool_bits;
121 int busy_configuring;
122 int busy_initializing;
124 struct mutex busy_shutting_down;
126 /* This element holds the zero based queue number of the last
127 * queue to be started. It is used for fairness.
131 /* Disk structures we need to pass back */
132 struct gendisk *gendisk[CISS_MAX_LUN];
133 #ifdef CONFIG_CISS_SCSI_TAPE
134 struct cciss_scsi_adapter_data_t *scsi_ctlr;
137 struct list_head scan_list;
138 struct completion scan_wait;
141 * Performant mode tables.
145 struct TransTable_struct *transtable;
146 unsigned long transMethod;
149 * Performant mode completion buffer
152 dma_addr_t reply_pool_dhandle;
153 u64 *reply_pool_head;
154 size_t reply_pool_size;
155 unsigned char reply_pool_wraparound;
156 u32 *blockFetchTable;
159 /* Defining the diffent access_methods
161 * Memory mapped FIFO interface (SMART 53xx cards)
163 #define SA5_DOORBELL 0x20
164 #define SA5_REQUEST_PORT_OFFSET 0x40
165 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
166 #define SA5_REPLY_PORT_OFFSET 0x44
167 #define SA5_INTR_STATUS 0x30
168 #define SA5_SCRATCHPAD_OFFSET 0xB0
170 #define SA5_CTCFG_OFFSET 0xB4
171 #define SA5_CTMEM_OFFSET 0xB8
173 #define SA5_INTR_OFF 0x08
174 #define SA5B_INTR_OFF 0x04
175 #define SA5_INTR_PENDING 0x08
176 #define SA5B_INTR_PENDING 0x04
177 #define FIFO_EMPTY 0xffffffff
178 #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
179 /* Perf. mode flags */
180 #define SA5_PERF_INTR_PENDING 0x04
181 #define SA5_PERF_INTR_OFF 0x05
182 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
183 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
184 #define SA5_OUTDB_CLEAR 0xA0
185 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
186 #define SA5_OUTDB_STATUS 0x9C
189 #define CISS_ERROR_BIT 0x02
191 #define CCISS_INTR_ON 1
192 #define CCISS_INTR_OFF 0
195 /* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board
196 * to become ready, in seconds, before giving up on it.
197 * CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
198 * between polling the board to see if it is ready, in
199 * milliseconds. CCISS_BOARD_READY_ITERATIONS is derived
202 #define CCISS_BOARD_READY_WAIT_SECS (120)
203 #define CCISS_BOARD_NOT_READY_WAIT_SECS (10)
204 #define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
205 #define CCISS_BOARD_READY_ITERATIONS \
206 ((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
207 CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
208 #define CCISS_BOARD_NOT_READY_ITERATIONS \
209 ((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
210 CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
211 #define CCISS_POST_RESET_PAUSE_MSECS (3000)
212 #define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (1000)
213 #define CCISS_POST_RESET_NOOP_RETRIES (12)
216 Send the command to the hardware
218 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
221 printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
222 h->ctlr, c->busaddr);
223 #endif /* CCISS_DEBUG */
224 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
225 h->commands_outstanding++;
226 if ( h->commands_outstanding > h->max_outstanding)
227 h->max_outstanding = h->commands_outstanding;
231 * This card is the opposite of the other cards.
232 * 0 turns interrupts on...
233 * 0x08 turns them off...
235 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
238 { /* Turn interrupts on */
239 h->interrupts_enabled = 1;
240 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
241 } else /* Turn them off */
243 h->interrupts_enabled = 0;
244 writel( SA5_INTR_OFF,
245 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
249 * This card is the opposite of the other cards.
250 * 0 turns interrupts on...
251 * 0x04 turns them off...
253 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
256 { /* Turn interrupts on */
257 h->interrupts_enabled = 1;
258 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
259 } else /* Turn them off */
261 h->interrupts_enabled = 0;
262 writel( SA5B_INTR_OFF,
263 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
267 /* Performant mode intr_mask */
268 static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
270 if (val) { /* turn on interrupts */
271 h->interrupts_enabled = 1;
272 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
274 h->interrupts_enabled = 0;
275 writel(SA5_PERF_INTR_OFF,
276 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
281 * Returns true if fifo is full.
284 static unsigned long SA5_fifo_full(ctlr_info_t *h)
286 if( h->commands_outstanding >= h->max_commands)
293 * returns value read from hardware.
294 * returns FIFO_EMPTY if there is nothing to read
296 static unsigned long SA5_completed(ctlr_info_t *h)
298 unsigned long register_value
299 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
300 if(register_value != FIFO_EMPTY)
302 h->commands_outstanding--;
304 printk("cciss: Read %lx back from board\n", register_value);
305 #endif /* CCISS_DEBUG */
310 printk("cciss: FIFO Empty read\n");
313 return ( register_value);
317 /* Performant mode command completed */
318 static unsigned long SA5_performant_completed(ctlr_info_t *h)
320 unsigned long register_value = FIFO_EMPTY;
322 /* flush the controller write of the reply queue by reading
323 * outbound doorbell status register.
325 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
326 /* msi auto clears the interrupt pending bit. */
327 if (!(h->msi_vector || h->msix_vector)) {
328 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
329 /* Do a read in order to flush the write to the controller
332 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
335 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
336 register_value = *(h->reply_pool_head);
337 (h->reply_pool_head)++;
338 h->commands_outstanding--;
340 register_value = FIFO_EMPTY;
342 /* Check for wraparound */
343 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
344 h->reply_pool_head = h->reply_pool;
345 h->reply_pool_wraparound ^= 1;
348 return register_value;
351 * Returns true if an interrupt is pending..
353 static bool SA5_intr_pending(ctlr_info_t *h)
355 unsigned long register_value =
356 readl(h->vaddr + SA5_INTR_STATUS);
358 printk("cciss: intr_pending %lx\n", register_value);
359 #endif /* CCISS_DEBUG */
360 if( register_value & SA5_INTR_PENDING)
366 * Returns true if an interrupt is pending..
368 static bool SA5B_intr_pending(ctlr_info_t *h)
370 unsigned long register_value =
371 readl(h->vaddr + SA5_INTR_STATUS);
373 printk("cciss: intr_pending %lx\n", register_value);
374 #endif /* CCISS_DEBUG */
375 if( register_value & SA5B_INTR_PENDING)
380 static bool SA5_performant_intr_pending(ctlr_info_t *h)
382 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
387 if (h->msi_vector || h->msix_vector)
390 /* Read outbound doorbell to flush */
391 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
392 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
395 static struct access_method SA5_access = {
403 static struct access_method SA5B_access = {
411 static struct access_method SA5_performant_access = {
413 SA5_performant_intr_mask,
415 SA5_performant_intr_pending,
416 SA5_performant_completed,
422 struct access_method *access;
423 int nr_cmds; /* Max cmds this kind of ctlr can handle. */