2 * Register map access API - MMIO support
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/module.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
26 struct regmap_mmio_context {
34 static inline void regmap_mmio_regsize_check(size_t reg_size)
49 static int regmap_mmio_regbits_check(size_t reg_bits)
64 static inline void regmap_mmio_count_check(size_t count, u32 offset)
66 BUG_ON(count <= offset);
69 static int regmap_mmio_gather_write(void *context,
70 const void *reg, size_t reg_size,
71 const void *val, size_t val_size)
73 struct regmap_mmio_context *ctx = context;
77 regmap_mmio_regsize_check(reg_size);
79 if (!IS_ERR(ctx->clk)) {
80 ret = clk_enable(ctx->clk);
88 switch (ctx->val_bytes) {
90 writeb(*(u8 *)val, ctx->regs + offset);
93 writew(*(u16 *)val, ctx->regs + offset);
96 writel(*(u32 *)val, ctx->regs + offset);
100 writeq(*(u64 *)val, ctx->regs + offset);
104 /* Should be caught by regmap_mmio_check_config */
107 val_size -= ctx->val_bytes;
108 val += ctx->val_bytes;
109 offset += ctx->val_bytes;
112 if (!IS_ERR(ctx->clk))
113 clk_disable(ctx->clk);
118 static int regmap_mmio_write(void *context, const void *data, size_t count)
120 struct regmap_mmio_context *ctx = context;
121 u32 offset = ctx->reg_bytes + ctx->pad_bytes;
123 regmap_mmio_count_check(count, offset);
125 return regmap_mmio_gather_write(context, data, ctx->reg_bytes,
126 data + offset, count - offset);
129 static int regmap_mmio_read(void *context,
130 const void *reg, size_t reg_size,
131 void *val, size_t val_size)
133 struct regmap_mmio_context *ctx = context;
137 regmap_mmio_regsize_check(reg_size);
139 if (!IS_ERR(ctx->clk)) {
140 ret = clk_enable(ctx->clk);
145 offset = *(u32 *)reg;
148 switch (ctx->val_bytes) {
150 *(u8 *)val = readb(ctx->regs + offset);
153 *(u16 *)val = readw(ctx->regs + offset);
156 *(u32 *)val = readl(ctx->regs + offset);
160 *(u64 *)val = readq(ctx->regs + offset);
164 /* Should be caught by regmap_mmio_check_config */
167 val_size -= ctx->val_bytes;
168 val += ctx->val_bytes;
169 offset += ctx->val_bytes;
172 if (!IS_ERR(ctx->clk))
173 clk_disable(ctx->clk);
178 static void regmap_mmio_free_context(void *context)
180 struct regmap_mmio_context *ctx = context;
182 if (!IS_ERR(ctx->clk)) {
183 clk_unprepare(ctx->clk);
189 static struct regmap_bus regmap_mmio = {
191 .write = regmap_mmio_write,
192 .gather_write = regmap_mmio_gather_write,
193 .read = regmap_mmio_read,
194 .free_context = regmap_mmio_free_context,
195 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
196 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
199 static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
202 const struct regmap_config *config)
204 struct regmap_mmio_context *ctx;
208 ret = regmap_mmio_regbits_check(config->reg_bits);
212 if (config->pad_bits)
213 return ERR_PTR(-EINVAL);
215 switch (config->val_bits) {
217 /* The core treats 0 as 1 */
233 return ERR_PTR(-EINVAL);
236 if (config->reg_stride < min_stride)
237 return ERR_PTR(-EINVAL);
239 switch (config->reg_format_endian) {
240 case REGMAP_ENDIAN_DEFAULT:
241 case REGMAP_ENDIAN_NATIVE:
244 return ERR_PTR(-EINVAL);
247 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
249 return ERR_PTR(-ENOMEM);
252 ctx->val_bytes = config->val_bits / 8;
253 ctx->reg_bytes = config->reg_bits / 8;
254 ctx->pad_bytes = config->pad_bits / 8;
255 ctx->clk = ERR_PTR(-ENODEV);
260 ctx->clk = clk_get(dev, clk_id);
261 if (IS_ERR(ctx->clk)) {
262 ret = PTR_ERR(ctx->clk);
266 ret = clk_prepare(ctx->clk);
281 * regmap_init_mmio_clk(): Initialise register map with register clock
283 * @dev: Device that will be interacted with
284 * @clk_id: register clock consumer ID
285 * @regs: Pointer to memory-mapped IO region
286 * @config: Configuration for register map
288 * The return value will be an ERR_PTR() on error or a valid pointer to
291 struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
293 const struct regmap_config *config)
295 struct regmap_mmio_context *ctx;
297 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
299 return ERR_CAST(ctx);
301 return regmap_init(dev, ®map_mmio, ctx, config);
303 EXPORT_SYMBOL_GPL(regmap_init_mmio_clk);
306 * devm_regmap_init_mmio_clk(): Initialise managed register map with clock
308 * @dev: Device that will be interacted with
309 * @clk_id: register clock consumer ID
310 * @regs: Pointer to memory-mapped IO region
311 * @config: Configuration for register map
313 * The return value will be an ERR_PTR() on error or a valid pointer
314 * to a struct regmap. The regmap will be automatically freed by the
315 * device management code.
317 struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
319 const struct regmap_config *config)
321 struct regmap_mmio_context *ctx;
323 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
325 return ERR_CAST(ctx);
327 return devm_regmap_init(dev, ®map_mmio, ctx, config);
329 EXPORT_SYMBOL_GPL(devm_regmap_init_mmio_clk);
331 MODULE_LICENSE("GPL v2");