2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2004 Red Hat, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware information only available under NDA.
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
68 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
69 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
70 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
80 /* PDC_GLOBAL_CTL bit definitions */
81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
82 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
83 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
84 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
85 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
86 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
87 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
88 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
89 PDC_DRIVE_ERR = (1 << 21), /* drive error */
90 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
91 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
92 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
93 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
95 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
96 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
97 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
98 PDC1_ERR_MASK | PDC2_ERR_MASK,
100 board_2037x = 0, /* FastTrak S150 TX2plus */
101 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
102 board_20319 = 2, /* FastTrak S150 TX4 */
103 board_20619 = 3, /* FastTrak TX4000 */
104 board_2057x = 4, /* SATAII150 Tx2plus */
105 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
106 board_40518 = 6, /* SATAII150 Tx4 */
108 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
110 /* Sequence counter control registers bit definitions */
111 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
113 /* Feature register values */
114 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
115 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
117 /* Device/Head register values */
118 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
120 /* PDC_CTLSTAT bit definitions */
121 PDC_DMA_ENABLE = (1 << 7),
122 PDC_IRQ_DISABLE = (1 << 10),
123 PDC_RESET = (1 << 11), /* HDMA reset */
125 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
127 ATA_FLAG_PIO_POLLING,
130 PDC_FLAG_GEN_II = (1 << 24),
131 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
132 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
135 struct pdc_port_priv {
140 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
141 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
142 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
143 static int pdc_common_port_start(struct ata_port *ap);
144 static int pdc_sata_port_start(struct ata_port *ap);
145 static void pdc_qc_prep(struct ata_queued_cmd *qc);
146 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
147 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
148 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
149 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
150 static void pdc_irq_clear(struct ata_port *ap);
151 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
152 static void pdc_freeze(struct ata_port *ap);
153 static void pdc_sata_freeze(struct ata_port *ap);
154 static void pdc_thaw(struct ata_port *ap);
155 static void pdc_sata_thaw(struct ata_port *ap);
156 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
157 unsigned long deadline);
158 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
159 unsigned long deadline);
160 static void pdc_error_handler(struct ata_port *ap);
161 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
162 static int pdc_pata_cable_detect(struct ata_port *ap);
163 static int pdc_sata_cable_detect(struct ata_port *ap);
165 static struct scsi_host_template pdc_ata_sht = {
166 ATA_BASE_SHT(DRV_NAME),
167 .sg_tablesize = PDC_MAX_PRD,
168 .dma_boundary = ATA_DMA_BOUNDARY,
171 static const struct ata_port_operations pdc_common_ops = {
172 .inherits = &ata_sff_port_ops,
174 .sff_tf_load = pdc_tf_load_mmio,
175 .sff_exec_command = pdc_exec_command_mmio,
176 .check_atapi_dma = pdc_check_atapi_dma,
177 .qc_prep = pdc_qc_prep,
178 .qc_issue = pdc_qc_issue,
180 .sff_irq_clear = pdc_irq_clear,
181 .lost_interrupt = ATA_OP_NULL,
183 .post_internal_cmd = pdc_post_internal_cmd,
184 .error_handler = pdc_error_handler,
187 static struct ata_port_operations pdc_sata_ops = {
188 .inherits = &pdc_common_ops,
189 .cable_detect = pdc_sata_cable_detect,
190 .freeze = pdc_sata_freeze,
191 .thaw = pdc_sata_thaw,
192 .scr_read = pdc_sata_scr_read,
193 .scr_write = pdc_sata_scr_write,
194 .port_start = pdc_sata_port_start,
195 .hardreset = pdc_sata_hardreset,
198 /* First-generation chips need a more restrictive ->check_atapi_dma op,
199 and ->freeze/thaw that ignore the hotplug controls. */
200 static struct ata_port_operations pdc_old_sata_ops = {
201 .inherits = &pdc_sata_ops,
202 .freeze = pdc_freeze,
204 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
207 static struct ata_port_operations pdc_pata_ops = {
208 .inherits = &pdc_common_ops,
209 .cable_detect = pdc_pata_cable_detect,
210 .freeze = pdc_freeze,
212 .port_start = pdc_common_port_start,
213 .softreset = pdc_pata_softreset,
216 static const struct ata_port_info pdc_port_info[] = {
219 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
221 .pio_mask = ATA_PIO4,
222 .mwdma_mask = ATA_MWDMA2,
223 .udma_mask = ATA_UDMA6,
224 .port_ops = &pdc_old_sata_ops,
229 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
230 .pio_mask = ATA_PIO4,
231 .mwdma_mask = ATA_MWDMA2,
232 .udma_mask = ATA_UDMA6,
233 .port_ops = &pdc_pata_ops,
238 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
240 .pio_mask = ATA_PIO4,
241 .mwdma_mask = ATA_MWDMA2,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &pdc_old_sata_ops,
248 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
250 .pio_mask = ATA_PIO4,
251 .mwdma_mask = ATA_MWDMA2,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &pdc_pata_ops,
258 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
259 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
260 .pio_mask = ATA_PIO4,
261 .mwdma_mask = ATA_MWDMA2,
262 .udma_mask = ATA_UDMA6,
263 .port_ops = &pdc_sata_ops,
268 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
270 .pio_mask = ATA_PIO4,
271 .mwdma_mask = ATA_MWDMA2,
272 .udma_mask = ATA_UDMA6,
273 .port_ops = &pdc_pata_ops,
278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
279 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
280 .pio_mask = ATA_PIO4,
281 .mwdma_mask = ATA_MWDMA2,
282 .udma_mask = ATA_UDMA6,
283 .port_ops = &pdc_sata_ops,
287 static const struct pci_device_id pdc_ata_pci_tbl[] = {
288 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
289 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
290 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
291 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
292 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
295 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
296 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
297 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
299 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
300 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
301 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
302 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
303 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
304 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
306 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
308 { } /* terminate list */
311 static struct pci_driver pdc_ata_pci_driver = {
313 .id_table = pdc_ata_pci_tbl,
314 .probe = pdc_ata_init_one,
315 .remove = ata_pci_remove_one,
318 static int pdc_common_port_start(struct ata_port *ap)
320 struct device *dev = ap->host->dev;
321 struct pdc_port_priv *pp;
324 rc = ata_port_start(ap);
328 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
332 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
336 ap->private_data = pp;
341 static int pdc_sata_port_start(struct ata_port *ap)
345 rc = pdc_common_port_start(ap);
349 /* fix up PHYMODE4 align timing */
350 if (ap->flags & PDC_FLAG_GEN_II) {
351 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
354 tmp = readl(sata_mmio + PDC_PHYMODE4);
355 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
356 writel(tmp, sata_mmio + PDC_PHYMODE4);
362 static void pdc_reset_port(struct ata_port *ap)
364 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
368 for (i = 11; i > 0; i--) {
369 tmp = readl(ata_ctlstat_mmio);
376 writel(tmp, ata_ctlstat_mmio);
380 writel(tmp, ata_ctlstat_mmio);
381 readl(ata_ctlstat_mmio); /* flush */
384 static int pdc_pata_cable_detect(struct ata_port *ap)
387 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
389 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
391 return ATA_CBL_PATA40;
392 return ATA_CBL_PATA80;
395 static int pdc_sata_cable_detect(struct ata_port *ap)
400 static int pdc_sata_scr_read(struct ata_link *link,
401 unsigned int sc_reg, u32 *val)
403 if (sc_reg > SCR_CONTROL)
405 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
409 static int pdc_sata_scr_write(struct ata_link *link,
410 unsigned int sc_reg, u32 val)
412 if (sc_reg > SCR_CONTROL)
414 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
418 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
420 struct ata_port *ap = qc->ap;
421 dma_addr_t sg_table = ap->prd_dma;
422 unsigned int cdb_len = qc->dev->cdb_len;
424 struct pdc_port_priv *pp = ap->private_data;
426 __le32 *buf32 = (__le32 *) buf;
427 unsigned int dev_sel, feature;
429 /* set control bits (byte 0), zero delay seq id (byte 3),
430 * and seq id (byte 2)
432 switch (qc->tf.protocol) {
434 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
435 buf32[0] = cpu_to_le32(PDC_PKT_READ);
439 case ATAPI_PROT_NODATA:
440 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
446 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
447 buf32[2] = 0; /* no next-packet */
450 if (sata_scr_valid(&ap->link))
451 dev_sel = PDC_DEVICE_SATA;
453 dev_sel = qc->tf.device;
455 buf[12] = (1 << 5) | ATA_REG_DEVICE;
457 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
458 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
460 buf[16] = (1 << 5) | ATA_REG_NSECT;
461 buf[17] = qc->tf.nsect;
462 buf[18] = (1 << 5) | ATA_REG_LBAL;
463 buf[19] = qc->tf.lbal;
465 /* set feature and byte counter registers */
466 if (qc->tf.protocol != ATAPI_PROT_DMA)
467 feature = PDC_FEATURE_ATAPI_PIO;
469 feature = PDC_FEATURE_ATAPI_DMA;
471 buf[20] = (1 << 5) | ATA_REG_FEATURE;
473 buf[22] = (1 << 5) | ATA_REG_BYTEL;
474 buf[23] = qc->tf.lbam;
475 buf[24] = (1 << 5) | ATA_REG_BYTEH;
476 buf[25] = qc->tf.lbah;
478 /* send ATAPI packet command 0xA0 */
479 buf[26] = (1 << 5) | ATA_REG_CMD;
480 buf[27] = qc->tf.command;
482 /* select drive and check DRQ */
483 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
486 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
487 BUG_ON(cdb_len & ~0x1E);
489 /* append the CDB as the final part */
490 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
491 memcpy(buf+31, cdb, cdb_len);
495 * pdc_fill_sg - Fill PCI IDE PRD table
496 * @qc: Metadata associated with taskfile to be transferred
498 * Fill PCI IDE PRD (scatter-gather) table with segments
499 * associated with the current disk command.
500 * Make sure hardware does not choke on it.
503 * spin_lock_irqsave(host lock)
506 static void pdc_fill_sg(struct ata_queued_cmd *qc)
508 struct ata_port *ap = qc->ap;
509 struct scatterlist *sg;
510 const u32 SG_COUNT_ASIC_BUG = 41*4;
511 unsigned int si, idx;
514 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
518 for_each_sg(qc->sg, sg, qc->n_elem, si) {
522 /* determine if physical DMA addr spans 64K boundary.
523 * Note h/w doesn't support 64-bit, so we unconditionally
524 * truncate dma_addr_t to u32.
526 addr = (u32) sg_dma_address(sg);
527 sg_len = sg_dma_len(sg);
530 offset = addr & 0xffff;
532 if ((offset + sg_len) > 0x10000)
533 len = 0x10000 - offset;
535 ap->prd[idx].addr = cpu_to_le32(addr);
536 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
537 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
545 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
547 if (len > SG_COUNT_ASIC_BUG) {
550 VPRINTK("Splitting last PRD.\n");
552 addr = le32_to_cpu(ap->prd[idx - 1].addr);
553 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
554 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
556 addr = addr + len - SG_COUNT_ASIC_BUG;
557 len = SG_COUNT_ASIC_BUG;
558 ap->prd[idx].addr = cpu_to_le32(addr);
559 ap->prd[idx].flags_len = cpu_to_le32(len);
560 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
565 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
568 static void pdc_qc_prep(struct ata_queued_cmd *qc)
570 struct pdc_port_priv *pp = qc->ap->private_data;
575 switch (qc->tf.protocol) {
579 case ATA_PROT_NODATA:
580 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
581 qc->dev->devno, pp->pkt);
582 if (qc->tf.flags & ATA_TFLAG_LBA48)
583 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
585 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
586 pdc_pkt_footer(&qc->tf, pp->pkt, i);
594 case ATAPI_PROT_NODATA:
602 static int pdc_is_sataii_tx4(unsigned long flags)
604 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
605 return (flags & mask) == mask;
608 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
611 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
612 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
615 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
617 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
620 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
622 const struct ata_host *host = ap->host;
623 unsigned int nr_ports = pdc_sata_nr_ports(ap);
626 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
628 BUG_ON(i >= nr_ports);
629 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
632 static void pdc_freeze(struct ata_port *ap)
634 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
637 tmp = readl(ata_mmio + PDC_CTLSTAT);
638 tmp |= PDC_IRQ_DISABLE;
639 tmp &= ~PDC_DMA_ENABLE;
640 writel(tmp, ata_mmio + PDC_CTLSTAT);
641 readl(ata_mmio + PDC_CTLSTAT); /* flush */
644 static void pdc_sata_freeze(struct ata_port *ap)
646 struct ata_host *host = ap->host;
647 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
648 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
649 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
652 /* Disable hotplug events on this port.
655 * 1) hotplug register accesses must be serialised via host->lock
656 * 2) ap->lock == &ap->host->lock
657 * 3) ->freeze() and ->thaw() are called with ap->lock held
659 hotplug_status = readl(host_mmio + hotplug_offset);
660 hotplug_status |= 0x11 << (ata_no + 16);
661 writel(hotplug_status, host_mmio + hotplug_offset);
662 readl(host_mmio + hotplug_offset); /* flush */
667 static void pdc_thaw(struct ata_port *ap)
669 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
673 readl(ata_mmio + PDC_COMMAND);
675 /* turn IRQ back on */
676 tmp = readl(ata_mmio + PDC_CTLSTAT);
677 tmp &= ~PDC_IRQ_DISABLE;
678 writel(tmp, ata_mmio + PDC_CTLSTAT);
679 readl(ata_mmio + PDC_CTLSTAT); /* flush */
682 static void pdc_sata_thaw(struct ata_port *ap)
684 struct ata_host *host = ap->host;
685 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
686 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
687 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
692 /* Enable hotplug events on this port.
693 * Locking: see pdc_sata_freeze().
695 hotplug_status = readl(host_mmio + hotplug_offset);
696 hotplug_status |= 0x11 << ata_no;
697 hotplug_status &= ~(0x11 << (ata_no + 16));
698 writel(hotplug_status, host_mmio + hotplug_offset);
699 readl(host_mmio + hotplug_offset); /* flush */
702 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
705 pdc_reset_port(link->ap);
706 return ata_sff_softreset(link, class, deadline);
709 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
710 unsigned long deadline)
712 pdc_reset_port(link->ap);
713 return sata_sff_hardreset(link, class, deadline);
716 static void pdc_error_handler(struct ata_port *ap)
718 if (!(ap->pflags & ATA_PFLAG_FROZEN))
721 ata_std_error_handler(ap);
724 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
726 struct ata_port *ap = qc->ap;
728 /* make DMA engine forget about the failed command */
729 if (qc->flags & ATA_QCFLAG_FAILED)
733 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
734 u32 port_status, u32 err_mask)
736 struct ata_eh_info *ehi = &ap->link.eh_info;
737 unsigned int ac_err_mask = 0;
739 ata_ehi_clear_desc(ehi);
740 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
741 port_status &= err_mask;
743 if (port_status & PDC_DRIVE_ERR)
744 ac_err_mask |= AC_ERR_DEV;
745 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
746 ac_err_mask |= AC_ERR_HSM;
747 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
748 ac_err_mask |= AC_ERR_ATA_BUS;
749 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
750 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
751 ac_err_mask |= AC_ERR_HOST_BUS;
753 if (sata_scr_valid(&ap->link)) {
756 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
757 ehi->serror |= serror;
760 qc->err_mask |= ac_err_mask;
767 static unsigned int pdc_host_intr(struct ata_port *ap,
768 struct ata_queued_cmd *qc)
770 unsigned int handled = 0;
771 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
772 u32 port_status, err_mask;
774 err_mask = PDC_ERR_MASK;
775 if (ap->flags & PDC_FLAG_GEN_II)
776 err_mask &= ~PDC1_ERR_MASK;
778 err_mask &= ~PDC2_ERR_MASK;
779 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
780 if (unlikely(port_status & err_mask)) {
781 pdc_error_intr(ap, qc, port_status, err_mask);
785 switch (qc->tf.protocol) {
787 case ATA_PROT_NODATA:
789 case ATAPI_PROT_NODATA:
790 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
795 ap->stats.idle_irq++;
802 static void pdc_irq_clear(struct ata_port *ap)
804 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
806 readl(ata_mmio + PDC_COMMAND);
809 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
811 struct ata_host *host = dev_instance;
815 unsigned int handled = 0;
816 void __iomem *host_mmio;
817 unsigned int hotplug_offset, ata_no;
823 if (!host || !host->iomap[PDC_MMIO_BAR]) {
824 VPRINTK("QUICK EXIT\n");
828 host_mmio = host->iomap[PDC_MMIO_BAR];
830 spin_lock(&host->lock);
832 /* read and clear hotplug flags for all ports */
833 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
834 hotplug_offset = PDC2_SATA_PLUG_CSR;
835 hotplug_status = readl(host_mmio + hotplug_offset);
836 if (hotplug_status & 0xff)
837 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
838 hotplug_status &= 0xff; /* clear uninteresting bits */
842 /* reading should also clear interrupts */
843 mask = readl(host_mmio + PDC_INT_SEQMASK);
845 if (mask == 0xffffffff && hotplug_status == 0) {
846 VPRINTK("QUICK EXIT 2\n");
850 mask &= 0xffff; /* only 16 SEQIDs possible */
851 if (mask == 0 && hotplug_status == 0) {
852 VPRINTK("QUICK EXIT 3\n");
856 writel(mask, host_mmio + PDC_INT_SEQMASK);
858 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
860 for (i = 0; i < host->n_ports; i++) {
861 VPRINTK("port %u\n", i);
864 /* check for a plug or unplug event */
865 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
866 tmp = hotplug_status & (0x11 << ata_no);
868 !(ap->flags & ATA_FLAG_DISABLED)) {
869 struct ata_eh_info *ehi = &ap->link.eh_info;
870 ata_ehi_clear_desc(ehi);
871 ata_ehi_hotplugged(ehi);
872 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
878 /* check for a packet interrupt */
879 tmp = mask & (1 << (i + 1));
881 !(ap->flags & ATA_FLAG_DISABLED)) {
882 struct ata_queued_cmd *qc;
884 qc = ata_qc_from_tag(ap, ap->link.active_tag);
885 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
886 handled += pdc_host_intr(ap, qc);
893 spin_unlock(&host->lock);
894 return IRQ_RETVAL(handled);
897 static void pdc_packet_start(struct ata_queued_cmd *qc)
899 struct ata_port *ap = qc->ap;
900 struct pdc_port_priv *pp = ap->private_data;
901 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
902 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
903 unsigned int port_no = ap->port_no;
904 u8 seq = (u8) (port_no + 1);
906 VPRINTK("ENTER, ap %p\n", ap);
908 writel(0x00000001, host_mmio + (seq * 4));
909 readl(host_mmio + (seq * 4)); /* flush */
912 wmb(); /* flush PRD, pkt writes */
913 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
914 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
917 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
919 switch (qc->tf.protocol) {
920 case ATAPI_PROT_NODATA:
921 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
924 case ATA_PROT_NODATA:
925 if (qc->tf.flags & ATA_TFLAG_POLLING)
930 pdc_packet_start(qc);
935 return ata_sff_qc_issue(qc);
938 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
940 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
941 ata_sff_tf_load(ap, tf);
944 static void pdc_exec_command_mmio(struct ata_port *ap,
945 const struct ata_taskfile *tf)
947 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
948 ata_sff_exec_command(ap, tf);
951 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
953 u8 *scsicmd = qc->scsicmd->cmnd;
954 int pio = 1; /* atapi dma off by default */
956 /* Whitelist commands that may use DMA. */
957 switch (scsicmd[0]) {
964 case 0xad: /* READ_DVD_STRUCTURE */
965 case 0xbe: /* READ_CD */
968 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
969 if (scsicmd[0] == WRITE_10) {
975 if (lba >= 0xFFFF4FA2)
981 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
983 /* First generation chips cannot use ATAPI DMA on SATA ports */
987 static void pdc_ata_setup_port(struct ata_port *ap,
988 void __iomem *base, void __iomem *scr_addr)
990 ap->ioaddr.cmd_addr = base;
991 ap->ioaddr.data_addr = base;
992 ap->ioaddr.feature_addr =
993 ap->ioaddr.error_addr = base + 0x4;
994 ap->ioaddr.nsect_addr = base + 0x8;
995 ap->ioaddr.lbal_addr = base + 0xc;
996 ap->ioaddr.lbam_addr = base + 0x10;
997 ap->ioaddr.lbah_addr = base + 0x14;
998 ap->ioaddr.device_addr = base + 0x18;
999 ap->ioaddr.command_addr =
1000 ap->ioaddr.status_addr = base + 0x1c;
1001 ap->ioaddr.altstatus_addr =
1002 ap->ioaddr.ctl_addr = base + 0x38;
1003 ap->ioaddr.scr_addr = scr_addr;
1006 static void pdc_host_init(struct ata_host *host)
1008 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1009 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1014 hotplug_offset = PDC2_SATA_PLUG_CSR;
1016 hotplug_offset = PDC_SATA_PLUG_CSR;
1019 * Except for the hotplug stuff, this is voodoo from the
1020 * Promise driver. Label this entire section
1021 * "TODO: figure out why we do this"
1024 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1025 tmp = readl(host_mmio + PDC_FLASH_CTL);
1026 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1028 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1029 writel(tmp, host_mmio + PDC_FLASH_CTL);
1031 /* clear plug/unplug flags for all ports */
1032 tmp = readl(host_mmio + hotplug_offset);
1033 writel(tmp | 0xff, host_mmio + hotplug_offset);
1035 tmp = readl(host_mmio + hotplug_offset);
1036 if (is_gen2) /* unmask plug/unplug ints */
1037 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1038 else /* mask plug/unplug ints */
1039 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1041 /* don't initialise TBG or SLEW on 2nd generation chips */
1045 /* reduce TBG clock to 133 Mhz. */
1046 tmp = readl(host_mmio + PDC_TBG_MODE);
1047 tmp &= ~0x30000; /* clear bit 17, 16*/
1048 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1049 writel(tmp, host_mmio + PDC_TBG_MODE);
1051 readl(host_mmio + PDC_TBG_MODE); /* flush */
1054 /* adjust slew rate control register. */
1055 tmp = readl(host_mmio + PDC_SLEW_CTL);
1056 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1057 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1058 writel(tmp, host_mmio + PDC_SLEW_CTL);
1061 static int pdc_ata_init_one(struct pci_dev *pdev,
1062 const struct pci_device_id *ent)
1064 static int printed_version;
1065 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1066 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1067 struct ata_host *host;
1068 void __iomem *host_mmio;
1072 if (!printed_version++)
1073 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1075 /* enable and acquire resources */
1076 rc = pcim_enable_device(pdev);
1080 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1082 pcim_pin_device(pdev);
1085 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1087 /* determine port configuration and setup host */
1089 if (pi->flags & PDC_FLAG_4_PORTS)
1091 for (i = 0; i < n_ports; i++)
1094 if (pi->flags & PDC_FLAG_SATA_PATA) {
1095 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1097 ppi[n_ports++] = pi + 1;
1100 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1102 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1105 host->iomap = pcim_iomap_table(pdev);
1107 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1108 for (i = 0; i < host->n_ports; i++) {
1109 struct ata_port *ap = host->ports[i];
1110 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1111 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1112 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1114 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1116 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1117 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1120 /* initialize adapter */
1121 pdc_host_init(host);
1123 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1126 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1130 /* start host, request IRQ and attach */
1131 pci_set_master(pdev);
1132 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1136 static int __init pdc_ata_init(void)
1138 return pci_register_driver(&pdc_ata_pci_driver);
1141 static void __exit pdc_ata_exit(void)
1143 pci_unregister_driver(&pdc_ata_pci_driver);
1146 MODULE_AUTHOR("Jeff Garzik");
1147 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1148 MODULE_LICENSE("GPL");
1149 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1150 MODULE_VERSION(DRV_VERSION);
1152 module_init(pdc_ata_init);
1153 module_exit(pdc_ata_exit);