2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> Develop a low-power-consumption strategy, and implement it.
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
44 * 80x1-B2 errata PCI#11:
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
69 #include <linux/of_irq.h>
70 #include <scsi/scsi_host.h>
71 #include <scsi/scsi_cmnd.h>
72 #include <scsi/scsi_device.h>
73 #include <linux/libata.h>
75 #define DRV_NAME "sata_mv"
76 #define DRV_VERSION "1.28"
84 module_param(msi, int, S_IRUGO);
85 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
88 static int irq_coalescing_io_count;
89 module_param(irq_coalescing_io_count, int, S_IRUGO);
90 MODULE_PARM_DESC(irq_coalescing_io_count,
91 "IRQ coalescing I/O count threshold (0..255)");
93 static int irq_coalescing_usecs;
94 module_param(irq_coalescing_usecs, int, S_IRUGO);
95 MODULE_PARM_DESC(irq_coalescing_usecs,
96 "IRQ coalescing time threshold in usecs");
99 /* BAR's are enumerated in terms of pci_resource_start() terms */
100 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
101 MV_IO_BAR = 2, /* offset 0x18: IO space */
102 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
104 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
105 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
107 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
108 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
109 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
110 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
115 * Per-chip ("all ports") interrupt coalescing feature.
116 * This is only for GEN_II / GEN_IIE hardware.
118 * Coalescing defers the interrupt until either the IO_THRESHOLD
119 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
121 COAL_REG_BASE = 0x18000,
122 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
123 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
125 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
126 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
129 * Registers for the (unused here) transaction coalescing feature:
131 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
132 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
134 SATAHC0_REG_BASE = 0x20000,
136 GPIO_PORT_CTL = 0x104f0,
139 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
140 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
141 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
142 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
145 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
147 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
148 * CRPB needs alignment on a 256B boundary. Size == 256B
149 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
151 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
152 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
154 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
156 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
157 MV_PORT_HC_SHIFT = 2,
158 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
159 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
160 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
163 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
165 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
167 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
169 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
170 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
172 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
174 CRQB_FLAG_READ = (1 << 0),
176 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
177 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
178 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
179 CRQB_CMD_ADDR_SHIFT = 8,
180 CRQB_CMD_CS = (0x2 << 11),
181 CRQB_CMD_LAST = (1 << 15),
183 CRPB_FLAG_STATUS_SHIFT = 8,
184 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
185 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
187 EPRD_FLAG_END_OF_TBL = (1 << 31),
189 /* PCI interface registers */
191 MV_PCI_COMMAND = 0xc00,
192 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
193 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
195 PCI_MAIN_CMD_STS = 0xd30,
196 STOP_PCI_MASTER = (1 << 2),
197 PCI_MASTER_EMPTY = (1 << 3),
198 GLOB_SFT_RST = (1 << 4),
201 MV_PCI_MODE_MASK = 0x30,
203 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
204 MV_PCI_DISC_TIMER = 0xd04,
205 MV_PCI_MSI_TRIGGER = 0xc38,
206 MV_PCI_SERR_MASK = 0xc28,
207 MV_PCI_XBAR_TMOUT = 0x1d04,
208 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
209 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
210 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
211 MV_PCI_ERR_COMMAND = 0x1d50,
213 PCI_IRQ_CAUSE = 0x1d58,
214 PCI_IRQ_MASK = 0x1d5c,
215 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
217 PCIE_IRQ_CAUSE = 0x1900,
218 PCIE_IRQ_MASK = 0x1910,
219 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
221 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
222 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
223 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
224 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
225 SOC_HC_MAIN_IRQ_MASK = 0x20024,
226 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
227 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
228 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
229 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
230 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
231 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
233 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
234 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
235 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
236 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
237 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
238 GPIO_INT = (1 << 22),
239 SELF_INT = (1 << 23),
240 TWSI_INT = (1 << 24),
241 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
242 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
243 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
245 /* SATAHC registers */
249 DMA_IRQ = (1 << 0), /* shift by port # */
250 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
251 DEV_IRQ = (1 << 8), /* shift by port # */
254 * Per-HC (Host-Controller) interrupt coalescing feature.
255 * This is present on all chip generations.
257 * Coalescing defers the interrupt until either the IO_THRESHOLD
258 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
260 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
261 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
264 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
265 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
266 /* with dev activity LED */
268 /* Shadow block registers */
270 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
273 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
275 FIS_IRQ_CAUSE = 0x364,
276 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
278 LTMODE = 0x30c, /* requires read-after-write */
279 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
284 PHY_MODE4 = 0x314, /* requires read-after-write */
285 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
286 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
287 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
288 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
291 SATA_TESTCTL = 0x348,
293 VENDOR_UNIQUE_FIS = 0x35c,
296 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
297 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
299 PHY_MODE9_GEN2 = 0x398,
300 PHY_MODE9_GEN1 = 0x39c,
301 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
309 MV_M2_PREAMP_MASK = 0x7e0,
313 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
314 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
315 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
316 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
317 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
318 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
319 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
321 EDMA_ERR_IRQ_CAUSE = 0x8,
322 EDMA_ERR_IRQ_MASK = 0xc,
323 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
324 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
325 EDMA_ERR_DEV = (1 << 2), /* device error */
326 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
327 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
328 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
329 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
330 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
331 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
332 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
333 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
334 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
335 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
336 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
338 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
339 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
340 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
341 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
342 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
344 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
346 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
347 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
348 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
349 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
350 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
351 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
353 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
355 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
356 EDMA_ERR_OVERRUN_5 = (1 << 5),
357 EDMA_ERR_UNDERRUN_5 = (1 << 6),
359 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
360 EDMA_ERR_LNK_CTRL_RX_1 |
361 EDMA_ERR_LNK_CTRL_RX_3 |
362 EDMA_ERR_LNK_CTRL_TX,
364 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
374 EDMA_ERR_LNK_CTRL_RX_2 |
375 EDMA_ERR_LNK_DATA_RX |
376 EDMA_ERR_LNK_DATA_TX |
377 EDMA_ERR_TRANS_PROTO,
379 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
384 EDMA_ERR_UNDERRUN_5 |
385 EDMA_ERR_SELF_DIS_5 |
391 EDMA_REQ_Q_BASE_HI = 0x10,
392 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
394 EDMA_REQ_Q_OUT_PTR = 0x18,
395 EDMA_REQ_Q_PTR_SHIFT = 5,
397 EDMA_RSP_Q_BASE_HI = 0x1c,
398 EDMA_RSP_Q_IN_PTR = 0x20,
399 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
400 EDMA_RSP_Q_PTR_SHIFT = 3,
402 EDMA_CMD = 0x28, /* EDMA command register */
403 EDMA_EN = (1 << 0), /* enable EDMA */
404 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
405 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
407 EDMA_STATUS = 0x30, /* EDMA engine status */
408 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
409 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
411 EDMA_IORDY_TMOUT = 0x34,
414 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
415 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
417 BMDMA_CMD = 0x224, /* bmdma command register */
418 BMDMA_STATUS = 0x228, /* bmdma status register */
419 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
420 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
422 /* Host private flags (hp_flags) */
423 MV_HP_FLAG_MSI = (1 << 0),
424 MV_HP_ERRATA_50XXB0 = (1 << 1),
425 MV_HP_ERRATA_50XXB2 = (1 << 2),
426 MV_HP_ERRATA_60X1B2 = (1 << 3),
427 MV_HP_ERRATA_60X1C0 = (1 << 4),
428 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
429 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
430 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
431 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
432 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
433 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
434 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
435 MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */
437 /* Port private flags (pp_flags) */
438 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
439 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
440 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
441 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
442 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
445 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
446 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
447 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
448 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
449 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
451 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
452 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
455 /* DMA boundary 0xffff is required by the s/g splitting
456 * we need on /length/ in mv_fill-sg().
458 MV_DMA_BOUNDARY = 0xffffU,
460 /* mask of register bits containing lower 32 bits
461 * of EDMA request queue DMA address
463 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
465 /* ditto, for response queue */
466 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
480 /* Command ReQuest Block: 32B */
496 /* Command ResPonse Block: 8B */
503 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
512 * We keep a local cache of a few frequently accessed port
513 * registers here, to avoid having to read them (very slow)
514 * when switching between EDMA and non-EDMA modes.
516 struct mv_cached_regs {
523 struct mv_port_priv {
524 struct mv_crqb *crqb;
526 struct mv_crpb *crpb;
528 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
529 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
531 unsigned int req_idx;
532 unsigned int resp_idx;
535 struct mv_cached_regs cached;
536 unsigned int delayed_eh_pmp_map;
539 struct mv_port_signal {
544 struct mv_host_priv {
546 unsigned int board_idx;
548 struct mv_port_signal signal[8];
549 const struct mv_hw_ops *ops;
552 void __iomem *main_irq_cause_addr;
553 void __iomem *main_irq_mask_addr;
554 u32 irq_cause_offset;
558 #if defined(CONFIG_HAVE_CLK)
560 struct clk **port_clks;
563 * These consistent DMA memory pools give us guaranteed
564 * alignment for hardware-accessed data structures,
565 * and less memory waste in accomplishing the alignment.
567 struct dma_pool *crqb_pool;
568 struct dma_pool *crpb_pool;
569 struct dma_pool *sg_tbl_pool;
573 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
576 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
578 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
580 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
581 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
584 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
585 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
586 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
587 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
588 static int mv_port_start(struct ata_port *ap);
589 static void mv_port_stop(struct ata_port *ap);
590 static int mv_qc_defer(struct ata_queued_cmd *qc);
591 static void mv_qc_prep(struct ata_queued_cmd *qc);
592 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
593 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
594 static int mv_hardreset(struct ata_link *link, unsigned int *class,
595 unsigned long deadline);
596 static void mv_eh_freeze(struct ata_port *ap);
597 static void mv_eh_thaw(struct ata_port *ap);
598 static void mv6_dev_config(struct ata_device *dev);
600 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
602 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
603 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
605 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
607 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
608 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
610 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
612 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
613 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
615 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
617 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
618 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
620 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
622 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
623 void __iomem *mmio, unsigned int n_hc);
624 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
626 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
627 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
628 void __iomem *mmio, unsigned int port);
629 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
630 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
631 unsigned int port_no);
632 static int mv_stop_edma(struct ata_port *ap);
633 static int mv_stop_edma_engine(void __iomem *port_mmio);
634 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
636 static void mv_pmp_select(struct ata_port *ap, int pmp);
637 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
638 unsigned long deadline);
639 static int mv_softreset(struct ata_link *link, unsigned int *class,
640 unsigned long deadline);
641 static void mv_pmp_error_handler(struct ata_port *ap);
642 static void mv_process_crpb_entries(struct ata_port *ap,
643 struct mv_port_priv *pp);
645 static void mv_sff_irq_clear(struct ata_port *ap);
646 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
647 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
648 static void mv_bmdma_start(struct ata_queued_cmd *qc);
649 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
650 static u8 mv_bmdma_status(struct ata_port *ap);
651 static u8 mv_sff_check_status(struct ata_port *ap);
653 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
654 * because we have to allow room for worst case splitting of
655 * PRDs for 64K boundaries in mv_fill_sg().
658 static struct scsi_host_template mv5_sht = {
659 ATA_BASE_SHT(DRV_NAME),
660 .sg_tablesize = MV_MAX_SG_CT / 2,
661 .dma_boundary = MV_DMA_BOUNDARY,
664 static struct scsi_host_template mv6_sht = {
665 ATA_NCQ_SHT(DRV_NAME),
666 .can_queue = MV_MAX_Q_DEPTH - 1,
667 .sg_tablesize = MV_MAX_SG_CT / 2,
668 .dma_boundary = MV_DMA_BOUNDARY,
671 static struct ata_port_operations mv5_ops = {
672 .inherits = &ata_sff_port_ops,
674 .lost_interrupt = ATA_OP_NULL,
676 .qc_defer = mv_qc_defer,
677 .qc_prep = mv_qc_prep,
678 .qc_issue = mv_qc_issue,
680 .freeze = mv_eh_freeze,
682 .hardreset = mv_hardreset,
684 .scr_read = mv5_scr_read,
685 .scr_write = mv5_scr_write,
687 .port_start = mv_port_start,
688 .port_stop = mv_port_stop,
691 static struct ata_port_operations mv6_ops = {
692 .inherits = &ata_bmdma_port_ops,
694 .lost_interrupt = ATA_OP_NULL,
696 .qc_defer = mv_qc_defer,
697 .qc_prep = mv_qc_prep,
698 .qc_issue = mv_qc_issue,
700 .dev_config = mv6_dev_config,
702 .freeze = mv_eh_freeze,
704 .hardreset = mv_hardreset,
705 .softreset = mv_softreset,
706 .pmp_hardreset = mv_pmp_hardreset,
707 .pmp_softreset = mv_softreset,
708 .error_handler = mv_pmp_error_handler,
710 .scr_read = mv_scr_read,
711 .scr_write = mv_scr_write,
713 .sff_check_status = mv_sff_check_status,
714 .sff_irq_clear = mv_sff_irq_clear,
715 .check_atapi_dma = mv_check_atapi_dma,
716 .bmdma_setup = mv_bmdma_setup,
717 .bmdma_start = mv_bmdma_start,
718 .bmdma_stop = mv_bmdma_stop,
719 .bmdma_status = mv_bmdma_status,
721 .port_start = mv_port_start,
722 .port_stop = mv_port_stop,
725 static struct ata_port_operations mv_iie_ops = {
726 .inherits = &mv6_ops,
727 .dev_config = ATA_OP_NULL,
728 .qc_prep = mv_qc_prep_iie,
731 static const struct ata_port_info mv_port_info[] = {
733 .flags = MV_GEN_I_FLAGS,
734 .pio_mask = ATA_PIO4,
735 .udma_mask = ATA_UDMA6,
736 .port_ops = &mv5_ops,
739 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
740 .pio_mask = ATA_PIO4,
741 .udma_mask = ATA_UDMA6,
742 .port_ops = &mv5_ops,
745 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
746 .pio_mask = ATA_PIO4,
747 .udma_mask = ATA_UDMA6,
748 .port_ops = &mv5_ops,
751 .flags = MV_GEN_II_FLAGS,
752 .pio_mask = ATA_PIO4,
753 .udma_mask = ATA_UDMA6,
754 .port_ops = &mv6_ops,
757 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
758 .pio_mask = ATA_PIO4,
759 .udma_mask = ATA_UDMA6,
760 .port_ops = &mv6_ops,
763 .flags = MV_GEN_IIE_FLAGS,
764 .pio_mask = ATA_PIO4,
765 .udma_mask = ATA_UDMA6,
766 .port_ops = &mv_iie_ops,
769 .flags = MV_GEN_IIE_FLAGS,
770 .pio_mask = ATA_PIO4,
771 .udma_mask = ATA_UDMA6,
772 .port_ops = &mv_iie_ops,
775 .flags = MV_GEN_IIE_FLAGS,
776 .pio_mask = ATA_PIO4,
777 .udma_mask = ATA_UDMA6,
778 .port_ops = &mv_iie_ops,
782 static const struct pci_device_id mv_pci_tbl[] = {
783 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
784 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
785 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
786 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
787 /* RocketRAID 1720/174x have different identifiers */
788 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
789 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
790 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
792 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
793 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
794 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
795 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
796 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
798 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
801 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
803 /* Marvell 7042 support */
804 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
806 /* Highpoint RocketRAID PCIe series */
807 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
808 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
810 { } /* terminate list */
813 static const struct mv_hw_ops mv5xxx_ops = {
814 .phy_errata = mv5_phy_errata,
815 .enable_leds = mv5_enable_leds,
816 .read_preamp = mv5_read_preamp,
817 .reset_hc = mv5_reset_hc,
818 .reset_flash = mv5_reset_flash,
819 .reset_bus = mv5_reset_bus,
822 static const struct mv_hw_ops mv6xxx_ops = {
823 .phy_errata = mv6_phy_errata,
824 .enable_leds = mv6_enable_leds,
825 .read_preamp = mv6_read_preamp,
826 .reset_hc = mv6_reset_hc,
827 .reset_flash = mv6_reset_flash,
828 .reset_bus = mv_reset_pci_bus,
831 static const struct mv_hw_ops mv_soc_ops = {
832 .phy_errata = mv6_phy_errata,
833 .enable_leds = mv_soc_enable_leds,
834 .read_preamp = mv_soc_read_preamp,
835 .reset_hc = mv_soc_reset_hc,
836 .reset_flash = mv_soc_reset_flash,
837 .reset_bus = mv_soc_reset_bus,
840 static const struct mv_hw_ops mv_soc_65n_ops = {
841 .phy_errata = mv_soc_65n_phy_errata,
842 .enable_leds = mv_soc_enable_leds,
843 .reset_hc = mv_soc_reset_hc,
844 .reset_flash = mv_soc_reset_flash,
845 .reset_bus = mv_soc_reset_bus,
852 static inline void writelfl(unsigned long data, void __iomem *addr)
855 (void) readl(addr); /* flush to avoid PCI posted write */
858 static inline unsigned int mv_hc_from_port(unsigned int port)
860 return port >> MV_PORT_HC_SHIFT;
863 static inline unsigned int mv_hardport_from_port(unsigned int port)
865 return port & MV_PORT_MASK;
869 * Consolidate some rather tricky bit shift calculations.
870 * This is hot-path stuff, so not a function.
871 * Simple code, with two return values, so macro rather than inline.
873 * port is the sole input, in range 0..7.
874 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
875 * hardport is the other output, in range 0..3.
877 * Note that port and hardport may be the same variable in some cases.
879 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
881 shift = mv_hc_from_port(port) * HC_SHIFT; \
882 hardport = mv_hardport_from_port(port); \
883 shift += hardport * 2; \
886 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
888 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
891 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
894 return mv_hc_base(base, mv_hc_from_port(port));
897 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
899 return mv_hc_base_from_port(base, port) +
900 MV_SATAHC_ARBTR_REG_SZ +
901 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
904 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
906 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
907 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
909 return hc_mmio + ofs;
912 static inline void __iomem *mv_host_base(struct ata_host *host)
914 struct mv_host_priv *hpriv = host->private_data;
918 static inline void __iomem *mv_ap_base(struct ata_port *ap)
920 return mv_port_base(mv_host_base(ap->host), ap->port_no);
923 static inline int mv_get_hc_count(unsigned long port_flags)
925 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
929 * mv_save_cached_regs - (re-)initialize cached port registers
930 * @ap: the port whose registers we are caching
932 * Initialize the local cache of port registers,
933 * so that reading them over and over again can
934 * be avoided on the hotter paths of this driver.
935 * This saves a few microseconds each time we switch
936 * to/from EDMA mode to perform (eg.) a drive cache flush.
938 static void mv_save_cached_regs(struct ata_port *ap)
940 void __iomem *port_mmio = mv_ap_base(ap);
941 struct mv_port_priv *pp = ap->private_data;
943 pp->cached.fiscfg = readl(port_mmio + FISCFG);
944 pp->cached.ltmode = readl(port_mmio + LTMODE);
945 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
946 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
950 * mv_write_cached_reg - write to a cached port register
951 * @addr: hardware address of the register
952 * @old: pointer to cached value of the register
953 * @new: new value for the register
955 * Write a new value to a cached register,
956 * but only if the value is different from before.
958 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
964 * Workaround for 88SX60x1-B2 FEr SATA#13:
965 * Read-after-write is needed to prevent generating 64-bit
966 * write cycles on the PCI bus for SATA interface registers
967 * at offsets ending in 0x4 or 0xc.
969 * Looks like a lot of fuss, but it avoids an unnecessary
970 * +1 usec read-after-write delay for unaffected registers.
972 laddr = (long)addr & 0xffff;
973 if (laddr >= 0x300 && laddr <= 0x33c) {
975 if (laddr == 0x4 || laddr == 0xc) {
976 writelfl(new, addr); /* read after write */
980 writel(new, addr); /* unaffected by the errata */
984 static void mv_set_edma_ptrs(void __iomem *port_mmio,
985 struct mv_host_priv *hpriv,
986 struct mv_port_priv *pp)
991 * initialize request queue
993 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
994 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
996 WARN_ON(pp->crqb_dma & 0x3ff);
997 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
998 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
999 port_mmio + EDMA_REQ_Q_IN_PTR);
1000 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
1003 * initialize response queue
1005 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1006 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1008 WARN_ON(pp->crpb_dma & 0xff);
1009 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1010 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1011 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
1012 port_mmio + EDMA_RSP_Q_OUT_PTR);
1015 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1018 * When writing to the main_irq_mask in hardware,
1019 * we must ensure exclusivity between the interrupt coalescing bits
1020 * and the corresponding individual port DONE_IRQ bits.
1022 * Note that this register is really an "IRQ enable" register,
1023 * not an "IRQ mask" register as Marvell's naming might suggest.
1025 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1026 mask &= ~DONE_IRQ_0_3;
1027 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1028 mask &= ~DONE_IRQ_4_7;
1029 writelfl(mask, hpriv->main_irq_mask_addr);
1032 static void mv_set_main_irq_mask(struct ata_host *host,
1033 u32 disable_bits, u32 enable_bits)
1035 struct mv_host_priv *hpriv = host->private_data;
1036 u32 old_mask, new_mask;
1038 old_mask = hpriv->main_irq_mask;
1039 new_mask = (old_mask & ~disable_bits) | enable_bits;
1040 if (new_mask != old_mask) {
1041 hpriv->main_irq_mask = new_mask;
1042 mv_write_main_irq_mask(new_mask, hpriv);
1046 static void mv_enable_port_irqs(struct ata_port *ap,
1047 unsigned int port_bits)
1049 unsigned int shift, hardport, port = ap->port_no;
1050 u32 disable_bits, enable_bits;
1052 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1054 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1055 enable_bits = port_bits << shift;
1056 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1059 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1060 void __iomem *port_mmio,
1061 unsigned int port_irqs)
1063 struct mv_host_priv *hpriv = ap->host->private_data;
1064 int hardport = mv_hardport_from_port(ap->port_no);
1065 void __iomem *hc_mmio = mv_hc_base_from_port(
1066 mv_host_base(ap->host), ap->port_no);
1069 /* clear EDMA event indicators, if any */
1070 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1072 /* clear pending irq events */
1073 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1074 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1076 /* clear FIS IRQ Cause */
1077 if (IS_GEN_IIE(hpriv))
1078 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1080 mv_enable_port_irqs(ap, port_irqs);
1083 static void mv_set_irq_coalescing(struct ata_host *host,
1084 unsigned int count, unsigned int usecs)
1086 struct mv_host_priv *hpriv = host->private_data;
1087 void __iomem *mmio = hpriv->base, *hc_mmio;
1088 u32 coal_enable = 0;
1089 unsigned long flags;
1090 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1091 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1092 ALL_PORTS_COAL_DONE;
1094 /* Disable IRQ coalescing if either threshold is zero */
1095 if (!usecs || !count) {
1098 /* Respect maximum limits of the hardware */
1099 clks = usecs * COAL_CLOCKS_PER_USEC;
1100 if (clks > MAX_COAL_TIME_THRESHOLD)
1101 clks = MAX_COAL_TIME_THRESHOLD;
1102 if (count > MAX_COAL_IO_COUNT)
1103 count = MAX_COAL_IO_COUNT;
1106 spin_lock_irqsave(&host->lock, flags);
1107 mv_set_main_irq_mask(host, coal_disable, 0);
1109 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1111 * GEN_II/GEN_IIE with dual host controllers:
1112 * one set of global thresholds for the entire chip.
1114 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1115 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1116 /* clear leftover coal IRQ bit */
1117 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1119 coal_enable = ALL_PORTS_COAL_DONE;
1120 clks = count = 0; /* force clearing of regular regs below */
1124 * All chips: independent thresholds for each HC on the chip.
1126 hc_mmio = mv_hc_base_from_port(mmio, 0);
1127 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1128 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1129 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1131 coal_enable |= PORTS_0_3_COAL_DONE;
1133 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1134 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1135 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1136 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1138 coal_enable |= PORTS_4_7_COAL_DONE;
1141 mv_set_main_irq_mask(host, 0, coal_enable);
1142 spin_unlock_irqrestore(&host->lock, flags);
1146 * mv_start_edma - Enable eDMA engine
1147 * @base: port base address
1148 * @pp: port private data
1150 * Verify the local cache of the eDMA state is accurate with a
1154 * Inherited from caller.
1156 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1157 struct mv_port_priv *pp, u8 protocol)
1159 int want_ncq = (protocol == ATA_PROT_NCQ);
1161 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1162 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1163 if (want_ncq != using_ncq)
1166 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1167 struct mv_host_priv *hpriv = ap->host->private_data;
1169 mv_edma_cfg(ap, want_ncq, 1);
1171 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1172 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1174 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1175 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1179 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1181 void __iomem *port_mmio = mv_ap_base(ap);
1182 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1183 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1187 * Wait for the EDMA engine to finish transactions in progress.
1188 * No idea what a good "timeout" value might be, but measurements
1189 * indicate that it often requires hundreds of microseconds
1190 * with two drives in-use. So we use the 15msec value above
1191 * as a rough guess at what even more drives might require.
1193 for (i = 0; i < timeout; ++i) {
1194 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1195 if ((edma_stat & empty_idle) == empty_idle)
1199 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
1203 * mv_stop_edma_engine - Disable eDMA engine
1204 * @port_mmio: io base address
1207 * Inherited from caller.
1209 static int mv_stop_edma_engine(void __iomem *port_mmio)
1213 /* Disable eDMA. The disable bit auto clears. */
1214 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1216 /* Wait for the chip to confirm eDMA is off. */
1217 for (i = 10000; i > 0; i--) {
1218 u32 reg = readl(port_mmio + EDMA_CMD);
1219 if (!(reg & EDMA_EN))
1226 static int mv_stop_edma(struct ata_port *ap)
1228 void __iomem *port_mmio = mv_ap_base(ap);
1229 struct mv_port_priv *pp = ap->private_data;
1232 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1234 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1235 mv_wait_for_edma_empty_idle(ap);
1236 if (mv_stop_edma_engine(port_mmio)) {
1237 ata_port_err(ap, "Unable to stop eDMA\n");
1240 mv_edma_cfg(ap, 0, 0);
1245 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1248 for (b = 0; b < bytes; ) {
1249 DPRINTK("%p: ", start + b);
1250 for (w = 0; b < bytes && w < 4; w++) {
1251 printk("%08x ", readl(start + b));
1258 #if defined(ATA_DEBUG) || defined(CONFIG_PCI)
1259 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1264 for (b = 0; b < bytes; ) {
1265 DPRINTK("%02x: ", b);
1266 for (w = 0; b < bytes && w < 4; w++) {
1267 (void) pci_read_config_dword(pdev, b, &dw);
1268 printk("%08x ", dw);
1276 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1277 struct pci_dev *pdev)
1280 void __iomem *hc_base = mv_hc_base(mmio_base,
1281 port >> MV_PORT_HC_SHIFT);
1282 void __iomem *port_base;
1283 int start_port, num_ports, p, start_hc, num_hcs, hc;
1286 start_hc = start_port = 0;
1287 num_ports = 8; /* shld be benign for 4 port devs */
1290 start_hc = port >> MV_PORT_HC_SHIFT;
1292 num_ports = num_hcs = 1;
1294 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1295 num_ports > 1 ? num_ports - 1 : start_port);
1298 DPRINTK("PCI config space regs:\n");
1299 mv_dump_pci_cfg(pdev, 0x68);
1301 DPRINTK("PCI regs:\n");
1302 mv_dump_mem(mmio_base+0xc00, 0x3c);
1303 mv_dump_mem(mmio_base+0xd00, 0x34);
1304 mv_dump_mem(mmio_base+0xf00, 0x4);
1305 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1306 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1307 hc_base = mv_hc_base(mmio_base, hc);
1308 DPRINTK("HC regs (HC %i):\n", hc);
1309 mv_dump_mem(hc_base, 0x1c);
1311 for (p = start_port; p < start_port + num_ports; p++) {
1312 port_base = mv_port_base(mmio_base, p);
1313 DPRINTK("EDMA regs (port %i):\n", p);
1314 mv_dump_mem(port_base, 0x54);
1315 DPRINTK("SATA regs (port %i):\n", p);
1316 mv_dump_mem(port_base+0x300, 0x60);
1321 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1325 switch (sc_reg_in) {
1329 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1332 ofs = SATA_ACTIVE; /* active is not with the others */
1341 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1343 unsigned int ofs = mv_scr_offset(sc_reg_in);
1345 if (ofs != 0xffffffffU) {
1346 *val = readl(mv_ap_base(link->ap) + ofs);
1352 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1354 unsigned int ofs = mv_scr_offset(sc_reg_in);
1356 if (ofs != 0xffffffffU) {
1357 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1358 struct mv_host_priv *hpriv = link->ap->host->private_data;
1359 if (sc_reg_in == SCR_CONTROL) {
1361 * Workaround for 88SX60x1 FEr SATA#26:
1363 * COMRESETs have to take care not to accidentally
1364 * put the drive to sleep when writing SCR_CONTROL.
1365 * Setting bits 12..15 prevents this problem.
1367 * So if we see an outbound COMMRESET, set those bits.
1368 * Ditto for the followup write that clears the reset.
1370 * The proprietary driver does this for
1371 * all chip versions, and so do we.
1373 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1376 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
1377 void __iomem *lp_phy_addr =
1378 mv_ap_base(link->ap) + LP_PHY_CTL;
1380 * Set PHY speed according to SControl speed.
1382 if ((val & 0xf0) == 0x10)
1383 writelfl(0x7, lp_phy_addr);
1385 writelfl(0x227, lp_phy_addr);
1388 writelfl(val, addr);
1394 static void mv6_dev_config(struct ata_device *adev)
1397 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1399 * Gen-II does not support NCQ over a port multiplier
1400 * (no FIS-based switching).
1402 if (adev->flags & ATA_DFLAG_NCQ) {
1403 if (sata_pmp_attached(adev->link->ap)) {
1404 adev->flags &= ~ATA_DFLAG_NCQ;
1406 "NCQ disabled for command-based switching\n");
1411 static int mv_qc_defer(struct ata_queued_cmd *qc)
1413 struct ata_link *link = qc->dev->link;
1414 struct ata_port *ap = link->ap;
1415 struct mv_port_priv *pp = ap->private_data;
1418 * Don't allow new commands if we're in a delayed EH state
1419 * for NCQ and/or FIS-based switching.
1421 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1422 return ATA_DEFER_PORT;
1424 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1425 * can run concurrently.
1426 * set excl_link when we want to send a PIO command in DMA mode
1427 * or a non-NCQ command in NCQ mode.
1428 * When we receive a command from that link, and there are no
1429 * outstanding commands, mark a flag to clear excl_link and let
1430 * the command go through.
1432 if (unlikely(ap->excl_link)) {
1433 if (link == ap->excl_link) {
1434 if (ap->nr_active_links)
1435 return ATA_DEFER_PORT;
1436 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1439 return ATA_DEFER_PORT;
1443 * If the port is completely idle, then allow the new qc.
1445 if (ap->nr_active_links == 0)
1449 * The port is operating in host queuing mode (EDMA) with NCQ
1450 * enabled, allow multiple NCQ commands. EDMA also allows
1451 * queueing multiple DMA commands but libata core currently
1454 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1455 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1456 if (ata_is_ncq(qc->tf.protocol))
1459 ap->excl_link = link;
1460 return ATA_DEFER_PORT;
1464 return ATA_DEFER_PORT;
1467 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1469 struct mv_port_priv *pp = ap->private_data;
1470 void __iomem *port_mmio;
1472 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1473 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1474 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1476 ltmode = *old_ltmode & ~LTMODE_BIT8;
1477 haltcond = *old_haltcond | EDMA_ERR_DEV;
1480 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1481 ltmode = *old_ltmode | LTMODE_BIT8;
1483 haltcond &= ~EDMA_ERR_DEV;
1485 fiscfg |= FISCFG_WAIT_DEV_ERR;
1487 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1490 port_mmio = mv_ap_base(ap);
1491 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1492 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1493 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1496 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1498 struct mv_host_priv *hpriv = ap->host->private_data;
1501 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1502 old = readl(hpriv->base + GPIO_PORT_CTL);
1504 new = old | (1 << 22);
1506 new = old & ~(1 << 22);
1508 writel(new, hpriv->base + GPIO_PORT_CTL);
1512 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1513 * @ap: Port being initialized
1515 * There are two DMA modes on these chips: basic DMA, and EDMA.
1517 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1518 * of basic DMA on the GEN_IIE versions of the chips.
1520 * This bit survives EDMA resets, and must be set for basic DMA
1521 * to function, and should be cleared when EDMA is active.
1523 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1525 struct mv_port_priv *pp = ap->private_data;
1526 u32 new, *old = &pp->cached.unknown_rsvd;
1532 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1536 * SOC chips have an issue whereby the HDD LEDs don't always blink
1537 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1538 * of the SOC takes care of it, generating a steady blink rate when
1539 * any drive on the chip is active.
1541 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1542 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1544 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1545 * LED operation works then, and provides better (more accurate) feedback.
1547 * Note that this code assumes that an SOC never has more than one HC onboard.
1549 static void mv_soc_led_blink_enable(struct ata_port *ap)
1551 struct ata_host *host = ap->host;
1552 struct mv_host_priv *hpriv = host->private_data;
1553 void __iomem *hc_mmio;
1556 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1558 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1559 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1560 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1561 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1564 static void mv_soc_led_blink_disable(struct ata_port *ap)
1566 struct ata_host *host = ap->host;
1567 struct mv_host_priv *hpriv = host->private_data;
1568 void __iomem *hc_mmio;
1572 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1575 /* disable led-blink only if no ports are using NCQ */
1576 for (port = 0; port < hpriv->n_ports; port++) {
1577 struct ata_port *this_ap = host->ports[port];
1578 struct mv_port_priv *pp = this_ap->private_data;
1580 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1584 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1585 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1586 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1587 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1590 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1593 struct mv_port_priv *pp = ap->private_data;
1594 struct mv_host_priv *hpriv = ap->host->private_data;
1595 void __iomem *port_mmio = mv_ap_base(ap);
1597 /* set up non-NCQ EDMA configuration */
1598 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1600 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1602 if (IS_GEN_I(hpriv))
1603 cfg |= (1 << 8); /* enab config burst size mask */
1605 else if (IS_GEN_II(hpriv)) {
1606 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1607 mv_60x1_errata_sata25(ap, want_ncq);
1609 } else if (IS_GEN_IIE(hpriv)) {
1610 int want_fbs = sata_pmp_attached(ap);
1612 * Possible future enhancement:
1614 * The chip can use FBS with non-NCQ, if we allow it,
1615 * But first we need to have the error handling in place
1616 * for this mode (datasheet section 7.3.15.4.2.3).
1617 * So disallow non-NCQ FBS for now.
1619 want_fbs &= want_ncq;
1621 mv_config_fbs(ap, want_ncq, want_fbs);
1624 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1625 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1628 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1630 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1632 cfg |= (1 << 18); /* enab early completion */
1634 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1635 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1636 mv_bmdma_enable_iie(ap, !want_edma);
1638 if (IS_SOC(hpriv)) {
1640 mv_soc_led_blink_enable(ap);
1642 mv_soc_led_blink_disable(ap);
1647 cfg |= EDMA_CFG_NCQ;
1648 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1651 writelfl(cfg, port_mmio + EDMA_CFG);
1654 static void mv_port_free_dma_mem(struct ata_port *ap)
1656 struct mv_host_priv *hpriv = ap->host->private_data;
1657 struct mv_port_priv *pp = ap->private_data;
1661 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1665 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1669 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1670 * For later hardware, we have one unique sg_tbl per NCQ tag.
1672 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1673 if (pp->sg_tbl[tag]) {
1674 if (tag == 0 || !IS_GEN_I(hpriv))
1675 dma_pool_free(hpriv->sg_tbl_pool,
1677 pp->sg_tbl_dma[tag]);
1678 pp->sg_tbl[tag] = NULL;
1684 * mv_port_start - Port specific init/start routine.
1685 * @ap: ATA channel to manipulate
1687 * Allocate and point to DMA memory, init port private memory,
1691 * Inherited from caller.
1693 static int mv_port_start(struct ata_port *ap)
1695 struct device *dev = ap->host->dev;
1696 struct mv_host_priv *hpriv = ap->host->private_data;
1697 struct mv_port_priv *pp;
1698 unsigned long flags;
1701 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1704 ap->private_data = pp;
1706 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1709 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1711 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1713 goto out_port_free_dma_mem;
1714 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1716 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1717 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1718 ap->flags |= ATA_FLAG_AN;
1720 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1721 * For later hardware, we need one unique sg_tbl per NCQ tag.
1723 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1724 if (tag == 0 || !IS_GEN_I(hpriv)) {
1725 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1726 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1727 if (!pp->sg_tbl[tag])
1728 goto out_port_free_dma_mem;
1730 pp->sg_tbl[tag] = pp->sg_tbl[0];
1731 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1735 spin_lock_irqsave(ap->lock, flags);
1736 mv_save_cached_regs(ap);
1737 mv_edma_cfg(ap, 0, 0);
1738 spin_unlock_irqrestore(ap->lock, flags);
1742 out_port_free_dma_mem:
1743 mv_port_free_dma_mem(ap);
1748 * mv_port_stop - Port specific cleanup/stop routine.
1749 * @ap: ATA channel to manipulate
1751 * Stop DMA, cleanup port memory.
1754 * This routine uses the host lock to protect the DMA stop.
1756 static void mv_port_stop(struct ata_port *ap)
1758 unsigned long flags;
1760 spin_lock_irqsave(ap->lock, flags);
1762 mv_enable_port_irqs(ap, 0);
1763 spin_unlock_irqrestore(ap->lock, flags);
1764 mv_port_free_dma_mem(ap);
1768 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1769 * @qc: queued command whose SG list to source from
1771 * Populate the SG list and mark the last entry.
1774 * Inherited from caller.
1776 static void mv_fill_sg(struct ata_queued_cmd *qc)
1778 struct mv_port_priv *pp = qc->ap->private_data;
1779 struct scatterlist *sg;
1780 struct mv_sg *mv_sg, *last_sg = NULL;
1783 mv_sg = pp->sg_tbl[qc->tag];
1784 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1785 dma_addr_t addr = sg_dma_address(sg);
1786 u32 sg_len = sg_dma_len(sg);
1789 u32 offset = addr & 0xffff;
1792 if (offset + len > 0x10000)
1793 len = 0x10000 - offset;
1795 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1796 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1797 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1798 mv_sg->reserved = 0;
1808 if (likely(last_sg))
1809 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1810 mb(); /* ensure data structure is visible to the chipset */
1813 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1815 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1816 (last ? CRQB_CMD_LAST : 0);
1817 *cmdw = cpu_to_le16(tmp);
1821 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1822 * @ap: Port associated with this ATA transaction.
1824 * We need this only for ATAPI bmdma transactions,
1825 * as otherwise we experience spurious interrupts
1826 * after libata-sff handles the bmdma interrupts.
1828 static void mv_sff_irq_clear(struct ata_port *ap)
1830 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1834 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1835 * @qc: queued command to check for chipset/DMA compatibility.
1837 * The bmdma engines cannot handle speculative data sizes
1838 * (bytecount under/over flow). So only allow DMA for
1839 * data transfer commands with known data sizes.
1842 * Inherited from caller.
1844 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1846 struct scsi_cmnd *scmd = qc->scsicmd;
1849 switch (scmd->cmnd[0]) {
1857 case GPCMD_SEND_DVD_STRUCTURE:
1858 case GPCMD_SEND_CUE_SHEET:
1859 return 0; /* DMA is safe */
1862 return -EOPNOTSUPP; /* use PIO instead */
1866 * mv_bmdma_setup - Set up BMDMA transaction
1867 * @qc: queued command to prepare DMA for.
1870 * Inherited from caller.
1872 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1874 struct ata_port *ap = qc->ap;
1875 void __iomem *port_mmio = mv_ap_base(ap);
1876 struct mv_port_priv *pp = ap->private_data;
1880 /* clear all DMA cmd bits */
1881 writel(0, port_mmio + BMDMA_CMD);
1883 /* load PRD table addr. */
1884 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1885 port_mmio + BMDMA_PRD_HIGH);
1886 writelfl(pp->sg_tbl_dma[qc->tag],
1887 port_mmio + BMDMA_PRD_LOW);
1889 /* issue r/w command */
1890 ap->ops->sff_exec_command(ap, &qc->tf);
1894 * mv_bmdma_start - Start a BMDMA transaction
1895 * @qc: queued command to start DMA on.
1898 * Inherited from caller.
1900 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1902 struct ata_port *ap = qc->ap;
1903 void __iomem *port_mmio = mv_ap_base(ap);
1904 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1905 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1907 /* start host DMA transaction */
1908 writelfl(cmd, port_mmio + BMDMA_CMD);
1912 * mv_bmdma_stop - Stop BMDMA transfer
1913 * @qc: queued command to stop DMA on.
1915 * Clears the ATA_DMA_START flag in the bmdma control register
1918 * Inherited from caller.
1920 static void mv_bmdma_stop_ap(struct ata_port *ap)
1922 void __iomem *port_mmio = mv_ap_base(ap);
1925 /* clear start/stop bit */
1926 cmd = readl(port_mmio + BMDMA_CMD);
1927 if (cmd & ATA_DMA_START) {
1928 cmd &= ~ATA_DMA_START;
1929 writelfl(cmd, port_mmio + BMDMA_CMD);
1931 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1932 ata_sff_dma_pause(ap);
1936 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1938 mv_bmdma_stop_ap(qc->ap);
1942 * mv_bmdma_status - Read BMDMA status
1943 * @ap: port for which to retrieve DMA status.
1945 * Read and return equivalent of the sff BMDMA status register.
1948 * Inherited from caller.
1950 static u8 mv_bmdma_status(struct ata_port *ap)
1952 void __iomem *port_mmio = mv_ap_base(ap);
1956 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1957 * and the ATA_DMA_INTR bit doesn't exist.
1959 reg = readl(port_mmio + BMDMA_STATUS);
1960 if (reg & ATA_DMA_ACTIVE)
1961 status = ATA_DMA_ACTIVE;
1962 else if (reg & ATA_DMA_ERR)
1963 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1966 * Just because DMA_ACTIVE is 0 (DMA completed),
1967 * this does _not_ mean the device is "done".
1968 * So we should not yet be signalling ATA_DMA_INTR
1969 * in some cases. Eg. DSM/TRIM, and perhaps others.
1971 mv_bmdma_stop_ap(ap);
1972 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1975 status = ATA_DMA_INTR;
1980 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1982 struct ata_taskfile *tf = &qc->tf;
1984 * Workaround for 88SX60x1 FEr SATA#24.
1986 * Chip may corrupt WRITEs if multi_count >= 4kB.
1987 * Note that READs are unaffected.
1989 * It's not clear if this errata really means "4K bytes",
1990 * or if it always happens for multi_count > 7
1991 * regardless of device sector_size.
1993 * So, for safety, any write with multi_count > 7
1994 * gets converted here into a regular PIO write instead:
1996 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1997 if (qc->dev->multi_count > 7) {
1998 switch (tf->command) {
1999 case ATA_CMD_WRITE_MULTI:
2000 tf->command = ATA_CMD_PIO_WRITE;
2002 case ATA_CMD_WRITE_MULTI_FUA_EXT:
2003 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
2005 case ATA_CMD_WRITE_MULTI_EXT:
2006 tf->command = ATA_CMD_PIO_WRITE_EXT;
2014 * mv_qc_prep - Host specific command preparation.
2015 * @qc: queued command to prepare
2017 * This routine simply redirects to the general purpose routine
2018 * if command is not DMA. Else, it handles prep of the CRQB
2019 * (command request block), does some sanity checking, and calls
2020 * the SG load routine.
2023 * Inherited from caller.
2025 static void mv_qc_prep(struct ata_queued_cmd *qc)
2027 struct ata_port *ap = qc->ap;
2028 struct mv_port_priv *pp = ap->private_data;
2030 struct ata_taskfile *tf = &qc->tf;
2034 switch (tf->protocol) {
2036 if (tf->command == ATA_CMD_DSM)
2040 break; /* continue below */
2042 mv_rw_multi_errata_sata24(qc);
2048 /* Fill in command request block
2050 if (!(tf->flags & ATA_TFLAG_WRITE))
2051 flags |= CRQB_FLAG_READ;
2052 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2053 flags |= qc->tag << CRQB_TAG_SHIFT;
2054 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2056 /* get current queue index from software */
2057 in_index = pp->req_idx;
2059 pp->crqb[in_index].sg_addr =
2060 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2061 pp->crqb[in_index].sg_addr_hi =
2062 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2063 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2065 cw = &pp->crqb[in_index].ata_cmd[0];
2067 /* Sadly, the CRQB cannot accommodate all registers--there are
2068 * only 11 bytes...so we must pick and choose required
2069 * registers based on the command. So, we drop feature and
2070 * hob_feature for [RW] DMA commands, but they are needed for
2071 * NCQ. NCQ will drop hob_nsect, which is not needed there
2072 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2074 switch (tf->command) {
2076 case ATA_CMD_READ_EXT:
2078 case ATA_CMD_WRITE_EXT:
2079 case ATA_CMD_WRITE_FUA_EXT:
2080 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2082 case ATA_CMD_FPDMA_READ:
2083 case ATA_CMD_FPDMA_WRITE:
2084 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2085 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2088 /* The only other commands EDMA supports in non-queued and
2089 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2090 * of which are defined/used by Linux. If we get here, this
2091 * driver needs work.
2093 * FIXME: modify libata to give qc_prep a return value and
2094 * return error here.
2096 BUG_ON(tf->command);
2099 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2100 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2101 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2102 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2103 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2104 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2105 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2106 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2107 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2109 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2115 * mv_qc_prep_iie - Host specific command preparation.
2116 * @qc: queued command to prepare
2118 * This routine simply redirects to the general purpose routine
2119 * if command is not DMA. Else, it handles prep of the CRQB
2120 * (command request block), does some sanity checking, and calls
2121 * the SG load routine.
2124 * Inherited from caller.
2126 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2128 struct ata_port *ap = qc->ap;
2129 struct mv_port_priv *pp = ap->private_data;
2130 struct mv_crqb_iie *crqb;
2131 struct ata_taskfile *tf = &qc->tf;
2135 if ((tf->protocol != ATA_PROT_DMA) &&
2136 (tf->protocol != ATA_PROT_NCQ))
2138 if (tf->command == ATA_CMD_DSM)
2139 return; /* use bmdma for this */
2141 /* Fill in Gen IIE command request block */
2142 if (!(tf->flags & ATA_TFLAG_WRITE))
2143 flags |= CRQB_FLAG_READ;
2145 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2146 flags |= qc->tag << CRQB_TAG_SHIFT;
2147 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2148 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2150 /* get current queue index from software */
2151 in_index = pp->req_idx;
2153 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2154 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2155 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2156 crqb->flags = cpu_to_le32(flags);
2158 crqb->ata_cmd[0] = cpu_to_le32(
2159 (tf->command << 16) |
2162 crqb->ata_cmd[1] = cpu_to_le32(
2168 crqb->ata_cmd[2] = cpu_to_le32(
2169 (tf->hob_lbal << 0) |
2170 (tf->hob_lbam << 8) |
2171 (tf->hob_lbah << 16) |
2172 (tf->hob_feature << 24)
2174 crqb->ata_cmd[3] = cpu_to_le32(
2176 (tf->hob_nsect << 8)
2179 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2185 * mv_sff_check_status - fetch device status, if valid
2186 * @ap: ATA port to fetch status from
2188 * When using command issue via mv_qc_issue_fis(),
2189 * the initial ATA_BUSY state does not show up in the
2190 * ATA status (shadow) register. This can confuse libata!
2192 * So we have a hook here to fake ATA_BUSY for that situation,
2193 * until the first time a BUSY, DRQ, or ERR bit is seen.
2195 * The rest of the time, it simply returns the ATA status register.
2197 static u8 mv_sff_check_status(struct ata_port *ap)
2199 u8 stat = ioread8(ap->ioaddr.status_addr);
2200 struct mv_port_priv *pp = ap->private_data;
2202 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2203 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2204 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2212 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2213 * @fis: fis to be sent
2214 * @nwords: number of 32-bit words in the fis
2216 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2218 void __iomem *port_mmio = mv_ap_base(ap);
2219 u32 ifctl, old_ifctl, ifstat;
2220 int i, timeout = 200, final_word = nwords - 1;
2222 /* Initiate FIS transmission mode */
2223 old_ifctl = readl(port_mmio + SATA_IFCTL);
2224 ifctl = 0x100 | (old_ifctl & 0xf);
2225 writelfl(ifctl, port_mmio + SATA_IFCTL);
2227 /* Send all words of the FIS except for the final word */
2228 for (i = 0; i < final_word; ++i)
2229 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2231 /* Flag end-of-transmission, and then send the final word */
2232 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2233 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2236 * Wait for FIS transmission to complete.
2237 * This typically takes just a single iteration.
2240 ifstat = readl(port_mmio + SATA_IFSTAT);
2241 } while (!(ifstat & 0x1000) && --timeout);
2243 /* Restore original port configuration */
2244 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2246 /* See if it worked */
2247 if ((ifstat & 0x3000) != 0x1000) {
2248 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2250 return AC_ERR_OTHER;
2256 * mv_qc_issue_fis - Issue a command directly as a FIS
2257 * @qc: queued command to start
2259 * Note that the ATA shadow registers are not updated
2260 * after command issue, so the device will appear "READY"
2261 * if polled, even while it is BUSY processing the command.
2263 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2265 * Note: we don't get updated shadow regs on *completion*
2266 * of non-data commands. So avoid sending them via this function,
2267 * as they will appear to have completed immediately.
2269 * GEN_IIE has special registers that we could get the result tf from,
2270 * but earlier chipsets do not. For now, we ignore those registers.
2272 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2274 struct ata_port *ap = qc->ap;
2275 struct mv_port_priv *pp = ap->private_data;
2276 struct ata_link *link = qc->dev->link;
2280 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2281 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2285 switch (qc->tf.protocol) {
2286 case ATAPI_PROT_PIO:
2287 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2289 case ATAPI_PROT_NODATA:
2290 ap->hsm_task_state = HSM_ST_FIRST;
2293 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2294 if (qc->tf.flags & ATA_TFLAG_WRITE)
2295 ap->hsm_task_state = HSM_ST_FIRST;
2297 ap->hsm_task_state = HSM_ST;
2300 ap->hsm_task_state = HSM_ST_LAST;
2304 if (qc->tf.flags & ATA_TFLAG_POLLING)
2305 ata_sff_queue_pio_task(link, 0);
2310 * mv_qc_issue - Initiate a command to the host
2311 * @qc: queued command to start
2313 * This routine simply redirects to the general purpose routine
2314 * if command is not DMA. Else, it sanity checks our local
2315 * caches of the request producer/consumer indices then enables
2316 * DMA and bumps the request producer index.
2319 * Inherited from caller.
2321 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2323 static int limit_warnings = 10;
2324 struct ata_port *ap = qc->ap;
2325 void __iomem *port_mmio = mv_ap_base(ap);
2326 struct mv_port_priv *pp = ap->private_data;
2328 unsigned int port_irqs;
2330 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2332 switch (qc->tf.protocol) {
2334 if (qc->tf.command == ATA_CMD_DSM) {
2335 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2336 return AC_ERR_OTHER;
2337 break; /* use bmdma for this */
2341 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2342 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2343 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2345 /* Write the request in pointer to kick the EDMA to life */
2346 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2347 port_mmio + EDMA_REQ_Q_IN_PTR);
2352 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2354 * Someday, we might implement special polling workarounds
2355 * for these, but it all seems rather unnecessary since we
2356 * normally use only DMA for commands which transfer more
2357 * than a single block of data.
2359 * Much of the time, this could just work regardless.
2360 * So for now, just log the incident, and allow the attempt.
2362 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2364 ata_link_warn(qc->dev->link, DRV_NAME
2365 ": attempting PIO w/multiple DRQ: "
2366 "this may fail due to h/w errata\n");
2369 case ATA_PROT_NODATA:
2370 case ATAPI_PROT_PIO:
2371 case ATAPI_PROT_NODATA:
2372 if (ap->flags & ATA_FLAG_PIO_POLLING)
2373 qc->tf.flags |= ATA_TFLAG_POLLING;
2377 if (qc->tf.flags & ATA_TFLAG_POLLING)
2378 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2380 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2383 * We're about to send a non-EDMA capable command to the
2384 * port. Turn off EDMA so there won't be problems accessing
2385 * shadow block, etc registers.
2388 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2389 mv_pmp_select(ap, qc->dev->link->pmp);
2391 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2392 struct mv_host_priv *hpriv = ap->host->private_data;
2394 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2396 * After any NCQ error, the READ_LOG_EXT command
2397 * from libata-eh *must* use mv_qc_issue_fis().
2398 * Otherwise it might fail, due to chip errata.
2400 * Rather than special-case it, we'll just *always*
2401 * use this method here for READ_LOG_EXT, making for
2404 if (IS_GEN_II(hpriv))
2405 return mv_qc_issue_fis(qc);
2407 return ata_bmdma_qc_issue(qc);
2410 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2412 struct mv_port_priv *pp = ap->private_data;
2413 struct ata_queued_cmd *qc;
2415 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2417 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2418 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2423 static void mv_pmp_error_handler(struct ata_port *ap)
2425 unsigned int pmp, pmp_map;
2426 struct mv_port_priv *pp = ap->private_data;
2428 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2430 * Perform NCQ error analysis on failed PMPs
2431 * before we freeze the port entirely.
2433 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2435 pmp_map = pp->delayed_eh_pmp_map;
2436 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2437 for (pmp = 0; pmp_map != 0; pmp++) {
2438 unsigned int this_pmp = (1 << pmp);
2439 if (pmp_map & this_pmp) {
2440 struct ata_link *link = &ap->pmp_link[pmp];
2441 pmp_map &= ~this_pmp;
2442 ata_eh_analyze_ncq_error(link);
2445 ata_port_freeze(ap);
2447 sata_pmp_error_handler(ap);
2450 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2452 void __iomem *port_mmio = mv_ap_base(ap);
2454 return readl(port_mmio + SATA_TESTCTL) >> 16;
2457 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2459 struct ata_eh_info *ehi;
2463 * Initialize EH info for PMPs which saw device errors
2465 ehi = &ap->link.eh_info;
2466 for (pmp = 0; pmp_map != 0; pmp++) {
2467 unsigned int this_pmp = (1 << pmp);
2468 if (pmp_map & this_pmp) {
2469 struct ata_link *link = &ap->pmp_link[pmp];
2471 pmp_map &= ~this_pmp;
2472 ehi = &link->eh_info;
2473 ata_ehi_clear_desc(ehi);
2474 ata_ehi_push_desc(ehi, "dev err");
2475 ehi->err_mask |= AC_ERR_DEV;
2476 ehi->action |= ATA_EH_RESET;
2477 ata_link_abort(link);
2482 static int mv_req_q_empty(struct ata_port *ap)
2484 void __iomem *port_mmio = mv_ap_base(ap);
2485 u32 in_ptr, out_ptr;
2487 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2488 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2489 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2490 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2491 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2494 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2496 struct mv_port_priv *pp = ap->private_data;
2498 unsigned int old_map, new_map;
2501 * Device error during FBS+NCQ operation:
2503 * Set a port flag to prevent further I/O being enqueued.
2504 * Leave the EDMA running to drain outstanding commands from this port.
2505 * Perform the post-mortem/EH only when all responses are complete.
2506 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2508 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2509 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2510 pp->delayed_eh_pmp_map = 0;
2512 old_map = pp->delayed_eh_pmp_map;
2513 new_map = old_map | mv_get_err_pmp_map(ap);
2515 if (old_map != new_map) {
2516 pp->delayed_eh_pmp_map = new_map;
2517 mv_pmp_eh_prep(ap, new_map & ~old_map);
2519 failed_links = hweight16(new_map);
2522 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2523 __func__, pp->delayed_eh_pmp_map,
2524 ap->qc_active, failed_links,
2525 ap->nr_active_links);
2527 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2528 mv_process_crpb_entries(ap, pp);
2531 ata_port_info(ap, "%s: done\n", __func__);
2532 return 1; /* handled */
2534 ata_port_info(ap, "%s: waiting\n", __func__);
2535 return 1; /* handled */
2538 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2541 * Possible future enhancement:
2543 * FBS+non-NCQ operation is not yet implemented.
2544 * See related notes in mv_edma_cfg().
2546 * Device error during FBS+non-NCQ operation:
2548 * We need to snapshot the shadow registers for each failed command.
2549 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2551 return 0; /* not handled */
2554 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2556 struct mv_port_priv *pp = ap->private_data;
2558 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2559 return 0; /* EDMA was not active: not handled */
2560 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2561 return 0; /* FBS was not active: not handled */
2563 if (!(edma_err_cause & EDMA_ERR_DEV))
2564 return 0; /* non DEV error: not handled */
2565 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2566 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2567 return 0; /* other problems: not handled */
2569 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2571 * EDMA should NOT have self-disabled for this case.
2572 * If it did, then something is wrong elsewhere,
2573 * and we cannot handle it here.
2575 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2576 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2577 __func__, edma_err_cause, pp->pp_flags);
2578 return 0; /* not handled */
2580 return mv_handle_fbs_ncq_dev_err(ap);
2583 * EDMA should have self-disabled for this case.
2584 * If it did not, then something is wrong elsewhere,
2585 * and we cannot handle it here.
2587 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2588 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2589 __func__, edma_err_cause, pp->pp_flags);
2590 return 0; /* not handled */
2592 return mv_handle_fbs_non_ncq_dev_err(ap);
2594 return 0; /* not handled */
2597 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2599 struct ata_eh_info *ehi = &ap->link.eh_info;
2600 char *when = "idle";
2602 ata_ehi_clear_desc(ehi);
2603 if (edma_was_enabled) {
2604 when = "EDMA enabled";
2606 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2607 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2610 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2611 ehi->err_mask |= AC_ERR_OTHER;
2612 ehi->action |= ATA_EH_RESET;
2613 ata_port_freeze(ap);
2617 * mv_err_intr - Handle error interrupts on the port
2618 * @ap: ATA channel to manipulate
2620 * Most cases require a full reset of the chip's state machine,
2621 * which also performs a COMRESET.
2622 * Also, if the port disabled DMA, update our cached copy to match.
2625 * Inherited from caller.
2627 static void mv_err_intr(struct ata_port *ap)
2629 void __iomem *port_mmio = mv_ap_base(ap);
2630 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2632 struct mv_port_priv *pp = ap->private_data;
2633 struct mv_host_priv *hpriv = ap->host->private_data;
2634 unsigned int action = 0, err_mask = 0;
2635 struct ata_eh_info *ehi = &ap->link.eh_info;
2636 struct ata_queued_cmd *qc;
2640 * Read and clear the SError and err_cause bits.
2641 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2642 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2644 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2645 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2647 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2648 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2649 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2650 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2652 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2654 if (edma_err_cause & EDMA_ERR_DEV) {
2656 * Device errors during FIS-based switching operation
2657 * require special handling.
2659 if (mv_handle_dev_err(ap, edma_err_cause))
2663 qc = mv_get_active_qc(ap);
2664 ata_ehi_clear_desc(ehi);
2665 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2666 edma_err_cause, pp->pp_flags);
2668 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2669 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2670 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2671 u32 ec = edma_err_cause &
2672 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2673 sata_async_notification(ap);
2675 return; /* Just an AN; no need for the nukes */
2676 ata_ehi_push_desc(ehi, "SDB notify");
2680 * All generations share these EDMA error cause bits:
2682 if (edma_err_cause & EDMA_ERR_DEV) {
2683 err_mask |= AC_ERR_DEV;
2684 action |= ATA_EH_RESET;
2685 ata_ehi_push_desc(ehi, "dev error");
2687 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2688 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2689 EDMA_ERR_INTRL_PAR)) {
2690 err_mask |= AC_ERR_ATA_BUS;
2691 action |= ATA_EH_RESET;
2692 ata_ehi_push_desc(ehi, "parity error");
2694 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2695 ata_ehi_hotplugged(ehi);
2696 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2697 "dev disconnect" : "dev connect");
2698 action |= ATA_EH_RESET;
2702 * Gen-I has a different SELF_DIS bit,
2703 * different FREEZE bits, and no SERR bit:
2705 if (IS_GEN_I(hpriv)) {
2706 eh_freeze_mask = EDMA_EH_FREEZE_5;
2707 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2708 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2709 ata_ehi_push_desc(ehi, "EDMA self-disable");
2712 eh_freeze_mask = EDMA_EH_FREEZE;
2713 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2714 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2715 ata_ehi_push_desc(ehi, "EDMA self-disable");
2717 if (edma_err_cause & EDMA_ERR_SERR) {
2718 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2719 err_mask |= AC_ERR_ATA_BUS;
2720 action |= ATA_EH_RESET;
2725 err_mask = AC_ERR_OTHER;
2726 action |= ATA_EH_RESET;
2729 ehi->serror |= serr;
2730 ehi->action |= action;
2733 qc->err_mask |= err_mask;
2735 ehi->err_mask |= err_mask;
2737 if (err_mask == AC_ERR_DEV) {
2739 * Cannot do ata_port_freeze() here,
2740 * because it would kill PIO access,
2741 * which is needed for further diagnosis.
2745 } else if (edma_err_cause & eh_freeze_mask) {
2747 * Note to self: ata_port_freeze() calls ata_port_abort()
2749 ata_port_freeze(ap);
2756 ata_link_abort(qc->dev->link);
2762 static bool mv_process_crpb_response(struct ata_port *ap,
2763 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2766 u16 edma_status = le16_to_cpu(response->flags);
2769 * edma_status from a response queue entry:
2770 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2771 * MSB is saved ATA status from command completion.
2774 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2777 * Error will be seen/handled by
2778 * mv_err_intr(). So do nothing at all here.
2783 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2784 if (!ac_err_mask(ata_status))
2786 /* else: leave it for mv_err_intr() */
2790 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2792 void __iomem *port_mmio = mv_ap_base(ap);
2793 struct mv_host_priv *hpriv = ap->host->private_data;
2795 bool work_done = false;
2797 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2799 /* Get the hardware queue position index */
2800 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2801 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2803 /* Process new responses from since the last time we looked */
2804 while (in_index != pp->resp_idx) {
2806 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2808 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2810 if (IS_GEN_I(hpriv)) {
2811 /* 50xx: no NCQ, only one command active at a time */
2812 tag = ap->link.active_tag;
2814 /* Gen II/IIE: get command tag from CRPB entry */
2815 tag = le16_to_cpu(response->id) & 0x1f;
2817 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2818 done_mask |= 1 << tag;
2823 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2825 /* Update the software queue position index in hardware */
2826 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2827 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2828 port_mmio + EDMA_RSP_Q_OUT_PTR);
2832 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2834 struct mv_port_priv *pp;
2835 int edma_was_enabled;
2838 * Grab a snapshot of the EDMA_EN flag setting,
2839 * so that we have a consistent view for this port,
2840 * even if something we call of our routines changes it.
2842 pp = ap->private_data;
2843 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2845 * Process completed CRPB response(s) before other events.
2847 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2848 mv_process_crpb_entries(ap, pp);
2849 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2850 mv_handle_fbs_ncq_dev_err(ap);
2853 * Handle chip-reported errors, or continue on to handle PIO.
2855 if (unlikely(port_cause & ERR_IRQ)) {
2857 } else if (!edma_was_enabled) {
2858 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2860 ata_bmdma_port_intr(ap, qc);
2862 mv_unexpected_intr(ap, edma_was_enabled);
2867 * mv_host_intr - Handle all interrupts on the given host controller
2868 * @host: host specific structure
2869 * @main_irq_cause: Main interrupt cause register for the chip.
2872 * Inherited from caller.
2874 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2876 struct mv_host_priv *hpriv = host->private_data;
2877 void __iomem *mmio = hpriv->base, *hc_mmio;
2878 unsigned int handled = 0, port;
2880 /* If asserted, clear the "all ports" IRQ coalescing bit */
2881 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2882 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2884 for (port = 0; port < hpriv->n_ports; port++) {
2885 struct ata_port *ap = host->ports[port];
2886 unsigned int p, shift, hardport, port_cause;
2888 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2890 * Each hc within the host has its own hc_irq_cause register,
2891 * where the interrupting ports bits get ack'd.
2893 if (hardport == 0) { /* first port on this hc ? */
2894 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2895 u32 port_mask, ack_irqs;
2897 * Skip this entire hc if nothing pending for any ports
2900 port += MV_PORTS_PER_HC - 1;
2904 * We don't need/want to read the hc_irq_cause register,
2905 * because doing so hurts performance, and
2906 * main_irq_cause already gives us everything we need.
2908 * But we do have to *write* to the hc_irq_cause to ack
2909 * the ports that we are handling this time through.
2911 * This requires that we create a bitmap for those
2912 * ports which interrupted us, and use that bitmap
2913 * to ack (only) those ports via hc_irq_cause.
2916 if (hc_cause & PORTS_0_3_COAL_DONE)
2917 ack_irqs = HC_COAL_IRQ;
2918 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2919 if ((port + p) >= hpriv->n_ports)
2921 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2922 if (hc_cause & port_mask)
2923 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2925 hc_mmio = mv_hc_base_from_port(mmio, port);
2926 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2930 * Handle interrupts signalled for this port:
2932 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2934 mv_port_intr(ap, port_cause);
2939 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2941 struct mv_host_priv *hpriv = host->private_data;
2942 struct ata_port *ap;
2943 struct ata_queued_cmd *qc;
2944 struct ata_eh_info *ehi;
2945 unsigned int i, err_mask, printed = 0;
2948 err_cause = readl(mmio + hpriv->irq_cause_offset);
2950 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
2952 DPRINTK("All regs @ PCI error\n");
2953 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2955 writelfl(0, mmio + hpriv->irq_cause_offset);
2957 for (i = 0; i < host->n_ports; i++) {
2958 ap = host->ports[i];
2959 if (!ata_link_offline(&ap->link)) {
2960 ehi = &ap->link.eh_info;
2961 ata_ehi_clear_desc(ehi);
2963 ata_ehi_push_desc(ehi,
2964 "PCI err cause 0x%08x", err_cause);
2965 err_mask = AC_ERR_HOST_BUS;
2966 ehi->action = ATA_EH_RESET;
2967 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2969 qc->err_mask |= err_mask;
2971 ehi->err_mask |= err_mask;
2973 ata_port_freeze(ap);
2976 return 1; /* handled */
2980 * mv_interrupt - Main interrupt event handler
2982 * @dev_instance: private data; in this case the host structure
2984 * Read the read only register to determine if any host
2985 * controllers have pending interrupts. If so, call lower level
2986 * routine to handle. Also check for PCI errors which are only
2990 * This routine holds the host lock while processing pending
2993 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2995 struct ata_host *host = dev_instance;
2996 struct mv_host_priv *hpriv = host->private_data;
2997 unsigned int handled = 0;
2998 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2999 u32 main_irq_cause, pending_irqs;
3001 spin_lock(&host->lock);
3003 /* for MSI: block new interrupts while in here */
3005 mv_write_main_irq_mask(0, hpriv);
3007 main_irq_cause = readl(hpriv->main_irq_cause_addr);
3008 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
3010 * Deal with cases where we either have nothing pending, or have read
3011 * a bogus register value which can indicate HW removal or PCI fault.
3013 if (pending_irqs && main_irq_cause != 0xffffffffU) {
3014 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
3015 handled = mv_pci_error(host, hpriv->base);
3017 handled = mv_host_intr(host, pending_irqs);
3020 /* for MSI: unmask; interrupt cause bits will retrigger now */
3022 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
3024 spin_unlock(&host->lock);
3026 return IRQ_RETVAL(handled);
3029 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3033 switch (sc_reg_in) {
3037 ofs = sc_reg_in * sizeof(u32);
3046 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3048 struct mv_host_priv *hpriv = link->ap->host->private_data;
3049 void __iomem *mmio = hpriv->base;
3050 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3051 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3053 if (ofs != 0xffffffffU) {
3054 *val = readl(addr + ofs);
3060 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3062 struct mv_host_priv *hpriv = link->ap->host->private_data;
3063 void __iomem *mmio = hpriv->base;
3064 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3065 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3067 if (ofs != 0xffffffffU) {
3068 writelfl(val, addr + ofs);
3074 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3076 struct pci_dev *pdev = to_pci_dev(host->dev);
3079 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3082 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3084 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3087 mv_reset_pci_bus(host, mmio);
3090 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3092 writel(0x0fcfffff, mmio + FLASH_CTL);
3095 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3098 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3101 tmp = readl(phy_mmio + MV5_PHY_MODE);
3103 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3104 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3107 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3111 writel(0, mmio + GPIO_PORT_CTL);
3113 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3115 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3117 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3120 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3123 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3124 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3126 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3129 tmp = readl(phy_mmio + MV5_LTMODE);
3131 writel(tmp, phy_mmio + MV5_LTMODE);
3133 tmp = readl(phy_mmio + MV5_PHY_CTL);
3136 writel(tmp, phy_mmio + MV5_PHY_CTL);
3139 tmp = readl(phy_mmio + MV5_PHY_MODE);
3141 tmp |= hpriv->signal[port].pre;
3142 tmp |= hpriv->signal[port].amps;
3143 writel(tmp, phy_mmio + MV5_PHY_MODE);
3148 #define ZERO(reg) writel(0, port_mmio + (reg))
3149 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3152 void __iomem *port_mmio = mv_port_base(mmio, port);
3154 mv_reset_channel(hpriv, mmio, port);
3156 ZERO(0x028); /* command */
3157 writel(0x11f, port_mmio + EDMA_CFG);
3158 ZERO(0x004); /* timer */
3159 ZERO(0x008); /* irq err cause */
3160 ZERO(0x00c); /* irq err mask */
3161 ZERO(0x010); /* rq bah */
3162 ZERO(0x014); /* rq inp */
3163 ZERO(0x018); /* rq outp */
3164 ZERO(0x01c); /* respq bah */
3165 ZERO(0x024); /* respq outp */
3166 ZERO(0x020); /* respq inp */
3167 ZERO(0x02c); /* test control */
3168 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3172 #define ZERO(reg) writel(0, hc_mmio + (reg))
3173 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3176 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3184 tmp = readl(hc_mmio + 0x20);
3187 writel(tmp, hc_mmio + 0x20);
3191 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3194 unsigned int hc, port;
3196 for (hc = 0; hc < n_hc; hc++) {
3197 for (port = 0; port < MV_PORTS_PER_HC; port++)
3198 mv5_reset_hc_port(hpriv, mmio,
3199 (hc * MV_PORTS_PER_HC) + port);
3201 mv5_reset_one_hc(hpriv, mmio, hc);
3208 #define ZERO(reg) writel(0, mmio + (reg))
3209 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3211 struct mv_host_priv *hpriv = host->private_data;
3214 tmp = readl(mmio + MV_PCI_MODE);
3216 writel(tmp, mmio + MV_PCI_MODE);
3218 ZERO(MV_PCI_DISC_TIMER);
3219 ZERO(MV_PCI_MSI_TRIGGER);
3220 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3221 ZERO(MV_PCI_SERR_MASK);
3222 ZERO(hpriv->irq_cause_offset);
3223 ZERO(hpriv->irq_mask_offset);
3224 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3225 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3226 ZERO(MV_PCI_ERR_ATTRIBUTE);
3227 ZERO(MV_PCI_ERR_COMMAND);
3231 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3235 mv5_reset_flash(hpriv, mmio);
3237 tmp = readl(mmio + GPIO_PORT_CTL);
3239 tmp |= (1 << 5) | (1 << 6);
3240 writel(tmp, mmio + GPIO_PORT_CTL);
3244 * mv6_reset_hc - Perform the 6xxx global soft reset
3245 * @mmio: base address of the HBA
3247 * This routine only applies to 6xxx parts.
3250 * Inherited from caller.
3252 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3255 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3259 /* Following procedure defined in PCI "main command and status
3263 writel(t | STOP_PCI_MASTER, reg);
3265 for (i = 0; i < 1000; i++) {
3268 if (PCI_MASTER_EMPTY & t)
3271 if (!(PCI_MASTER_EMPTY & t)) {
3272 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3280 writel(t | GLOB_SFT_RST, reg);
3283 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3285 if (!(GLOB_SFT_RST & t)) {
3286 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3291 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3294 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3297 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3299 if (GLOB_SFT_RST & t) {
3300 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3307 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3310 void __iomem *port_mmio;
3313 tmp = readl(mmio + RESET_CFG);
3314 if ((tmp & (1 << 0)) == 0) {
3315 hpriv->signal[idx].amps = 0x7 << 8;
3316 hpriv->signal[idx].pre = 0x1 << 5;
3320 port_mmio = mv_port_base(mmio, idx);
3321 tmp = readl(port_mmio + PHY_MODE2);
3323 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3324 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3327 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3329 writel(0x00000060, mmio + GPIO_PORT_CTL);
3332 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3335 void __iomem *port_mmio = mv_port_base(mmio, port);
3337 u32 hp_flags = hpriv->hp_flags;
3339 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3341 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3344 if (fix_phy_mode2) {
3345 m2 = readl(port_mmio + PHY_MODE2);
3348 writel(m2, port_mmio + PHY_MODE2);
3352 m2 = readl(port_mmio + PHY_MODE2);
3353 m2 &= ~((1 << 16) | (1 << 31));
3354 writel(m2, port_mmio + PHY_MODE2);
3360 * Gen-II/IIe PHY_MODE3 errata RM#2:
3361 * Achieves better receiver noise performance than the h/w default:
3363 m3 = readl(port_mmio + PHY_MODE3);
3364 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3366 /* Guideline 88F5182 (GL# SATA-S11) */
3370 if (fix_phy_mode4) {
3371 u32 m4 = readl(port_mmio + PHY_MODE4);
3373 * Enforce reserved-bit restrictions on GenIIe devices only.
3374 * For earlier chipsets, force only the internal config field
3375 * (workaround for errata FEr SATA#10 part 1).
3377 if (IS_GEN_IIE(hpriv))
3378 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3380 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3381 writel(m4, port_mmio + PHY_MODE4);
3384 * Workaround for 60x1-B2 errata SATA#13:
3385 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3386 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3387 * Or ensure we use writelfl() when writing PHY_MODE4.
3389 writel(m3, port_mmio + PHY_MODE3);
3391 /* Revert values of pre-emphasis and signal amps to the saved ones */
3392 m2 = readl(port_mmio + PHY_MODE2);
3394 m2 &= ~MV_M2_PREAMP_MASK;
3395 m2 |= hpriv->signal[port].amps;
3396 m2 |= hpriv->signal[port].pre;
3399 /* according to mvSata 3.6.1, some IIE values are fixed */
3400 if (IS_GEN_IIE(hpriv)) {
3405 writel(m2, port_mmio + PHY_MODE2);
3408 /* TODO: use the generic LED interface to configure the SATA Presence */
3409 /* & Acitivy LEDs on the board */
3410 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3416 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3419 void __iomem *port_mmio;
3422 port_mmio = mv_port_base(mmio, idx);
3423 tmp = readl(port_mmio + PHY_MODE2);
3425 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3426 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3430 #define ZERO(reg) writel(0, port_mmio + (reg))
3431 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3432 void __iomem *mmio, unsigned int port)
3434 void __iomem *port_mmio = mv_port_base(mmio, port);
3436 mv_reset_channel(hpriv, mmio, port);
3438 ZERO(0x028); /* command */
3439 writel(0x101f, port_mmio + EDMA_CFG);
3440 ZERO(0x004); /* timer */
3441 ZERO(0x008); /* irq err cause */
3442 ZERO(0x00c); /* irq err mask */
3443 ZERO(0x010); /* rq bah */
3444 ZERO(0x014); /* rq inp */
3445 ZERO(0x018); /* rq outp */
3446 ZERO(0x01c); /* respq bah */
3447 ZERO(0x024); /* respq outp */
3448 ZERO(0x020); /* respq inp */
3449 ZERO(0x02c); /* test control */
3450 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3455 #define ZERO(reg) writel(0, hc_mmio + (reg))
3456 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3459 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3469 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3470 void __iomem *mmio, unsigned int n_hc)
3474 for (port = 0; port < hpriv->n_ports; port++)
3475 mv_soc_reset_hc_port(hpriv, mmio, port);
3477 mv_soc_reset_one_hc(hpriv, mmio);
3482 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3488 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3493 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3494 void __iomem *mmio, unsigned int port)
3496 void __iomem *port_mmio = mv_port_base(mmio, port);
3499 reg = readl(port_mmio + PHY_MODE3);
3500 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3502 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3504 writel(reg, port_mmio + PHY_MODE3);
3506 reg = readl(port_mmio + PHY_MODE4);
3507 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3509 writel(reg, port_mmio + PHY_MODE4);
3511 reg = readl(port_mmio + PHY_MODE9_GEN2);
3512 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3514 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3515 writel(reg, port_mmio + PHY_MODE9_GEN2);
3517 reg = readl(port_mmio + PHY_MODE9_GEN1);
3518 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3520 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3521 writel(reg, port_mmio + PHY_MODE9_GEN1);
3525 * soc_is_65 - check if the soc is 65 nano device
3527 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3528 * register, this register should contain non-zero value and it exists only
3529 * in the 65 nano devices, when reading it from older devices we get 0.
3531 static bool soc_is_65n(struct mv_host_priv *hpriv)
3533 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3535 if (readl(port0_mmio + PHYCFG_OFS))
3540 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3542 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3544 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3546 ifcfg |= (1 << 7); /* enable gen2i speed */
3547 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3550 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3551 unsigned int port_no)
3553 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3556 * The datasheet warns against setting EDMA_RESET when EDMA is active
3557 * (but doesn't say what the problem might be). So we first try
3558 * to disable the EDMA engine before doing the EDMA_RESET operation.
3560 mv_stop_edma_engine(port_mmio);
3561 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3563 if (!IS_GEN_I(hpriv)) {
3564 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3565 mv_setup_ifcfg(port_mmio, 1);
3568 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3569 * link, and physical layers. It resets all SATA interface registers
3570 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3572 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3573 udelay(25); /* allow reset propagation */
3574 writelfl(0, port_mmio + EDMA_CMD);
3576 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3578 if (IS_GEN_I(hpriv))
3582 static void mv_pmp_select(struct ata_port *ap, int pmp)
3584 if (sata_pmp_supported(ap)) {
3585 void __iomem *port_mmio = mv_ap_base(ap);
3586 u32 reg = readl(port_mmio + SATA_IFCTL);
3587 int old = reg & 0xf;
3590 reg = (reg & ~0xf) | pmp;
3591 writelfl(reg, port_mmio + SATA_IFCTL);
3596 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3597 unsigned long deadline)
3599 mv_pmp_select(link->ap, sata_srst_pmp(link));
3600 return sata_std_hardreset(link, class, deadline);
3603 static int mv_softreset(struct ata_link *link, unsigned int *class,
3604 unsigned long deadline)
3606 mv_pmp_select(link->ap, sata_srst_pmp(link));
3607 return ata_sff_softreset(link, class, deadline);
3610 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3611 unsigned long deadline)
3613 struct ata_port *ap = link->ap;
3614 struct mv_host_priv *hpriv = ap->host->private_data;
3615 struct mv_port_priv *pp = ap->private_data;
3616 void __iomem *mmio = hpriv->base;
3617 int rc, attempts = 0, extra = 0;
3621 mv_reset_channel(hpriv, mmio, ap->port_no);
3622 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3624 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3626 /* Workaround for errata FEr SATA#10 (part 2) */
3628 const unsigned long *timing =
3629 sata_ehc_deb_timing(&link->eh_context);
3631 rc = sata_link_hardreset(link, timing, deadline + extra,
3633 rc = online ? -EAGAIN : rc;
3636 sata_scr_read(link, SCR_STATUS, &sstatus);
3637 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3638 /* Force 1.5gb/s link speed and try again */
3639 mv_setup_ifcfg(mv_ap_base(ap), 0);
3640 if (time_after(jiffies + HZ, deadline))
3641 extra = HZ; /* only extend it once, max */
3643 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3644 mv_save_cached_regs(ap);
3645 mv_edma_cfg(ap, 0, 0);
3650 static void mv_eh_freeze(struct ata_port *ap)
3653 mv_enable_port_irqs(ap, 0);
3656 static void mv_eh_thaw(struct ata_port *ap)
3658 struct mv_host_priv *hpriv = ap->host->private_data;
3659 unsigned int port = ap->port_no;
3660 unsigned int hardport = mv_hardport_from_port(port);
3661 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3662 void __iomem *port_mmio = mv_ap_base(ap);
3665 /* clear EDMA errors on this port */
3666 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3668 /* clear pending irq events */
3669 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3670 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3672 mv_enable_port_irqs(ap, ERR_IRQ);
3676 * mv_port_init - Perform some early initialization on a single port.
3677 * @port: libata data structure storing shadow register addresses
3678 * @port_mmio: base address of the port
3680 * Initialize shadow register mmio addresses, clear outstanding
3681 * interrupts on the port, and unmask interrupts for the future
3682 * start of the port.
3685 * Inherited from caller.
3687 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3689 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3691 /* PIO related setup
3693 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3695 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3696 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3697 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3698 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3699 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3700 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3702 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3703 /* special case: control/altstatus doesn't have ATA_REG_ address */
3704 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3706 /* Clear any currently outstanding port interrupt conditions */
3707 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3708 writelfl(readl(serr), serr);
3709 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3711 /* unmask all non-transient EDMA error interrupts */
3712 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3714 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3715 readl(port_mmio + EDMA_CFG),
3716 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3717 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3720 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3722 struct mv_host_priv *hpriv = host->private_data;
3723 void __iomem *mmio = hpriv->base;
3726 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3727 return 0; /* not PCI-X capable */
3728 reg = readl(mmio + MV_PCI_MODE);
3729 if ((reg & MV_PCI_MODE_MASK) == 0)
3730 return 0; /* conventional PCI mode */
3731 return 1; /* chip is in PCI-X mode */
3734 static int mv_pci_cut_through_okay(struct ata_host *host)
3736 struct mv_host_priv *hpriv = host->private_data;
3737 void __iomem *mmio = hpriv->base;
3740 if (!mv_in_pcix_mode(host)) {
3741 reg = readl(mmio + MV_PCI_COMMAND);
3742 if (reg & MV_PCI_COMMAND_MRDTRIG)
3743 return 0; /* not okay */
3745 return 1; /* okay */
3748 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3750 struct mv_host_priv *hpriv = host->private_data;
3751 void __iomem *mmio = hpriv->base;
3753 /* workaround for 60x1-B2 errata PCI#7 */
3754 if (mv_in_pcix_mode(host)) {
3755 u32 reg = readl(mmio + MV_PCI_COMMAND);
3756 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3760 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3762 struct pci_dev *pdev = to_pci_dev(host->dev);
3763 struct mv_host_priv *hpriv = host->private_data;
3764 u32 hp_flags = hpriv->hp_flags;
3766 switch (board_idx) {
3768 hpriv->ops = &mv5xxx_ops;
3769 hp_flags |= MV_HP_GEN_I;
3771 switch (pdev->revision) {
3773 hp_flags |= MV_HP_ERRATA_50XXB0;
3776 hp_flags |= MV_HP_ERRATA_50XXB2;
3779 dev_warn(&pdev->dev,
3780 "Applying 50XXB2 workarounds to unknown rev\n");
3781 hp_flags |= MV_HP_ERRATA_50XXB2;
3788 hpriv->ops = &mv5xxx_ops;
3789 hp_flags |= MV_HP_GEN_I;
3791 switch (pdev->revision) {
3793 hp_flags |= MV_HP_ERRATA_50XXB0;
3796 hp_flags |= MV_HP_ERRATA_50XXB2;
3799 dev_warn(&pdev->dev,
3800 "Applying B2 workarounds to unknown rev\n");
3801 hp_flags |= MV_HP_ERRATA_50XXB2;
3808 hpriv->ops = &mv6xxx_ops;
3809 hp_flags |= MV_HP_GEN_II;
3811 switch (pdev->revision) {
3813 mv_60x1b2_errata_pci7(host);
3814 hp_flags |= MV_HP_ERRATA_60X1B2;
3817 hp_flags |= MV_HP_ERRATA_60X1C0;
3820 dev_warn(&pdev->dev,
3821 "Applying B2 workarounds to unknown rev\n");
3822 hp_flags |= MV_HP_ERRATA_60X1B2;
3828 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3829 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3830 (pdev->device == 0x2300 || pdev->device == 0x2310))
3833 * Highpoint RocketRAID PCIe 23xx series cards:
3835 * Unconfigured drives are treated as "Legacy"
3836 * by the BIOS, and it overwrites sector 8 with
3837 * a "Lgcy" metadata block prior to Linux boot.
3839 * Configured drives (RAID or JBOD) leave sector 8
3840 * alone, but instead overwrite a high numbered
3841 * sector for the RAID metadata. This sector can
3842 * be determined exactly, by truncating the physical
3843 * drive capacity to a nice even GB value.
3845 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3847 * Warn the user, lest they think we're just buggy.
3849 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3850 " BIOS CORRUPTS DATA on all attached drives,"
3851 " regardless of if/how they are configured."
3853 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3854 " use sectors 8-9 on \"Legacy\" drives,"
3855 " and avoid the final two gigabytes on"
3856 " all RocketRAID BIOS initialized drives.\n");
3860 hpriv->ops = &mv6xxx_ops;
3861 hp_flags |= MV_HP_GEN_IIE;
3862 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3863 hp_flags |= MV_HP_CUT_THROUGH;
3865 switch (pdev->revision) {
3866 case 0x2: /* Rev.B0: the first/only public release */
3867 hp_flags |= MV_HP_ERRATA_60X1C0;
3870 dev_warn(&pdev->dev,
3871 "Applying 60X1C0 workarounds to unknown rev\n");
3872 hp_flags |= MV_HP_ERRATA_60X1C0;
3877 if (soc_is_65n(hpriv))
3878 hpriv->ops = &mv_soc_65n_ops;
3880 hpriv->ops = &mv_soc_ops;
3881 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3882 MV_HP_ERRATA_60X1C0;
3886 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
3890 hpriv->hp_flags = hp_flags;
3891 if (hp_flags & MV_HP_PCIE) {
3892 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3893 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3894 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3896 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3897 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3898 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3905 * mv_init_host - Perform some early initialization of the host.
3906 * @host: ATA host to initialize
3908 * If possible, do an early global reset of the host. Then do
3909 * our port init and clear/unmask all/relevant host interrupts.
3912 * Inherited from caller.
3914 static int mv_init_host(struct ata_host *host)
3916 int rc = 0, n_hc, port, hc;
3917 struct mv_host_priv *hpriv = host->private_data;
3918 void __iomem *mmio = hpriv->base;
3920 rc = mv_chip_id(host, hpriv->board_idx);
3924 if (IS_SOC(hpriv)) {
3925 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3926 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3928 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3929 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3932 /* initialize shadow irq mask with register's value */
3933 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3935 /* global interrupt mask: 0 == mask everything */
3936 mv_set_main_irq_mask(host, ~0, 0);
3938 n_hc = mv_get_hc_count(host->ports[0]->flags);
3940 for (port = 0; port < host->n_ports; port++)
3941 if (hpriv->ops->read_preamp)
3942 hpriv->ops->read_preamp(hpriv, port, mmio);
3944 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3948 hpriv->ops->reset_flash(hpriv, mmio);
3949 hpriv->ops->reset_bus(host, mmio);
3950 hpriv->ops->enable_leds(hpriv, mmio);
3952 for (port = 0; port < host->n_ports; port++) {
3953 struct ata_port *ap = host->ports[port];
3954 void __iomem *port_mmio = mv_port_base(mmio, port);
3956 mv_port_init(&ap->ioaddr, port_mmio);
3959 for (hc = 0; hc < n_hc; hc++) {
3960 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3962 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3963 "(before clear)=0x%08x\n", hc,
3964 readl(hc_mmio + HC_CFG),
3965 readl(hc_mmio + HC_IRQ_CAUSE));
3967 /* Clear any currently outstanding hc interrupt conditions */
3968 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3971 if (!IS_SOC(hpriv)) {
3972 /* Clear any currently outstanding host interrupt conditions */
3973 writelfl(0, mmio + hpriv->irq_cause_offset);
3975 /* and unmask interrupt generation for host regs */
3976 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3980 * enable only global host interrupts for now.
3981 * The per-port interrupts get done later as ports are set up.
3983 mv_set_main_irq_mask(host, 0, PCI_ERR);
3984 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3985 irq_coalescing_usecs);
3990 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3992 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3994 if (!hpriv->crqb_pool)
3997 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3999 if (!hpriv->crpb_pool)
4002 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
4004 if (!hpriv->sg_tbl_pool)
4010 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
4011 const struct mbus_dram_target_info *dram)
4015 for (i = 0; i < 4; i++) {
4016 writel(0, hpriv->base + WINDOW_CTRL(i));
4017 writel(0, hpriv->base + WINDOW_BASE(i));
4020 for (i = 0; i < dram->num_cs; i++) {
4021 const struct mbus_dram_window *cs = dram->cs + i;
4023 writel(((cs->size - 1) & 0xffff0000) |
4024 (cs->mbus_attr << 8) |
4025 (dram->mbus_dram_target_id << 4) | 1,
4026 hpriv->base + WINDOW_CTRL(i));
4027 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4032 * mv_platform_probe - handle a positive probe of an soc Marvell
4034 * @pdev: platform device found
4037 * Inherited from caller.
4039 static int mv_platform_probe(struct platform_device *pdev)
4041 const struct mv_sata_platform_data *mv_platform_data;
4042 const struct mbus_dram_target_info *dram;
4043 const struct ata_port_info *ppi[] =
4044 { &mv_port_info[chip_soc], NULL };
4045 struct ata_host *host;
4046 struct mv_host_priv *hpriv;
4047 struct resource *res;
4048 int n_ports = 0, irq = 0;
4050 #if defined(CONFIG_HAVE_CLK)
4054 ata_print_version_once(&pdev->dev, DRV_VERSION);
4057 * Simple resource validation ..
4059 if (unlikely(pdev->num_resources != 2)) {
4060 dev_err(&pdev->dev, "invalid number of resources\n");
4065 * Get the register base first
4067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4072 if (pdev->dev.of_node) {
4073 of_property_read_u32(pdev->dev.of_node, "nr-ports", &n_ports);
4074 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
4076 mv_platform_data = pdev->dev.platform_data;
4077 n_ports = mv_platform_data->n_ports;
4078 irq = platform_get_irq(pdev, 0);
4081 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4082 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4084 if (!host || !hpriv)
4086 #if defined(CONFIG_HAVE_CLK)
4087 hpriv->port_clks = devm_kzalloc(&pdev->dev,
4088 sizeof(struct clk *) * n_ports,
4090 if (!hpriv->port_clks)
4093 host->private_data = hpriv;
4094 hpriv->n_ports = n_ports;
4095 hpriv->board_idx = chip_soc;
4098 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4099 resource_size(res));
4100 hpriv->base -= SATAHC0_REG_BASE;
4102 #if defined(CONFIG_HAVE_CLK)
4103 hpriv->clk = clk_get(&pdev->dev, NULL);
4104 if (IS_ERR(hpriv->clk))
4105 dev_notice(&pdev->dev, "cannot get optional clkdev\n");
4107 clk_prepare_enable(hpriv->clk);
4109 for (port = 0; port < n_ports; port++) {
4110 char port_number[16];
4111 sprintf(port_number, "%d", port);
4112 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4113 if (!IS_ERR(hpriv->port_clks[port]))
4114 clk_prepare_enable(hpriv->port_clks[port]);
4119 * (Re-)program MBUS remapping windows if we are asked to.
4121 dram = mv_mbus_dram_info();
4123 mv_conf_mbus_windows(hpriv, dram);
4125 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4130 * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
4131 * updated in the LP_PHY_CTL register.
4133 if (pdev->dev.of_node &&
4134 of_device_is_compatible(pdev->dev.of_node,
4135 "marvell,armada-370-sata"))
4136 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
4138 /* initialize adapter */
4139 rc = mv_init_host(host);
4143 dev_info(&pdev->dev, "slots %u ports %d\n",
4144 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
4146 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
4151 #if defined(CONFIG_HAVE_CLK)
4152 if (!IS_ERR(hpriv->clk)) {
4153 clk_disable_unprepare(hpriv->clk);
4154 clk_put(hpriv->clk);
4156 for (port = 0; port < n_ports; port++) {
4157 if (!IS_ERR(hpriv->port_clks[port])) {
4158 clk_disable_unprepare(hpriv->port_clks[port]);
4159 clk_put(hpriv->port_clks[port]);
4169 * mv_platform_remove - unplug a platform interface
4170 * @pdev: platform device
4172 * A platform bus SATA device has been unplugged. Perform the needed
4173 * cleanup. Also called on module unload for any active devices.
4175 static int mv_platform_remove(struct platform_device *pdev)
4177 struct ata_host *host = platform_get_drvdata(pdev);
4178 #if defined(CONFIG_HAVE_CLK)
4179 struct mv_host_priv *hpriv = host->private_data;
4182 ata_host_detach(host);
4184 #if defined(CONFIG_HAVE_CLK)
4185 if (!IS_ERR(hpriv->clk)) {
4186 clk_disable_unprepare(hpriv->clk);
4187 clk_put(hpriv->clk);
4189 for (port = 0; port < host->n_ports; port++) {
4190 if (!IS_ERR(hpriv->port_clks[port])) {
4191 clk_disable_unprepare(hpriv->port_clks[port]);
4192 clk_put(hpriv->port_clks[port]);
4200 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4202 struct ata_host *host = platform_get_drvdata(pdev);
4204 return ata_host_suspend(host, state);
4209 static int mv_platform_resume(struct platform_device *pdev)
4211 struct ata_host *host = platform_get_drvdata(pdev);
4212 const struct mbus_dram_target_info *dram;
4216 struct mv_host_priv *hpriv = host->private_data;
4219 * (Re-)program MBUS remapping windows if we are asked to.
4221 dram = mv_mbus_dram_info();
4223 mv_conf_mbus_windows(hpriv, dram);
4225 /* initialize adapter */
4226 ret = mv_init_host(host);
4228 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4231 ata_host_resume(host);
4237 #define mv_platform_suspend NULL
4238 #define mv_platform_resume NULL
4242 static struct of_device_id mv_sata_dt_ids[] = {
4243 { .compatible = "marvell,armada-370-sata", },
4244 { .compatible = "marvell,orion-sata", },
4247 MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
4250 static struct platform_driver mv_platform_driver = {
4251 .probe = mv_platform_probe,
4252 .remove = mv_platform_remove,
4253 .suspend = mv_platform_suspend,
4254 .resume = mv_platform_resume,
4257 .owner = THIS_MODULE,
4258 .of_match_table = of_match_ptr(mv_sata_dt_ids),
4264 static int mv_pci_init_one(struct pci_dev *pdev,
4265 const struct pci_device_id *ent);
4267 static int mv_pci_device_resume(struct pci_dev *pdev);
4271 static struct pci_driver mv_pci_driver = {
4273 .id_table = mv_pci_tbl,
4274 .probe = mv_pci_init_one,
4275 .remove = ata_pci_remove_one,
4277 .suspend = ata_pci_device_suspend,
4278 .resume = mv_pci_device_resume,
4283 /* move to PCI layer or libata core? */
4284 static int pci_go_64(struct pci_dev *pdev)
4288 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4289 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4291 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4294 "64-bit DMA enable failed\n");
4299 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4301 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
4304 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4307 "32-bit consistent DMA enable failed\n");
4316 * mv_print_info - Dump key info to kernel log for perusal.
4317 * @host: ATA host to print info about
4319 * FIXME: complete this.
4322 * Inherited from caller.
4324 static void mv_print_info(struct ata_host *host)
4326 struct pci_dev *pdev = to_pci_dev(host->dev);
4327 struct mv_host_priv *hpriv = host->private_data;
4329 const char *scc_s, *gen;
4331 /* Use this to determine the HW stepping of the chip so we know
4332 * what errata to workaround
4334 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4337 else if (scc == 0x01)
4342 if (IS_GEN_I(hpriv))
4344 else if (IS_GEN_II(hpriv))
4346 else if (IS_GEN_IIE(hpriv))
4351 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4352 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4353 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4357 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4358 * @pdev: PCI device found
4359 * @ent: PCI device ID entry for the matched host
4362 * Inherited from caller.
4364 static int mv_pci_init_one(struct pci_dev *pdev,
4365 const struct pci_device_id *ent)
4367 unsigned int board_idx = (unsigned int)ent->driver_data;
4368 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4369 struct ata_host *host;
4370 struct mv_host_priv *hpriv;
4371 int n_ports, port, rc;
4373 ata_print_version_once(&pdev->dev, DRV_VERSION);
4376 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4378 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4379 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4380 if (!host || !hpriv)
4382 host->private_data = hpriv;
4383 hpriv->n_ports = n_ports;
4384 hpriv->board_idx = board_idx;
4386 /* acquire resources */
4387 rc = pcim_enable_device(pdev);
4391 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4393 pcim_pin_device(pdev);
4396 host->iomap = pcim_iomap_table(pdev);
4397 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4399 rc = pci_go_64(pdev);
4403 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4407 for (port = 0; port < host->n_ports; port++) {
4408 struct ata_port *ap = host->ports[port];
4409 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4410 unsigned int offset = port_mmio - hpriv->base;
4412 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4413 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4416 /* initialize adapter */
4417 rc = mv_init_host(host);
4421 /* Enable message-switched interrupts, if requested */
4422 if (msi && pci_enable_msi(pdev) == 0)
4423 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4425 mv_dump_pci_cfg(pdev, 0x68);
4426 mv_print_info(host);
4428 pci_set_master(pdev);
4429 pci_try_set_mwi(pdev);
4430 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4431 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4435 static int mv_pci_device_resume(struct pci_dev *pdev)
4437 struct ata_host *host = pci_get_drvdata(pdev);
4440 rc = ata_pci_device_do_resume(pdev);
4444 /* initialize adapter */
4445 rc = mv_init_host(host);
4449 ata_host_resume(host);
4456 static int mv_platform_probe(struct platform_device *pdev);
4457 static int mv_platform_remove(struct platform_device *pdev);
4459 static int __init mv_init(void)
4463 rc = pci_register_driver(&mv_pci_driver);
4467 rc = platform_driver_register(&mv_platform_driver);
4471 pci_unregister_driver(&mv_pci_driver);
4476 static void __exit mv_exit(void)
4479 pci_unregister_driver(&mv_pci_driver);
4481 platform_driver_unregister(&mv_platform_driver);
4484 MODULE_AUTHOR("Brett Russ");
4485 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4486 MODULE_LICENSE("GPL");
4487 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4488 MODULE_VERSION(DRV_VERSION);
4489 MODULE_ALIAS("platform:" DRV_NAME);
4491 module_init(mv_init);
4492 module_exit(mv_exit);