2 * Calxeda Highbank AHCI SATA platform driver
3 * Copyright 2012 Calxeda, Inc.
5 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kernel.h>
20 #include <linux/gfp.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/types.h>
24 #include <linux/err.h>
26 #include <linux/spinlock.h>
27 #include <linux/device.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/platform_device.h>
31 #include <linux/libata.h>
32 #include <linux/ahci_platform.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/export.h>
36 #include <linux/gpio.h>
37 #include <linux/of_gpio.h>
41 #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
42 #define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
43 #define SERDES_CR_CTL 0x80a0
44 #define SERDES_CR_ADDR 0x80a1
45 #define SERDES_CR_DATA 0x80a2
46 #define CR_BUSY 0x0001
47 #define CR_START 0x0001
48 #define CR_WR_RDN 0x0002
49 #define CPHY_RX_INPUT_STS 0x2002
50 #define CPHY_SATA_OVERRIDE 0x4000
51 #define CPHY_OVERRIDE 0x2005
52 #define SPHY_LANE 0x100
53 #define SPHY_HALF_RATE 0x0001
54 #define CPHY_SATA_DPLL_MODE 0x0700
55 #define CPHY_SATA_DPLL_SHIFT 8
56 #define CPHY_SATA_DPLL_RESET (1 << 11)
57 #define CPHY_PHY_COUNT 6
58 #define CPHY_LANE_COUNT 4
59 #define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
61 static DEFINE_SPINLOCK(cphy_lock);
62 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
63 * sata ports to their phys and then to their lanes within the phys
65 struct phy_lane_info {
66 void __iomem *phy_base;
70 static struct phy_lane_info port_data[CPHY_PORT_COUNT];
72 static DEFINE_SPINLOCK(sgpio_lock);
79 /* can be cast as an ahci_host_priv for compatibility with most functions */
80 struct ecx_plat_data {
82 unsigned sgpio_gpio[SGPIO_PINS];
84 u32 port_to_sgpio[SGPIO_PORTS];
87 #define SGPIO_SIGNALS 3
88 #define ECX_ACTIVITY_BITS 0x300000
89 #define ECX_ACTIVITY_SHIFT 0
90 #define ECX_LOCATE_BITS 0x80000
91 #define ECX_LOCATE_SHIFT 1
92 #define ECX_FAULT_BITS 0x400000
93 #define ECX_FAULT_SHIFT 2
94 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
97 return 1 << (3 * pdata->port_to_sgpio[port] + shift);
100 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
102 if (state & ECX_ACTIVITY_BITS)
103 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
106 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
108 if (state & ECX_LOCATE_BITS)
109 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
112 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
114 if (state & ECX_FAULT_BITS)
115 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
118 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
123 * Tell the LED controller that the signal has changed by raising the clock
124 * line for 50 uS and then lowering it for 50 uS.
126 static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
128 gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1);
130 gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0);
134 static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
137 struct ahci_host_priv *hpriv = ap->host->private_data;
138 struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
139 struct ahci_port_priv *pp = ap->private_data;
142 struct ahci_em_priv *emp;
145 /* get the slot number from the message */
146 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
147 if (pmp < EM_MAX_SLOTS)
148 emp = &pp->em_priv[pmp];
152 if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
155 spin_lock_irqsave(&sgpio_lock, flags);
156 ecx_parse_sgpio(pdata, ap->port_no, state);
157 sgpio_out = pdata->sgpio_pattern;
158 gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
159 ecx_led_cycle_clock(pdata);
160 gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
162 * bit-bang out the SGPIO pattern, by consuming a bit and then
165 for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
166 gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
168 ecx_led_cycle_clock(pdata);
171 /* save off new led state for port/slot */
172 emp->led_state = state;
174 spin_unlock_irqrestore(&sgpio_lock, flags);
178 static void highbank_set_em_messages(struct device *dev,
179 struct ahci_host_priv *hpriv,
180 struct ata_port_info *pi)
182 struct device_node *np = dev->of_node;
183 struct ecx_plat_data *pdata = hpriv->plat_data;
187 for (i = 0; i < SGPIO_PINS; i++) {
188 err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i);
189 if (IS_ERR_VALUE(err))
192 pdata->sgpio_gpio[i] = err;
193 err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO");
195 pr_err("sata_highbank gpio_request %d failed: %d\n",
199 gpio_direction_output(pdata->sgpio_gpio[i], 1);
201 of_property_read_u32_array(np, "calxeda,led-order",
202 pdata->port_to_sgpio,
207 hpriv->em_buf_sz = 4;
208 hpriv->em_msg_type = EM_MSG_TYPE_LED;
209 pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
212 static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
215 u8 dev = port_data[sata_port].phy_devs;
216 spin_lock(&cphy_lock);
217 writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
218 data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
219 spin_unlock(&cphy_lock);
223 static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
225 u8 dev = port_data[sata_port].phy_devs;
226 spin_lock(&cphy_lock);
227 writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
228 writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
229 spin_unlock(&cphy_lock);
232 static void combo_phy_wait_for_ready(u8 sata_port)
234 while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
238 static u32 combo_phy_read(u8 sata_port, u32 addr)
240 combo_phy_wait_for_ready(sata_port);
241 __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
242 __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
243 combo_phy_wait_for_ready(sata_port);
244 return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
247 static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
249 combo_phy_wait_for_ready(sata_port);
250 __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
251 __combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
252 __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
255 static void highbank_cphy_disable_overrides(u8 sata_port)
257 u8 lane = port_data[sata_port].lane_mapping;
259 if (unlikely(port_data[sata_port].phy_base == NULL))
261 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
262 tmp &= ~CPHY_SATA_OVERRIDE;
263 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
266 static void cphy_override_rx_mode(u8 sata_port, u32 val)
268 u8 lane = port_data[sata_port].lane_mapping;
270 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
271 tmp &= ~CPHY_SATA_OVERRIDE;
272 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
274 tmp |= CPHY_SATA_OVERRIDE;
275 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
277 tmp &= ~CPHY_SATA_DPLL_MODE;
278 tmp |= val << CPHY_SATA_DPLL_SHIFT;
279 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
281 tmp |= CPHY_SATA_DPLL_RESET;
282 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
284 tmp &= ~CPHY_SATA_DPLL_RESET;
285 combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
290 static void highbank_cphy_override_lane(u8 sata_port)
292 u8 lane = port_data[sata_port].lane_mapping;
295 if (unlikely(port_data[sata_port].phy_base == NULL))
298 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
300 } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
301 cphy_override_rx_mode(sata_port, 3);
304 static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
306 struct device_node *sata_node = dev->of_node;
307 int phy_count = 0, phy, port = 0;
308 void __iomem *cphy_base[CPHY_PHY_COUNT];
309 struct device_node *phy_nodes[CPHY_PHY_COUNT];
310 memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
311 memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);
315 struct of_phandle_args phy_data;
316 if (of_parse_phandle_with_args(sata_node,
317 "calxeda,port-phys", "#phy-cells",
320 for (phy = 0; phy < phy_count; phy++) {
321 if (phy_nodes[phy] == phy_data.np)
324 if (phy_nodes[phy] == NULL) {
325 phy_nodes[phy] = phy_data.np;
326 cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
327 if (cphy_base[phy] == NULL) {
332 port_data[port].lane_mapping = phy_data.args[0];
333 of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
334 port_data[port].phy_devs = tmp;
335 port_data[port].phy_base = cphy_base[phy];
336 of_node_put(phy_data.np);
338 } while (port < CPHY_PORT_COUNT);
343 * The Calxeda SATA phy intermittently fails to bring up a link with Gen3
344 * Retrying the phy hard reset can work around the issue, but the drive
345 * may fail again. In less than 150 out of 15000 test runs, it took more
346 * than 10 tries for the link to be established (but never more than 35).
347 * Triple the maximum observed retry count to provide plenty of margin for
348 * rare events and to guarantee that the link is established.
350 * Also, the default 2 second time-out on a failed drive is too long in
351 * this situation. The uboot implementation of the same driver function
352 * uses a much shorter time-out period and never experiences a time out
353 * issue. Reducing the time-out to 500ms improves the responsiveness.
354 * The other timing constants were kept the same as the stock AHCI driver.
355 * This change was also tested 15000 times on 24 drives and none of them
356 * experienced a time out.
358 static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
359 unsigned long deadline)
361 static const unsigned long timing[] = { 5, 100, 500};
362 struct ata_port *ap = link->ap;
363 struct ahci_port_priv *pp = ap->private_data;
364 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
365 struct ata_taskfile tf;
371 ahci_stop_engine(ap);
373 /* clear D2H reception area to properly wait for D2H FIS */
374 ata_tf_init(link->device, &tf);
375 tf.command = ATA_BUSY;
376 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
379 highbank_cphy_disable_overrides(link->ap->port_no);
380 rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
381 highbank_cphy_override_lane(link->ap->port_no);
383 /* If the status is 1, we are connected, but the link did not
384 * come up. So retry resetting the link again.
386 if (sata_scr_read(link, SCR_STATUS, &sstatus))
388 if (!(sstatus & 0x3))
390 } while (!online && retry--);
392 ahci_start_engine(ap);
395 *class = ahci_dev_classify(ap);
400 static struct ata_port_operations ahci_highbank_ops = {
401 .inherits = &ahci_ops,
402 .hardreset = ahci_highbank_hardreset,
403 .transmit_led_message = ecx_transmit_led_message,
406 static const struct ata_port_info ahci_highbank_port_info = {
407 .flags = AHCI_FLAG_COMMON,
408 .pio_mask = ATA_PIO4,
409 .udma_mask = ATA_UDMA6,
410 .port_ops = &ahci_highbank_ops,
413 static struct scsi_host_template ahci_highbank_platform_sht = {
414 AHCI_SHT("sata_highbank"),
417 static const struct of_device_id ahci_of_match[] = {
418 { .compatible = "calxeda,hb-ahci" },
421 MODULE_DEVICE_TABLE(of, ahci_of_match);
423 static int ahci_highbank_probe(struct platform_device *pdev)
425 struct device *dev = &pdev->dev;
426 struct ahci_host_priv *hpriv;
427 struct ecx_plat_data *pdata;
428 struct ata_host *host;
429 struct resource *mem;
434 struct ata_port_info pi = ahci_highbank_port_info;
435 const struct ata_port_info *ppi[] = { &pi, NULL };
437 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
439 dev_err(dev, "no mmio space\n");
443 irq = platform_get_irq(pdev, 0);
445 dev_err(dev, "no irq\n");
449 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
451 dev_err(dev, "can't alloc ahci_host_priv\n");
454 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
456 dev_err(dev, "can't alloc ecx_plat_data\n");
460 hpriv->flags |= (unsigned long)pi.private_data;
462 hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
464 dev_err(dev, "can't map %pR\n", mem);
468 rc = highbank_initialize_phys(dev, hpriv->mmio);
473 ahci_save_initial_config(dev, hpriv, 0, 0);
476 if (hpriv->cap & HOST_CAP_NCQ)
477 pi.flags |= ATA_FLAG_NCQ;
479 if (hpriv->cap & HOST_CAP_PMP)
480 pi.flags |= ATA_FLAG_PMP;
482 /* CAP.NP sometimes indicate the index of the last enabled
483 * port, at other times, that of the last possible port, so
484 * determining the maximum port number requires looking at
485 * both CAP.NP and port_map.
487 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
489 pdata->n_ports = n_ports;
490 hpriv->plat_data = pdata;
491 highbank_set_em_messages(dev, hpriv, &pi);
493 host = ata_host_alloc_pinfo(dev, ppi, n_ports);
499 host->private_data = hpriv;
501 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
502 host->flags |= ATA_HOST_PARALLEL_SCAN;
504 for (i = 0; i < host->n_ports; i++) {
505 struct ata_port *ap = host->ports[i];
507 ata_port_desc(ap, "mmio %pR", mem);
508 ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
510 /* set enclosure management message type */
511 if (ap->flags & ATA_FLAG_EM)
512 ap->em_message_type = hpriv->em_msg_type;
514 /* disabled/not-implemented port */
515 if (!(hpriv->port_map & (1 << i)))
516 ap->ops = &ata_dummy_port_ops;
519 rc = ahci_reset_controller(host);
523 ahci_init_controller(host);
524 ahci_print_info(host, "platform");
526 rc = ata_host_activate(host, irq, ahci_interrupt, 0,
527 &ahci_highbank_platform_sht);
536 #ifdef CONFIG_PM_SLEEP
537 static int ahci_highbank_suspend(struct device *dev)
539 struct ata_host *host = dev_get_drvdata(dev);
540 struct ahci_host_priv *hpriv = host->private_data;
541 void __iomem *mmio = hpriv->mmio;
545 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
546 dev_err(dev, "firmware update required for suspend/resume\n");
551 * AHCI spec rev1.1 section 8.3.3:
552 * Software must disable interrupts prior to requesting a
553 * transition of the HBA to D3 state.
555 ctl = readl(mmio + HOST_CTL);
557 writel(ctl, mmio + HOST_CTL);
558 readl(mmio + HOST_CTL); /* flush */
560 rc = ata_host_suspend(host, PMSG_SUSPEND);
567 static int ahci_highbank_resume(struct device *dev)
569 struct ata_host *host = dev_get_drvdata(dev);
572 if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
573 rc = ahci_reset_controller(host);
577 ahci_init_controller(host);
580 ata_host_resume(host);
586 static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
587 ahci_highbank_suspend, ahci_highbank_resume);
589 static struct platform_driver ahci_highbank_driver = {
590 .remove = ata_platform_remove_one,
592 .name = "highbank-ahci",
593 .owner = THIS_MODULE,
594 .of_match_table = ahci_of_match,
595 .pm = &ahci_highbank_pm_ops,
597 .probe = ahci_highbank_probe,
600 module_platform_driver(ahci_highbank_driver);
602 MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
603 MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
604 MODULE_LICENSE("GPL");
605 MODULE_ALIAS("sata:highbank");