2 * pata_cmd64x.c - CMD64x PATA for new ATA layer
4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
6 * (C) 2012 MontaVista Software, LLC <source@mvista.com>
9 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
11 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
12 * Note, this driver is not used at all on other systems because
13 * there the "BIOS" has done all of the following already.
14 * Due to massive hardware bugs, UltraDMA is only supported
15 * on the 646U2 and not on the 646U.
17 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
18 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
20 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
34 #define DRV_NAME "pata_cmd64x"
35 #define DRV_VERSION "0.2.18"
38 * CMD64x specific registers definition.
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
61 MRDMODE_INTR_CH0 = 0x04,
62 MRDMODE_INTR_CH1 = 0x08,
72 static int cmd648_cable_detect(struct ata_port *ap)
74 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
77 /* Check cable detect bits */
78 pci_read_config_byte(pdev, BMIDECSR, &r);
79 if (r & (1 << ap->port_no))
80 return ATA_CBL_PATA80;
81 return ATA_CBL_PATA40;
85 * cmd64x_set_timing - set PIO and MWDMA timing
90 * Called to do the PIO and MWDMA mode setup.
93 static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
95 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
97 const unsigned long T = 1000000 / 33;
98 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
102 /* Port layout is not logical so use a table */
103 const u8 arttim_port[2][2] = {
104 { ARTTIM0, ARTTIM1 },
105 { ARTTIM23, ARTTIM23 }
107 const u8 drwtim_port[2][2] = {
108 { DRWTIM0, DRWTIM1 },
112 int arttim = arttim_port[ap->port_no][adev->devno];
113 int drwtim = drwtim_port[ap->port_no][adev->devno];
115 /* ata_timing_compute is smart and will produce timings for MWDMA
116 that don't violate the drives PIO capabilities. */
117 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
118 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
122 /* Slave has shared address setup */
123 struct ata_device *pair = ata_dev_pair(adev);
126 struct ata_timing tp;
127 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
128 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
132 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
133 t.active, t.recover, t.setup);
134 if (t.recover > 16) {
135 t.active += t.recover - 16;
141 /* Now convert the clocks into values we can actually stuff into
146 else if (t.recover > 1)
154 t.setup = setup_data[t.setup];
156 t.active &= 0x0F; /* 0 = 16 */
158 /* Load setup timing */
159 pci_read_config_byte(pdev, arttim, ®);
162 pci_write_config_byte(pdev, arttim, reg);
164 /* Load active/recovery */
165 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
169 * cmd64x_set_piomode - set initial PIO mode data
173 * Used when configuring the devices ot set the PIO timings. All the
174 * actual work is done by the PIO/MWDMA setting helper
177 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
179 cmd64x_set_timing(ap, adev, adev->pio_mode);
183 * cmd64x_set_dmamode - set initial DMA mode data
187 * Called to do the DMA mode setup.
190 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
192 static const u8 udma_data[] = {
193 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
196 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
199 int pciU = UDIDETCR0 + 8 * ap->port_no;
200 int pciD = BMIDESR0 + 8 * ap->port_no;
201 int shift = 2 * adev->devno;
203 pci_read_config_byte(pdev, pciD, ®D);
204 pci_read_config_byte(pdev, pciU, ®U);
207 regD &= ~(0x20 << adev->devno);
208 /* DMA control bits */
209 regU &= ~(0x30 << shift);
210 /* DMA timing bits */
211 regU &= ~(0x05 << adev->devno);
213 if (adev->dma_mode >= XFER_UDMA_0) {
214 /* Merge the timing value */
215 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
216 /* Merge the control bits */
217 regU |= 1 << adev->devno; /* UDMA on */
218 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
219 regU |= 4 << adev->devno;
221 regU &= ~ (1 << adev->devno); /* UDMA off */
222 cmd64x_set_timing(ap, adev, adev->dma_mode);
225 regD |= 0x20 << adev->devno;
227 pci_write_config_byte(pdev, pciU, regU);
228 pci_write_config_byte(pdev, pciD, regD);
232 * cmd64x_sff_irq_check - check IDE interrupt
235 * Check IDE interrupt in CFR/ARTTIM23 registers.
238 static bool cmd64x_sff_irq_check(struct ata_port *ap)
240 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
241 int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
242 int irq_reg = ap->port_no ? ARTTIM23 : CFR;
245 /* NOTE: reading the register should clear the interrupt */
246 pci_read_config_byte(pdev, irq_reg, &irq_stat);
248 return irq_stat & irq_mask;
252 * cmd64x_sff_irq_clear - clear IDE interrupt
255 * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
258 static void cmd64x_sff_irq_clear(struct ata_port *ap)
260 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
261 int irq_reg = ap->port_no ? ARTTIM23 : CFR;
264 ata_bmdma_irq_clear(ap);
266 /* Reading the register should be enough to clear the interrupt */
267 pci_read_config_byte(pdev, irq_reg, &irq_stat);
271 * cmd648_sff_irq_check - check IDE interrupt
274 * Check IDE interrupt in MRDMODE register.
277 static bool cmd648_sff_irq_check(struct ata_port *ap)
279 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
280 unsigned long base = pci_resource_start(pdev, 4);
281 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
282 u8 mrdmode = inb(base + 1);
284 return mrdmode & irq_mask;
288 * cmd648_sff_irq_clear - clear IDE interrupt
291 * Clear IDE interrupt in MRDMODE and DMA status registers.
294 static void cmd648_sff_irq_clear(struct ata_port *ap)
296 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
297 unsigned long base = pci_resource_start(pdev, 4);
298 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
301 ata_bmdma_irq_clear(ap);
303 /* Clear this port's interrupt bit (leaving the other port alone) */
304 mrdmode = inb(base + 1);
305 mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
306 outb(mrdmode | irq_mask, base + 1);
310 * cmd646r1_bmdma_stop - DMA stop callback
311 * @qc: Command in progress
313 * Stub for now while investigating the r1 quirk in the old driver.
316 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
321 static struct scsi_host_template cmd64x_sht = {
322 ATA_BMDMA_SHT(DRV_NAME),
325 static const struct ata_port_operations cmd64x_base_ops = {
326 .inherits = &ata_bmdma_port_ops,
327 .set_piomode = cmd64x_set_piomode,
328 .set_dmamode = cmd64x_set_dmamode,
331 static struct ata_port_operations cmd64x_port_ops = {
332 .inherits = &cmd64x_base_ops,
333 .sff_irq_check = cmd64x_sff_irq_check,
334 .sff_irq_clear = cmd64x_sff_irq_clear,
335 .cable_detect = ata_cable_40wire,
338 static struct ata_port_operations cmd646r1_port_ops = {
339 .inherits = &cmd64x_base_ops,
340 .sff_irq_check = cmd64x_sff_irq_check,
341 .sff_irq_clear = cmd64x_sff_irq_clear,
342 .bmdma_stop = cmd646r1_bmdma_stop,
343 .cable_detect = ata_cable_40wire,
346 static struct ata_port_operations cmd646r3_port_ops = {
347 .inherits = &cmd64x_base_ops,
348 .sff_irq_check = cmd648_sff_irq_check,
349 .sff_irq_clear = cmd648_sff_irq_clear,
350 .cable_detect = ata_cable_40wire,
353 static struct ata_port_operations cmd648_port_ops = {
354 .inherits = &cmd64x_base_ops,
355 .sff_irq_check = cmd648_sff_irq_check,
356 .sff_irq_clear = cmd648_sff_irq_clear,
357 .cable_detect = cmd648_cable_detect,
360 static void cmd64x_fixup(struct pci_dev *pdev)
364 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
365 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
366 mrdmode &= ~0x30; /* IRQ set up */
367 mrdmode |= 0x02; /* Memory read line enable */
368 pci_write_config_byte(pdev, MRDMODE, mrdmode);
370 /* PPC specific fixup copied from old driver */
372 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
376 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
378 static const struct ata_port_info cmd_info[7] = {
379 { /* CMD 643 - no UDMA */
380 .flags = ATA_FLAG_SLAVE_POSS,
381 .pio_mask = ATA_PIO4,
382 .mwdma_mask = ATA_MWDMA2,
383 .port_ops = &cmd64x_port_ops
385 { /* CMD 646 with broken UDMA */
386 .flags = ATA_FLAG_SLAVE_POSS,
387 .pio_mask = ATA_PIO4,
388 .mwdma_mask = ATA_MWDMA2,
389 .port_ops = &cmd64x_port_ops
391 { /* CMD 646U with broken UDMA */
392 .flags = ATA_FLAG_SLAVE_POSS,
393 .pio_mask = ATA_PIO4,
394 .mwdma_mask = ATA_MWDMA2,
395 .port_ops = &cmd646r3_port_ops
397 { /* CMD 646U2 with working UDMA */
398 .flags = ATA_FLAG_SLAVE_POSS,
399 .pio_mask = ATA_PIO4,
400 .mwdma_mask = ATA_MWDMA2,
401 .udma_mask = ATA_UDMA2,
402 .port_ops = &cmd646r3_port_ops
404 { /* CMD 646 rev 1 */
405 .flags = ATA_FLAG_SLAVE_POSS,
406 .pio_mask = ATA_PIO4,
407 .mwdma_mask = ATA_MWDMA2,
408 .port_ops = &cmd646r1_port_ops
411 .flags = ATA_FLAG_SLAVE_POSS,
412 .pio_mask = ATA_PIO4,
413 .mwdma_mask = ATA_MWDMA2,
414 .udma_mask = ATA_UDMA4,
415 .port_ops = &cmd648_port_ops
418 .flags = ATA_FLAG_SLAVE_POSS,
419 .pio_mask = ATA_PIO4,
420 .mwdma_mask = ATA_MWDMA2,
421 .udma_mask = ATA_UDMA5,
422 .port_ops = &cmd648_port_ops
425 const struct ata_port_info *ppi[] = {
426 &cmd_info[id->driver_data],
427 &cmd_info[id->driver_data],
432 struct pci_dev *bridge = pdev->bus->self;
433 /* mobility split bridges don't report enabled ports correctly */
434 int port_ok = !(bridge && bridge->vendor ==
435 PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
436 /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
437 int cntrl_ch0_ok = (id->driver_data != 0);
439 rc = pcim_enable_device(pdev);
443 if (id->driver_data == 0) /* 643 */
444 ata_pci_bmdma_clear_simplex(pdev);
446 if (pdev->device == PCI_DEVICE_ID_CMD_646)
447 switch (pdev->revision) {
448 /* UDMA works since rev 5 */
450 ppi[0] = &cmd_info[3];
451 ppi[1] = &cmd_info[3];
453 /* Interrupts in MRDMODE since rev 3 */
456 ppi[0] = &cmd_info[2];
457 ppi[1] = &cmd_info[2];
459 /* Rev 1 with other problems? */
461 ppi[0] = &cmd_info[4];
462 ppi[1] = &cmd_info[4];
464 /* Early revs have no CNTRL_CH0 */
473 /* check for enabled ports */
474 pci_read_config_byte(pdev, CNTRL, ®);
476 dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
477 if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
478 dev_notice(&pdev->dev, "Primary port is disabled\n");
479 ppi[0] = &ata_dummy_port_info;
482 if (port_ok && !(reg & CNTRL_CH1)) {
483 dev_notice(&pdev->dev, "Secondary port is disabled\n");
484 ppi[1] = &ata_dummy_port_info;
487 return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
490 #ifdef CONFIG_PM_SLEEP
491 static int cmd64x_reinit_one(struct pci_dev *pdev)
493 struct ata_host *host = pci_get_drvdata(pdev);
496 rc = ata_pci_device_do_resume(pdev);
502 ata_host_resume(host);
507 static const struct pci_device_id cmd64x[] = {
508 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
509 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
510 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
511 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
516 static struct pci_driver cmd64x_pci_driver = {
519 .probe = cmd64x_init_one,
520 .remove = ata_pci_remove_one,
521 #ifdef CONFIG_PM_SLEEP
522 .suspend = ata_pci_device_suspend,
523 .resume = cmd64x_reinit_one,
527 module_pci_driver(cmd64x_pci_driver);
529 MODULE_AUTHOR("Alan Cox");
530 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
531 MODULE_LICENSE("GPL");
532 MODULE_DEVICE_TABLE(pci, cmd64x);
533 MODULE_VERSION(DRV_VERSION);