2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
49 static int ahci_skip_host_reset;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72 static int ahci_port_start(struct ata_port *ap);
73 static void ahci_port_stop(struct ata_port *ap);
74 static void ahci_qc_prep(struct ata_queued_cmd *qc);
75 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76 static void ahci_freeze(struct ata_port *ap);
77 static void ahci_thaw(struct ata_port *ap);
78 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static void ahci_dev_config(struct ata_device *dev);
93 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96 static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98 static void ahci_init_sw_activity(struct ata_link *link);
100 static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
113 static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
122 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
133 &dev_attr_em_message_supported,
136 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
138 struct device_attribute *ahci_sdev_attrs[] = {
139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
143 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
145 struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
153 .freeze = ahci_freeze,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
168 .set_lpm = ahci_set_lpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 .transmit_led_message = ahci_transmit_led_message,
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
181 EXPORT_SYMBOL_GPL(ahci_ops);
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
189 static bool ahci_em_messages __read_mostly = true;
190 EXPORT_SYMBOL_GPL(ahci_em_messages);
191 module_param(ahci_em_messages, bool, 0444);
192 /* add other LED protocol types when they become supported */
193 MODULE_PARM_DESC(ahci_em_messages,
194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
196 /* device sleep idle timeout in ms */
197 static int devslp_idle_timeout __read_mostly = 1000;
198 module_param(devslp_idle_timeout, int, 0644);
199 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
201 static void ahci_enable_ahci(void __iomem *mmio)
206 /* turn on AHCI_EN */
207 tmp = readl(mmio + HOST_CTL);
208 if (tmp & HOST_AHCI_EN)
211 /* Some controllers need AHCI_EN to be written multiple times.
212 * Try a few times before giving up.
214 for (i = 0; i < 5; i++) {
216 writel(tmp, mmio + HOST_CTL);
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
218 if (tmp & HOST_AHCI_EN)
226 static ssize_t ahci_show_host_caps(struct device *dev,
227 struct device_attribute *attr, char *buf)
229 struct Scsi_Host *shost = class_to_shost(dev);
230 struct ata_port *ap = ata_shost_to_port(shost);
231 struct ahci_host_priv *hpriv = ap->host->private_data;
233 return sprintf(buf, "%x\n", hpriv->cap);
236 static ssize_t ahci_show_host_cap2(struct device *dev,
237 struct device_attribute *attr, char *buf)
239 struct Scsi_Host *shost = class_to_shost(dev);
240 struct ata_port *ap = ata_shost_to_port(shost);
241 struct ahci_host_priv *hpriv = ap->host->private_data;
243 return sprintf(buf, "%x\n", hpriv->cap2);
246 static ssize_t ahci_show_host_version(struct device *dev,
247 struct device_attribute *attr, char *buf)
249 struct Scsi_Host *shost = class_to_shost(dev);
250 struct ata_port *ap = ata_shost_to_port(shost);
251 struct ahci_host_priv *hpriv = ap->host->private_data;
252 void __iomem *mmio = hpriv->mmio;
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
257 static ssize_t ahci_show_port_cmd(struct device *dev,
258 struct device_attribute *attr, char *buf)
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 void __iomem *port_mmio = ahci_port_base(ap);
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
267 static ssize_t ahci_read_em_buffer(struct device *dev,
268 struct device_attribute *attr, char *buf)
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273 void __iomem *mmio = hpriv->mmio;
274 void __iomem *em_mmio = mmio + hpriv->em_loc;
280 spin_lock_irqsave(ap->lock, flags);
282 em_ctl = readl(mmio + HOST_EM_CTL);
283 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
284 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
285 spin_unlock_irqrestore(ap->lock, flags);
289 if (!(em_ctl & EM_CTL_MR)) {
290 spin_unlock_irqrestore(ap->lock, flags);
294 if (!(em_ctl & EM_CTL_SMB))
295 em_mmio += hpriv->em_buf_sz;
297 count = hpriv->em_buf_sz;
299 /* the count should not be larger than PAGE_SIZE */
300 if (count > PAGE_SIZE) {
301 if (printk_ratelimit())
303 "EM read buffer size too large: "
304 "buffer size %u, page size %lu\n",
305 hpriv->em_buf_sz, PAGE_SIZE);
309 for (i = 0; i < count; i += 4) {
310 msg = readl(em_mmio + i);
312 buf[i + 1] = (msg >> 8) & 0xff;
313 buf[i + 2] = (msg >> 16) & 0xff;
314 buf[i + 3] = (msg >> 24) & 0xff;
317 spin_unlock_irqrestore(ap->lock, flags);
322 static ssize_t ahci_store_em_buffer(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf, size_t size)
326 struct Scsi_Host *shost = class_to_shost(dev);
327 struct ata_port *ap = ata_shost_to_port(shost);
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 void __iomem *mmio = hpriv->mmio;
330 void __iomem *em_mmio = mmio + hpriv->em_loc;
331 const unsigned char *msg_buf = buf;
336 /* check size validity */
337 if (!(ap->flags & ATA_FLAG_EM) ||
338 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
339 size % 4 || size > hpriv->em_buf_sz)
342 spin_lock_irqsave(ap->lock, flags);
344 em_ctl = readl(mmio + HOST_EM_CTL);
345 if (em_ctl & EM_CTL_TM) {
346 spin_unlock_irqrestore(ap->lock, flags);
350 for (i = 0; i < size; i += 4) {
351 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
352 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
353 writel(msg, em_mmio + i);
356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
358 spin_unlock_irqrestore(ap->lock, flags);
363 static ssize_t ahci_show_em_supported(struct device *dev,
364 struct device_attribute *attr, char *buf)
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
372 em_ctl = readl(mmio + HOST_EM_CTL);
374 return sprintf(buf, "%s%s%s%s\n",
375 em_ctl & EM_CTL_LED ? "led " : "",
376 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
377 em_ctl & EM_CTL_SES ? "ses-2 " : "",
378 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values
386 * Some registers containing configuration info might be setup by
387 * BIOS and might be cleared on reset. This function saves the
388 * initial values of those registers into @hpriv such that they
389 * can be restored after controller reset.
391 * If inconsistent, config values are fixed up by this function.
393 * If it is not set already this function sets hpriv->start_engine to
399 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
401 void __iomem *mmio = hpriv->mmio;
402 u32 cap, cap2, vers, port_map;
405 /* make sure AHCI mode is enabled before accessing CAP */
406 ahci_enable_ahci(mmio);
408 /* Values prefixed with saved_ are written back to host after
409 * reset. Values without are used for driver operation.
411 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
412 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
414 /* CAP2 register is only defined for AHCI 1.2 and later */
415 vers = readl(mmio + HOST_VERSION);
416 if ((vers >> 16) > 1 ||
417 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
418 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
420 hpriv->saved_cap2 = cap2 = 0;
422 /* some chips have errata preventing 64bit use */
423 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
424 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
428 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
429 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
430 cap &= ~HOST_CAP_NCQ;
433 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
434 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
438 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
439 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
440 cap &= ~HOST_CAP_PMP;
443 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
445 "controller can't do SNTF, turning off CAP_SNTF\n");
446 cap &= ~HOST_CAP_SNTF;
449 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
451 "controller can't do DEVSLP, turning off\n");
452 cap2 &= ~HOST_CAP2_SDS;
453 cap2 &= ~HOST_CAP2_SADM;
456 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
457 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
461 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
462 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
463 cap &= ~HOST_CAP_FBS;
466 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
467 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
468 port_map, hpriv->force_port_map);
469 port_map = hpriv->force_port_map;
470 hpriv->saved_port_map = port_map;
473 if (hpriv->mask_port_map) {
474 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
476 port_map & hpriv->mask_port_map);
477 port_map &= hpriv->mask_port_map;
480 /* cross check port_map and cap.n_ports */
484 for (i = 0; i < AHCI_MAX_PORTS; i++)
485 if (port_map & (1 << i))
488 /* If PI has more ports than n_ports, whine, clear
489 * port_map and let it be generated from n_ports.
491 if (map_ports > ahci_nr_ports(cap)) {
493 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
494 port_map, ahci_nr_ports(cap));
499 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
500 if (!port_map && vers < 0x10300) {
501 port_map = (1 << ahci_nr_ports(cap)) - 1;
502 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
504 /* write the fixed up value to the PI register */
505 hpriv->saved_port_map = port_map;
508 /* record values to use during operation */
511 hpriv->port_map = port_map;
513 if (!hpriv->start_engine)
514 hpriv->start_engine = ahci_start_engine;
516 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
519 * ahci_restore_initial_config - Restore initial config
520 * @host: target ATA host
522 * Restore initial config stored by ahci_save_initial_config().
527 static void ahci_restore_initial_config(struct ata_host *host)
529 struct ahci_host_priv *hpriv = host->private_data;
530 void __iomem *mmio = hpriv->mmio;
532 writel(hpriv->saved_cap, mmio + HOST_CAP);
533 if (hpriv->saved_cap2)
534 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
535 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
536 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
539 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
541 static const int offset[] = {
542 [SCR_STATUS] = PORT_SCR_STAT,
543 [SCR_CONTROL] = PORT_SCR_CTL,
544 [SCR_ERROR] = PORT_SCR_ERR,
545 [SCR_ACTIVE] = PORT_SCR_ACT,
546 [SCR_NOTIFICATION] = PORT_SCR_NTF,
548 struct ahci_host_priv *hpriv = ap->host->private_data;
550 if (sc_reg < ARRAY_SIZE(offset) &&
551 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
552 return offset[sc_reg];
556 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
558 void __iomem *port_mmio = ahci_port_base(link->ap);
559 int offset = ahci_scr_offset(link->ap, sc_reg);
562 *val = readl(port_mmio + offset);
568 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
570 void __iomem *port_mmio = ahci_port_base(link->ap);
571 int offset = ahci_scr_offset(link->ap, sc_reg);
574 writel(val, port_mmio + offset);
580 void ahci_start_engine(struct ata_port *ap)
582 void __iomem *port_mmio = ahci_port_base(ap);
586 tmp = readl(port_mmio + PORT_CMD);
587 tmp |= PORT_CMD_START;
588 writel(tmp, port_mmio + PORT_CMD);
589 readl(port_mmio + PORT_CMD); /* flush */
591 EXPORT_SYMBOL_GPL(ahci_start_engine);
593 int ahci_stop_engine(struct ata_port *ap)
595 void __iomem *port_mmio = ahci_port_base(ap);
598 tmp = readl(port_mmio + PORT_CMD);
600 /* check if the HBA is idle */
601 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
604 /* setting HBA to idle */
605 tmp &= ~PORT_CMD_START;
606 writel(tmp, port_mmio + PORT_CMD);
608 /* wait for engine to stop. This could be as long as 500 msec */
609 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
610 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
611 if (tmp & PORT_CMD_LIST_ON)
616 EXPORT_SYMBOL_GPL(ahci_stop_engine);
618 void ahci_start_fis_rx(struct ata_port *ap)
620 void __iomem *port_mmio = ahci_port_base(ap);
621 struct ahci_host_priv *hpriv = ap->host->private_data;
622 struct ahci_port_priv *pp = ap->private_data;
625 /* set FIS registers */
626 if (hpriv->cap & HOST_CAP_64)
627 writel((pp->cmd_slot_dma >> 16) >> 16,
628 port_mmio + PORT_LST_ADDR_HI);
629 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
631 if (hpriv->cap & HOST_CAP_64)
632 writel((pp->rx_fis_dma >> 16) >> 16,
633 port_mmio + PORT_FIS_ADDR_HI);
634 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
636 /* enable FIS reception */
637 tmp = readl(port_mmio + PORT_CMD);
638 tmp |= PORT_CMD_FIS_RX;
639 writel(tmp, port_mmio + PORT_CMD);
642 readl(port_mmio + PORT_CMD);
644 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
646 static int ahci_stop_fis_rx(struct ata_port *ap)
648 void __iomem *port_mmio = ahci_port_base(ap);
651 /* disable FIS reception */
652 tmp = readl(port_mmio + PORT_CMD);
653 tmp &= ~PORT_CMD_FIS_RX;
654 writel(tmp, port_mmio + PORT_CMD);
656 /* wait for completion, spec says 500ms, give it 1000 */
657 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
658 PORT_CMD_FIS_ON, 10, 1000);
659 if (tmp & PORT_CMD_FIS_ON)
665 static void ahci_power_up(struct ata_port *ap)
667 struct ahci_host_priv *hpriv = ap->host->private_data;
668 void __iomem *port_mmio = ahci_port_base(ap);
671 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
674 if (hpriv->cap & HOST_CAP_SSS) {
675 cmd |= PORT_CMD_SPIN_UP;
676 writel(cmd, port_mmio + PORT_CMD);
680 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
683 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
686 struct ata_port *ap = link->ap;
687 struct ahci_host_priv *hpriv = ap->host->private_data;
688 struct ahci_port_priv *pp = ap->private_data;
689 void __iomem *port_mmio = ahci_port_base(ap);
691 if (policy != ATA_LPM_MAX_POWER) {
693 * Disable interrupts on Phy Ready. This keeps us from
694 * getting woken up due to spurious phy ready
697 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
698 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
700 sata_link_scr_lpm(link, policy, false);
703 if (hpriv->cap & HOST_CAP_ALPM) {
704 u32 cmd = readl(port_mmio + PORT_CMD);
706 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
707 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
708 cmd |= PORT_CMD_ICC_ACTIVE;
710 writel(cmd, port_mmio + PORT_CMD);
711 readl(port_mmio + PORT_CMD);
713 /* wait 10ms to be sure we've come out of LPM state */
716 cmd |= PORT_CMD_ALPE;
717 if (policy == ATA_LPM_MIN_POWER)
720 /* write out new cmd value */
721 writel(cmd, port_mmio + PORT_CMD);
725 /* set aggressive device sleep */
726 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
727 (hpriv->cap2 & HOST_CAP2_SADM) &&
728 (link->device->flags & ATA_DFLAG_DEVSLP)) {
729 if (policy == ATA_LPM_MIN_POWER)
730 ahci_set_aggressive_devslp(ap, true);
732 ahci_set_aggressive_devslp(ap, false);
735 if (policy == ATA_LPM_MAX_POWER) {
736 sata_link_scr_lpm(link, policy, false);
738 /* turn PHYRDY IRQ back on */
739 pp->intr_mask |= PORT_IRQ_PHYRDY;
740 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
747 static void ahci_power_down(struct ata_port *ap)
749 struct ahci_host_priv *hpriv = ap->host->private_data;
750 void __iomem *port_mmio = ahci_port_base(ap);
753 if (!(hpriv->cap & HOST_CAP_SSS))
756 /* put device into listen mode, first set PxSCTL.DET to 0 */
757 scontrol = readl(port_mmio + PORT_SCR_CTL);
759 writel(scontrol, port_mmio + PORT_SCR_CTL);
761 /* then set PxCMD.SUD to 0 */
762 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
763 cmd &= ~PORT_CMD_SPIN_UP;
764 writel(cmd, port_mmio + PORT_CMD);
768 static void ahci_start_port(struct ata_port *ap)
770 struct ahci_host_priv *hpriv = ap->host->private_data;
771 struct ahci_port_priv *pp = ap->private_data;
772 struct ata_link *link;
773 struct ahci_em_priv *emp;
777 /* enable FIS reception */
778 ahci_start_fis_rx(ap);
781 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
782 hpriv->start_engine(ap);
785 if (ap->flags & ATA_FLAG_EM) {
786 ata_for_each_link(link, ap, EDGE) {
787 emp = &pp->em_priv[link->pmp];
789 /* EM Transmit bit maybe busy during init */
790 for (i = 0; i < EM_MAX_RETRY; i++) {
791 rc = ap->ops->transmit_led_message(ap,
795 * If busy, give a breather but do not
796 * release EH ownership by using msleep()
797 * instead of ata_msleep(). EM Transmit
798 * bit is busy for the whole host and
799 * releasing ownership will cause other
800 * ports to fail the same way.
810 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
811 ata_for_each_link(link, ap, EDGE)
812 ahci_init_sw_activity(link);
816 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
821 rc = ahci_stop_engine(ap);
823 *emsg = "failed to stop engine";
827 /* disable FIS reception */
828 rc = ahci_stop_fis_rx(ap);
830 *emsg = "failed stop FIS RX";
837 int ahci_reset_controller(struct ata_host *host)
839 struct ahci_host_priv *hpriv = host->private_data;
840 void __iomem *mmio = hpriv->mmio;
843 /* we must be in AHCI mode, before using anything
844 * AHCI-specific, such as HOST_RESET.
846 ahci_enable_ahci(mmio);
848 /* global controller reset */
849 if (!ahci_skip_host_reset) {
850 tmp = readl(mmio + HOST_CTL);
851 if ((tmp & HOST_RESET) == 0) {
852 writel(tmp | HOST_RESET, mmio + HOST_CTL);
853 readl(mmio + HOST_CTL); /* flush */
857 * to perform host reset, OS should set HOST_RESET
858 * and poll until this bit is read to be "0".
859 * reset must complete within 1 second, or
860 * the hardware should be considered fried.
862 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
863 HOST_RESET, 10, 1000);
865 if (tmp & HOST_RESET) {
866 dev_err(host->dev, "controller reset failed (0x%x)\n",
871 /* turn on AHCI mode */
872 ahci_enable_ahci(mmio);
874 /* Some registers might be cleared on reset. Restore
877 ahci_restore_initial_config(host);
879 dev_info(host->dev, "skipping global host reset\n");
883 EXPORT_SYMBOL_GPL(ahci_reset_controller);
885 static void ahci_sw_activity(struct ata_link *link)
887 struct ata_port *ap = link->ap;
888 struct ahci_port_priv *pp = ap->private_data;
889 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
891 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
895 if (!timer_pending(&emp->timer))
896 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
899 static void ahci_sw_activity_blink(unsigned long arg)
901 struct ata_link *link = (struct ata_link *)arg;
902 struct ata_port *ap = link->ap;
903 struct ahci_port_priv *pp = ap->private_data;
904 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
905 unsigned long led_message = emp->led_state;
906 u32 activity_led_state;
909 led_message &= EM_MSG_LED_VALUE;
910 led_message |= ap->port_no | (link->pmp << 8);
912 /* check to see if we've had activity. If so,
913 * toggle state of LED and reset timer. If not,
914 * turn LED to desired idle state.
916 spin_lock_irqsave(ap->lock, flags);
917 if (emp->saved_activity != emp->activity) {
918 emp->saved_activity = emp->activity;
919 /* get the current LED state */
920 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
922 if (activity_led_state)
923 activity_led_state = 0;
925 activity_led_state = 1;
927 /* clear old state */
928 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
931 led_message |= (activity_led_state << 16);
932 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
935 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
936 if (emp->blink_policy == BLINK_OFF)
937 led_message |= (1 << 16);
939 spin_unlock_irqrestore(ap->lock, flags);
940 ap->ops->transmit_led_message(ap, led_message, 4);
943 static void ahci_init_sw_activity(struct ata_link *link)
945 struct ata_port *ap = link->ap;
946 struct ahci_port_priv *pp = ap->private_data;
947 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
949 /* init activity stats, setup timer */
950 emp->saved_activity = emp->activity = 0;
951 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
953 /* check our blink policy and set flag for link if it's enabled */
954 if (emp->blink_policy)
955 link->flags |= ATA_LFLAG_SW_ACTIVITY;
958 int ahci_reset_em(struct ata_host *host)
960 struct ahci_host_priv *hpriv = host->private_data;
961 void __iomem *mmio = hpriv->mmio;
964 em_ctl = readl(mmio + HOST_EM_CTL);
965 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
968 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
971 EXPORT_SYMBOL_GPL(ahci_reset_em);
973 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
976 struct ahci_host_priv *hpriv = ap->host->private_data;
977 struct ahci_port_priv *pp = ap->private_data;
978 void __iomem *mmio = hpriv->mmio;
980 u32 message[] = {0, 0};
983 struct ahci_em_priv *emp;
985 /* get the slot number from the message */
986 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
987 if (pmp < EM_MAX_SLOTS)
988 emp = &pp->em_priv[pmp];
992 spin_lock_irqsave(ap->lock, flags);
995 * if we are still busy transmitting a previous message,
998 em_ctl = readl(mmio + HOST_EM_CTL);
999 if (em_ctl & EM_CTL_TM) {
1000 spin_unlock_irqrestore(ap->lock, flags);
1004 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1006 * create message header - this is all zero except for
1007 * the message size, which is 4 bytes.
1009 message[0] |= (4 << 8);
1011 /* ignore 0:4 of byte zero, fill in port info yourself */
1012 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1014 /* write message to EM_LOC */
1015 writel(message[0], mmio + hpriv->em_loc);
1016 writel(message[1], mmio + hpriv->em_loc+4);
1019 * tell hardware to transmit the message
1021 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1024 /* save off new led state for port/slot */
1025 emp->led_state = state;
1027 spin_unlock_irqrestore(ap->lock, flags);
1031 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1033 struct ahci_port_priv *pp = ap->private_data;
1034 struct ata_link *link;
1035 struct ahci_em_priv *emp;
1038 ata_for_each_link(link, ap, EDGE) {
1039 emp = &pp->em_priv[link->pmp];
1040 rc += sprintf(buf, "%lx\n", emp->led_state);
1045 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1050 struct ahci_port_priv *pp = ap->private_data;
1051 struct ahci_em_priv *emp;
1053 if (kstrtouint(buf, 0, &state) < 0)
1056 /* get the slot number from the message */
1057 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1058 if (pmp < EM_MAX_SLOTS)
1059 emp = &pp->em_priv[pmp];
1063 /* mask off the activity bits if we are in sw_activity
1064 * mode, user should turn off sw_activity before setting
1065 * activity led through em_message
1067 if (emp->blink_policy)
1068 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1070 return ap->ops->transmit_led_message(ap, state, size);
1073 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1075 struct ata_link *link = dev->link;
1076 struct ata_port *ap = link->ap;
1077 struct ahci_port_priv *pp = ap->private_data;
1078 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1079 u32 port_led_state = emp->led_state;
1081 /* save the desired Activity LED behavior */
1084 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1086 /* set the LED to OFF */
1087 port_led_state &= EM_MSG_LED_VALUE_OFF;
1088 port_led_state |= (ap->port_no | (link->pmp << 8));
1089 ap->ops->transmit_led_message(ap, port_led_state, 4);
1091 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1092 if (val == BLINK_OFF) {
1093 /* set LED to ON for idle */
1094 port_led_state &= EM_MSG_LED_VALUE_OFF;
1095 port_led_state |= (ap->port_no | (link->pmp << 8));
1096 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1097 ap->ops->transmit_led_message(ap, port_led_state, 4);
1100 emp->blink_policy = val;
1104 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1106 struct ata_link *link = dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct ahci_port_priv *pp = ap->private_data;
1109 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1111 /* display the saved value of activity behavior for this
1114 return sprintf(buf, "%d\n", emp->blink_policy);
1117 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1118 int port_no, void __iomem *mmio,
1119 void __iomem *port_mmio)
1121 struct ahci_host_priv *hpriv = ap->host->private_data;
1122 const char *emsg = NULL;
1126 /* make sure port is not active */
1127 rc = ahci_deinit_port(ap, &emsg);
1129 dev_warn(dev, "%s (%d)\n", emsg, rc);
1132 tmp = readl(port_mmio + PORT_SCR_ERR);
1133 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1134 writel(tmp, port_mmio + PORT_SCR_ERR);
1136 /* clear port IRQ */
1137 tmp = readl(port_mmio + PORT_IRQ_STAT);
1138 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1140 writel(tmp, port_mmio + PORT_IRQ_STAT);
1142 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1144 /* mark esata ports */
1145 tmp = readl(port_mmio + PORT_CMD);
1146 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1147 ap->pflags |= ATA_PFLAG_EXTERNAL;
1150 void ahci_init_controller(struct ata_host *host)
1152 struct ahci_host_priv *hpriv = host->private_data;
1153 void __iomem *mmio = hpriv->mmio;
1155 void __iomem *port_mmio;
1158 for (i = 0; i < host->n_ports; i++) {
1159 struct ata_port *ap = host->ports[i];
1161 port_mmio = ahci_port_base(ap);
1162 if (ata_port_is_dummy(ap))
1165 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1168 tmp = readl(mmio + HOST_CTL);
1169 VPRINTK("HOST_CTL 0x%x\n", tmp);
1170 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1171 tmp = readl(mmio + HOST_CTL);
1172 VPRINTK("HOST_CTL 0x%x\n", tmp);
1174 EXPORT_SYMBOL_GPL(ahci_init_controller);
1176 static void ahci_dev_config(struct ata_device *dev)
1178 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1180 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1181 dev->max_sectors = 255;
1183 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1187 unsigned int ahci_dev_classify(struct ata_port *ap)
1189 void __iomem *port_mmio = ahci_port_base(ap);
1190 struct ata_taskfile tf;
1193 tmp = readl(port_mmio + PORT_SIG);
1194 tf.lbah = (tmp >> 24) & 0xff;
1195 tf.lbam = (tmp >> 16) & 0xff;
1196 tf.lbal = (tmp >> 8) & 0xff;
1197 tf.nsect = (tmp) & 0xff;
1199 return ata_dev_classify(&tf);
1201 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1203 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1206 dma_addr_t cmd_tbl_dma;
1208 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1210 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1211 pp->cmd_slot[tag].status = 0;
1212 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1213 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1215 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1217 int ahci_kick_engine(struct ata_port *ap)
1219 void __iomem *port_mmio = ahci_port_base(ap);
1220 struct ahci_host_priv *hpriv = ap->host->private_data;
1221 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1226 rc = ahci_stop_engine(ap);
1231 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1233 busy = status & (ATA_BUSY | ATA_DRQ);
1234 if (!busy && !sata_pmp_attached(ap)) {
1239 if (!(hpriv->cap & HOST_CAP_CLO)) {
1245 tmp = readl(port_mmio + PORT_CMD);
1246 tmp |= PORT_CMD_CLO;
1247 writel(tmp, port_mmio + PORT_CMD);
1250 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1251 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1252 if (tmp & PORT_CMD_CLO)
1255 /* restart engine */
1257 hpriv->start_engine(ap);
1260 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1262 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1263 struct ata_taskfile *tf, int is_cmd, u16 flags,
1264 unsigned long timeout_msec)
1266 const u32 cmd_fis_len = 5; /* five dwords */
1267 struct ahci_port_priv *pp = ap->private_data;
1268 void __iomem *port_mmio = ahci_port_base(ap);
1269 u8 *fis = pp->cmd_tbl;
1272 /* prep the command */
1273 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1274 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1276 /* set port value for softreset of Port Multiplier */
1277 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1278 tmp = readl(port_mmio + PORT_FBS);
1279 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1280 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1281 writel(tmp, port_mmio + PORT_FBS);
1282 pp->fbs_last_dev = pmp;
1286 writel(1, port_mmio + PORT_CMD_ISSUE);
1289 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1290 0x1, 0x1, 1, timeout_msec);
1292 ahci_kick_engine(ap);
1296 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1301 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1302 int pmp, unsigned long deadline,
1303 int (*check_ready)(struct ata_link *link))
1305 struct ata_port *ap = link->ap;
1306 struct ahci_host_priv *hpriv = ap->host->private_data;
1307 struct ahci_port_priv *pp = ap->private_data;
1308 const char *reason = NULL;
1309 unsigned long now, msecs;
1310 struct ata_taskfile tf;
1311 bool fbs_disabled = false;
1316 /* prepare for SRST (AHCI-1.1 10.4.1) */
1317 rc = ahci_kick_engine(ap);
1318 if (rc && rc != -EOPNOTSUPP)
1319 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1322 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1323 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1324 * that is attached to port multiplier.
1326 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1327 ahci_disable_fbs(ap);
1328 fbs_disabled = true;
1331 ata_tf_init(link->device, &tf);
1333 /* issue the first D2H Register FIS */
1336 if (time_after(deadline, now))
1337 msecs = jiffies_to_msecs(deadline - now);
1340 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1341 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1343 reason = "1st FIS failed";
1347 /* spec says at least 5us, but be generous and sleep for 1ms */
1350 /* issue the second D2H Register FIS */
1351 tf.ctl &= ~ATA_SRST;
1352 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1354 /* wait for link to become ready */
1355 rc = ata_wait_after_reset(link, deadline, check_ready);
1356 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1358 * Workaround for cases where link online status can't
1359 * be trusted. Treat device readiness timeout as link
1362 ata_link_info(link, "device not ready, treating as offline\n");
1363 *class = ATA_DEV_NONE;
1365 /* link occupied, -ENODEV too is an error */
1366 reason = "device not ready";
1369 *class = ahci_dev_classify(ap);
1371 /* re-enable FBS if disabled before */
1373 ahci_enable_fbs(ap);
1375 DPRINTK("EXIT, class=%u\n", *class);
1379 ata_link_err(link, "softreset failed (%s)\n", reason);
1383 int ahci_check_ready(struct ata_link *link)
1385 void __iomem *port_mmio = ahci_port_base(link->ap);
1386 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1388 return ata_check_ready(status);
1390 EXPORT_SYMBOL_GPL(ahci_check_ready);
1392 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1393 unsigned long deadline)
1395 int pmp = sata_srst_pmp(link);
1399 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1401 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1403 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1405 void __iomem *port_mmio = ahci_port_base(link->ap);
1406 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1407 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1410 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1411 * which can save timeout delay.
1413 if (irq_status & PORT_IRQ_BAD_PMP)
1416 return ata_check_ready(status);
1419 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1420 unsigned long deadline)
1422 struct ata_port *ap = link->ap;
1423 void __iomem *port_mmio = ahci_port_base(ap);
1424 int pmp = sata_srst_pmp(link);
1430 rc = ahci_do_softreset(link, class, pmp, deadline,
1431 ahci_bad_pmp_check_ready);
1434 * Soft reset fails with IPMS set when PMP is enabled but
1435 * SATA HDD/ODD is connected to SATA port, do soft reset
1439 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1440 if (irq_sts & PORT_IRQ_BAD_PMP) {
1442 "applying PMP SRST workaround "
1444 rc = ahci_do_softreset(link, class, 0, deadline,
1452 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1453 unsigned long deadline)
1455 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1456 struct ata_port *ap = link->ap;
1457 struct ahci_port_priv *pp = ap->private_data;
1458 struct ahci_host_priv *hpriv = ap->host->private_data;
1459 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1460 struct ata_taskfile tf;
1466 ahci_stop_engine(ap);
1468 /* clear D2H reception area to properly wait for D2H FIS */
1469 ata_tf_init(link->device, &tf);
1470 tf.command = ATA_BUSY;
1471 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1473 rc = sata_link_hardreset(link, timing, deadline, &online,
1476 hpriv->start_engine(ap);
1479 *class = ahci_dev_classify(ap);
1481 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1485 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1487 struct ata_port *ap = link->ap;
1488 void __iomem *port_mmio = ahci_port_base(ap);
1491 ata_std_postreset(link, class);
1493 /* Make sure port's ATAPI bit is set appropriately */
1494 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1495 if (*class == ATA_DEV_ATAPI)
1496 new_tmp |= PORT_CMD_ATAPI;
1498 new_tmp &= ~PORT_CMD_ATAPI;
1499 if (new_tmp != tmp) {
1500 writel(new_tmp, port_mmio + PORT_CMD);
1501 readl(port_mmio + PORT_CMD); /* flush */
1505 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1507 struct scatterlist *sg;
1508 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1514 * Next, the S/G list.
1516 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1517 dma_addr_t addr = sg_dma_address(sg);
1518 u32 sg_len = sg_dma_len(sg);
1520 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1521 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1522 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1528 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1530 struct ata_port *ap = qc->ap;
1531 struct ahci_port_priv *pp = ap->private_data;
1533 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1534 return ata_std_qc_defer(qc);
1536 return sata_pmp_qc_defer_cmd_switch(qc);
1539 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1541 struct ata_port *ap = qc->ap;
1542 struct ahci_port_priv *pp = ap->private_data;
1543 int is_atapi = ata_is_atapi(qc->tf.protocol);
1546 const u32 cmd_fis_len = 5; /* five dwords */
1547 unsigned int n_elem;
1550 * Fill in command table information. First, the header,
1551 * a SATA Register - Host to Device command FIS.
1553 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1555 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1557 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1558 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1562 if (qc->flags & ATA_QCFLAG_DMAMAP)
1563 n_elem = ahci_fill_sg(qc, cmd_tbl);
1566 * Fill in command slot information.
1568 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1569 if (qc->tf.flags & ATA_TFLAG_WRITE)
1570 opts |= AHCI_CMD_WRITE;
1572 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1574 ahci_fill_cmd_slot(pp, qc->tag, opts);
1577 static void ahci_fbs_dec_intr(struct ata_port *ap)
1579 struct ahci_port_priv *pp = ap->private_data;
1580 void __iomem *port_mmio = ahci_port_base(ap);
1581 u32 fbs = readl(port_mmio + PORT_FBS);
1585 BUG_ON(!pp->fbs_enabled);
1587 /* time to wait for DEC is not specified by AHCI spec,
1588 * add a retry loop for safety.
1590 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1591 fbs = readl(port_mmio + PORT_FBS);
1592 while ((fbs & PORT_FBS_DEC) && retries--) {
1594 fbs = readl(port_mmio + PORT_FBS);
1597 if (fbs & PORT_FBS_DEC)
1598 dev_err(ap->host->dev, "failed to clear device error\n");
1601 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1603 struct ahci_host_priv *hpriv = ap->host->private_data;
1604 struct ahci_port_priv *pp = ap->private_data;
1605 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1606 struct ata_link *link = NULL;
1607 struct ata_queued_cmd *active_qc;
1608 struct ata_eh_info *active_ehi;
1609 bool fbs_need_dec = false;
1612 /* determine active link with error */
1613 if (pp->fbs_enabled) {
1614 void __iomem *port_mmio = ahci_port_base(ap);
1615 u32 fbs = readl(port_mmio + PORT_FBS);
1616 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1618 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1619 link = &ap->pmp_link[pmp];
1620 fbs_need_dec = true;
1624 ata_for_each_link(link, ap, EDGE)
1625 if (ata_link_active(link))
1631 active_qc = ata_qc_from_tag(ap, link->active_tag);
1632 active_ehi = &link->eh_info;
1634 /* record irq stat */
1635 ata_ehi_clear_desc(host_ehi);
1636 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1638 /* AHCI needs SError cleared; otherwise, it might lock up */
1639 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1640 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1641 host_ehi->serror |= serror;
1643 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1644 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1645 irq_stat &= ~PORT_IRQ_IF_ERR;
1647 if (irq_stat & PORT_IRQ_TF_ERR) {
1648 /* If qc is active, charge it; otherwise, the active
1649 * link. There's no active qc on NCQ errors. It will
1650 * be determined by EH by reading log page 10h.
1653 active_qc->err_mask |= AC_ERR_DEV;
1655 active_ehi->err_mask |= AC_ERR_DEV;
1657 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1658 host_ehi->serror &= ~SERR_INTERNAL;
1661 if (irq_stat & PORT_IRQ_UNK_FIS) {
1662 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1664 active_ehi->err_mask |= AC_ERR_HSM;
1665 active_ehi->action |= ATA_EH_RESET;
1666 ata_ehi_push_desc(active_ehi,
1667 "unknown FIS %08x %08x %08x %08x" ,
1668 unk[0], unk[1], unk[2], unk[3]);
1671 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1672 active_ehi->err_mask |= AC_ERR_HSM;
1673 active_ehi->action |= ATA_EH_RESET;
1674 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1677 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1678 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1679 host_ehi->action |= ATA_EH_RESET;
1680 ata_ehi_push_desc(host_ehi, "host bus error");
1683 if (irq_stat & PORT_IRQ_IF_ERR) {
1685 active_ehi->err_mask |= AC_ERR_DEV;
1687 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1688 host_ehi->action |= ATA_EH_RESET;
1691 ata_ehi_push_desc(host_ehi, "interface fatal error");
1694 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1695 ata_ehi_hotplugged(host_ehi);
1696 ata_ehi_push_desc(host_ehi, "%s",
1697 irq_stat & PORT_IRQ_CONNECT ?
1698 "connection status changed" : "PHY RDY changed");
1701 /* okay, let's hand over to EH */
1703 if (irq_stat & PORT_IRQ_FREEZE)
1704 ata_port_freeze(ap);
1705 else if (fbs_need_dec) {
1706 ata_link_abort(link);
1707 ahci_fbs_dec_intr(ap);
1712 static void ahci_handle_port_interrupt(struct ata_port *ap,
1713 void __iomem *port_mmio, u32 status)
1715 struct ata_eh_info *ehi = &ap->link.eh_info;
1716 struct ahci_port_priv *pp = ap->private_data;
1717 struct ahci_host_priv *hpriv = ap->host->private_data;
1718 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1722 /* ignore BAD_PMP while resetting */
1723 if (unlikely(resetting))
1724 status &= ~PORT_IRQ_BAD_PMP;
1726 if (sata_lpm_ignore_phy_events(&ap->link)) {
1727 status &= ~PORT_IRQ_PHYRDY;
1728 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1731 if (unlikely(status & PORT_IRQ_ERROR)) {
1732 ahci_error_intr(ap, status);
1736 if (status & PORT_IRQ_SDB_FIS) {
1737 /* If SNotification is available, leave notification
1738 * handling to sata_async_notification(). If not,
1739 * emulate it by snooping SDB FIS RX area.
1741 * Snooping FIS RX area is probably cheaper than
1742 * poking SNotification but some constrollers which
1743 * implement SNotification, ICH9 for example, don't
1744 * store AN SDB FIS into receive area.
1746 if (hpriv->cap & HOST_CAP_SNTF)
1747 sata_async_notification(ap);
1749 /* If the 'N' bit in word 0 of the FIS is set,
1750 * we just received asynchronous notification.
1751 * Tell libata about it.
1753 * Lack of SNotification should not appear in
1754 * ahci 1.2, so the workaround is unnecessary
1755 * when FBS is enabled.
1757 if (pp->fbs_enabled)
1760 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1761 u32 f0 = le32_to_cpu(f[0]);
1763 sata_async_notification(ap);
1768 /* pp->active_link is not reliable once FBS is enabled, both
1769 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1770 * NCQ and non-NCQ commands may be in flight at the same time.
1772 if (pp->fbs_enabled) {
1773 if (ap->qc_active) {
1774 qc_active = readl(port_mmio + PORT_SCR_ACT);
1775 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1778 /* pp->active_link is valid iff any command is in flight */
1779 if (ap->qc_active && pp->active_link->sactive)
1780 qc_active = readl(port_mmio + PORT_SCR_ACT);
1782 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1786 rc = ata_qc_complete_multiple(ap, qc_active);
1788 /* while resetting, invalid completions are expected */
1789 if (unlikely(rc < 0 && !resetting)) {
1790 ehi->err_mask |= AC_ERR_HSM;
1791 ehi->action |= ATA_EH_RESET;
1792 ata_port_freeze(ap);
1796 static void ahci_port_intr(struct ata_port *ap)
1798 void __iomem *port_mmio = ahci_port_base(ap);
1801 status = readl(port_mmio + PORT_IRQ_STAT);
1802 writel(status, port_mmio + PORT_IRQ_STAT);
1804 ahci_handle_port_interrupt(ap, port_mmio, status);
1807 static irqreturn_t ahci_port_thread_fn(int irq, void *dev_instance)
1809 struct ata_port *ap = dev_instance;
1810 struct ahci_port_priv *pp = ap->private_data;
1811 void __iomem *port_mmio = ahci_port_base(ap);
1814 status = atomic_xchg(&pp->intr_status, 0);
1818 spin_lock_bh(ap->lock);
1819 ahci_handle_port_interrupt(ap, port_mmio, status);
1820 spin_unlock_bh(ap->lock);
1825 static irqreturn_t ahci_multi_irqs_intr(int irq, void *dev_instance)
1827 struct ata_port *ap = dev_instance;
1828 void __iomem *port_mmio = ahci_port_base(ap);
1829 struct ahci_port_priv *pp = ap->private_data;
1834 status = readl(port_mmio + PORT_IRQ_STAT);
1835 writel(status, port_mmio + PORT_IRQ_STAT);
1837 atomic_or(status, &pp->intr_status);
1841 return IRQ_WAKE_THREAD;
1844 static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1846 unsigned int i, handled = 0;
1848 for (i = 0; i < host->n_ports; i++) {
1849 struct ata_port *ap;
1851 if (!(irq_masked & (1 << i)))
1854 ap = host->ports[i];
1857 VPRINTK("port %u\n", i);
1859 VPRINTK("port %u (no irq)\n", i);
1860 if (ata_ratelimit())
1862 "interrupt on disabled port %u\n", i);
1871 static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
1873 struct ata_host *host = dev_instance;
1874 struct ahci_host_priv *hpriv;
1875 unsigned int rc = 0;
1877 u32 irq_stat, irq_masked;
1881 hpriv = host->private_data;
1884 /* sigh. 0xffffffff is a valid return from h/w */
1885 irq_stat = readl(mmio + HOST_IRQ_STAT);
1889 irq_masked = irq_stat & hpriv->port_map;
1891 spin_lock(&host->lock);
1894 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1895 * it should be cleared before all the port events are cleared.
1897 writel(irq_stat, mmio + HOST_IRQ_STAT);
1899 rc = ahci_handle_port_intr(host, irq_masked);
1901 spin_unlock(&host->lock);
1905 return IRQ_RETVAL(rc);
1908 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1910 struct ata_host *host = dev_instance;
1911 struct ahci_host_priv *hpriv;
1912 unsigned int rc = 0;
1914 u32 irq_stat, irq_masked;
1918 hpriv = host->private_data;
1921 /* sigh. 0xffffffff is a valid return from h/w */
1922 irq_stat = readl(mmio + HOST_IRQ_STAT);
1926 irq_masked = irq_stat & hpriv->port_map;
1928 spin_lock(&host->lock);
1930 rc = ahci_handle_port_intr(host, irq_masked);
1932 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1933 * it should be cleared after all the port events are cleared;
1934 * otherwise, it will raise a spurious interrupt after each
1935 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1938 * Also, use the unmasked value to clear interrupt as spurious
1939 * pending event on a dummy port might cause screaming IRQ.
1941 writel(irq_stat, mmio + HOST_IRQ_STAT);
1943 spin_unlock(&host->lock);
1947 return IRQ_RETVAL(rc);
1950 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1952 struct ata_port *ap = qc->ap;
1953 void __iomem *port_mmio = ahci_port_base(ap);
1954 struct ahci_port_priv *pp = ap->private_data;
1956 /* Keep track of the currently active link. It will be used
1957 * in completion path to determine whether NCQ phase is in
1960 pp->active_link = qc->dev->link;
1962 if (qc->tf.protocol == ATA_PROT_NCQ)
1963 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1965 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1966 u32 fbs = readl(port_mmio + PORT_FBS);
1967 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1968 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1969 writel(fbs, port_mmio + PORT_FBS);
1970 pp->fbs_last_dev = qc->dev->link->pmp;
1973 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1975 ahci_sw_activity(qc->dev->link);
1979 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1981 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1983 struct ahci_port_priv *pp = qc->ap->private_data;
1984 u8 *rx_fis = pp->rx_fis;
1986 if (pp->fbs_enabled)
1987 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1990 * After a successful execution of an ATA PIO data-in command,
1991 * the device doesn't send D2H Reg FIS to update the TF and
1992 * the host should take TF and E_Status from the preceding PIO
1995 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1996 !(qc->flags & ATA_QCFLAG_FAILED)) {
1997 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1998 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2000 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2005 static void ahci_freeze(struct ata_port *ap)
2007 void __iomem *port_mmio = ahci_port_base(ap);
2010 writel(0, port_mmio + PORT_IRQ_MASK);
2013 static void ahci_thaw(struct ata_port *ap)
2015 struct ahci_host_priv *hpriv = ap->host->private_data;
2016 void __iomem *mmio = hpriv->mmio;
2017 void __iomem *port_mmio = ahci_port_base(ap);
2019 struct ahci_port_priv *pp = ap->private_data;
2022 tmp = readl(port_mmio + PORT_IRQ_STAT);
2023 writel(tmp, port_mmio + PORT_IRQ_STAT);
2024 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2026 /* turn IRQ back on */
2027 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2030 void ahci_error_handler(struct ata_port *ap)
2032 struct ahci_host_priv *hpriv = ap->host->private_data;
2034 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2035 /* restart engine */
2036 ahci_stop_engine(ap);
2037 hpriv->start_engine(ap);
2040 sata_pmp_error_handler(ap);
2042 if (!ata_dev_enabled(ap->link.device))
2043 ahci_stop_engine(ap);
2045 EXPORT_SYMBOL_GPL(ahci_error_handler);
2047 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2049 struct ata_port *ap = qc->ap;
2051 /* make DMA engine forget about the failed command */
2052 if (qc->flags & ATA_QCFLAG_FAILED)
2053 ahci_kick_engine(ap);
2056 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2058 struct ahci_host_priv *hpriv = ap->host->private_data;
2059 void __iomem *port_mmio = ahci_port_base(ap);
2060 struct ata_device *dev = ap->link.device;
2061 u32 devslp, dm, dito, mdat, deto;
2063 unsigned int err_mask;
2065 devslp = readl(port_mmio + PORT_DEVSLP);
2066 if (!(devslp & PORT_DEVSLP_DSP)) {
2067 dev_info(ap->host->dev, "port does not support device sleep\n");
2071 /* disable device sleep */
2073 if (devslp & PORT_DEVSLP_ADSE) {
2074 writel(devslp & ~PORT_DEVSLP_ADSE,
2075 port_mmio + PORT_DEVSLP);
2076 err_mask = ata_dev_set_feature(dev,
2077 SETFEATURES_SATA_DISABLE,
2079 if (err_mask && err_mask != AC_ERR_DEV)
2080 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2085 /* device sleep was already enabled */
2086 if (devslp & PORT_DEVSLP_ADSE)
2089 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2090 rc = ahci_stop_engine(ap);
2094 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2095 dito = devslp_idle_timeout / (dm + 1);
2099 /* Use the nominal value 10 ms if the read MDAT is zero,
2100 * the nominal value of DETO is 20 ms.
2102 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2103 ATA_LOG_DEVSLP_VALID_MASK) {
2104 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2105 ATA_LOG_DEVSLP_MDAT_MASK;
2108 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2116 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2117 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2118 (deto << PORT_DEVSLP_DETO_OFFSET) |
2120 writel(devslp, port_mmio + PORT_DEVSLP);
2122 hpriv->start_engine(ap);
2124 /* enable device sleep feature for the drive */
2125 err_mask = ata_dev_set_feature(dev,
2126 SETFEATURES_SATA_ENABLE,
2128 if (err_mask && err_mask != AC_ERR_DEV)
2129 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2132 static void ahci_enable_fbs(struct ata_port *ap)
2134 struct ahci_host_priv *hpriv = ap->host->private_data;
2135 struct ahci_port_priv *pp = ap->private_data;
2136 void __iomem *port_mmio = ahci_port_base(ap);
2140 if (!pp->fbs_supported)
2143 fbs = readl(port_mmio + PORT_FBS);
2144 if (fbs & PORT_FBS_EN) {
2145 pp->fbs_enabled = true;
2146 pp->fbs_last_dev = -1; /* initialization */
2150 rc = ahci_stop_engine(ap);
2154 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2155 fbs = readl(port_mmio + PORT_FBS);
2156 if (fbs & PORT_FBS_EN) {
2157 dev_info(ap->host->dev, "FBS is enabled\n");
2158 pp->fbs_enabled = true;
2159 pp->fbs_last_dev = -1; /* initialization */
2161 dev_err(ap->host->dev, "Failed to enable FBS\n");
2163 hpriv->start_engine(ap);
2166 static void ahci_disable_fbs(struct ata_port *ap)
2168 struct ahci_host_priv *hpriv = ap->host->private_data;
2169 struct ahci_port_priv *pp = ap->private_data;
2170 void __iomem *port_mmio = ahci_port_base(ap);
2174 if (!pp->fbs_supported)
2177 fbs = readl(port_mmio + PORT_FBS);
2178 if ((fbs & PORT_FBS_EN) == 0) {
2179 pp->fbs_enabled = false;
2183 rc = ahci_stop_engine(ap);
2187 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2188 fbs = readl(port_mmio + PORT_FBS);
2189 if (fbs & PORT_FBS_EN)
2190 dev_err(ap->host->dev, "Failed to disable FBS\n");
2192 dev_info(ap->host->dev, "FBS is disabled\n");
2193 pp->fbs_enabled = false;
2196 hpriv->start_engine(ap);
2199 static void ahci_pmp_attach(struct ata_port *ap)
2201 void __iomem *port_mmio = ahci_port_base(ap);
2202 struct ahci_port_priv *pp = ap->private_data;
2205 cmd = readl(port_mmio + PORT_CMD);
2206 cmd |= PORT_CMD_PMP;
2207 writel(cmd, port_mmio + PORT_CMD);
2209 ahci_enable_fbs(ap);
2211 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2214 * We must not change the port interrupt mask register if the
2215 * port is marked frozen, the value in pp->intr_mask will be
2216 * restored later when the port is thawed.
2218 * Note that during initialization, the port is marked as
2219 * frozen since the irq handler is not yet registered.
2221 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2222 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2225 static void ahci_pmp_detach(struct ata_port *ap)
2227 void __iomem *port_mmio = ahci_port_base(ap);
2228 struct ahci_port_priv *pp = ap->private_data;
2231 ahci_disable_fbs(ap);
2233 cmd = readl(port_mmio + PORT_CMD);
2234 cmd &= ~PORT_CMD_PMP;
2235 writel(cmd, port_mmio + PORT_CMD);
2237 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2239 /* see comment above in ahci_pmp_attach() */
2240 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2241 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2244 int ahci_port_resume(struct ata_port *ap)
2247 ahci_start_port(ap);
2249 if (sata_pmp_attached(ap))
2250 ahci_pmp_attach(ap);
2252 ahci_pmp_detach(ap);
2256 EXPORT_SYMBOL_GPL(ahci_port_resume);
2259 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2261 const char *emsg = NULL;
2264 rc = ahci_deinit_port(ap, &emsg);
2266 ahci_power_down(ap);
2268 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2269 ata_port_freeze(ap);
2276 static int ahci_port_start(struct ata_port *ap)
2278 struct ahci_host_priv *hpriv = ap->host->private_data;
2279 struct device *dev = ap->host->dev;
2280 struct ahci_port_priv *pp;
2283 size_t dma_sz, rx_fis_sz;
2285 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2289 if (ap->host->n_ports > 1) {
2290 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2291 if (!pp->irq_desc) {
2292 devm_kfree(dev, pp);
2295 snprintf(pp->irq_desc, 8,
2296 "%s%d", dev_driver_string(dev), ap->port_no);
2299 /* check FBS capability */
2300 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2301 void __iomem *port_mmio = ahci_port_base(ap);
2302 u32 cmd = readl(port_mmio + PORT_CMD);
2303 if (cmd & PORT_CMD_FBSCP)
2304 pp->fbs_supported = true;
2305 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2306 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2308 pp->fbs_supported = true;
2310 dev_warn(dev, "port %d is not capable of FBS\n",
2314 if (pp->fbs_supported) {
2315 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2316 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2318 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2319 rx_fis_sz = AHCI_RX_FIS_SZ;
2322 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2325 memset(mem, 0, dma_sz);
2328 * First item in chunk of DMA memory: 32-slot command table,
2329 * 32 bytes each in size
2332 pp->cmd_slot_dma = mem_dma;
2334 mem += AHCI_CMD_SLOT_SZ;
2335 mem_dma += AHCI_CMD_SLOT_SZ;
2338 * Second item: Received-FIS area
2341 pp->rx_fis_dma = mem_dma;
2344 mem_dma += rx_fis_sz;
2347 * Third item: data area for storing a single command
2348 * and its scatter-gather table
2351 pp->cmd_tbl_dma = mem_dma;
2354 * Save off initial list of interrupts to be enabled.
2355 * This could be changed later
2357 pp->intr_mask = DEF_PORT_IRQ;
2360 * Switch to per-port locking in case each port has its own MSI vector.
2362 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2363 spin_lock_init(&pp->lock);
2364 ap->lock = &pp->lock;
2367 ap->private_data = pp;
2369 /* engage engines, captain */
2370 return ahci_port_resume(ap);
2373 static void ahci_port_stop(struct ata_port *ap)
2375 const char *emsg = NULL;
2378 /* de-initialize port */
2379 rc = ahci_deinit_port(ap, &emsg);
2381 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2384 void ahci_print_info(struct ata_host *host, const char *scc_s)
2386 struct ahci_host_priv *hpriv = host->private_data;
2387 void __iomem *mmio = hpriv->mmio;
2388 u32 vers, cap, cap2, impl, speed;
2389 const char *speed_s;
2391 vers = readl(mmio + HOST_VERSION);
2394 impl = hpriv->port_map;
2396 speed = (cap >> 20) & 0xf;
2399 else if (speed == 2)
2401 else if (speed == 3)
2407 "AHCI %02x%02x.%02x%02x "
2408 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2411 (vers >> 24) & 0xff,
2412 (vers >> 16) & 0xff,
2416 ((cap >> 8) & 0x1f) + 1,
2430 cap & HOST_CAP_64 ? "64bit " : "",
2431 cap & HOST_CAP_NCQ ? "ncq " : "",
2432 cap & HOST_CAP_SNTF ? "sntf " : "",
2433 cap & HOST_CAP_MPS ? "ilck " : "",
2434 cap & HOST_CAP_SSS ? "stag " : "",
2435 cap & HOST_CAP_ALPM ? "pm " : "",
2436 cap & HOST_CAP_LED ? "led " : "",
2437 cap & HOST_CAP_CLO ? "clo " : "",
2438 cap & HOST_CAP_ONLY ? "only " : "",
2439 cap & HOST_CAP_PMP ? "pmp " : "",
2440 cap & HOST_CAP_FBS ? "fbs " : "",
2441 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2442 cap & HOST_CAP_SSC ? "slum " : "",
2443 cap & HOST_CAP_PART ? "part " : "",
2444 cap & HOST_CAP_CCC ? "ccc " : "",
2445 cap & HOST_CAP_EMS ? "ems " : "",
2446 cap & HOST_CAP_SXS ? "sxs " : "",
2447 cap2 & HOST_CAP2_DESO ? "deso " : "",
2448 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2449 cap2 & HOST_CAP2_SDS ? "sds " : "",
2450 cap2 & HOST_CAP2_APST ? "apst " : "",
2451 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2452 cap2 & HOST_CAP2_BOH ? "boh " : ""
2455 EXPORT_SYMBOL_GPL(ahci_print_info);
2457 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2458 struct ata_port_info *pi)
2461 void __iomem *mmio = hpriv->mmio;
2462 u32 em_loc = readl(mmio + HOST_EM_LOC);
2463 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2465 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2468 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2472 hpriv->em_loc = ((em_loc >> 16) * 4);
2473 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2474 hpriv->em_msg_type = messages;
2475 pi->flags |= ATA_FLAG_EM;
2476 if (!(em_ctl & EM_CTL_ALHD))
2477 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2480 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2482 static int ahci_host_activate_multi_irqs(struct ata_host *host, int irq,
2483 struct scsi_host_template *sht)
2487 rc = ata_host_start(host);
2491 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2492 * allocated. That is one MSI per port, starting from @irq.
2494 for (i = 0; i < host->n_ports; i++) {
2495 struct ahci_port_priv *pp = host->ports[i]->private_data;
2497 /* Do not receive interrupts sent by dummy ports */
2499 disable_irq(irq + i);
2503 rc = devm_request_threaded_irq(host->dev, irq + i,
2504 ahci_multi_irqs_intr,
2505 ahci_port_thread_fn, 0,
2506 pp->irq_desc, host->ports[i]);
2509 ata_port_desc(host->ports[i], "irq %d", irq + i);
2511 return ata_host_register(host, sht);
2515 * ahci_host_activate - start AHCI host, request IRQs and register it
2516 * @host: target ATA host
2517 * @sht: scsi_host_template to use when registering the host
2520 * Inherited from calling layer (may sleep).
2523 * 0 on success, -errno otherwise.
2525 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2527 struct ahci_host_priv *hpriv = host->private_data;
2528 int irq = hpriv->irq;
2531 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
2532 rc = ahci_host_activate_multi_irqs(host, irq, sht);
2533 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
2534 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
2537 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
2541 EXPORT_SYMBOL_GPL(ahci_host_activate);
2543 MODULE_AUTHOR("Jeff Garzik");
2544 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2545 MODULE_LICENSE("GPL");