2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 static struct scsi_host_template ahci_sht = {
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
108 static const struct ata_port_info ahci_port_info[] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
116 [board_ahci_ign_iferr] = {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
123 [board_ahci_noncq] = {
124 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
130 [board_ahci_nosntf] = {
131 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
137 [board_ahci_yes_fbs] = {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
145 [board_ahci_mcp65] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
153 [board_ahci_mcp77] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
160 [board_ahci_mcp89] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
175 [board_ahci_sb600] = {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
184 [board_ahci_sb700] = { /* for SB700 and SB800 */
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_pmp_retry_srst_ops,
191 [board_ahci_vt8251] = {
192 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_vt8251_ops,
200 static const struct pci_device_id ahci_pci_tbl[] = {
202 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
203 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
204 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
205 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
206 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
207 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
208 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
209 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
212 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
213 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
216 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
230 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
232 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
237 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
245 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
249 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
250 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
253 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
256 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
261 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
263 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
269 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
271 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
295 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
299 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
303 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
305 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
308 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
309 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
310 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
311 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
312 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
313 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
314 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
316 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
317 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
318 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
319 /* JMicron 362B and 362C have an AHCI function with IDE class code */
320 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
321 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
324 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
325 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
326 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
333 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
334 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
335 /* AMD is using RAID class only for ahci controllers */
336 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
337 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
340 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
341 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
344 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
430 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
431 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
432 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
434 /* ST Microelectronics */
435 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
438 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
439 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
441 .class = PCI_CLASS_STORAGE_SATA_AHCI,
442 .class_mask = 0xffffff,
443 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
446 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
447 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
448 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
450 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
452 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
454 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
455 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
456 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
457 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
458 .driver_data = board_ahci_yes_fbs },
459 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
460 .driver_data = board_ahci_yes_fbs },
461 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
462 .driver_data = board_ahci_yes_fbs },
463 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
464 .driver_data = board_ahci_yes_fbs },
467 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
468 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
471 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
472 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
473 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
474 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
477 * Samsung SSDs found on some macbooks. NCQ times out.
478 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
480 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
483 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
485 /* Generic, PCI class code for AHCI */
486 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
487 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
489 { } /* terminate list */
493 static struct pci_driver ahci_pci_driver = {
495 .id_table = ahci_pci_tbl,
496 .probe = ahci_init_one,
497 .remove = ata_pci_remove_one,
499 .suspend = ahci_pci_device_suspend,
500 .resume = ahci_pci_device_resume,
504 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
505 static int marvell_enable;
507 static int marvell_enable = 1;
509 module_param(marvell_enable, int, 0644);
510 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
513 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
514 struct ahci_host_priv *hpriv)
516 unsigned int force_port_map = 0;
517 unsigned int mask_port_map = 0;
519 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
520 dev_info(&pdev->dev, "JMB361 has only one port\n");
525 * Temporary Marvell 6145 hack: PATA port presence
526 * is asserted through the standard AHCI port
527 * presence register, as bit 4 (counting from 0)
529 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
530 if (pdev->device == 0x6121)
535 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
538 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
542 static int ahci_pci_reset_controller(struct ata_host *host)
544 struct pci_dev *pdev = to_pci_dev(host->dev);
546 ahci_reset_controller(host);
548 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
549 struct ahci_host_priv *hpriv = host->private_data;
553 pci_read_config_word(pdev, 0x92, &tmp16);
554 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
555 tmp16 |= hpriv->port_map;
556 pci_write_config_word(pdev, 0x92, tmp16);
563 static void ahci_pci_init_controller(struct ata_host *host)
565 struct ahci_host_priv *hpriv = host->private_data;
566 struct pci_dev *pdev = to_pci_dev(host->dev);
567 void __iomem *port_mmio;
571 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
572 if (pdev->device == 0x6121)
576 port_mmio = __ahci_port_base(host, mv);
578 writel(0, port_mmio + PORT_IRQ_MASK);
581 tmp = readl(port_mmio + PORT_IRQ_STAT);
582 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
584 writel(tmp, port_mmio + PORT_IRQ_STAT);
587 ahci_init_controller(host);
590 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline)
593 struct ata_port *ap = link->ap;
599 ahci_stop_engine(ap);
601 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
602 deadline, &online, NULL);
604 ahci_start_engine(ap);
606 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
608 /* vt8251 doesn't clear BSY on signature FIS reception,
609 * request follow-up softreset.
611 return online ? -EAGAIN : rc;
614 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
615 unsigned long deadline)
617 struct ata_port *ap = link->ap;
618 struct ahci_port_priv *pp = ap->private_data;
619 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
620 struct ata_taskfile tf;
624 ahci_stop_engine(ap);
626 /* clear D2H reception area to properly wait for D2H FIS */
627 ata_tf_init(link->device, &tf);
629 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
631 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
632 deadline, &online, NULL);
634 ahci_start_engine(ap);
636 /* The pseudo configuration device on SIMG4726 attached to
637 * ASUS P5W-DH Deluxe doesn't send signature FIS after
638 * hardreset if no device is attached to the first downstream
639 * port && the pseudo device locks up on SRST w/ PMP==0. To
640 * work around this, wait for !BSY only briefly. If BSY isn't
641 * cleared, perform CLO and proceed to IDENTIFY (achieved by
642 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
644 * Wait for two seconds. Devices attached to downstream port
645 * which can't process the following IDENTIFY after this will
646 * have to be reset again. For most cases, this should
647 * suffice while making probing snappish enough.
650 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
653 ahci_kick_engine(ap);
659 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
661 struct ata_host *host = dev_get_drvdata(&pdev->dev);
662 struct ahci_host_priv *hpriv = host->private_data;
663 void __iomem *mmio = hpriv->mmio;
666 if (mesg.event & PM_EVENT_SUSPEND &&
667 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
669 "BIOS update required for suspend/resume\n");
673 if (mesg.event & PM_EVENT_SLEEP) {
674 /* AHCI spec rev1.1 section 8.3.3:
675 * Software must disable interrupts prior to requesting a
676 * transition of the HBA to D3 state.
678 ctl = readl(mmio + HOST_CTL);
680 writel(ctl, mmio + HOST_CTL);
681 readl(mmio + HOST_CTL); /* flush */
684 return ata_pci_device_suspend(pdev, mesg);
687 static int ahci_pci_device_resume(struct pci_dev *pdev)
689 struct ata_host *host = dev_get_drvdata(&pdev->dev);
692 rc = ata_pci_device_do_resume(pdev);
696 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
697 rc = ahci_pci_reset_controller(host);
701 ahci_pci_init_controller(host);
704 ata_host_resume(host);
710 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
715 * If the device fixup already set the dma_mask to some non-standard
716 * value, don't extend it here. This happens on STA2X11, for example.
718 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
722 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
723 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
725 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
728 "64-bit DMA enable failed\n");
733 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
735 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
738 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
741 "32-bit consistent DMA enable failed\n");
748 static void ahci_pci_print_info(struct ata_host *host)
750 struct pci_dev *pdev = to_pci_dev(host->dev);
754 pci_read_config_word(pdev, 0x0a, &cc);
755 if (cc == PCI_CLASS_STORAGE_IDE)
757 else if (cc == PCI_CLASS_STORAGE_SATA)
759 else if (cc == PCI_CLASS_STORAGE_RAID)
764 ahci_print_info(host, scc_s);
767 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
768 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
769 * support PMP and the 4726 either directly exports the device
770 * attached to the first downstream port or acts as a hardware storage
771 * controller and emulate a single ATA device (can be RAID 0/1 or some
772 * other configuration).
774 * When there's no device attached to the first downstream port of the
775 * 4726, "Config Disk" appears, which is a pseudo ATA device to
776 * configure the 4726. However, ATA emulation of the device is very
777 * lame. It doesn't send signature D2H Reg FIS after the initial
778 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
780 * The following function works around the problem by always using
781 * hardreset on the port and not depending on receiving signature FIS
782 * afterward. If signature FIS isn't received soon, ATA class is
783 * assumed without follow-up softreset.
785 static void ahci_p5wdh_workaround(struct ata_host *host)
787 static struct dmi_system_id sysids[] = {
789 .ident = "P5W DH Deluxe",
791 DMI_MATCH(DMI_SYS_VENDOR,
792 "ASUSTEK COMPUTER INC"),
793 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
798 struct pci_dev *pdev = to_pci_dev(host->dev);
800 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
801 dmi_check_system(sysids)) {
802 struct ata_port *ap = host->ports[1];
805 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
807 ap->ops = &ahci_p5wdh_ops;
808 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
812 /* only some SB600 ahci controllers can do 64bit DMA */
813 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
815 static const struct dmi_system_id sysids[] = {
817 * The oldest version known to be broken is 0901 and
818 * working is 1501 which was released on 2007-10-26.
819 * Enable 64bit DMA on 1501 and anything newer.
821 * Please read bko#9412 for more info.
824 .ident = "ASUS M2A-VM",
826 DMI_MATCH(DMI_BOARD_VENDOR,
827 "ASUSTeK Computer INC."),
828 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
830 .driver_data = "20071026", /* yyyymmdd */
833 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
836 * BIOS versions earlier than 1.5 had the Manufacturer DMI
837 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
838 * This spelling mistake was fixed in BIOS version 1.5, so
839 * 1.5 and later have the Manufacturer as
840 * "MICRO-STAR INTERNATIONAL CO.,LTD".
841 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
843 * BIOS versions earlier than 1.9 had a Board Product Name
844 * DMI field of "MS-7376". This was changed to be
845 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
846 * match on DMI_BOARD_NAME of "MS-7376".
849 .ident = "MSI K9A2 Platinum",
851 DMI_MATCH(DMI_BOARD_VENDOR,
853 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
857 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
860 * This board also had the typo mentioned above in the
861 * Manufacturer DMI field (fixed in BIOS version 1.5), so
862 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
865 .ident = "MSI K9AGM2",
867 DMI_MATCH(DMI_BOARD_VENDOR,
869 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
873 * All BIOS versions for the Asus M3A support 64bit DMA.
874 * (all release versions from 0301 to 1206 were tested)
879 DMI_MATCH(DMI_BOARD_VENDOR,
880 "ASUSTeK Computer INC."),
881 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
886 const struct dmi_system_id *match;
887 int year, month, date;
890 match = dmi_first_match(sysids);
891 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
895 if (!match->driver_data)
898 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
899 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
901 if (strcmp(buf, match->driver_data) >= 0)
905 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
911 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
915 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
917 static const struct dmi_system_id broken_systems[] = {
919 .ident = "HP Compaq nx6310",
921 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
922 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
924 /* PCI slot number of the controller */
925 .driver_data = (void *)0x1FUL,
928 .ident = "HP Compaq 6720s",
930 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
931 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
933 /* PCI slot number of the controller */
934 .driver_data = (void *)0x1FUL,
937 { } /* terminate list */
939 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
942 unsigned long slot = (unsigned long)dmi->driver_data;
943 /* apply the quirk only to on-board controllers */
944 return slot == PCI_SLOT(pdev->devfn);
950 static bool ahci_broken_suspend(struct pci_dev *pdev)
952 static const struct dmi_system_id sysids[] = {
954 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
955 * to the harddisk doesn't become online after
956 * resuming from STR. Warn and fail suspend.
958 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
960 * Use dates instead of versions to match as HP is
961 * apparently recycling both product and version
964 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
969 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
970 DMI_MATCH(DMI_PRODUCT_NAME,
971 "HP Pavilion dv4 Notebook PC"),
973 .driver_data = "20090105", /* F.30 */
978 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
979 DMI_MATCH(DMI_PRODUCT_NAME,
980 "HP Pavilion dv5 Notebook PC"),
982 .driver_data = "20090506", /* F.16 */
987 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
988 DMI_MATCH(DMI_PRODUCT_NAME,
989 "HP Pavilion dv6 Notebook PC"),
991 .driver_data = "20090423", /* F.21 */
996 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
997 DMI_MATCH(DMI_PRODUCT_NAME,
998 "HP HDX18 Notebook PC"),
1000 .driver_data = "20090430", /* F.23 */
1003 * Acer eMachines G725 has the same problem. BIOS
1004 * V1.03 is known to be broken. V3.04 is known to
1005 * work. Between, there are V1.06, V2.06 and V3.03
1006 * that we don't have much idea about. For now,
1007 * blacklist anything older than V3.04.
1009 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1014 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1017 .driver_data = "20091216", /* V3.04 */
1019 { } /* terminate list */
1021 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1022 int year, month, date;
1025 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1028 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1029 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1031 return strcmp(buf, dmi->driver_data) < 0;
1034 static bool ahci_broken_online(struct pci_dev *pdev)
1036 #define ENCODE_BUSDEVFN(bus, slot, func) \
1037 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1038 static const struct dmi_system_id sysids[] = {
1040 * There are several gigabyte boards which use
1041 * SIMG5723s configured as hardware RAID. Certain
1042 * 5723 firmware revisions shipped there keep the link
1043 * online but fail to answer properly to SRST or
1044 * IDENTIFY when no device is attached downstream
1045 * causing libata to retry quite a few times leading
1046 * to excessive detection delay.
1048 * As these firmwares respond to the second reset try
1049 * with invalid device signature, considering unknown
1050 * sig as offline works around the problem acceptably.
1053 .ident = "EP45-DQ6",
1055 DMI_MATCH(DMI_BOARD_VENDOR,
1056 "Gigabyte Technology Co., Ltd."),
1057 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1059 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1062 .ident = "EP45-DS5",
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "Gigabyte Technology Co., Ltd."),
1066 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1068 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1070 { } /* terminate list */
1072 #undef ENCODE_BUSDEVFN
1073 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1079 val = (unsigned long)dmi->driver_data;
1081 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1084 #ifdef CONFIG_ATA_ACPI
1085 static void ahci_gtf_filter_workaround(struct ata_host *host)
1087 static const struct dmi_system_id sysids[] = {
1089 * Aspire 3810T issues a bunch of SATA enable commands
1090 * via _GTF including an invalid one and one which is
1091 * rejected by the device. Among the successful ones
1092 * is FPDMA non-zero offset enable which when enabled
1093 * only on the drive side leads to NCQ command
1094 * failures. Filter it out.
1097 .ident = "Aspire 3810T",
1099 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1100 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1102 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1106 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1107 unsigned int filter;
1113 filter = (unsigned long)dmi->driver_data;
1114 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1115 filter, dmi->ident);
1117 for (i = 0; i < host->n_ports; i++) {
1118 struct ata_port *ap = host->ports[i];
1119 struct ata_link *link;
1120 struct ata_device *dev;
1122 ata_for_each_link(link, ap, EDGE)
1123 ata_for_each_dev(dev, link, ALL)
1124 dev->gtf_filter |= filter;
1128 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1132 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1135 unsigned int maxvec;
1137 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1138 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1140 if ((rc == maxvec) || (rc == 1))
1143 * Assume that advantage of multipe MSIs is negated,
1144 * so fallback to single MSI mode to save resources
1146 pci_disable_msi(pdev);
1147 if (!pci_enable_msi(pdev))
1157 * ahci_host_activate - start AHCI host, request IRQs and register it
1158 * @host: target ATA host
1159 * @irq: base IRQ number to request
1160 * @n_msis: number of MSIs allocated for this host
1161 * @irq_handler: irq_handler used when requesting IRQs
1162 * @irq_flags: irq_flags used when requesting IRQs
1164 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1165 * when multiple MSIs were allocated. That is one MSI per port, starting
1169 * Inherited from calling layer (may sleep).
1172 * 0 on success, -errno otherwise.
1174 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1178 /* Sharing Last Message among several ports is not supported */
1179 if (n_msis < host->n_ports)
1182 rc = ata_host_start(host);
1186 for (i = 0; i < host->n_ports; i++) {
1187 rc = devm_request_threaded_irq(host->dev,
1188 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1189 dev_driver_string(host->dev), host->ports[i]);
1194 for (i = 0; i < host->n_ports; i++)
1195 ata_port_desc(host->ports[i], "irq %d", irq + i);
1197 rc = ata_host_register(host, &ahci_sht);
1199 goto out_free_all_irqs;
1206 for (i--; i >= 0; i--)
1207 devm_free_irq(host->dev, irq + i, host->ports[i]);
1212 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1214 unsigned int board_id = ent->driver_data;
1215 struct ata_port_info pi = ahci_port_info[board_id];
1216 const struct ata_port_info *ppi[] = { &pi, NULL };
1217 struct device *dev = &pdev->dev;
1218 struct ahci_host_priv *hpriv;
1219 struct ata_host *host;
1220 int n_ports, n_msis, i, rc;
1221 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1225 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1227 ata_print_version_once(&pdev->dev, DRV_VERSION);
1229 /* The AHCI driver can only drive the SATA ports, the PATA driver
1230 can drive them all so if both drivers are selected make sure
1231 AHCI stays out of the way */
1232 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1236 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1237 * ahci, use ata_generic instead.
1239 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1240 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1241 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1242 pdev->subsystem_device == 0xcb89)
1245 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1246 * At the moment, we can only use the AHCI mode. Let the users know
1247 * that for SAS drives they're out of luck.
1249 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1250 dev_info(&pdev->dev,
1251 "PDC42819 can only drive SATA devices with this driver\n");
1253 /* Both Connext and Enmotus devices use non-standard BARs */
1254 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1255 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1256 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1257 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1259 /* acquire resources */
1260 rc = pcim_enable_device(pdev);
1264 /* AHCI controllers often implement SFF compatible interface.
1265 * Grab all PCI BARs just in case.
1267 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1269 pcim_pin_device(pdev);
1273 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1274 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1277 /* ICH6s share the same PCI ID for both piix and ahci
1278 * modes. Enabling ahci mode while MAP indicates
1279 * combined mode is a bad idea. Yield to ata_piix.
1281 pci_read_config_byte(pdev, ICH_MAP, &map);
1283 dev_info(&pdev->dev,
1284 "controller is in combined mode, can't enable AHCI mode\n");
1289 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1292 hpriv->flags |= (unsigned long)pi.private_data;
1294 /* MCP65 revision A1 and A2 can't do MSI */
1295 if (board_id == board_ahci_mcp65 &&
1296 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1297 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1299 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1300 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1301 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1303 /* only some SB600s can do 64bit DMA */
1304 if (ahci_sb600_enable_64bit(pdev))
1305 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1307 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1309 n_msis = ahci_init_interrupts(pdev, hpriv);
1311 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1313 /* save initial config */
1314 ahci_pci_save_initial_config(pdev, hpriv);
1317 if (hpriv->cap & HOST_CAP_NCQ) {
1318 pi.flags |= ATA_FLAG_NCQ;
1320 * Auto-activate optimization is supposed to be
1321 * supported on all AHCI controllers indicating NCQ
1322 * capability, but it seems to be broken on some
1323 * chipsets including NVIDIAs.
1325 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1326 pi.flags |= ATA_FLAG_FPDMA_AA;
1329 if (hpriv->cap & HOST_CAP_PMP)
1330 pi.flags |= ATA_FLAG_PMP;
1332 ahci_set_em_messages(hpriv, &pi);
1334 if (ahci_broken_system_poweroff(pdev)) {
1335 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1336 dev_info(&pdev->dev,
1337 "quirky BIOS, skipping spindown on poweroff\n");
1340 if (ahci_broken_suspend(pdev)) {
1341 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1342 dev_warn(&pdev->dev,
1343 "BIOS update required for suspend/resume\n");
1346 if (ahci_broken_online(pdev)) {
1347 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1348 dev_info(&pdev->dev,
1349 "online status unreliable, applying workaround\n");
1352 /* CAP.NP sometimes indicate the index of the last enabled
1353 * port, at other times, that of the last possible port, so
1354 * determining the maximum port number requires looking at
1355 * both CAP.NP and port_map.
1357 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1359 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1362 host->private_data = hpriv;
1364 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1365 host->flags |= ATA_HOST_PARALLEL_SCAN;
1367 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1369 if (pi.flags & ATA_FLAG_EM)
1370 ahci_reset_em(host);
1372 for (i = 0; i < host->n_ports; i++) {
1373 struct ata_port *ap = host->ports[i];
1375 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1376 ata_port_pbar_desc(ap, ahci_pci_bar,
1377 0x100 + ap->port_no * 0x80, "port");
1379 /* set enclosure management message type */
1380 if (ap->flags & ATA_FLAG_EM)
1381 ap->em_message_type = hpriv->em_msg_type;
1384 /* disabled/not-implemented port */
1385 if (!(hpriv->port_map & (1 << i)))
1386 ap->ops = &ata_dummy_port_ops;
1389 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1390 ahci_p5wdh_workaround(host);
1392 /* apply gtf filter quirk */
1393 ahci_gtf_filter_workaround(host);
1395 /* initialize adapter */
1396 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1400 rc = ahci_pci_reset_controller(host);
1404 ahci_pci_init_controller(host);
1405 ahci_pci_print_info(host);
1407 pci_set_master(pdev);
1409 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1410 return ahci_host_activate(host, pdev->irq, n_msis);
1412 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1416 module_pci_driver(ahci_pci_driver);
1418 MODULE_AUTHOR("Jeff Garzik");
1419 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1420 MODULE_LICENSE("GPL");
1421 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1422 MODULE_VERSION(DRV_VERSION);