2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
83 /* global controller registers */
84 HOST_CAP = 0x00, /* host capabilities */
85 HOST_CTL = 0x04, /* global host control */
86 HOST_IRQ_STAT = 0x08, /* interrupt status */
87 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
88 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91 HOST_RESET = (1 << 0), /* reset controller; self-clear */
92 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
93 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
97 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
98 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
99 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
100 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
102 /* registers for each SATA port */
103 PORT_LST_ADDR = 0x00, /* command list DMA addr */
104 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
105 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
106 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
107 PORT_IRQ_STAT = 0x10, /* interrupt status */
108 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
109 PORT_CMD = 0x18, /* port command */
110 PORT_TFDATA = 0x20, /* taskfile data */
111 PORT_SIG = 0x24, /* device TF signature */
112 PORT_CMD_ISSUE = 0x38, /* command issue */
113 PORT_SCR = 0x28, /* SATA phy register block */
114 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
115 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
116 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
117 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
119 /* PORT_IRQ_{STAT,MASK} bits */
120 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
121 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
122 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
123 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
124 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
125 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
126 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
127 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
129 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
130 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
131 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
132 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
133 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
134 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
135 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
136 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
137 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
139 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
146 PORT_IRQ_HBUS_DATA_ERR,
147 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
148 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
149 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
152 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
153 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
154 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
155 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
156 PORT_CMD_CLO = (1 << 3), /* Command list override */
157 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
158 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
159 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
161 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
162 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
163 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
164 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
166 /* hpriv->flags bits */
167 AHCI_FLAG_MSI = (1 << 0),
170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
174 struct ahci_cmd_hdr {
189 struct ahci_host_priv {
191 u32 cap; /* cache of HOST_CAP register */
192 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
195 struct ahci_port_priv {
196 struct ahci_cmd_hdr *cmd_slot;
197 dma_addr_t cmd_slot_dma;
199 dma_addr_t cmd_tbl_dma;
201 dma_addr_t rx_fis_dma;
204 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
205 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
206 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
207 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
208 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
209 static void ahci_irq_clear(struct ata_port *ap);
210 static int ahci_port_start(struct ata_port *ap);
211 static void ahci_port_stop(struct ata_port *ap);
212 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
213 static void ahci_qc_prep(struct ata_queued_cmd *qc);
214 static u8 ahci_check_status(struct ata_port *ap);
215 static void ahci_freeze(struct ata_port *ap);
216 static void ahci_thaw(struct ata_port *ap);
217 static void ahci_error_handler(struct ata_port *ap);
218 static void ahci_vt8251_error_handler(struct ata_port *ap);
219 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
220 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
221 static int ahci_port_resume(struct ata_port *ap);
222 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
223 static int ahci_pci_device_resume(struct pci_dev *pdev);
224 static void ahci_remove_one (struct pci_dev *pdev);
226 static struct scsi_host_template ahci_sht = {
227 .module = THIS_MODULE,
229 .ioctl = ata_scsi_ioctl,
230 .queuecommand = ata_scsi_queuecmd,
231 .change_queue_depth = ata_scsi_change_queue_depth,
232 .can_queue = AHCI_MAX_CMDS - 1,
233 .this_id = ATA_SHT_THIS_ID,
234 .sg_tablesize = AHCI_MAX_SG,
235 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
236 .emulated = ATA_SHT_EMULATED,
237 .use_clustering = AHCI_USE_CLUSTERING,
238 .proc_name = DRV_NAME,
239 .dma_boundary = AHCI_DMA_BOUNDARY,
240 .slave_configure = ata_scsi_slave_config,
241 .slave_destroy = ata_scsi_slave_destroy,
242 .bios_param = ata_std_bios_param,
243 .suspend = ata_scsi_device_suspend,
244 .resume = ata_scsi_device_resume,
247 static const struct ata_port_operations ahci_ops = {
248 .port_disable = ata_port_disable,
250 .check_status = ahci_check_status,
251 .check_altstatus = ahci_check_status,
252 .dev_select = ata_noop_dev_select,
254 .tf_read = ahci_tf_read,
256 .qc_prep = ahci_qc_prep,
257 .qc_issue = ahci_qc_issue,
259 .irq_handler = ahci_interrupt,
260 .irq_clear = ahci_irq_clear,
262 .scr_read = ahci_scr_read,
263 .scr_write = ahci_scr_write,
265 .freeze = ahci_freeze,
268 .error_handler = ahci_error_handler,
269 .post_internal_cmd = ahci_post_internal_cmd,
271 .port_suspend = ahci_port_suspend,
272 .port_resume = ahci_port_resume,
274 .port_start = ahci_port_start,
275 .port_stop = ahci_port_stop,
278 static const struct ata_port_operations ahci_vt8251_ops = {
279 .port_disable = ata_port_disable,
281 .check_status = ahci_check_status,
282 .check_altstatus = ahci_check_status,
283 .dev_select = ata_noop_dev_select,
285 .tf_read = ahci_tf_read,
287 .qc_prep = ahci_qc_prep,
288 .qc_issue = ahci_qc_issue,
290 .irq_handler = ahci_interrupt,
291 .irq_clear = ahci_irq_clear,
293 .scr_read = ahci_scr_read,
294 .scr_write = ahci_scr_write,
296 .freeze = ahci_freeze,
299 .error_handler = ahci_vt8251_error_handler,
300 .post_internal_cmd = ahci_post_internal_cmd,
302 .port_suspend = ahci_port_suspend,
303 .port_resume = ahci_port_resume,
305 .port_start = ahci_port_start,
306 .port_stop = ahci_port_stop,
309 static const struct ata_port_info ahci_port_info[] = {
313 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
314 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
315 ATA_FLAG_SKIP_D2H_BSY,
316 .pio_mask = 0x1f, /* pio0-4 */
317 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
318 .port_ops = &ahci_ops,
320 /* board_ahci_vt8251 */
323 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
324 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
325 ATA_FLAG_SKIP_D2H_BSY |
326 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
327 .pio_mask = 0x1f, /* pio0-4 */
328 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
329 .port_ops = &ahci_vt8251_ops,
331 /* board_ahci_ign_iferr */
334 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
335 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
336 ATA_FLAG_SKIP_D2H_BSY |
337 AHCI_FLAG_IGN_IRQ_IF_ERR,
338 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
340 .port_ops = &ahci_ops,
344 static const struct pci_device_id ahci_pci_tbl[] = {
346 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
347 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
348 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
349 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
350 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
351 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
352 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
353 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
354 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
355 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
356 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
357 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
358 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
359 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
360 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
361 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
362 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
363 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
364 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
365 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
366 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
367 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
368 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
369 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
370 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
371 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
374 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
375 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
376 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
377 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
378 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
381 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
382 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
385 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
388 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
389 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
390 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
391 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
392 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
398 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
399 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
402 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
403 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
404 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
406 /* Generic, PCI class code for AHCI */
407 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
408 0x010601, 0xffffff, board_ahci },
410 { } /* terminate list */
414 static struct pci_driver ahci_pci_driver = {
416 .id_table = ahci_pci_tbl,
417 .probe = ahci_init_one,
418 .suspend = ahci_pci_device_suspend,
419 .resume = ahci_pci_device_resume,
420 .remove = ahci_remove_one,
424 static inline int ahci_nr_ports(u32 cap)
426 return (cap & 0x1f) + 1;
429 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
431 return base + 0x100 + (port * 0x80);
434 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
436 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
439 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
444 case SCR_STATUS: sc_reg = 0; break;
445 case SCR_CONTROL: sc_reg = 1; break;
446 case SCR_ERROR: sc_reg = 2; break;
447 case SCR_ACTIVE: sc_reg = 3; break;
452 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
456 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
462 case SCR_STATUS: sc_reg = 0; break;
463 case SCR_CONTROL: sc_reg = 1; break;
464 case SCR_ERROR: sc_reg = 2; break;
465 case SCR_ACTIVE: sc_reg = 3; break;
470 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
473 static void ahci_start_engine(void __iomem *port_mmio)
478 tmp = readl(port_mmio + PORT_CMD);
479 tmp |= PORT_CMD_START;
480 writel(tmp, port_mmio + PORT_CMD);
481 readl(port_mmio + PORT_CMD); /* flush */
484 static int ahci_stop_engine(void __iomem *port_mmio)
488 tmp = readl(port_mmio + PORT_CMD);
490 /* check if the HBA is idle */
491 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
494 /* setting HBA to idle */
495 tmp &= ~PORT_CMD_START;
496 writel(tmp, port_mmio + PORT_CMD);
498 /* wait for engine to stop. This could be as long as 500 msec */
499 tmp = ata_wait_register(port_mmio + PORT_CMD,
500 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
501 if (tmp & PORT_CMD_LIST_ON)
507 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
508 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
512 /* set FIS registers */
513 if (cap & HOST_CAP_64)
514 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
515 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
517 if (cap & HOST_CAP_64)
518 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
519 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
521 /* enable FIS reception */
522 tmp = readl(port_mmio + PORT_CMD);
523 tmp |= PORT_CMD_FIS_RX;
524 writel(tmp, port_mmio + PORT_CMD);
527 readl(port_mmio + PORT_CMD);
530 static int ahci_stop_fis_rx(void __iomem *port_mmio)
534 /* disable FIS reception */
535 tmp = readl(port_mmio + PORT_CMD);
536 tmp &= ~PORT_CMD_FIS_RX;
537 writel(tmp, port_mmio + PORT_CMD);
539 /* wait for completion, spec says 500ms, give it 1000 */
540 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
541 PORT_CMD_FIS_ON, 10, 1000);
542 if (tmp & PORT_CMD_FIS_ON)
548 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
552 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
555 if (cap & HOST_CAP_SSS) {
556 cmd |= PORT_CMD_SPIN_UP;
557 writel(cmd, port_mmio + PORT_CMD);
561 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
564 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
568 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
570 if (cap & HOST_CAP_SSC) {
571 /* enable transitions to slumber mode */
572 scontrol = readl(port_mmio + PORT_SCR_CTL);
573 if ((scontrol & 0x0f00) > 0x100) {
575 writel(scontrol, port_mmio + PORT_SCR_CTL);
578 /* put device into slumber mode */
579 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
581 /* wait for the transition to complete */
582 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
583 PORT_CMD_ICC_SLUMBER, 1, 50);
586 /* put device into listen mode */
587 if (cap & HOST_CAP_SSS) {
588 /* first set PxSCTL.DET to 0 */
589 scontrol = readl(port_mmio + PORT_SCR_CTL);
591 writel(scontrol, port_mmio + PORT_SCR_CTL);
593 /* then set PxCMD.SUD to 0 */
594 cmd &= ~PORT_CMD_SPIN_UP;
595 writel(cmd, port_mmio + PORT_CMD);
599 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
600 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
603 ahci_power_up(port_mmio, cap);
605 /* enable FIS reception */
606 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
609 ahci_start_engine(port_mmio);
612 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
617 rc = ahci_stop_engine(port_mmio);
619 *emsg = "failed to stop engine";
623 /* disable FIS reception */
624 rc = ahci_stop_fis_rx(port_mmio);
626 *emsg = "failed stop FIS RX";
630 /* put device into slumber mode */
631 ahci_power_down(port_mmio, cap);
636 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
638 u32 cap_save, impl_save, tmp;
640 cap_save = readl(mmio + HOST_CAP);
641 cap_save &= ( (1<<28) | (1<<17) );
642 cap_save |= (1 << 27);
643 impl_save = readl(mmio + HOST_PORTS_IMPL);
645 /* global controller reset */
646 tmp = readl(mmio + HOST_CTL);
647 if ((tmp & HOST_RESET) == 0) {
648 writel(tmp | HOST_RESET, mmio + HOST_CTL);
649 readl(mmio + HOST_CTL); /* flush */
652 /* reset must complete within 1 second, or
653 * the hardware should be considered fried.
657 tmp = readl(mmio + HOST_CTL);
658 if (tmp & HOST_RESET) {
659 dev_printk(KERN_ERR, &pdev->dev,
660 "controller reset failed (0x%x)\n", tmp);
664 /* turn on AHCI mode */
665 writel(HOST_AHCI_EN, mmio + HOST_CTL);
666 (void) readl(mmio + HOST_CTL); /* flush */
668 /* These write-once registers are normally cleared on reset.
669 * Restore BIOS values... which we HOPE were present before
673 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
674 dev_printk(KERN_WARNING, &pdev->dev,
675 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
677 writel(cap_save, mmio + HOST_CAP);
678 writel(impl_save, mmio + HOST_PORTS_IMPL);
679 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
681 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
685 pci_read_config_word(pdev, 0x92, &tmp16);
687 pci_write_config_word(pdev, 0x92, tmp16);
693 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
694 int n_ports, u32 cap)
699 for (i = 0; i < n_ports; i++) {
700 void __iomem *port_mmio = ahci_port_base(mmio, i);
701 const char *emsg = NULL;
703 #if 0 /* BIOSen initialize this incorrectly */
704 if (!(hpriv->port_map & (1 << i)))
708 /* make sure port is not active */
709 rc = ahci_deinit_port(port_mmio, cap, &emsg);
711 dev_printk(KERN_WARNING, &pdev->dev,
712 "%s (%d)\n", emsg, rc);
715 tmp = readl(port_mmio + PORT_SCR_ERR);
716 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
717 writel(tmp, port_mmio + PORT_SCR_ERR);
720 tmp = readl(port_mmio + PORT_IRQ_STAT);
721 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
723 writel(tmp, port_mmio + PORT_IRQ_STAT);
725 writel(1 << i, mmio + HOST_IRQ_STAT);
728 tmp = readl(mmio + HOST_CTL);
729 VPRINTK("HOST_CTL 0x%x\n", tmp);
730 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
731 tmp = readl(mmio + HOST_CTL);
732 VPRINTK("HOST_CTL 0x%x\n", tmp);
735 static unsigned int ahci_dev_classify(struct ata_port *ap)
737 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
738 struct ata_taskfile tf;
741 tmp = readl(port_mmio + PORT_SIG);
742 tf.lbah = (tmp >> 24) & 0xff;
743 tf.lbam = (tmp >> 16) & 0xff;
744 tf.lbal = (tmp >> 8) & 0xff;
745 tf.nsect = (tmp) & 0xff;
747 return ata_dev_classify(&tf);
750 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
753 dma_addr_t cmd_tbl_dma;
755 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
757 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
758 pp->cmd_slot[tag].status = 0;
759 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
760 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
763 static int ahci_clo(struct ata_port *ap)
765 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
766 struct ahci_host_priv *hpriv = ap->host->private_data;
769 if (!(hpriv->cap & HOST_CAP_CLO))
772 tmp = readl(port_mmio + PORT_CMD);
774 writel(tmp, port_mmio + PORT_CMD);
776 tmp = ata_wait_register(port_mmio + PORT_CMD,
777 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
778 if (tmp & PORT_CMD_CLO)
784 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
786 struct ahci_port_priv *pp = ap->private_data;
787 void __iomem *mmio = ap->host->mmio_base;
788 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
789 const u32 cmd_fis_len = 5; /* five dwords */
790 const char *reason = NULL;
791 struct ata_taskfile tf;
798 if (ata_port_offline(ap)) {
799 DPRINTK("PHY reports no device\n");
800 *class = ATA_DEV_NONE;
804 /* prepare for SRST (AHCI-1.1 10.4.1) */
805 rc = ahci_stop_engine(port_mmio);
807 reason = "failed to stop engine";
811 /* check BUSY/DRQ, perform Command List Override if necessary */
812 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
815 if (rc == -EOPNOTSUPP) {
816 reason = "port busy but CLO unavailable";
819 reason = "port busy but CLO failed";
825 ahci_start_engine(port_mmio);
827 ata_tf_init(ap->device, &tf);
830 /* issue the first D2H Register FIS */
831 ahci_fill_cmd_slot(pp, 0,
832 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
835 ata_tf_to_fis(&tf, fis, 0);
836 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
838 writel(1, port_mmio + PORT_CMD_ISSUE);
840 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
843 reason = "1st FIS failed";
847 /* spec says at least 5us, but be generous and sleep for 1ms */
850 /* issue the second D2H Register FIS */
851 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
854 ata_tf_to_fis(&tf, fis, 0);
855 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
857 writel(1, port_mmio + PORT_CMD_ISSUE);
858 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
860 /* spec mandates ">= 2ms" before checking status.
861 * We wait 150ms, because that was the magic delay used for
862 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
863 * between when the ATA command register is written, and then
864 * status is checked. Because waiting for "a while" before
865 * checking status is fine, post SRST, we perform this magic
866 * delay here as well.
870 *class = ATA_DEV_NONE;
871 if (ata_port_online(ap)) {
872 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
874 reason = "device not ready";
877 *class = ahci_dev_classify(ap);
880 DPRINTK("EXIT, class=%u\n", *class);
884 ahci_start_engine(port_mmio);
886 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
890 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
892 struct ahci_port_priv *pp = ap->private_data;
893 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
894 struct ata_taskfile tf;
895 void __iomem *mmio = ap->host->mmio_base;
896 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
901 ahci_stop_engine(port_mmio);
903 /* clear D2H reception area to properly wait for D2H FIS */
904 ata_tf_init(ap->device, &tf);
906 ata_tf_to_fis(&tf, d2h_fis, 0);
908 rc = sata_std_hardreset(ap, class);
910 ahci_start_engine(port_mmio);
912 if (rc == 0 && ata_port_online(ap))
913 *class = ahci_dev_classify(ap);
914 if (*class == ATA_DEV_UNKNOWN)
915 *class = ATA_DEV_NONE;
917 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
921 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
923 void __iomem *mmio = ap->host->mmio_base;
924 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
929 ahci_stop_engine(port_mmio);
931 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
933 /* vt8251 needs SError cleared for the port to operate */
934 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
936 ahci_start_engine(port_mmio);
938 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
940 /* vt8251 doesn't clear BSY on signature FIS reception,
941 * request follow-up softreset.
943 return rc ?: -EAGAIN;
946 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
948 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
951 ata_std_postreset(ap, class);
953 /* Make sure port's ATAPI bit is set appropriately */
954 new_tmp = tmp = readl(port_mmio + PORT_CMD);
955 if (*class == ATA_DEV_ATAPI)
956 new_tmp |= PORT_CMD_ATAPI;
958 new_tmp &= ~PORT_CMD_ATAPI;
959 if (new_tmp != tmp) {
960 writel(new_tmp, port_mmio + PORT_CMD);
961 readl(port_mmio + PORT_CMD); /* flush */
965 static u8 ahci_check_status(struct ata_port *ap)
967 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
969 return readl(mmio + PORT_TFDATA) & 0xFF;
972 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
974 struct ahci_port_priv *pp = ap->private_data;
975 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
977 ata_tf_from_fis(d2h_fis, tf);
980 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
982 struct scatterlist *sg;
983 struct ahci_sg *ahci_sg;
984 unsigned int n_sg = 0;
989 * Next, the S/G list.
991 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
992 ata_for_each_sg(sg, qc) {
993 dma_addr_t addr = sg_dma_address(sg);
994 u32 sg_len = sg_dma_len(sg);
996 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
997 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
998 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1007 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1009 struct ata_port *ap = qc->ap;
1010 struct ahci_port_priv *pp = ap->private_data;
1011 int is_atapi = is_atapi_taskfile(&qc->tf);
1014 const u32 cmd_fis_len = 5; /* five dwords */
1015 unsigned int n_elem;
1018 * Fill in command table information. First, the header,
1019 * a SATA Register - Host to Device command FIS.
1021 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1023 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1025 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1026 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1030 if (qc->flags & ATA_QCFLAG_DMAMAP)
1031 n_elem = ahci_fill_sg(qc, cmd_tbl);
1034 * Fill in command slot information.
1036 opts = cmd_fis_len | n_elem << 16;
1037 if (qc->tf.flags & ATA_TFLAG_WRITE)
1038 opts |= AHCI_CMD_WRITE;
1040 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1042 ahci_fill_cmd_slot(pp, qc->tag, opts);
1045 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1047 struct ahci_port_priv *pp = ap->private_data;
1048 struct ata_eh_info *ehi = &ap->eh_info;
1049 unsigned int err_mask = 0, action = 0;
1050 struct ata_queued_cmd *qc;
1053 ata_ehi_clear_desc(ehi);
1055 /* AHCI needs SError cleared; otherwise, it might lock up */
1056 serror = ahci_scr_read(ap, SCR_ERROR);
1057 ahci_scr_write(ap, SCR_ERROR, serror);
1059 /* analyze @irq_stat */
1060 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1062 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1063 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1064 irq_stat &= ~PORT_IRQ_IF_ERR;
1066 if (irq_stat & PORT_IRQ_TF_ERR)
1067 err_mask |= AC_ERR_DEV;
1069 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1070 err_mask |= AC_ERR_HOST_BUS;
1071 action |= ATA_EH_SOFTRESET;
1074 if (irq_stat & PORT_IRQ_IF_ERR) {
1075 err_mask |= AC_ERR_ATA_BUS;
1076 action |= ATA_EH_SOFTRESET;
1077 ata_ehi_push_desc(ehi, ", interface fatal error");
1080 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1081 ata_ehi_hotplugged(ehi);
1082 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1083 "connection status changed" : "PHY RDY changed");
1086 if (irq_stat & PORT_IRQ_UNK_FIS) {
1087 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1089 err_mask |= AC_ERR_HSM;
1090 action |= ATA_EH_SOFTRESET;
1091 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1092 unk[0], unk[1], unk[2], unk[3]);
1095 /* okay, let's hand over to EH */
1096 ehi->serror |= serror;
1097 ehi->action |= action;
1099 qc = ata_qc_from_tag(ap, ap->active_tag);
1101 qc->err_mask |= err_mask;
1103 ehi->err_mask |= err_mask;
1105 if (irq_stat & PORT_IRQ_FREEZE)
1106 ata_port_freeze(ap);
1111 static void ahci_host_intr(struct ata_port *ap)
1113 void __iomem *mmio = ap->host->mmio_base;
1114 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1115 struct ata_eh_info *ehi = &ap->eh_info;
1116 u32 status, qc_active;
1119 status = readl(port_mmio + PORT_IRQ_STAT);
1120 writel(status, port_mmio + PORT_IRQ_STAT);
1122 if (unlikely(status & PORT_IRQ_ERROR)) {
1123 ahci_error_intr(ap, status);
1128 qc_active = readl(port_mmio + PORT_SCR_ACT);
1130 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1132 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1136 ehi->err_mask |= AC_ERR_HSM;
1137 ehi->action |= ATA_EH_SOFTRESET;
1138 ata_port_freeze(ap);
1142 /* hmmm... a spurious interupt */
1144 /* some devices send D2H reg with I bit set during NCQ command phase */
1145 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1148 /* ignore interim PIO setup fis interrupts */
1149 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1152 if (ata_ratelimit())
1153 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1154 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1155 status, ap->active_tag, ap->sactive);
1158 static void ahci_irq_clear(struct ata_port *ap)
1163 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1165 struct ata_host *host = dev_instance;
1166 struct ahci_host_priv *hpriv;
1167 unsigned int i, handled = 0;
1169 u32 irq_stat, irq_ack = 0;
1173 hpriv = host->private_data;
1174 mmio = host->mmio_base;
1176 /* sigh. 0xffffffff is a valid return from h/w */
1177 irq_stat = readl(mmio + HOST_IRQ_STAT);
1178 irq_stat &= hpriv->port_map;
1182 spin_lock(&host->lock);
1184 for (i = 0; i < host->n_ports; i++) {
1185 struct ata_port *ap;
1187 if (!(irq_stat & (1 << i)))
1190 ap = host->ports[i];
1193 VPRINTK("port %u\n", i);
1195 VPRINTK("port %u (no irq)\n", i);
1196 if (ata_ratelimit())
1197 dev_printk(KERN_WARNING, host->dev,
1198 "interrupt on disabled port %u\n", i);
1201 irq_ack |= (1 << i);
1205 writel(irq_ack, mmio + HOST_IRQ_STAT);
1209 spin_unlock(&host->lock);
1213 return IRQ_RETVAL(handled);
1216 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1218 struct ata_port *ap = qc->ap;
1219 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1221 if (qc->tf.protocol == ATA_PROT_NCQ)
1222 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1223 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1224 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1229 static void ahci_freeze(struct ata_port *ap)
1231 void __iomem *mmio = ap->host->mmio_base;
1232 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1235 writel(0, port_mmio + PORT_IRQ_MASK);
1238 static void ahci_thaw(struct ata_port *ap)
1240 void __iomem *mmio = ap->host->mmio_base;
1241 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1245 tmp = readl(port_mmio + PORT_IRQ_STAT);
1246 writel(tmp, port_mmio + PORT_IRQ_STAT);
1247 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1249 /* turn IRQ back on */
1250 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1253 static void ahci_error_handler(struct ata_port *ap)
1255 void __iomem *mmio = ap->host->mmio_base;
1256 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1258 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1259 /* restart engine */
1260 ahci_stop_engine(port_mmio);
1261 ahci_start_engine(port_mmio);
1264 /* perform recovery */
1265 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1269 static void ahci_vt8251_error_handler(struct ata_port *ap)
1271 void __iomem *mmio = ap->host->mmio_base;
1272 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1274 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1275 /* restart engine */
1276 ahci_stop_engine(port_mmio);
1277 ahci_start_engine(port_mmio);
1280 /* perform recovery */
1281 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1285 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1287 struct ata_port *ap = qc->ap;
1288 void __iomem *mmio = ap->host->mmio_base;
1289 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1291 if (qc->flags & ATA_QCFLAG_FAILED)
1292 qc->err_mask |= AC_ERR_OTHER;
1295 /* make DMA engine forget about the failed command */
1296 ahci_stop_engine(port_mmio);
1297 ahci_start_engine(port_mmio);
1301 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1303 struct ahci_host_priv *hpriv = ap->host->private_data;
1304 struct ahci_port_priv *pp = ap->private_data;
1305 void __iomem *mmio = ap->host->mmio_base;
1306 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1307 const char *emsg = NULL;
1310 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1312 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1313 ahci_init_port(port_mmio, hpriv->cap,
1314 pp->cmd_slot_dma, pp->rx_fis_dma);
1320 static int ahci_port_resume(struct ata_port *ap)
1322 struct ahci_port_priv *pp = ap->private_data;
1323 struct ahci_host_priv *hpriv = ap->host->private_data;
1324 void __iomem *mmio = ap->host->mmio_base;
1325 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1327 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1332 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1334 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1335 void __iomem *mmio = host->mmio_base;
1338 if (mesg.event == PM_EVENT_SUSPEND) {
1339 /* AHCI spec rev1.1 section 8.3.3:
1340 * Software must disable interrupts prior to requesting a
1341 * transition of the HBA to D3 state.
1343 ctl = readl(mmio + HOST_CTL);
1344 ctl &= ~HOST_IRQ_EN;
1345 writel(ctl, mmio + HOST_CTL);
1346 readl(mmio + HOST_CTL); /* flush */
1349 return ata_pci_device_suspend(pdev, mesg);
1352 static int ahci_pci_device_resume(struct pci_dev *pdev)
1354 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1355 struct ahci_host_priv *hpriv = host->private_data;
1356 void __iomem *mmio = host->mmio_base;
1359 ata_pci_device_do_resume(pdev);
1361 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1362 rc = ahci_reset_controller(mmio, pdev);
1366 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
1369 ata_host_resume(host);
1374 static int ahci_port_start(struct ata_port *ap)
1376 struct device *dev = ap->host->dev;
1377 struct ahci_host_priv *hpriv = ap->host->private_data;
1378 struct ahci_port_priv *pp;
1379 void __iomem *mmio = ap->host->mmio_base;
1380 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1385 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1388 memset(pp, 0, sizeof(*pp));
1390 rc = ata_pad_alloc(ap, dev);
1396 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1398 ata_pad_free(ap, dev);
1402 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1405 * First item in chunk of DMA memory: 32-slot command table,
1406 * 32 bytes each in size
1409 pp->cmd_slot_dma = mem_dma;
1411 mem += AHCI_CMD_SLOT_SZ;
1412 mem_dma += AHCI_CMD_SLOT_SZ;
1415 * Second item: Received-FIS area
1418 pp->rx_fis_dma = mem_dma;
1420 mem += AHCI_RX_FIS_SZ;
1421 mem_dma += AHCI_RX_FIS_SZ;
1424 * Third item: data area for storing a single command
1425 * and its scatter-gather table
1428 pp->cmd_tbl_dma = mem_dma;
1430 ap->private_data = pp;
1432 /* initialize port */
1433 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1438 static void ahci_port_stop(struct ata_port *ap)
1440 struct device *dev = ap->host->dev;
1441 struct ahci_host_priv *hpriv = ap->host->private_data;
1442 struct ahci_port_priv *pp = ap->private_data;
1443 void __iomem *mmio = ap->host->mmio_base;
1444 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1445 const char *emsg = NULL;
1448 /* de-initialize port */
1449 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1451 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1453 ap->private_data = NULL;
1454 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1455 pp->cmd_slot, pp->cmd_slot_dma);
1456 ata_pad_free(ap, dev);
1460 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1461 unsigned int port_idx)
1463 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1464 base = ahci_port_base_ul(base, port_idx);
1465 VPRINTK("base now==0x%lx\n", base);
1467 port->cmd_addr = base;
1468 port->scr_addr = base + PORT_SCR;
1473 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1475 struct ahci_host_priv *hpriv = probe_ent->private_data;
1476 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1477 void __iomem *mmio = probe_ent->mmio_base;
1478 unsigned int i, using_dac;
1481 rc = ahci_reset_controller(mmio, pdev);
1485 hpriv->cap = readl(mmio + HOST_CAP);
1486 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1487 probe_ent->n_ports = ahci_nr_ports(hpriv->cap);
1489 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1490 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1492 using_dac = hpriv->cap & HOST_CAP_64;
1494 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1495 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1497 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1499 dev_printk(KERN_ERR, &pdev->dev,
1500 "64-bit DMA enable failed\n");
1505 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1507 dev_printk(KERN_ERR, &pdev->dev,
1508 "32-bit DMA enable failed\n");
1511 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1513 dev_printk(KERN_ERR, &pdev->dev,
1514 "32-bit consistent DMA enable failed\n");
1519 for (i = 0; i < probe_ent->n_ports; i++)
1520 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1522 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1524 pci_set_master(pdev);
1529 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1531 struct ahci_host_priv *hpriv = probe_ent->private_data;
1532 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1533 void __iomem *mmio = probe_ent->mmio_base;
1534 u32 vers, cap, impl, speed;
1535 const char *speed_s;
1539 vers = readl(mmio + HOST_VERSION);
1541 impl = hpriv->port_map;
1543 speed = (cap >> 20) & 0xf;
1546 else if (speed == 2)
1551 pci_read_config_word(pdev, 0x0a, &cc);
1554 else if (cc == 0x0106)
1556 else if (cc == 0x0104)
1561 dev_printk(KERN_INFO, &pdev->dev,
1562 "AHCI %02x%02x.%02x%02x "
1563 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1566 (vers >> 24) & 0xff,
1567 (vers >> 16) & 0xff,
1571 ((cap >> 8) & 0x1f) + 1,
1577 dev_printk(KERN_INFO, &pdev->dev,
1583 cap & (1 << 31) ? "64bit " : "",
1584 cap & (1 << 30) ? "ncq " : "",
1585 cap & (1 << 28) ? "ilck " : "",
1586 cap & (1 << 27) ? "stag " : "",
1587 cap & (1 << 26) ? "pm " : "",
1588 cap & (1 << 25) ? "led " : "",
1590 cap & (1 << 24) ? "clo " : "",
1591 cap & (1 << 19) ? "nz " : "",
1592 cap & (1 << 18) ? "only " : "",
1593 cap & (1 << 17) ? "pmp " : "",
1594 cap & (1 << 15) ? "pio " : "",
1595 cap & (1 << 14) ? "slum " : "",
1596 cap & (1 << 13) ? "part " : ""
1600 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1602 static int printed_version;
1603 struct ata_probe_ent *probe_ent = NULL;
1604 struct ahci_host_priv *hpriv;
1606 void __iomem *mmio_base;
1607 unsigned int board_idx = (unsigned int) ent->driver_data;
1608 int have_msi, pci_dev_busy = 0;
1613 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1615 if (!printed_version++)
1616 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1618 /* JMicron-specific fixup: make sure we're in AHCI mode */
1619 /* This is protected from races with ata_jmicron by the pci probe
1621 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1622 /* AHCI enable, AHCI on function 0 */
1623 pci_write_config_byte(pdev, 0x41, 0xa1);
1624 /* Function 1 is the PATA controller */
1625 if (PCI_FUNC(pdev->devfn))
1629 rc = pci_enable_device(pdev);
1633 rc = pci_request_regions(pdev, DRV_NAME);
1639 if (pci_enable_msi(pdev) == 0)
1646 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1647 if (probe_ent == NULL) {
1652 memset(probe_ent, 0, sizeof(*probe_ent));
1653 probe_ent->dev = pci_dev_to_dev(pdev);
1654 INIT_LIST_HEAD(&probe_ent->node);
1656 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1657 if (mmio_base == NULL) {
1659 goto err_out_free_ent;
1661 base = (unsigned long) mmio_base;
1663 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1666 goto err_out_iounmap;
1668 memset(hpriv, 0, sizeof(*hpriv));
1670 probe_ent->sht = ahci_port_info[board_idx].sht;
1671 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1672 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1673 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1674 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1676 probe_ent->irq = pdev->irq;
1677 probe_ent->irq_flags = IRQF_SHARED;
1678 probe_ent->mmio_base = mmio_base;
1679 probe_ent->private_data = hpriv;
1682 hpriv->flags |= AHCI_FLAG_MSI;
1684 /* initialize adapter */
1685 rc = ahci_host_init(probe_ent);
1689 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1690 (hpriv->cap & HOST_CAP_NCQ))
1691 probe_ent->port_flags |= ATA_FLAG_NCQ;
1693 ahci_print_info(probe_ent);
1695 /* FIXME: check ata_device_add return value */
1696 ata_device_add(probe_ent);
1704 pci_iounmap(pdev, mmio_base);
1709 pci_disable_msi(pdev);
1712 pci_release_regions(pdev);
1715 pci_disable_device(pdev);
1719 static void ahci_remove_one (struct pci_dev *pdev)
1721 struct device *dev = pci_dev_to_dev(pdev);
1722 struct ata_host *host = dev_get_drvdata(dev);
1723 struct ahci_host_priv *hpriv = host->private_data;
1727 for (i = 0; i < host->n_ports; i++)
1728 ata_port_detach(host->ports[i]);
1730 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1731 free_irq(host->irq, host);
1733 for (i = 0; i < host->n_ports; i++) {
1734 struct ata_port *ap = host->ports[i];
1736 ata_scsi_release(ap->scsi_host);
1737 scsi_host_put(ap->scsi_host);
1741 pci_iounmap(pdev, host->mmio_base);
1745 pci_disable_msi(pdev);
1748 pci_release_regions(pdev);
1749 pci_disable_device(pdev);
1750 dev_set_drvdata(dev, NULL);
1753 static int __init ahci_init(void)
1755 return pci_register_driver(&ahci_pci_driver);
1758 static void __exit ahci_exit(void)
1760 pci_unregister_driver(&ahci_pci_driver);
1764 MODULE_AUTHOR("Jeff Garzik");
1765 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1766 MODULE_LICENSE("GPL");
1767 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1768 MODULE_VERSION(DRV_VERSION);
1770 module_init(ahci_init);
1771 module_exit(ahci_exit);