2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 static struct scsi_host_template ahci_sht = {
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
108 static const struct ata_port_info ahci_port_info[] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
116 [board_ahci_ign_iferr] = {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
123 [board_ahci_noncq] = {
124 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
130 [board_ahci_nosntf] = {
131 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
137 [board_ahci_yes_fbs] = {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
145 [board_ahci_mcp65] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
153 [board_ahci_mcp77] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
160 [board_ahci_mcp89] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
175 [board_ahci_sb600] = {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
184 [board_ahci_sb700] = { /* for SB700 and SB800 */
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_pmp_retry_srst_ops,
191 [board_ahci_vt8251] = {
192 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_vt8251_ops,
200 static const struct pci_device_id ahci_pci_tbl[] = {
202 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
203 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
204 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
205 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
206 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
207 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
208 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
209 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
212 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
213 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
216 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
230 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
232 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
237 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
245 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
249 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
250 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
253 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
256 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
261 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
263 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
269 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
271 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
295 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
299 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
303 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
305 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
308 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
309 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
310 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
311 /* JMicron 362B and 362C have an AHCI function with IDE class code */
312 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
313 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
316 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
317 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
325 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
326 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
327 /* AMD is using RAID class only for ahci controllers */
328 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
329 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
332 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
333 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
336 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
426 /* ST Microelectronics */
427 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
430 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
431 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
433 .class = PCI_CLASS_STORAGE_SATA_AHCI,
434 .class_mask = 0xffffff,
435 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
438 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
439 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
440 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
442 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
448 .driver_data = board_ahci_yes_fbs },
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
450 .driver_data = board_ahci_yes_fbs },
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
452 .driver_data = board_ahci_yes_fbs },
453 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
454 .driver_data = board_ahci_yes_fbs },
457 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
460 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
461 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
462 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
463 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
466 * Samsung SSDs found on some macbooks. NCQ times out.
467 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
469 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
472 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
474 /* Generic, PCI class code for AHCI */
475 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
476 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
478 { } /* terminate list */
482 static struct pci_driver ahci_pci_driver = {
484 .id_table = ahci_pci_tbl,
485 .probe = ahci_init_one,
486 .remove = ata_pci_remove_one,
488 .suspend = ahci_pci_device_suspend,
489 .resume = ahci_pci_device_resume,
493 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
494 static int marvell_enable;
496 static int marvell_enable = 1;
498 module_param(marvell_enable, int, 0644);
499 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
502 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
503 struct ahci_host_priv *hpriv)
505 unsigned int force_port_map = 0;
506 unsigned int mask_port_map = 0;
508 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
509 dev_info(&pdev->dev, "JMB361 has only one port\n");
514 * Temporary Marvell 6145 hack: PATA port presence
515 * is asserted through the standard AHCI port
516 * presence register, as bit 4 (counting from 0)
518 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
519 if (pdev->device == 0x6121)
524 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
527 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
531 static int ahci_pci_reset_controller(struct ata_host *host)
533 struct pci_dev *pdev = to_pci_dev(host->dev);
535 ahci_reset_controller(host);
537 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
538 struct ahci_host_priv *hpriv = host->private_data;
542 pci_read_config_word(pdev, 0x92, &tmp16);
543 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
544 tmp16 |= hpriv->port_map;
545 pci_write_config_word(pdev, 0x92, tmp16);
552 static void ahci_pci_init_controller(struct ata_host *host)
554 struct ahci_host_priv *hpriv = host->private_data;
555 struct pci_dev *pdev = to_pci_dev(host->dev);
556 void __iomem *port_mmio;
560 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
561 if (pdev->device == 0x6121)
565 port_mmio = __ahci_port_base(host, mv);
567 writel(0, port_mmio + PORT_IRQ_MASK);
570 tmp = readl(port_mmio + PORT_IRQ_STAT);
571 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
573 writel(tmp, port_mmio + PORT_IRQ_STAT);
576 ahci_init_controller(host);
579 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
580 unsigned long deadline)
582 struct ata_port *ap = link->ap;
588 ahci_stop_engine(ap);
590 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
591 deadline, &online, NULL);
593 ahci_start_engine(ap);
595 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
597 /* vt8251 doesn't clear BSY on signature FIS reception,
598 * request follow-up softreset.
600 return online ? -EAGAIN : rc;
603 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
604 unsigned long deadline)
606 struct ata_port *ap = link->ap;
607 struct ahci_port_priv *pp = ap->private_data;
608 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
609 struct ata_taskfile tf;
613 ahci_stop_engine(ap);
615 /* clear D2H reception area to properly wait for D2H FIS */
616 ata_tf_init(link->device, &tf);
618 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
620 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
621 deadline, &online, NULL);
623 ahci_start_engine(ap);
625 /* The pseudo configuration device on SIMG4726 attached to
626 * ASUS P5W-DH Deluxe doesn't send signature FIS after
627 * hardreset if no device is attached to the first downstream
628 * port && the pseudo device locks up on SRST w/ PMP==0. To
629 * work around this, wait for !BSY only briefly. If BSY isn't
630 * cleared, perform CLO and proceed to IDENTIFY (achieved by
631 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
633 * Wait for two seconds. Devices attached to downstream port
634 * which can't process the following IDENTIFY after this will
635 * have to be reset again. For most cases, this should
636 * suffice while making probing snappish enough.
639 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
642 ahci_kick_engine(ap);
648 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
650 struct ata_host *host = dev_get_drvdata(&pdev->dev);
651 struct ahci_host_priv *hpriv = host->private_data;
652 void __iomem *mmio = hpriv->mmio;
655 if (mesg.event & PM_EVENT_SUSPEND &&
656 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
658 "BIOS update required for suspend/resume\n");
662 if (mesg.event & PM_EVENT_SLEEP) {
663 /* AHCI spec rev1.1 section 8.3.3:
664 * Software must disable interrupts prior to requesting a
665 * transition of the HBA to D3 state.
667 ctl = readl(mmio + HOST_CTL);
669 writel(ctl, mmio + HOST_CTL);
670 readl(mmio + HOST_CTL); /* flush */
673 return ata_pci_device_suspend(pdev, mesg);
676 static int ahci_pci_device_resume(struct pci_dev *pdev)
678 struct ata_host *host = dev_get_drvdata(&pdev->dev);
681 rc = ata_pci_device_do_resume(pdev);
685 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
686 rc = ahci_pci_reset_controller(host);
690 ahci_pci_init_controller(host);
693 ata_host_resume(host);
699 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
704 * If the device fixup already set the dma_mask to some non-standard
705 * value, don't extend it here. This happens on STA2X11, for example.
707 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
711 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
712 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
714 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
717 "64-bit DMA enable failed\n");
722 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
724 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
727 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
730 "32-bit consistent DMA enable failed\n");
737 static void ahci_pci_print_info(struct ata_host *host)
739 struct pci_dev *pdev = to_pci_dev(host->dev);
743 pci_read_config_word(pdev, 0x0a, &cc);
744 if (cc == PCI_CLASS_STORAGE_IDE)
746 else if (cc == PCI_CLASS_STORAGE_SATA)
748 else if (cc == PCI_CLASS_STORAGE_RAID)
753 ahci_print_info(host, scc_s);
756 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
757 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
758 * support PMP and the 4726 either directly exports the device
759 * attached to the first downstream port or acts as a hardware storage
760 * controller and emulate a single ATA device (can be RAID 0/1 or some
761 * other configuration).
763 * When there's no device attached to the first downstream port of the
764 * 4726, "Config Disk" appears, which is a pseudo ATA device to
765 * configure the 4726. However, ATA emulation of the device is very
766 * lame. It doesn't send signature D2H Reg FIS after the initial
767 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
769 * The following function works around the problem by always using
770 * hardreset on the port and not depending on receiving signature FIS
771 * afterward. If signature FIS isn't received soon, ATA class is
772 * assumed without follow-up softreset.
774 static void ahci_p5wdh_workaround(struct ata_host *host)
776 static struct dmi_system_id sysids[] = {
778 .ident = "P5W DH Deluxe",
780 DMI_MATCH(DMI_SYS_VENDOR,
781 "ASUSTEK COMPUTER INC"),
782 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
787 struct pci_dev *pdev = to_pci_dev(host->dev);
789 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
790 dmi_check_system(sysids)) {
791 struct ata_port *ap = host->ports[1];
794 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
796 ap->ops = &ahci_p5wdh_ops;
797 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
801 /* only some SB600 ahci controllers can do 64bit DMA */
802 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
804 static const struct dmi_system_id sysids[] = {
806 * The oldest version known to be broken is 0901 and
807 * working is 1501 which was released on 2007-10-26.
808 * Enable 64bit DMA on 1501 and anything newer.
810 * Please read bko#9412 for more info.
813 .ident = "ASUS M2A-VM",
815 DMI_MATCH(DMI_BOARD_VENDOR,
816 "ASUSTeK Computer INC."),
817 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
819 .driver_data = "20071026", /* yyyymmdd */
822 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
825 * BIOS versions earlier than 1.5 had the Manufacturer DMI
826 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
827 * This spelling mistake was fixed in BIOS version 1.5, so
828 * 1.5 and later have the Manufacturer as
829 * "MICRO-STAR INTERNATIONAL CO.,LTD".
830 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
832 * BIOS versions earlier than 1.9 had a Board Product Name
833 * DMI field of "MS-7376". This was changed to be
834 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
835 * match on DMI_BOARD_NAME of "MS-7376".
838 .ident = "MSI K9A2 Platinum",
840 DMI_MATCH(DMI_BOARD_VENDOR,
842 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
846 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
849 * This board also had the typo mentioned above in the
850 * Manufacturer DMI field (fixed in BIOS version 1.5), so
851 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
854 .ident = "MSI K9AGM2",
856 DMI_MATCH(DMI_BOARD_VENDOR,
858 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
862 * All BIOS versions for the Asus M3A support 64bit DMA.
863 * (all release versions from 0301 to 1206 were tested)
868 DMI_MATCH(DMI_BOARD_VENDOR,
869 "ASUSTeK Computer INC."),
870 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
875 const struct dmi_system_id *match;
876 int year, month, date;
879 match = dmi_first_match(sysids);
880 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
884 if (!match->driver_data)
887 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
888 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
890 if (strcmp(buf, match->driver_data) >= 0)
894 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
900 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
904 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
906 static const struct dmi_system_id broken_systems[] = {
908 .ident = "HP Compaq nx6310",
910 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
911 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
913 /* PCI slot number of the controller */
914 .driver_data = (void *)0x1FUL,
917 .ident = "HP Compaq 6720s",
919 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
920 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
922 /* PCI slot number of the controller */
923 .driver_data = (void *)0x1FUL,
926 { } /* terminate list */
928 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
931 unsigned long slot = (unsigned long)dmi->driver_data;
932 /* apply the quirk only to on-board controllers */
933 return slot == PCI_SLOT(pdev->devfn);
939 static bool ahci_broken_suspend(struct pci_dev *pdev)
941 static const struct dmi_system_id sysids[] = {
943 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
944 * to the harddisk doesn't become online after
945 * resuming from STR. Warn and fail suspend.
947 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
949 * Use dates instead of versions to match as HP is
950 * apparently recycling both product and version
953 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
958 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
959 DMI_MATCH(DMI_PRODUCT_NAME,
960 "HP Pavilion dv4 Notebook PC"),
962 .driver_data = "20090105", /* F.30 */
967 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
968 DMI_MATCH(DMI_PRODUCT_NAME,
969 "HP Pavilion dv5 Notebook PC"),
971 .driver_data = "20090506", /* F.16 */
976 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
977 DMI_MATCH(DMI_PRODUCT_NAME,
978 "HP Pavilion dv6 Notebook PC"),
980 .driver_data = "20090423", /* F.21 */
985 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
986 DMI_MATCH(DMI_PRODUCT_NAME,
987 "HP HDX18 Notebook PC"),
989 .driver_data = "20090430", /* F.23 */
992 * Acer eMachines G725 has the same problem. BIOS
993 * V1.03 is known to be broken. V3.04 is known to
994 * work. Between, there are V1.06, V2.06 and V3.03
995 * that we don't have much idea about. For now,
996 * blacklist anything older than V3.04.
998 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1003 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1004 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1006 .driver_data = "20091216", /* V3.04 */
1008 { } /* terminate list */
1010 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1011 int year, month, date;
1014 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1017 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1018 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1020 return strcmp(buf, dmi->driver_data) < 0;
1023 static bool ahci_broken_online(struct pci_dev *pdev)
1025 #define ENCODE_BUSDEVFN(bus, slot, func) \
1026 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1027 static const struct dmi_system_id sysids[] = {
1029 * There are several gigabyte boards which use
1030 * SIMG5723s configured as hardware RAID. Certain
1031 * 5723 firmware revisions shipped there keep the link
1032 * online but fail to answer properly to SRST or
1033 * IDENTIFY when no device is attached downstream
1034 * causing libata to retry quite a few times leading
1035 * to excessive detection delay.
1037 * As these firmwares respond to the second reset try
1038 * with invalid device signature, considering unknown
1039 * sig as offline works around the problem acceptably.
1042 .ident = "EP45-DQ6",
1044 DMI_MATCH(DMI_BOARD_VENDOR,
1045 "Gigabyte Technology Co., Ltd."),
1046 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1048 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1051 .ident = "EP45-DS5",
1053 DMI_MATCH(DMI_BOARD_VENDOR,
1054 "Gigabyte Technology Co., Ltd."),
1055 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1057 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1059 { } /* terminate list */
1061 #undef ENCODE_BUSDEVFN
1062 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1068 val = (unsigned long)dmi->driver_data;
1070 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1073 #ifdef CONFIG_ATA_ACPI
1074 static void ahci_gtf_filter_workaround(struct ata_host *host)
1076 static const struct dmi_system_id sysids[] = {
1078 * Aspire 3810T issues a bunch of SATA enable commands
1079 * via _GTF including an invalid one and one which is
1080 * rejected by the device. Among the successful ones
1081 * is FPDMA non-zero offset enable which when enabled
1082 * only on the drive side leads to NCQ command
1083 * failures. Filter it out.
1086 .ident = "Aspire 3810T",
1088 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1089 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1091 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1095 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1096 unsigned int filter;
1102 filter = (unsigned long)dmi->driver_data;
1103 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1104 filter, dmi->ident);
1106 for (i = 0; i < host->n_ports; i++) {
1107 struct ata_port *ap = host->ports[i];
1108 struct ata_link *link;
1109 struct ata_device *dev;
1111 ata_for_each_link(link, ap, EDGE)
1112 ata_for_each_dev(dev, link, ALL)
1113 dev->gtf_filter |= filter;
1117 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1121 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1124 unsigned int maxvec;
1126 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1127 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1129 if ((rc == maxvec) || (rc == 1))
1132 * Assume that advantage of multipe MSIs is negated,
1133 * so fallback to single MSI mode to save resources
1135 pci_disable_msi(pdev);
1136 if (!pci_enable_msi(pdev))
1146 * ahci_host_activate - start AHCI host, request IRQs and register it
1147 * @host: target ATA host
1148 * @irq: base IRQ number to request
1149 * @n_msis: number of MSIs allocated for this host
1150 * @irq_handler: irq_handler used when requesting IRQs
1151 * @irq_flags: irq_flags used when requesting IRQs
1153 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1154 * when multiple MSIs were allocated. That is one MSI per port, starting
1158 * Inherited from calling layer (may sleep).
1161 * 0 on success, -errno otherwise.
1163 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1167 /* Sharing Last Message among several ports is not supported */
1168 if (n_msis < host->n_ports)
1171 rc = ata_host_start(host);
1175 for (i = 0; i < host->n_ports; i++) {
1176 rc = devm_request_threaded_irq(host->dev,
1177 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1178 dev_driver_string(host->dev), host->ports[i]);
1183 for (i = 0; i < host->n_ports; i++)
1184 ata_port_desc(host->ports[i], "irq %d", irq + i);
1186 rc = ata_host_register(host, &ahci_sht);
1188 goto out_free_all_irqs;
1195 for (i--; i >= 0; i--)
1196 devm_free_irq(host->dev, irq + i, host->ports[i]);
1201 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1203 unsigned int board_id = ent->driver_data;
1204 struct ata_port_info pi = ahci_port_info[board_id];
1205 const struct ata_port_info *ppi[] = { &pi, NULL };
1206 struct device *dev = &pdev->dev;
1207 struct ahci_host_priv *hpriv;
1208 struct ata_host *host;
1209 int n_ports, n_msis, i, rc;
1210 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1214 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1216 ata_print_version_once(&pdev->dev, DRV_VERSION);
1218 /* The AHCI driver can only drive the SATA ports, the PATA driver
1219 can drive them all so if both drivers are selected make sure
1220 AHCI stays out of the way */
1221 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1225 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1226 * ahci, use ata_generic instead.
1228 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1229 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1230 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1231 pdev->subsystem_device == 0xcb89)
1234 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1235 * At the moment, we can only use the AHCI mode. Let the users know
1236 * that for SAS drives they're out of luck.
1238 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1239 dev_info(&pdev->dev,
1240 "PDC42819 can only drive SATA devices with this driver\n");
1242 /* Both Connext and Enmotus devices use non-standard BARs */
1243 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1244 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1245 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1246 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1248 /* acquire resources */
1249 rc = pcim_enable_device(pdev);
1253 /* AHCI controllers often implement SFF compatible interface.
1254 * Grab all PCI BARs just in case.
1256 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1258 pcim_pin_device(pdev);
1262 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1263 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1266 /* ICH6s share the same PCI ID for both piix and ahci
1267 * modes. Enabling ahci mode while MAP indicates
1268 * combined mode is a bad idea. Yield to ata_piix.
1270 pci_read_config_byte(pdev, ICH_MAP, &map);
1272 dev_info(&pdev->dev,
1273 "controller is in combined mode, can't enable AHCI mode\n");
1278 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1281 hpriv->flags |= (unsigned long)pi.private_data;
1283 /* MCP65 revision A1 and A2 can't do MSI */
1284 if (board_id == board_ahci_mcp65 &&
1285 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1286 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1288 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1289 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1290 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1292 /* only some SB600s can do 64bit DMA */
1293 if (ahci_sb600_enable_64bit(pdev))
1294 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1296 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1298 n_msis = ahci_init_interrupts(pdev, hpriv);
1300 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1302 /* save initial config */
1303 ahci_pci_save_initial_config(pdev, hpriv);
1306 if (hpriv->cap & HOST_CAP_NCQ) {
1307 pi.flags |= ATA_FLAG_NCQ;
1309 * Auto-activate optimization is supposed to be
1310 * supported on all AHCI controllers indicating NCQ
1311 * capability, but it seems to be broken on some
1312 * chipsets including NVIDIAs.
1314 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1315 pi.flags |= ATA_FLAG_FPDMA_AA;
1318 if (hpriv->cap & HOST_CAP_PMP)
1319 pi.flags |= ATA_FLAG_PMP;
1321 ahci_set_em_messages(hpriv, &pi);
1323 if (ahci_broken_system_poweroff(pdev)) {
1324 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1325 dev_info(&pdev->dev,
1326 "quirky BIOS, skipping spindown on poweroff\n");
1329 if (ahci_broken_suspend(pdev)) {
1330 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1331 dev_warn(&pdev->dev,
1332 "BIOS update required for suspend/resume\n");
1335 if (ahci_broken_online(pdev)) {
1336 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1337 dev_info(&pdev->dev,
1338 "online status unreliable, applying workaround\n");
1341 /* CAP.NP sometimes indicate the index of the last enabled
1342 * port, at other times, that of the last possible port, so
1343 * determining the maximum port number requires looking at
1344 * both CAP.NP and port_map.
1346 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1348 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1351 host->private_data = hpriv;
1353 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1354 host->flags |= ATA_HOST_PARALLEL_SCAN;
1356 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1358 if (pi.flags & ATA_FLAG_EM)
1359 ahci_reset_em(host);
1361 for (i = 0; i < host->n_ports; i++) {
1362 struct ata_port *ap = host->ports[i];
1364 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1365 ata_port_pbar_desc(ap, ahci_pci_bar,
1366 0x100 + ap->port_no * 0x80, "port");
1368 /* set enclosure management message type */
1369 if (ap->flags & ATA_FLAG_EM)
1370 ap->em_message_type = hpriv->em_msg_type;
1373 /* disabled/not-implemented port */
1374 if (!(hpriv->port_map & (1 << i)))
1375 ap->ops = &ata_dummy_port_ops;
1378 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1379 ahci_p5wdh_workaround(host);
1381 /* apply gtf filter quirk */
1382 ahci_gtf_filter_workaround(host);
1384 /* initialize adapter */
1385 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1389 rc = ahci_pci_reset_controller(host);
1393 ahci_pci_init_controller(host);
1394 ahci_pci_print_info(host);
1396 pci_set_master(pdev);
1398 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1399 return ahci_host_activate(host, pdev->irq, n_msis);
1401 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1405 module_pci_driver(ahci_pci_driver);
1407 MODULE_AUTHOR("Jeff Garzik");
1408 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1409 MODULE_LICENSE("GPL");
1410 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1411 MODULE_VERSION(DRV_VERSION);