2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 static struct scsi_host_template ahci_sht = {
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
108 static const struct ata_port_info ahci_port_info[] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
116 [board_ahci_ign_iferr] = {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
123 [board_ahci_noncq] = {
124 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
130 [board_ahci_nosntf] = {
131 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
137 [board_ahci_yes_fbs] = {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
145 [board_ahci_mcp65] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
153 [board_ahci_mcp77] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
160 [board_ahci_mcp89] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
175 [board_ahci_sb600] = {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
184 [board_ahci_sb700] = { /* for SB700 and SB800 */
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_pmp_retry_srst_ops,
191 [board_ahci_vt8251] = {
192 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_vt8251_ops,
200 static const struct pci_device_id ahci_pci_tbl[] = {
202 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
203 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
204 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
205 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
206 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
207 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
208 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
209 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
212 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
213 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
216 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
230 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
232 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
237 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
245 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
249 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
250 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
253 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
256 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
261 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
263 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
269 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
271 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
295 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
299 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
303 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
305 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
308 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
309 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
310 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
311 /* JMicron 362B and 362C have an AHCI function with IDE class code */
312 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
313 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
316 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
317 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
325 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
326 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
327 /* AMD is using RAID class only for ahci controllers */
328 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
329 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
332 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
333 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
336 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
426 /* ST Microelectronics */
427 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
430 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
431 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
433 .class = PCI_CLASS_STORAGE_SATA_AHCI,
434 .class_mask = 0xffffff,
435 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
438 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
439 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
440 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
442 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
448 .driver_data = board_ahci_yes_fbs },
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
450 .driver_data = board_ahci_yes_fbs },
453 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
456 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
457 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
458 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
459 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
462 * Samsung SSDs found on some macbooks. NCQ times out.
463 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
465 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
468 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
470 /* Generic, PCI class code for AHCI */
471 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
472 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
474 { } /* terminate list */
478 static struct pci_driver ahci_pci_driver = {
480 .id_table = ahci_pci_tbl,
481 .probe = ahci_init_one,
482 .remove = ata_pci_remove_one,
484 .suspend = ahci_pci_device_suspend,
485 .resume = ahci_pci_device_resume,
489 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
490 static int marvell_enable;
492 static int marvell_enable = 1;
494 module_param(marvell_enable, int, 0644);
495 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
498 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
499 struct ahci_host_priv *hpriv)
501 unsigned int force_port_map = 0;
502 unsigned int mask_port_map = 0;
504 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
505 dev_info(&pdev->dev, "JMB361 has only one port\n");
510 * Temporary Marvell 6145 hack: PATA port presence
511 * is asserted through the standard AHCI port
512 * presence register, as bit 4 (counting from 0)
514 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
515 if (pdev->device == 0x6121)
520 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
523 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
527 static int ahci_pci_reset_controller(struct ata_host *host)
529 struct pci_dev *pdev = to_pci_dev(host->dev);
531 ahci_reset_controller(host);
533 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
534 struct ahci_host_priv *hpriv = host->private_data;
538 pci_read_config_word(pdev, 0x92, &tmp16);
539 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
540 tmp16 |= hpriv->port_map;
541 pci_write_config_word(pdev, 0x92, tmp16);
548 static void ahci_pci_init_controller(struct ata_host *host)
550 struct ahci_host_priv *hpriv = host->private_data;
551 struct pci_dev *pdev = to_pci_dev(host->dev);
552 void __iomem *port_mmio;
556 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
557 if (pdev->device == 0x6121)
561 port_mmio = __ahci_port_base(host, mv);
563 writel(0, port_mmio + PORT_IRQ_MASK);
566 tmp = readl(port_mmio + PORT_IRQ_STAT);
567 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
569 writel(tmp, port_mmio + PORT_IRQ_STAT);
572 ahci_init_controller(host);
575 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
576 unsigned long deadline)
578 struct ata_port *ap = link->ap;
584 ahci_stop_engine(ap);
586 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
587 deadline, &online, NULL);
589 ahci_start_engine(ap);
591 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
593 /* vt8251 doesn't clear BSY on signature FIS reception,
594 * request follow-up softreset.
596 return online ? -EAGAIN : rc;
599 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
600 unsigned long deadline)
602 struct ata_port *ap = link->ap;
603 struct ahci_port_priv *pp = ap->private_data;
604 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
605 struct ata_taskfile tf;
609 ahci_stop_engine(ap);
611 /* clear D2H reception area to properly wait for D2H FIS */
612 ata_tf_init(link->device, &tf);
614 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
616 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
617 deadline, &online, NULL);
619 ahci_start_engine(ap);
621 /* The pseudo configuration device on SIMG4726 attached to
622 * ASUS P5W-DH Deluxe doesn't send signature FIS after
623 * hardreset if no device is attached to the first downstream
624 * port && the pseudo device locks up on SRST w/ PMP==0. To
625 * work around this, wait for !BSY only briefly. If BSY isn't
626 * cleared, perform CLO and proceed to IDENTIFY (achieved by
627 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
629 * Wait for two seconds. Devices attached to downstream port
630 * which can't process the following IDENTIFY after this will
631 * have to be reset again. For most cases, this should
632 * suffice while making probing snappish enough.
635 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
638 ahci_kick_engine(ap);
644 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
646 struct ata_host *host = dev_get_drvdata(&pdev->dev);
647 struct ahci_host_priv *hpriv = host->private_data;
648 void __iomem *mmio = hpriv->mmio;
651 if (mesg.event & PM_EVENT_SUSPEND &&
652 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
654 "BIOS update required for suspend/resume\n");
658 if (mesg.event & PM_EVENT_SLEEP) {
659 /* AHCI spec rev1.1 section 8.3.3:
660 * Software must disable interrupts prior to requesting a
661 * transition of the HBA to D3 state.
663 ctl = readl(mmio + HOST_CTL);
665 writel(ctl, mmio + HOST_CTL);
666 readl(mmio + HOST_CTL); /* flush */
669 return ata_pci_device_suspend(pdev, mesg);
672 static int ahci_pci_device_resume(struct pci_dev *pdev)
674 struct ata_host *host = dev_get_drvdata(&pdev->dev);
677 rc = ata_pci_device_do_resume(pdev);
681 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
682 rc = ahci_pci_reset_controller(host);
686 ahci_pci_init_controller(host);
689 ata_host_resume(host);
695 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
700 * If the device fixup already set the dma_mask to some non-standard
701 * value, don't extend it here. This happens on STA2X11, for example.
703 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
707 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
708 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
710 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
713 "64-bit DMA enable failed\n");
718 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
720 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
723 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
726 "32-bit consistent DMA enable failed\n");
733 static void ahci_pci_print_info(struct ata_host *host)
735 struct pci_dev *pdev = to_pci_dev(host->dev);
739 pci_read_config_word(pdev, 0x0a, &cc);
740 if (cc == PCI_CLASS_STORAGE_IDE)
742 else if (cc == PCI_CLASS_STORAGE_SATA)
744 else if (cc == PCI_CLASS_STORAGE_RAID)
749 ahci_print_info(host, scc_s);
752 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
753 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
754 * support PMP and the 4726 either directly exports the device
755 * attached to the first downstream port or acts as a hardware storage
756 * controller and emulate a single ATA device (can be RAID 0/1 or some
757 * other configuration).
759 * When there's no device attached to the first downstream port of the
760 * 4726, "Config Disk" appears, which is a pseudo ATA device to
761 * configure the 4726. However, ATA emulation of the device is very
762 * lame. It doesn't send signature D2H Reg FIS after the initial
763 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
765 * The following function works around the problem by always using
766 * hardreset on the port and not depending on receiving signature FIS
767 * afterward. If signature FIS isn't received soon, ATA class is
768 * assumed without follow-up softreset.
770 static void ahci_p5wdh_workaround(struct ata_host *host)
772 static struct dmi_system_id sysids[] = {
774 .ident = "P5W DH Deluxe",
776 DMI_MATCH(DMI_SYS_VENDOR,
777 "ASUSTEK COMPUTER INC"),
778 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
783 struct pci_dev *pdev = to_pci_dev(host->dev);
785 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
786 dmi_check_system(sysids)) {
787 struct ata_port *ap = host->ports[1];
790 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
792 ap->ops = &ahci_p5wdh_ops;
793 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
797 /* only some SB600 ahci controllers can do 64bit DMA */
798 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
800 static const struct dmi_system_id sysids[] = {
802 * The oldest version known to be broken is 0901 and
803 * working is 1501 which was released on 2007-10-26.
804 * Enable 64bit DMA on 1501 and anything newer.
806 * Please read bko#9412 for more info.
809 .ident = "ASUS M2A-VM",
811 DMI_MATCH(DMI_BOARD_VENDOR,
812 "ASUSTeK Computer INC."),
813 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
815 .driver_data = "20071026", /* yyyymmdd */
818 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
821 * BIOS versions earlier than 1.5 had the Manufacturer DMI
822 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
823 * This spelling mistake was fixed in BIOS version 1.5, so
824 * 1.5 and later have the Manufacturer as
825 * "MICRO-STAR INTERNATIONAL CO.,LTD".
826 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
828 * BIOS versions earlier than 1.9 had a Board Product Name
829 * DMI field of "MS-7376". This was changed to be
830 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
831 * match on DMI_BOARD_NAME of "MS-7376".
834 .ident = "MSI K9A2 Platinum",
836 DMI_MATCH(DMI_BOARD_VENDOR,
838 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
842 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
845 * This board also had the typo mentioned above in the
846 * Manufacturer DMI field (fixed in BIOS version 1.5), so
847 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
850 .ident = "MSI K9AGM2",
852 DMI_MATCH(DMI_BOARD_VENDOR,
854 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
858 * All BIOS versions for the Asus M3A support 64bit DMA.
859 * (all release versions from 0301 to 1206 were tested)
864 DMI_MATCH(DMI_BOARD_VENDOR,
865 "ASUSTeK Computer INC."),
866 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
871 const struct dmi_system_id *match;
872 int year, month, date;
875 match = dmi_first_match(sysids);
876 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
880 if (!match->driver_data)
883 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
884 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
886 if (strcmp(buf, match->driver_data) >= 0)
890 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
896 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
900 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
902 static const struct dmi_system_id broken_systems[] = {
904 .ident = "HP Compaq nx6310",
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
909 /* PCI slot number of the controller */
910 .driver_data = (void *)0x1FUL,
913 .ident = "HP Compaq 6720s",
915 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
916 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
918 /* PCI slot number of the controller */
919 .driver_data = (void *)0x1FUL,
922 { } /* terminate list */
924 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
927 unsigned long slot = (unsigned long)dmi->driver_data;
928 /* apply the quirk only to on-board controllers */
929 return slot == PCI_SLOT(pdev->devfn);
935 static bool ahci_broken_suspend(struct pci_dev *pdev)
937 static const struct dmi_system_id sysids[] = {
939 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
940 * to the harddisk doesn't become online after
941 * resuming from STR. Warn and fail suspend.
943 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
945 * Use dates instead of versions to match as HP is
946 * apparently recycling both product and version
949 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
954 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
955 DMI_MATCH(DMI_PRODUCT_NAME,
956 "HP Pavilion dv4 Notebook PC"),
958 .driver_data = "20090105", /* F.30 */
963 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
964 DMI_MATCH(DMI_PRODUCT_NAME,
965 "HP Pavilion dv5 Notebook PC"),
967 .driver_data = "20090506", /* F.16 */
972 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
973 DMI_MATCH(DMI_PRODUCT_NAME,
974 "HP Pavilion dv6 Notebook PC"),
976 .driver_data = "20090423", /* F.21 */
981 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
982 DMI_MATCH(DMI_PRODUCT_NAME,
983 "HP HDX18 Notebook PC"),
985 .driver_data = "20090430", /* F.23 */
988 * Acer eMachines G725 has the same problem. BIOS
989 * V1.03 is known to be broken. V3.04 is known to
990 * work. Between, there are V1.06, V2.06 and V3.03
991 * that we don't have much idea about. For now,
992 * blacklist anything older than V3.04.
994 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
999 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1000 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1002 .driver_data = "20091216", /* V3.04 */
1004 { } /* terminate list */
1006 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1007 int year, month, date;
1010 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1013 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1014 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1016 return strcmp(buf, dmi->driver_data) < 0;
1019 static bool ahci_broken_online(struct pci_dev *pdev)
1021 #define ENCODE_BUSDEVFN(bus, slot, func) \
1022 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1023 static const struct dmi_system_id sysids[] = {
1025 * There are several gigabyte boards which use
1026 * SIMG5723s configured as hardware RAID. Certain
1027 * 5723 firmware revisions shipped there keep the link
1028 * online but fail to answer properly to SRST or
1029 * IDENTIFY when no device is attached downstream
1030 * causing libata to retry quite a few times leading
1031 * to excessive detection delay.
1033 * As these firmwares respond to the second reset try
1034 * with invalid device signature, considering unknown
1035 * sig as offline works around the problem acceptably.
1038 .ident = "EP45-DQ6",
1040 DMI_MATCH(DMI_BOARD_VENDOR,
1041 "Gigabyte Technology Co., Ltd."),
1042 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1044 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1047 .ident = "EP45-DS5",
1049 DMI_MATCH(DMI_BOARD_VENDOR,
1050 "Gigabyte Technology Co., Ltd."),
1051 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1053 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1055 { } /* terminate list */
1057 #undef ENCODE_BUSDEVFN
1058 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1064 val = (unsigned long)dmi->driver_data;
1066 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1069 #ifdef CONFIG_ATA_ACPI
1070 static void ahci_gtf_filter_workaround(struct ata_host *host)
1072 static const struct dmi_system_id sysids[] = {
1074 * Aspire 3810T issues a bunch of SATA enable commands
1075 * via _GTF including an invalid one and one which is
1076 * rejected by the device. Among the successful ones
1077 * is FPDMA non-zero offset enable which when enabled
1078 * only on the drive side leads to NCQ command
1079 * failures. Filter it out.
1082 .ident = "Aspire 3810T",
1084 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1085 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1087 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1091 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1092 unsigned int filter;
1098 filter = (unsigned long)dmi->driver_data;
1099 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1100 filter, dmi->ident);
1102 for (i = 0; i < host->n_ports; i++) {
1103 struct ata_port *ap = host->ports[i];
1104 struct ata_link *link;
1105 struct ata_device *dev;
1107 ata_for_each_link(link, ap, EDGE)
1108 ata_for_each_dev(dev, link, ALL)
1109 dev->gtf_filter |= filter;
1113 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1117 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1120 unsigned int maxvec;
1122 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1123 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1125 if ((rc == maxvec) || (rc == 1))
1128 * Assume that advantage of multipe MSIs is negated,
1129 * so fallback to single MSI mode to save resources
1131 pci_disable_msi(pdev);
1132 if (!pci_enable_msi(pdev))
1142 * ahci_host_activate - start AHCI host, request IRQs and register it
1143 * @host: target ATA host
1144 * @irq: base IRQ number to request
1145 * @n_msis: number of MSIs allocated for this host
1146 * @irq_handler: irq_handler used when requesting IRQs
1147 * @irq_flags: irq_flags used when requesting IRQs
1149 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1150 * when multiple MSIs were allocated. That is one MSI per port, starting
1154 * Inherited from calling layer (may sleep).
1157 * 0 on success, -errno otherwise.
1159 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1163 /* Sharing Last Message among several ports is not supported */
1164 if (n_msis < host->n_ports)
1167 rc = ata_host_start(host);
1171 for (i = 0; i < host->n_ports; i++) {
1172 rc = devm_request_threaded_irq(host->dev,
1173 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1174 dev_driver_string(host->dev), host->ports[i]);
1179 for (i = 0; i < host->n_ports; i++)
1180 ata_port_desc(host->ports[i], "irq %d", irq + i);
1182 rc = ata_host_register(host, &ahci_sht);
1184 goto out_free_all_irqs;
1191 for (i--; i >= 0; i--)
1192 devm_free_irq(host->dev, irq + i, host->ports[i]);
1197 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1199 unsigned int board_id = ent->driver_data;
1200 struct ata_port_info pi = ahci_port_info[board_id];
1201 const struct ata_port_info *ppi[] = { &pi, NULL };
1202 struct device *dev = &pdev->dev;
1203 struct ahci_host_priv *hpriv;
1204 struct ata_host *host;
1205 int n_ports, n_msis, i, rc;
1206 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1210 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1212 ata_print_version_once(&pdev->dev, DRV_VERSION);
1214 /* The AHCI driver can only drive the SATA ports, the PATA driver
1215 can drive them all so if both drivers are selected make sure
1216 AHCI stays out of the way */
1217 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1221 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1222 * ahci, use ata_generic instead.
1224 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1225 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1226 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1227 pdev->subsystem_device == 0xcb89)
1230 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1231 * At the moment, we can only use the AHCI mode. Let the users know
1232 * that for SAS drives they're out of luck.
1234 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1235 dev_info(&pdev->dev,
1236 "PDC42819 can only drive SATA devices with this driver\n");
1238 /* Both Connext and Enmotus devices use non-standard BARs */
1239 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1240 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1241 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1242 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1244 /* acquire resources */
1245 rc = pcim_enable_device(pdev);
1249 /* AHCI controllers often implement SFF compatible interface.
1250 * Grab all PCI BARs just in case.
1252 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1254 pcim_pin_device(pdev);
1258 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1259 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1262 /* ICH6s share the same PCI ID for both piix and ahci
1263 * modes. Enabling ahci mode while MAP indicates
1264 * combined mode is a bad idea. Yield to ata_piix.
1266 pci_read_config_byte(pdev, ICH_MAP, &map);
1268 dev_info(&pdev->dev,
1269 "controller is in combined mode, can't enable AHCI mode\n");
1274 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1277 hpriv->flags |= (unsigned long)pi.private_data;
1279 /* MCP65 revision A1 and A2 can't do MSI */
1280 if (board_id == board_ahci_mcp65 &&
1281 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1282 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1284 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1285 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1286 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1288 /* only some SB600s can do 64bit DMA */
1289 if (ahci_sb600_enable_64bit(pdev))
1290 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1292 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1294 n_msis = ahci_init_interrupts(pdev, hpriv);
1296 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1298 /* save initial config */
1299 ahci_pci_save_initial_config(pdev, hpriv);
1302 if (hpriv->cap & HOST_CAP_NCQ) {
1303 pi.flags |= ATA_FLAG_NCQ;
1305 * Auto-activate optimization is supposed to be
1306 * supported on all AHCI controllers indicating NCQ
1307 * capability, but it seems to be broken on some
1308 * chipsets including NVIDIAs.
1310 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1311 pi.flags |= ATA_FLAG_FPDMA_AA;
1314 if (hpriv->cap & HOST_CAP_PMP)
1315 pi.flags |= ATA_FLAG_PMP;
1317 ahci_set_em_messages(hpriv, &pi);
1319 if (ahci_broken_system_poweroff(pdev)) {
1320 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1321 dev_info(&pdev->dev,
1322 "quirky BIOS, skipping spindown on poweroff\n");
1325 if (ahci_broken_suspend(pdev)) {
1326 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1327 dev_warn(&pdev->dev,
1328 "BIOS update required for suspend/resume\n");
1331 if (ahci_broken_online(pdev)) {
1332 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1333 dev_info(&pdev->dev,
1334 "online status unreliable, applying workaround\n");
1337 /* CAP.NP sometimes indicate the index of the last enabled
1338 * port, at other times, that of the last possible port, so
1339 * determining the maximum port number requires looking at
1340 * both CAP.NP and port_map.
1342 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1344 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1347 host->private_data = hpriv;
1349 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1350 host->flags |= ATA_HOST_PARALLEL_SCAN;
1352 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1354 if (pi.flags & ATA_FLAG_EM)
1355 ahci_reset_em(host);
1357 for (i = 0; i < host->n_ports; i++) {
1358 struct ata_port *ap = host->ports[i];
1360 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1361 ata_port_pbar_desc(ap, ahci_pci_bar,
1362 0x100 + ap->port_no * 0x80, "port");
1364 /* set enclosure management message type */
1365 if (ap->flags & ATA_FLAG_EM)
1366 ap->em_message_type = hpriv->em_msg_type;
1369 /* disabled/not-implemented port */
1370 if (!(hpriv->port_map & (1 << i)))
1371 ap->ops = &ata_dummy_port_ops;
1374 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1375 ahci_p5wdh_workaround(host);
1377 /* apply gtf filter quirk */
1378 ahci_gtf_filter_workaround(host);
1380 /* initialize adapter */
1381 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1385 rc = ahci_pci_reset_controller(host);
1389 ahci_pci_init_controller(host);
1390 ahci_pci_print_info(host);
1392 pci_set_master(pdev);
1394 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1395 return ahci_host_activate(host, pdev->irq, n_msis);
1397 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1401 module_pci_driver(ahci_pci_driver);
1403 MODULE_AUTHOR("Jeff Garzik");
1404 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1405 MODULE_LICENSE("GPL");
1406 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1407 MODULE_VERSION(DRV_VERSION);