2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/delay.h>
26 ACPI_MODULE_NAME("acpi_lpss");
28 #ifdef CONFIG_X86_INTEL_LPSS
30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
32 #define LPSS_CLK_SIZE 0x04
33 #define LPSS_LTR_SIZE 0x18
35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
37 #define LPSS_RESETS 0x04
38 #define LPSS_RESETS_RESET_FUNC BIT(0)
39 #define LPSS_RESETS_RESET_APB BIT(1)
40 #define LPSS_GENERAL 0x08
41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
43 #define LPSS_SW_LTR 0x10
44 #define LPSS_AUTO_LTR 0x14
45 #define LPSS_LTR_SNOOP_REQ BIT(15)
46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
47 #define LPSS_LTR_SNOOP_LAT_1US 0x800
48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
51 #define LPSS_LTR_MAX_VAL 0x3FF
52 #define LPSS_TX_INT 0x20
53 #define LPSS_TX_INT_MASK BIT(1)
55 #define LPSS_PRV_REG_COUNT 9
58 #define LPSS_CLK BIT(0)
59 #define LPSS_CLK_GATE BIT(1)
60 #define LPSS_CLK_DIVIDER BIT(2)
61 #define LPSS_LTR BIT(3)
62 #define LPSS_SAVE_CTX BIT(4)
63 #define LPSS_NO_D3_DELAY BIT(5)
65 struct lpss_private_data;
67 struct lpss_device_desc {
69 const char *clk_con_id;
70 unsigned int prv_offset;
71 size_t prv_size_override;
72 void (*setup)(struct lpss_private_data *pdata);
75 static struct lpss_device_desc lpss_dma_desc = {
79 struct lpss_private_data {
80 void __iomem *mmio_base;
81 resource_size_t mmio_size;
82 unsigned int fixed_clk_rate;
84 const struct lpss_device_desc *dev_desc;
85 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
88 /* UART Component Parameter Register */
89 #define LPSS_UART_CPR 0xF4
90 #define LPSS_UART_CPR_AFCE BIT(4)
92 static void lpss_uart_setup(struct lpss_private_data *pdata)
97 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
98 val = readl(pdata->mmio_base + offset);
99 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
101 val = readl(pdata->mmio_base + LPSS_UART_CPR);
102 if (!(val & LPSS_UART_CPR_AFCE)) {
103 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
104 val = readl(pdata->mmio_base + offset);
105 val |= LPSS_GENERAL_UART_RTS_OVRD;
106 writel(val, pdata->mmio_base + offset);
110 static void lpss_deassert_reset(struct lpss_private_data *pdata)
115 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
116 val = readl(pdata->mmio_base + offset);
117 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
118 writel(val, pdata->mmio_base + offset);
121 #define LPSS_I2C_ENABLE 0x6c
123 static void byt_i2c_setup(struct lpss_private_data *pdata)
125 lpss_deassert_reset(pdata);
127 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
128 pdata->fixed_clk_rate = 133000000;
130 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
133 static const struct lpss_device_desc lpt_dev_desc = {
134 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
138 static const struct lpss_device_desc lpt_i2c_dev_desc = {
139 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
143 static const struct lpss_device_desc lpt_uart_dev_desc = {
144 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
145 .clk_con_id = "baudclk",
147 .setup = lpss_uart_setup,
150 static const struct lpss_device_desc lpt_sdio_dev_desc = {
152 .prv_offset = 0x1000,
153 .prv_size_override = 0x1018,
156 static const struct lpss_device_desc byt_pwm_dev_desc = {
157 .flags = LPSS_SAVE_CTX,
160 static const struct lpss_device_desc bsw_pwm_dev_desc = {
161 .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
164 static const struct lpss_device_desc byt_uart_dev_desc = {
165 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
166 .clk_con_id = "baudclk",
168 .setup = lpss_uart_setup,
171 static const struct lpss_device_desc bsw_uart_dev_desc = {
172 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
174 .clk_con_id = "baudclk",
176 .setup = lpss_uart_setup,
179 static const struct lpss_device_desc byt_spi_dev_desc = {
180 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
184 static const struct lpss_device_desc byt_sdio_dev_desc = {
188 static const struct lpss_device_desc byt_i2c_dev_desc = {
189 .flags = LPSS_CLK | LPSS_SAVE_CTX,
191 .setup = byt_i2c_setup,
194 static const struct lpss_device_desc bsw_i2c_dev_desc = {
195 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
197 .setup = byt_i2c_setup,
200 static struct lpss_device_desc bsw_spi_dev_desc = {
201 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
204 .setup = lpss_deassert_reset,
209 #define LPSS_ADDR(desc) (0UL)
211 #endif /* CONFIG_X86_INTEL_LPSS */
213 static const struct acpi_device_id acpi_lpss_device_ids[] = {
214 /* Generic LPSS devices */
215 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
217 /* Lynxpoint LPSS devices */
218 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
219 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
220 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
221 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
222 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
223 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
224 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
227 /* BayTrail LPSS devices */
228 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
229 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
230 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
231 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
232 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
236 /* Braswell LPSS devices */
237 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
238 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
239 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
240 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
242 /* Broadwell LPSS devices */
243 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
244 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
245 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
246 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
247 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
248 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
249 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
252 /* Wildcat Point LPSS devices */
253 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
258 #ifdef CONFIG_X86_INTEL_LPSS
260 static int is_memory(struct acpi_resource *res, void *not_used)
263 return !acpi_dev_resource_memory(res, &r);
266 /* LPSS main clock device. */
267 static struct platform_device *lpss_clk_dev;
269 static inline void lpt_register_clock_device(void)
271 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
274 static int register_device_clock(struct acpi_device *adev,
275 struct lpss_private_data *pdata)
277 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
278 const char *devname = dev_name(&adev->dev);
279 struct clk *clk = ERR_PTR(-ENODEV);
280 struct lpss_clk_data *clk_data;
281 const char *parent, *clk_name;
282 void __iomem *prv_base;
285 lpt_register_clock_device();
287 clk_data = platform_get_drvdata(lpss_clk_dev);
292 if (!pdata->mmio_base
293 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
296 parent = clk_data->name;
297 prv_base = pdata->mmio_base + dev_desc->prv_offset;
299 if (pdata->fixed_clk_rate) {
300 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
301 pdata->fixed_clk_rate);
305 if (dev_desc->flags & LPSS_CLK_GATE) {
306 clk = clk_register_gate(NULL, devname, parent, 0,
307 prv_base, 0, 0, NULL);
311 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
312 /* Prevent division by zero */
313 if (!readl(prv_base))
314 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
316 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
319 clk = clk_register_fractional_divider(NULL, clk_name, parent,
321 1, 15, 16, 15, 0, NULL);
324 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
329 clk = clk_register_gate(NULL, clk_name, parent,
330 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
331 prv_base, 31, 0, NULL);
340 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
344 static int acpi_lpss_create_device(struct acpi_device *adev,
345 const struct acpi_device_id *id)
347 const struct lpss_device_desc *dev_desc;
348 struct lpss_private_data *pdata;
349 struct resource_entry *rentry;
350 struct list_head resource_list;
351 struct platform_device *pdev;
354 dev_desc = (const struct lpss_device_desc *)id->driver_data;
356 pdev = acpi_create_platform_device(adev);
357 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
359 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
363 INIT_LIST_HEAD(&resource_list);
364 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
368 list_for_each_entry(rentry, &resource_list, node)
369 if (resource_type(rentry->res) == IORESOURCE_MEM) {
370 if (dev_desc->prv_size_override)
371 pdata->mmio_size = dev_desc->prv_size_override;
373 pdata->mmio_size = resource_size(rentry->res);
374 pdata->mmio_base = ioremap(rentry->res->start,
379 acpi_dev_free_resource_list(&resource_list);
381 if (!pdata->mmio_base) {
386 pdata->dev_desc = dev_desc;
389 dev_desc->setup(pdata);
391 if (dev_desc->flags & LPSS_CLK) {
392 ret = register_device_clock(adev, pdata);
394 /* Skip the device, but continue the namespace scan. */
401 * This works around a known issue in ACPI tables where LPSS devices
402 * have _PS0 and _PS3 without _PSC (and no power resources), so
403 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
405 ret = acpi_device_fix_up_power(adev);
407 /* Skip the device, but continue the namespace scan. */
412 adev->driver_data = pdata;
413 pdev = acpi_create_platform_device(adev);
414 if (!IS_ERR_OR_NULL(pdev)) {
419 adev->driver_data = NULL;
426 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
428 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
431 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
434 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
437 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
439 struct acpi_device *adev;
440 struct lpss_private_data *pdata;
444 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
448 spin_lock_irqsave(&dev->power.lock, flags);
449 if (pm_runtime_suspended(dev)) {
453 pdata = acpi_driver_data(adev);
454 if (WARN_ON(!pdata || !pdata->mmio_base)) {
458 *val = __lpss_reg_read(pdata, reg);
461 spin_unlock_irqrestore(&dev->power.lock, flags);
465 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
472 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
473 ret = lpss_reg_read(dev, reg, <r_value);
477 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
480 static ssize_t lpss_ltr_mode_show(struct device *dev,
481 struct device_attribute *attr, char *buf)
487 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
491 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
492 return sprintf(buf, "%s\n", outstr);
495 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
496 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
497 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
499 static struct attribute *lpss_attrs[] = {
500 &dev_attr_auto_ltr.attr,
501 &dev_attr_sw_ltr.attr,
502 &dev_attr_ltr_mode.attr,
506 static struct attribute_group lpss_attr_group = {
511 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
513 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
514 u32 ltr_mode, ltr_val;
516 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
518 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
519 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
520 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
524 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
525 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
526 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
527 val = LPSS_LTR_MAX_VAL;
528 } else if (val > LPSS_LTR_MAX_VAL) {
529 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
530 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
532 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
535 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
536 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
537 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
538 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
544 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
546 * @pdata: pointer to the private data of the LPSS device
548 * Most LPSS devices have private registers which may loose their context when
549 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
552 static void acpi_lpss_save_ctx(struct device *dev,
553 struct lpss_private_data *pdata)
557 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
558 unsigned long offset = i * sizeof(u32);
560 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
561 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
562 pdata->prv_reg_ctx[i], offset);
567 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
569 * @pdata: pointer to the private data of the LPSS device
571 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
573 static void acpi_lpss_restore_ctx(struct device *dev,
574 struct lpss_private_data *pdata)
579 * The following delay is needed or the subsequent write operations may
580 * fail. The LPSS devices are actually PCI devices and the PCI spec
581 * expects 10ms delay before the device can be accessed after D3 to D0
582 * transition. However some platforms like BSW does not need this delay.
584 unsigned int delay = 10; /* default 10ms delay */
586 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
591 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
592 unsigned long offset = i * sizeof(u32);
594 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
595 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
596 pdata->prv_reg_ctx[i], offset);
600 #ifdef CONFIG_PM_SLEEP
601 static int acpi_lpss_suspend_late(struct device *dev)
603 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
606 ret = pm_generic_suspend_late(dev);
610 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
611 acpi_lpss_save_ctx(dev, pdata);
613 return acpi_dev_suspend_late(dev);
616 static int acpi_lpss_resume_early(struct device *dev)
618 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
621 ret = acpi_dev_resume_early(dev);
625 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
626 acpi_lpss_restore_ctx(dev, pdata);
628 return pm_generic_resume_early(dev);
630 #endif /* CONFIG_PM_SLEEP */
632 static int acpi_lpss_runtime_suspend(struct device *dev)
634 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
637 ret = pm_generic_runtime_suspend(dev);
641 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
642 acpi_lpss_save_ctx(dev, pdata);
644 return acpi_dev_runtime_suspend(dev);
647 static int acpi_lpss_runtime_resume(struct device *dev)
649 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
652 ret = acpi_dev_runtime_resume(dev);
656 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
657 acpi_lpss_restore_ctx(dev, pdata);
659 return pm_generic_runtime_resume(dev);
661 #endif /* CONFIG_PM */
663 static struct dev_pm_domain acpi_lpss_pm_domain = {
666 #ifdef CONFIG_PM_SLEEP
667 .prepare = acpi_subsys_prepare,
668 .complete = acpi_subsys_complete,
669 .suspend = acpi_subsys_suspend,
670 .suspend_late = acpi_lpss_suspend_late,
671 .resume_early = acpi_lpss_resume_early,
672 .freeze = acpi_subsys_freeze,
673 .poweroff = acpi_subsys_suspend,
674 .poweroff_late = acpi_lpss_suspend_late,
675 .restore_early = acpi_lpss_resume_early,
677 .runtime_suspend = acpi_lpss_runtime_suspend,
678 .runtime_resume = acpi_lpss_runtime_resume,
683 static int acpi_lpss_platform_notify(struct notifier_block *nb,
684 unsigned long action, void *data)
686 struct platform_device *pdev = to_platform_device(data);
687 struct lpss_private_data *pdata;
688 struct acpi_device *adev;
689 const struct acpi_device_id *id;
691 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
692 if (!id || !id->driver_data)
695 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
698 pdata = acpi_driver_data(adev);
702 if (pdata->mmio_base &&
703 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
704 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
709 case BUS_NOTIFY_ADD_DEVICE:
710 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
711 if (pdata->dev_desc->flags & LPSS_LTR)
712 return sysfs_create_group(&pdev->dev.kobj,
715 case BUS_NOTIFY_DEL_DEVICE:
716 if (pdata->dev_desc->flags & LPSS_LTR)
717 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
718 pdev->dev.pm_domain = NULL;
727 static struct notifier_block acpi_lpss_nb = {
728 .notifier_call = acpi_lpss_platform_notify,
731 static void acpi_lpss_bind(struct device *dev)
733 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
735 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
738 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
739 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
741 dev_err(dev, "MMIO size insufficient to access LTR\n");
744 static void acpi_lpss_unbind(struct device *dev)
746 dev->power.set_latency_tolerance = NULL;
749 static struct acpi_scan_handler lpss_handler = {
750 .ids = acpi_lpss_device_ids,
751 .attach = acpi_lpss_create_device,
752 .bind = acpi_lpss_bind,
753 .unbind = acpi_lpss_unbind,
756 void __init acpi_lpss_init(void)
758 if (!lpt_clk_init()) {
759 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
760 acpi_scan_add_handler(&lpss_handler);
766 static struct acpi_scan_handler lpss_handler = {
767 .ids = acpi_lpss_device_ids,
770 void __init acpi_lpss_init(void)
772 acpi_scan_add_handler(&lpss_handler);
775 #endif /* CONFIG_X86_INTEL_LPSS */