1 tblgen - Target Description To C++ Code Generator
2 =================================================
7 :program:`tblgen` [*options*] [*filename*]
12 :program:`tblgen` translates from target description (``.td``) files into C++
13 code that can be included in the definition of an LLVM target library. Most
14 users of LLVM will not need to use this program. It is only for assisting with
15 writing an LLVM target backend.
17 The input and output of :program:`tblgen` is beyond the scope of this short
18 introduction; please see the :doc:`introduction to TableGen
21 The *filename* argument specifies the name of a Target Description (``.td``)
22 file to read as input.
31 Print a summary of command line options.
33 .. option:: -o filename
35 Specify the output file name. If ``filename`` is ``-``, then
36 :program:`tblgen` sends its output to standard output.
38 .. option:: -I directory
40 Specify where to find other target description files for inclusion. The
41 ``directory`` value should be a full or partial path to a directory that
42 contains target description files.
44 .. option:: -asmparsernum N
46 Make -gen-asm-parser emit assembly writer number ``N``.
48 .. option:: -asmwriternum N
50 Make -gen-asm-writer emit assembly writer number ``N``.
52 .. option:: -class className
54 Print the enumeration list for this class.
56 .. option:: -print-records
58 Print all records to standard output (default).
60 .. option:: -print-enums
62 Print enumeration values for a class.
64 .. option:: -print-sets
66 Print expanded sets for testing DAG exprs.
68 .. option:: -gen-emitter
70 Generate machine code emitter.
72 .. option:: -gen-register-info
74 Generate registers and register classes info.
76 .. option:: -gen-instr-info
78 Generate instruction descriptions.
80 .. option:: -gen-asm-writer
82 Generate the assembly writer.
84 .. option:: -gen-disassembler
86 Generate disassembler.
88 .. option:: -gen-pseudo-lowering
90 Generate pseudo instruction lowering.
92 .. option:: -gen-dag-isel
94 Generate a DAG (Directed Acycle Graph) instruction selector.
96 .. option:: -gen-asm-matcher
98 Generate assembly instruction matcher.
100 .. option:: -gen-dfa-packetizer
102 Generate DFA Packetizer for VLIW targets.
104 .. option:: -gen-fast-isel
106 Generate a "fast" instruction selector.
108 .. option:: -gen-subtarget
110 Generate subtarget enumerations.
112 .. option:: -gen-intrinsic
114 Generate intrinsic information.
116 .. option:: -gen-tgt-intrinsic
118 Generate target intrinsic information.
120 .. option:: -gen-enhanced-disassembly-info
122 Generate enhanced disassembly info.
126 Show the version number of this program.
131 If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
132 occurs, it will exit with a non-zero value.