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5 <title>The LLVM Target-Independent Code Generator</title>
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10 <div class="doc_title">
11 The LLVM Target-Independent Code Generator
15 <li><a href="#introduction">Introduction</a>
17 <li><a href="#required">Required components in the code generator</a></li>
18 <li><a href="#high-level-design">The high-level design of the code
20 <li><a href="#tablegen">Using TableGen for target description</a></li>
23 <li><a href="#targetdesc">Target description classes</a>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
35 <li><a href="#codegendesc">Machine code description classes</a>
37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
40 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
42 <li><a href="#instselect">Instruction Selection</a>
44 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
45 <li><a href="#selectiondag_process">SelectionDAG Code Generation
47 <li><a href="#selectiondag_build">Initial SelectionDAG
49 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
50 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
51 Phase: the DAG Combiner</a></li>
52 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
53 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Emission
55 <li><a href="#selectiondag_future">Future directions for the
60 <li><a href="#targetimpls">Target description implementations</a>
62 <li><a href="#x86">The X86 backend</a></li>
68 <div class="doc_author">
69 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
72 <div class="doc_warning">
73 <p>Warning: This is a work in progress.</p>
76 <!-- *********************************************************************** -->
77 <div class="doc_section">
78 <a name="introduction">Introduction</a>
80 <!-- *********************************************************************** -->
82 <div class="doc_text">
84 <p>The LLVM target-independent code generator is a framework that provides a
85 suite of reusable components for translating the LLVM internal representation to
86 the machine code for a specified target -- either in assembly form (suitable for
87 a static compiler) or in binary machine code format (usable for a JIT compiler).
88 The LLVM target-independent code generator consists of five main components:</p>
91 <li><a href="#targetdesc">Abstract target description</a> interfaces which
92 capture important properties about various aspects of the machine, independently
93 of how they will be used. These interfaces are defined in
94 <tt>include/llvm/Target/</tt>.</li>
96 <li>Classes used to represent the <a href="#codegendesc">machine code</a> being
97 generated for a target. These classes are intended to be abstract enough to
98 represent the machine code for <i>any</i> target machine. These classes are
99 defined in <tt>include/llvm/CodeGen/</tt>.</li>
101 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
102 various phases of native code generation (register allocation, scheduling, stack
103 frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
105 <li><a href="#targetimpls">Implementations of the abstract target description
106 interfaces</a> for particular targets. These machine descriptions make use of
107 the components provided by LLVM, and can optionally provide custom
108 target-specific passes, to build complete code generators for a specific target.
109 Target descriptions live in <tt>lib/Target/</tt>.</li>
111 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
112 completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
113 interface for target-specific issues. The code for the target-independent
114 JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
119 Depending on which part of the code generator you are interested in working on,
120 different pieces of this will be useful to you. In any case, you should be
121 familiar with the <a href="#targetdesc">target description</a> and <a
122 href="#codegendesc">machine code representation</a> classes. If you want to add
123 a backend for a new target, you will need to <a href="#targetimpls">implement the
124 target description</a> classes for your new target and understand the <a
125 href="LangRef.html">LLVM code representation</a>. If you are interested in
126 implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
127 should only depend on the target-description and machine code representation
128 classes, ensuring that it is portable.
133 <!-- ======================================================================= -->
134 <div class="doc_subsection">
135 <a name="required">Required components in the code generator</a>
138 <div class="doc_text">
140 <p>The two pieces of the LLVM code generator are the high-level interface to the
141 code generator and the set of reusable components that can be used to build
142 target-specific backends. The two most important interfaces (<a
143 href="#targetmachine"><tt>TargetMachine</tt></a> and <a
144 href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
145 required to be defined for a backend to fit into the LLVM system, but the others
146 must be defined if the reusable code generator components are going to be
149 <p>This design has two important implications. The first is that LLVM can
150 support completely non-traditional code generation targets. For example, the C
151 backend does not require register allocation, instruction selection, or any of
152 the other standard components provided by the system. As such, it only
153 implements these two interfaces, and does its own thing. Another example of a
154 code generator like this is a (purely hypothetical) backend that converts LLVM
155 to the GCC RTL form and uses GCC to emit machine code for a target.</p>
157 <p>This design also implies that it is possible to design and
158 implement radically different code generators in the LLVM system that do not
159 make use of any of the built-in components. Doing so is not recommended at all,
160 but could be required for radically different targets that do not fit into the
161 LLVM machine description model: programmable FPGAs for example.</p>
163 <p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
164 generator uses almost entirely different code paths than described in this
165 document. For this reason, there are some deprecated interfaces (such as
166 <tt>TargetRegInfo</tt> and <tt>TargetSchedInfo</tt>), which are only used by the
167 V9 backend and should not be used by any other targets. Also, all code in the
168 <tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
169 deprecated, and should not be used as the basis for future code generator work.
170 The SparcV9 backend is slowly being merged into the rest of the
171 target-independent code generators, but this is a low-priority process with no
172 predictable completion date.</p>
176 <!-- ======================================================================= -->
177 <div class="doc_subsection">
178 <a name="high-level-design">The high-level design of the code generator</a>
181 <div class="doc_text">
183 <p>The LLVM target-independent code generator is designed to support efficient and
184 quality code generation for standard register-based microprocessors. Code
185 generation in this model is divided into the following stages:</p>
188 <li><b><a href="#instselect">Instruction Selection</a></b> - Determining an
189 efficient implementation of the input LLVM code in the target instruction set.
190 This stage produces the initial code for the program in the target instruction
191 set, then makes use of virtual registers in SSA form and physical registers that
192 represent any required register assignments due to target constraints or calling
195 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
196 optional stage consists of a series of machine-code optimizations that
197 operate on the SSA-form produced by the instruction selector. Optimizations
198 like modulo-scheduling, normal scheduling, or peephole optimization work here.
201 <li><b><a name="#regalloc">Register Allocation</a></b> - The
202 target code is transformed from an infinite virtual register file in SSA form
203 to the concrete register file used by the target. This phase introduces spill
204 code and eliminates all virtual register references from the program.</li>
206 <li><b><a name="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
207 machine code has been generated for the function and the amount of stack space
208 required is known (used for LLVM alloca's and spill slots), the prolog and
209 epilog code for the function can be inserted and "abstract stack location
210 references" can be eliminated. This stage is responsible for implementing
211 optimizations like frame-pointer elimination and stack packing.</li>
213 <li><b><a name="latemco">Late Machine Code Optimizations</a></b> - Optimizations
214 that operate on "final" machine code can go here, such as spill code scheduling
215 and peephole optimizations.</li>
217 <li><b><a name="codemission">Code Emission</a></b> - The final stage actually
218 puts out the code for the current function, either in the target assembler
219 format or in machine code.</li>
224 The code generator is based on the assumption that the instruction selector will
225 use an optimal pattern matching selector to create high-quality sequences of
226 native instructions. Alternative code generator designs based on pattern
228 aggressive iterative peephole optimization are much slower. This design
229 permits efficient compilation (important for JIT environments) and
230 aggressive optimization (used when generating code offline) by allowing
231 components of varying levels of sophistication to be used for any step of
235 In addition to these stages, target implementations can insert arbitrary
236 target-specific passes into the flow. For example, the X86 target uses a
237 special pass to handle the 80x87 floating point stack architecture. Other
238 targets with unusual requirements can be supported with custom passes as needed.
244 <!-- ======================================================================= -->
245 <div class="doc_subsection">
246 <a name="tablegen">Using TableGen for target description</a>
249 <div class="doc_text">
251 <p>The target description classes require a detailed description of the target
252 architecture. These target descriptions often have a large amount of common
253 information (e.g., an <tt>add</tt> instruction is almost identical to a
254 <tt>sub</tt> instruction).
255 In order to allow the maximum amount of commonality to be factored out, the LLVM
256 code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
257 describe big chunks of the target machine, which allows the use of
258 domain-specific and target-specific abstractions to reduce the amount of
264 <!-- *********************************************************************** -->
265 <div class="doc_section">
266 <a name="targetdesc">Target description classes</a>
268 <!-- *********************************************************************** -->
270 <div class="doc_text">
272 <p>The LLVM target description classes (which are located in the
273 <tt>include/llvm/Target</tt> directory) provide an abstract description of the
274 target machine; independent of any particular client. These classes are
275 designed to capture the <i>abstract</i> properties of the target (such as the
276 instructions and registers it has), and do not incorporate any particular pieces
277 of code generation algorithms. These interfaces do not take interference graphs
278 as inputs or other algorithm-specific data structures.</p>
280 <p>All of the target description classes (except the <tt><a
281 href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
282 the concrete target implementation, and have virtual methods implemented. To
283 get to these implementations, the <tt><a
284 href="#targetmachine">TargetMachine</a></tt> class provides accessors that
285 should be implemented by the target.</p>
289 <!-- ======================================================================= -->
290 <div class="doc_subsection">
291 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
294 <div class="doc_text">
296 <p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
297 access the target-specific implementations of the various target description
298 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
299 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
300 designed to be specialized by
301 a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
302 implements the various virtual methods. The only required target description
303 class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
304 code generator components are to be used, the other interfaces should be
305 implemented as well.</p>
310 <!-- ======================================================================= -->
311 <div class="doc_subsection">
312 <a name="targetdata">The <tt>TargetData</tt> class</a>
315 <div class="doc_text">
317 <p>The <tt>TargetData</tt> class is the only required target description class,
318 and it is the only class that is not extensible. You cannot derived a new
319 class from it. <tt>TargetData</tt> specifies information about how the target
320 lays out memory for structures, the alignment requirements for various data
321 types, the size of pointers in the target, and whether the target is
322 little-endian or big-endian.</p>
326 <!-- ======================================================================= -->
327 <div class="doc_subsection">
328 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
331 <div class="doc_text">
333 <p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
334 selectors primarily to describe how LLVM code should be lowered to SelectionDAG
335 operations. Among other things, this class indicates:
336 <ul><li>an initial register class to use for various ValueTypes,</li>
337 <li>which operations are natively supported by the target machine,</li>
338 <li>the return type of setcc operations, and</li>
339 <li>the type to use for shift amounts, etc</li>.
348 <!-- ======================================================================= -->
349 <div class="doc_subsection">
350 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
353 <div class="doc_text">
355 <p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
356 <tt>TargetRegisterInfo</tt>) is used to describe the register file of the
357 target and any interactions between the registers.</p>
359 <p>Registers in the code generator are represented in the code generator by
360 unsigned numbers. Physical registers (those that actually exist in the target
361 description) are unique small numbers, and virtual registers are generally
364 <p>Each register in the processor description has an associated
365 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the register
366 (used for assembly output and debugging dumps) and a set of aliases (used to
367 indicate that one register overlaps with another).
370 <p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
371 exposes a set of processor specific register classes (instances of the
372 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
373 registers that have the same properties (for example, they are all 32-bit
374 integer registers). Each SSA virtual register created by the instruction
375 selector has an associated register class. When the register allocator runs, it
376 replaces virtual registers with a physical register in the set.</p>
379 The target-specific implementations of these classes is auto-generated from a <a
380 href="TableGenFundamentals.html">TableGen</a> description of the register file.
385 <!-- ======================================================================= -->
386 <div class="doc_subsection">
387 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
390 <div class="doc_text">
391 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
392 instructions supported by the target. It is essentially an array of
393 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
394 instruction the target supports. Descriptors define things like the mnemonic
395 for the opcode, the number of operands, the list of implicit register uses
396 and defs, whether the instruction has certain target-independent properties
397 (accesses memory, is commutable, etc), and holds any target-specific flags.</p>
400 <!-- ======================================================================= -->
401 <div class="doc_subsection">
402 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
405 <div class="doc_text">
406 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
407 stack frame layout of the target. It holds the direction of stack growth,
408 the known stack alignment on entry to each function, and the offset to the
409 locals area. The offset to the local area is the offset from the stack
410 pointer on function entry to the first location where function data (local
411 variables, spill locations) can be stored.</p>
414 <!-- ======================================================================= -->
415 <div class="doc_subsection">
416 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
419 <div class="doc_text">
426 <!-- ======================================================================= -->
427 <div class="doc_subsection">
428 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
431 <!-- *********************************************************************** -->
432 <div class="doc_section">
433 <a name="codegendesc">Machine code description classes</a>
435 <!-- *********************************************************************** -->
437 <div class="doc_text">
440 At the high-level, LLVM code is translated to a machine specific representation
441 formed out of MachineFunction, MachineBasicBlock, and <a
442 href="#machineinstr"><tt>MachineInstr</tt></a> instances
443 (defined in include/llvm/CodeGen). This representation is completely target
444 agnostic, representing instructions in their most abstract form: an opcode and a
445 series of operands. This representation is designed to support both SSA
446 representation for machine code, as well as a register allocated, non-SSA form.
451 <!-- ======================================================================= -->
452 <div class="doc_subsection">
453 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
456 <div class="doc_text">
458 <p>Target machine instructions are represented as instances of the
459 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
460 representing machine instructions. In particular, it only keeps track of
461 an opcode number and a set of operands.</p>
463 <p>The opcode number is a simple unsigned number that only has meaning to a
464 specific backend. All of the instructions for a target should be defined in
465 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
466 are auto-generated from this description. The <tt>MachineInstr</tt> class does
467 not have any information about how to interpret the instruction (i.e., what the
468 semantics of the instruction are): for that you must refer to the
469 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
471 <p>The operands of a machine instruction can be of several different types:
472 they can be a register reference, constant integer, basic block reference, etc.
473 In addition, a machine operand should be marked as a def or a use of the value
474 (though only registers are allowed to be defs).</p>
476 <p>By convention, the LLVM code generator orders instruction operands so that
477 all register definitions come before the register uses, even on architectures
478 that are normally printed in other orders. For example, the SPARC add
479 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
480 and stores the result into the "%i3" register. In the LLVM code generator,
481 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
484 <p>Keeping destination (definition) operands at the beginning of the operand
485 list has several advantages. In particular, the debugging printer will print
486 the instruction like this:</p>
492 <p>If the first operand is a def, and it is also easier to <a
493 href="#buildmi">create instructions</a> whose only def is the first
498 <!-- _______________________________________________________________________ -->
499 <div class="doc_subsubsection">
500 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
503 <div class="doc_text">
505 <p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
506 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
507 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
508 instructions. Usage of the <tt>BuildMI</tt> functions look like this:
512 // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
513 // instruction. The '1' specifies how many operands will be added.
514 MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
516 // Create the same instr, but insert it at the end of a basic block.
517 MachineBasicBlock &MBB = ...
518 BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
520 // Create the same instr, but insert it before a specified iterator point.
521 MachineBasicBlock::iterator MBBI = ...
522 BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
524 // Create a 'cmp Reg, 0' instruction, no destination reg.
525 MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
526 // Create an 'sahf' instruction which takes no operands and stores nothing.
527 MI = BuildMI(X86::SAHF, 0);
529 // Create a self looping branch instruction.
530 BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
534 The key thing to remember with the <tt>BuildMI</tt> functions is that you have
535 to specify the number of operands that the machine instruction will take. This
536 allows for efficient memory allocation. You also need to specify if operands
537 default to be uses of values, not definitions. If you need to add a definition
538 operand (other than the optional destination register), you must explicitly
544 <!-- _______________________________________________________________________ -->
545 <div class="doc_subsubsection">
546 <a name="fixedregs">Fixed (preassigned) registers</a>
549 <div class="doc_text">
551 <p>One important issue that the code generator needs to be aware of is the
552 presence of fixed registers. In particular, there are often places in the
553 instruction stream where the register allocator <em>must</em> arrange for a
554 particular value to be in a particular register. This can occur due to
555 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
556 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
557 conventions. In any case, the instruction selector should emit code that
558 copies a virtual register into or out of a physical register when needed.</p>
560 <p>For example, consider this simple LLVM example:</p>
563 int %test(int %X, int %Y) {
569 <p>The X86 instruction selector produces this machine code for the div
571 "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
575 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
576 %reg1027 = sar %reg1024, 31
577 %EDX = mov %reg1027 ;; Sign extend X into EDX
578 idiv %reg1025 ;; Divide by Y (in reg1025)
579 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
582 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
586 <p>By the end of code generation, the register allocator has coalesced
587 the registers and deleted the resultant identity moves, producing the
591 ;; X is in EAX, Y is in ECX
598 <p>This approach is extremely general (if it can handle the X86 architecture,
599 it can handle anything!) and allows all of the target specific
600 knowledge about the instruction stream to be isolated in the instruction
601 selector. Note that physical registers should have a short lifetime for good
602 code generation, and all physical registers are assumed dead on entry and
603 exit of basic blocks (before register allocation). Thus if you need a value
604 to be live across basic block boundaries, it <em>must</em> live in a virtual
609 <!-- _______________________________________________________________________ -->
610 <div class="doc_subsubsection">
611 <a name="ssa">Machine code SSA form</a>
614 <div class="doc_text">
616 <p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
617 are maintained in SSA-form until register allocation happens. For the most
618 part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
619 become machine code PHI nodes, and virtual registers are only allowed to have a
620 single definition.</p>
622 <p>After register allocation, machine code is no longer in SSA-form, as there
623 are no virtual registers left in the code.</p>
627 <!-- *********************************************************************** -->
628 <div class="doc_section">
629 <a name="codegenalgs">Target-independent code generation algorithms</a>
631 <!-- *********************************************************************** -->
633 <div class="doc_text">
635 <p>This section documents the phases described in the <a
636 href="high-level-design">high-level design of the code generator</a>. It
637 explains how they work and some of the rationale behind their design.</p>
641 <!-- ======================================================================= -->
642 <div class="doc_subsection">
643 <a name="instselect">Instruction Selection</a>
646 <div class="doc_text">
648 Instruction Selection is the process of translating LLVM code presented to the
649 code generator into target-specific machine instructions. There are several
650 well-known ways to do this in the literature. In LLVM there are two main forms:
651 the SelectionDAG based instruction selector framework and an old-style 'simple'
652 instruction selector (which effectively peephole selects each LLVM instruction
653 into a series of machine instructions). We recommend that all targets use the
654 SelectionDAG infrastructure.
657 <p>Portions of the DAG instruction selector are generated from the target
658 description files (<tt>*.td</tt>) files. Eventually, we aim for the entire
659 instruction selector to be generated from these <tt>.td</tt> files.</p>
662 <!-- _______________________________________________________________________ -->
663 <div class="doc_subsubsection">
664 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
667 <div class="doc_text">
670 The SelectionDAG provides an abstraction for code representation in a way that
671 is amenable to instruction selection using automatic techniques
672 (e.g. dynamic-programming based optimal pattern matching selectors), It is also
673 well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
674 large variety of very-low-level (but target-independent)
675 <a href="#selectiondag_optimize">optimizations</a> may be
676 performed: ones which require extensive information about the instructions
677 efficiently supported by the target.
681 The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
682 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
683 operation code (Opcode) that indicates what operation the node performs.
684 The various operation node types are described at the top of the
685 <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the
686 operation, nodes may contain additional information (e.g. the condition code
687 for a SETCC node) contained in a derived class.</p>
689 <p>Although most operations define a single value, each node in the graph may
690 define multiple values. For example, a combined div/rem operation will define
691 both the dividend and the remainder. Many other situations require multiple
692 values as well. Each node also has some number of operands, which are edges
693 to the node defining the used value. Because nodes may define multiple values,
694 edges are represented by instances of the <tt>SDOperand</tt> class, which is
695 a <SDNode, unsigned> pair, indicating the node and result
696 value being used, respectively. Each value produced by an SDNode has an
697 associated MVT::ValueType, indicating what type the value is.
701 SelectionDAGs contain two different kinds of values: those that represent data
702 flow and those that represent control flow dependencies. Data values are simple
703 edges with an integer or floating point value type. Control edges are
704 represented as "chain" edges which are of type MVT::Other. These edges provide
705 an ordering between nodes that have side effects (such as
706 loads/stores/calls/return/etc). All nodes that have side effects should take a
707 token chain as input and produce a new one as output. By convention, token
708 chain inputs are always operand #0, and chain results are always the last
709 value produced by an operation.</p>
712 A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
713 always a marker node with an Opcode of ISD::EntryToken. The Root node is the
714 final side-effecting node in the token chain. For example, in a single basic
715 block function, this would be the return node.
719 One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
720 DAG. A legal DAG for a target is one that only uses supported operations and
721 supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
722 or i64 type would be illegal. The <a href="#selectiondag_legalize">legalize</a>
723 phase is responsible for turning an illegal DAG into a legal DAG.
727 <!-- _______________________________________________________________________ -->
728 <div class="doc_subsubsection">
729 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
732 <div class="doc_text">
735 SelectionDAG-based instruction selection consists of the following steps:
739 <li><a href="#selectiondag_build">Build initial DAG</a> - This stage performs
740 a simple translation from the input LLVM code to an illegal SelectionDAG.
742 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
743 performs simple optimizations on the SelectionDAG to simplify it and
744 recognize meta instructions (like rotates and div/rem pairs) for
745 targets that support these meta operations. This makes the resultant code
746 more efficient and the 'select instructions from DAG' phase (below) simpler.
748 <li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
749 converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
750 unsupported operations and data types.</li>
751 <li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
752 second run of the SelectionDAG optimized the newly legalized DAG, to
753 eliminate inefficiencies introduced by legalization.</li>
754 <li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
755 the target instruction selector matches the DAG operations to target
756 instructions. This process translates the target-independent input DAG into
757 another DAG of target instructions.</li>
758 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Emission</a>
759 - The last phase assigns a linear order to the instructions in the
760 target-instruction DAG and emits them into the MachineFunction being
761 compiled. This step uses traditional prepass scheduling techniques.</li>
764 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
765 rest of the code generation passes are run.</p>
769 <!-- _______________________________________________________________________ -->
770 <div class="doc_subsubsection">
771 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
774 <div class="doc_text">
777 The initial SelectionDAG is naively peephole expanded from the LLVM input by
778 the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file. The
779 intent of this pass is to expose as much low-level, target-specific details
780 to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
781 add turns into an SDNode add while a geteelementptr is expanded into the obvious
782 arithmetic). This pass requires target-specific hooks to lower calls and
783 returns, varargs, etc. For these features, the TargetLowering interface is
789 <!-- _______________________________________________________________________ -->
790 <div class="doc_subsubsection">
791 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
794 <div class="doc_text">
796 <p>The Legalize phase is in charge of converting a DAG to only use the types and
797 operations that are natively supported by the target. This involves two major
801 <li><p>Convert values of unsupported types to values of supported types.</p>
802 <p>There are two main ways of doing this: promoting a small type to a larger
803 type (e.g. f32 -> f64, or i16 -> i32), and breaking up large
805 to smaller ones (e.g. implementing i64 with i32 operations where
806 possible). Type conversions can insert sign and zero extensions as
807 needed to make sure that the final code has the same behavior as the
811 <li><p>Eliminate operations that are not supported by the target in a supported
813 <p>Targets often have wierd constraints, such as not supporting every
814 operation on every supported datatype (e.g. X86 does not support byte
815 conditional moves). Legalize takes care of either open-coding another
816 sequence of operations to emulate the operation (this is known as
817 expansion), promoting to a larger type that supports the operation
818 (promotion), or using a target-specific hook to implement the
824 Instead of using a Legalize pass, we could require that every target-specific
825 <a href="#selectiondag_optimize">selector</a> supports and expands every
826 operator and type even if they are not supported and may require many
827 instructions to implement (in fact, this is the approach taken by the
828 "simple" selectors). However, using a Legalize pass allows all of the
829 cannonicalization patterns to be shared across targets which makes it very
830 easy to optimize the cannonicalized code because it is still in the form of
836 <!-- _______________________________________________________________________ -->
837 <div class="doc_subsubsection">
838 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
842 <div class="doc_text">
845 The SelectionDAG optimization phase is run twice for code generation: once
846 immediately after the DAG is built and once after legalization. The first run
847 of the pass allows the initial code to be cleaned up (e.g. performing
848 optimizations that depend on knowing that the operators have restricted type
849 inputs). The second run of the pass cleans up the messy code generated by the
850 Legalize pass, allowing Legalize to be very simple since it can ignore many
855 One important class of optimizations performed is optimizing inserted sign and
856 zero extension instructions. We currently use ad-hoc techniques, but could move
857 to more rigorous techniques in the future. Here are some good
858 papers on the subject:</p>
861 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
862 integer arithmetic</a>"<br>
863 Kevin Redwine and Norman Ramsey<br>
864 International Conference on Compiler Construction (CC) 2004
869 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
870 sign extension elimination</a>"<br>
871 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
872 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
878 <!-- _______________________________________________________________________ -->
879 <div class="doc_subsubsection">
880 <a name="selectiondag_select">SelectionDAG Select Phase</a>
883 <div class="doc_text">
885 <p>The Select phase is the bulk of the target-specific code for instruction
886 selection. This phase takes a legal SelectionDAG as input, and does simple
887 pattern matching on the DAG to generate code. In time, the Select phase will
888 be automatically generated from the target's InstrInfo.td file, which is why we
889 want to make the Select phase as simple and mechanical as possible.</p>
893 <!-- _______________________________________________________________________ -->
894 <div class="doc_subsubsection">
895 <a name="selectiondag_sched">SelectionDAG Scheduling and Emission Phase</a>
898 <div class="doc_text">
900 <p>The scheduling phase takes the DAG of target instructions from the selection
901 phase and assigns an order. The scheduler can pick an order depending on
902 various constraints of the machines (i.e. order for minimal register pressure or
903 try to cover instruction latencies). Once an order is established, the DAG is
904 converted to a list of <a href="#machineinstr">MachineInstr</a>s and the
905 Selection DAG is destroyed.
910 <!-- _______________________________________________________________________ -->
911 <div class="doc_subsubsection">
912 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
915 <div class="doc_text">
918 <li>Optional function-at-a-time selection.</li>
919 <li>Auto-generate entire selector from .td file.</li>
925 <!-- ======================================================================= -->
926 <div class="doc_subsection">
927 <a name="ssamco">SSA-based Machine Code Optimizations</a>
929 <div class="doc_text"><p>To Be Written</p></div>
930 <!-- ======================================================================= -->
931 <div class="doc_subsection">
932 <a name="regalloc">Register Allocation</a>
934 <div class="doc_text"><p>To Be Written</p></div>
935 <!-- ======================================================================= -->
936 <div class="doc_subsection">
937 <a name="proepicode">Prolog/Epilog Code Insertion</a>
939 <div class="doc_text"><p>To Be Written</p></div>
940 <!-- ======================================================================= -->
941 <div class="doc_subsection">
942 <a name="latemco">Late Machine Code Optimizations</a>
944 <div class="doc_text"><p>To Be Written</p></div>
945 <!-- ======================================================================= -->
946 <div class="doc_subsection">
947 <a name="codemission">Code Emission</a>
950 <!-- *********************************************************************** -->
951 <div class="doc_section">
952 <a name="targetimpls">Target description implementations</a>
954 <!-- *********************************************************************** -->
956 <div class="doc_text">
958 <p>This section of the document explains features or design decisions that
959 are specific to the code generator for a particular target.</p>
964 <!-- ======================================================================= -->
965 <div class="doc_subsection">
966 <a name="x86">The X86 backend</a>
969 <div class="doc_text">
972 The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
973 code generator currently targets a generic P6-like processor. As such, it
974 produces a few P6-and-above instructions (like conditional moves), but it does
975 not make use of newer features like MMX or SSE. In the future, the X86 backend
976 will have sub-target support added for specific processor families and
981 <!-- _______________________________________________________________________ -->
982 <div class="doc_subsubsection">
983 <a name="x86_tt">X86 Target Triples Supported</a>
986 <div class="doc_text">
988 The following are the known target triples that are supported by the X86
989 backend. This is not an exhaustive list, but it would be useful to add those
994 <li><b>i686-pc-linux-gnu</b> - Linux</li>
995 <li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
996 <li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
997 <li><b>i686-pc-mingw32</b> - MingW on Win32</li>
998 <li><b>i686-apple-darwin*</b> - Apple Darwin</li>
1003 <!-- _______________________________________________________________________ -->
1004 <div class="doc_subsubsection">
1005 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1008 <div class="doc_text">
1010 <p>The x86 has a very flexible way of accessing memory. It is capable of
1011 forming memory addresses of the following expression directly in integer
1012 instructions (which use ModR/M addressing):</p>
1015 Base+[1,2,4,8]*IndexReg+Disp32
1018 <p>In order to represent this, LLVM tracks no less than 4 operands for each
1019 memory operand of this form. This means that the "load" form of 'mov' has the
1020 following <tt>MachineOperand</tt>s in this order:</p>
1024 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1025 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1028 <p>Stores, and all other instructions, treat the four memory operands in the
1029 same way, in the same order.</p>
1033 <!-- _______________________________________________________________________ -->
1034 <div class="doc_subsubsection">
1035 <a name="x86_names">Instruction naming</a>
1038 <div class="doc_text">
1041 An instruction name consists of the base name, a default operand size, and a
1042 a character per operand with an optional special size. For example:</p>
1045 <tt>ADD8rr</tt> -> add, 8-bit register, 8-bit register<br>
1046 <tt>IMUL16rmi</tt> -> imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1047 <tt>IMUL16rmi8</tt> -> imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1048 <tt>MOVSX32rm16</tt> -> movsx, 32-bit register, 16-bit memory
1053 <!-- *********************************************************************** -->
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