2 * arch/xtensa/kernel/pci.c
4 * PCI bios-type initialisation for PCI machines
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Copyright (C) 2001-2005 Tensilica Inc.
13 * Based largely on work from Cort (ppc/kernel/pci.c)
14 * IO functions copied from sparc.
16 * Chris Zankel <chris@zankel.net>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/sched.h>
26 #include <linux/errno.h>
27 #include <linux/bootmem.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/platform.h>
35 #define DBG(x...) printk(x)
44 * pcibios_alloc_controller
45 * pcibios_enable_device
47 * pcibios_align_resource
54 struct pci_controller* pci_ctrl_head;
55 struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;
57 static int pci_bus_count;
60 * We need to avoid collisions with `mirrored' VGA ports
61 * and other strange ISA hardware, so we always want the
62 * addresses to be allocated in the 0x000-0x0ff region
65 * Why? Because some silly external IO cards only decode
66 * the low 10 bits of the IO address. The 0x00-0xff region
67 * is reserved for motherboard devices that decode all 16
68 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
69 * but we want to try to avoid allocating at 0x2900-0x2bff
70 * which might have be mirrored at 0x0100-0x03ff..
73 pcibios_align_resource(void *data, const struct resource *res,
74 resource_size_t size, resource_size_t align)
76 struct pci_dev *dev = data;
77 resource_size_t start = res->start;
79 if (res->flags & IORESOURCE_IO) {
81 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
82 " (%ld bytes)\n", pci_name(dev),
83 dev->resource - res, size);
87 start = (start + 0x3ff) & ~0x3ff;
94 pcibios_enable_resources(struct pci_dev *dev, int mask)
100 pci_read_config_word(dev, PCI_COMMAND, &cmd);
102 for(idx=0; idx<6; idx++) {
103 r = &dev->resource[idx];
104 if (!r->start && r->end) {
105 printk (KERN_ERR "PCI: Device %s not available because "
106 "of resource collisions\n", pci_name(dev));
109 if (r->flags & IORESOURCE_IO)
110 cmd |= PCI_COMMAND_IO;
111 if (r->flags & IORESOURCE_MEM)
112 cmd |= PCI_COMMAND_MEMORY;
114 if (dev->resource[PCI_ROM_RESOURCE].start)
115 cmd |= PCI_COMMAND_MEMORY;
116 if (cmd != old_cmd) {
117 printk("PCI: Enabling device %s (%04x -> %04x)\n",
118 pci_name(dev), old_cmd, cmd);
119 pci_write_config_word(dev, PCI_COMMAND, cmd);
124 struct pci_controller * __init pcibios_alloc_controller(void)
126 struct pci_controller *pci_ctrl;
128 pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl));
129 memset(pci_ctrl, 0, sizeof(struct pci_controller));
131 *pci_ctrl_tail = pci_ctrl;
132 pci_ctrl_tail = &pci_ctrl->next;
137 static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
138 struct list_head *resources)
140 struct resource *res;
141 unsigned long io_offset;
144 io_offset = (unsigned long)pci_ctrl->io_space.base;
145 res = &pci_ctrl->io_resource;
148 printk (KERN_ERR "I/O resource not set for host"
149 " bridge %d\n", pci_ctrl->index);
151 res->end = IO_SPACE_LIMIT;
152 res->flags = IORESOURCE_IO;
154 res->start += io_offset;
155 res->end += io_offset;
156 pci_add_resource_offset(resources, res, io_offset);
158 for (i = 0; i < 3; i++) {
159 res = &pci_ctrl->mem_resources[i];
163 printk(KERN_ERR "Memory resource not set for "
164 "host bridge %d\n", pci_ctrl->index);
167 res->flags = IORESOURCE_MEM;
169 pci_add_resource(resources, res);
173 static int __init pcibios_init(void)
175 struct pci_controller *pci_ctrl;
176 struct list_head resources;
178 int next_busno = 0, i;
180 printk("PCI: Probing PCI hardware\n");
182 /* Scan all of the recorded PCI controllers. */
183 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
184 pci_ctrl->last_busno = 0xff;
185 INIT_LIST_HEAD(&resources);
186 pci_controller_apertures(pci_ctrl, &resources);
187 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
188 pci_ctrl->ops, pci_ctrl, &resources);
190 pci_ctrl->last_busno = bus->busn_res.end;
191 if (next_busno <= pci_ctrl->last_busno)
192 next_busno = pci_ctrl->last_busno+1;
194 pci_bus_count = next_busno;
196 return platform_pcibios_fixup();
199 subsys_initcall(pcibios_init);
201 void __init pcibios_fixup_bus(struct pci_bus *bus)
204 /* This is a subordinate bridge */
205 pci_read_bridge_bases(bus);
209 char __init *pcibios_setup(char *str)
214 void pcibios_set_master(struct pci_dev *dev)
216 /* No special bus mastering setup handling */
219 /* the next one is stolen from the alpha port... */
222 pcibios_update_irq(struct pci_dev *dev, int irq)
224 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
227 int pcibios_enable_device(struct pci_dev *dev, int mask)
233 pci_read_config_word(dev, PCI_COMMAND, &cmd);
235 for (idx=0; idx<6; idx++) {
236 r = &dev->resource[idx];
237 if (!r->start && r->end) {
238 printk(KERN_ERR "PCI: Device %s not available because "
239 "of resource collisions\n", pci_name(dev));
242 if (r->flags & IORESOURCE_IO)
243 cmd |= PCI_COMMAND_IO;
244 if (r->flags & IORESOURCE_MEM)
245 cmd |= PCI_COMMAND_MEMORY;
247 if (cmd != old_cmd) {
248 printk("PCI: Enabling device %s (%04x -> %04x)\n",
249 pci_name(dev), old_cmd, cmd);
250 pci_write_config_word(dev, PCI_COMMAND, cmd);
256 #ifdef CONFIG_PROC_FS
259 * Return the index of the PCI controller for device pdev.
263 pci_controller_num(struct pci_dev *dev)
265 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
266 return pci_ctrl->index;
269 #endif /* CONFIG_PROC_FS */
272 * Platform support for /proc/bus/pci/X/Y mmap()s,
273 * modelled on the sparc64 implementation by Dave Miller.
278 * Adjust vm_pgoff of VMA such that it is the physical page offset
279 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
281 * Basically, the user finds the base address for his device which he wishes
282 * to mmap. They read the 32-bit value from the config space base register,
283 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
284 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
286 * Returns negative error code on failure, zero on success.
288 static __inline__ int
289 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
290 enum pci_mmap_state mmap_state)
292 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
293 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
294 unsigned long io_offset = 0;
298 return -EINVAL; /* should never happen */
300 /* If memory, add on the PCI bridge address offset */
301 if (mmap_state == pci_mmap_mem) {
302 res_bit = IORESOURCE_MEM;
304 io_offset = (unsigned long)pci_ctrl->io_space.base;
306 res_bit = IORESOURCE_IO;
310 * Check that the offset requested corresponds to one of the
311 * resources of the device.
313 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
314 struct resource *rp = &dev->resource[i];
315 int flags = rp->flags;
317 /* treat ROM as memory (should be already) */
318 if (i == PCI_ROM_RESOURCE)
319 flags |= IORESOURCE_MEM;
321 /* Active and same type? */
322 if ((flags & res_bit) == 0)
325 /* In the range of this resource? */
326 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
329 /* found it! construct the final physical address */
330 if (mmap_state == pci_mmap_io)
331 offset += pci_ctrl->io_space.start - io_offset;
332 vma->vm_pgoff = offset >> PAGE_SHIFT;
340 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
343 static __inline__ void
344 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
345 enum pci_mmap_state mmap_state, int write_combine)
347 int prot = pgprot_val(vma->vm_page_prot);
349 /* Set to write-through */
350 prot &= ~_PAGE_NO_CACHE;
353 prot |= _PAGE_WRITETHRU;
355 vma->vm_page_prot = __pgprot(prot);
359 * Perform the actual remap of the pages for a PCI device mapping, as
360 * appropriate for this architecture. The region in the process to map
361 * is described by vm_start and vm_end members of VMA, the base physical
362 * address is found in vm_pgoff.
363 * The pci device structure is provided so that architectures may make mapping
364 * decisions on a per-device or per-bus basis.
366 * Returns a negative error code on failure, zero on success.
368 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
369 enum pci_mmap_state mmap_state,
374 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
378 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
380 ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
381 vma->vm_end - vma->vm_start,vma->vm_page_prot);