arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53 #define __ex_clear(x, reg) \
  54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  55
  56 MODULE_AUTHOR("Qumranet");
  57 MODULE_LICENSE("GPL");
  58
  59 static const struct x86_cpu_id vmx_cpu_id[] = {
  60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  61         {}
  62 };
  63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  64
  65 static bool __read_mostly enable_vpid = 1;
  66 module_param_named(vpid, enable_vpid, bool, 0444);
  67
  68 static bool __read_mostly flexpriority_enabled = 1;
  69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_ept = 1;
  72 module_param_named(ept, enable_ept, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_unrestricted_guest = 1;
  75 module_param_named(unrestricted_guest,
  76                         enable_unrestricted_guest, bool, S_IRUGO);
  77
  78 static bool __read_mostly enable_ept_ad_bits = 1;
  79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  80
  81 static bool __read_mostly emulate_invalid_guest_state = true;
  82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  83
  84 static bool __read_mostly vmm_exclusive = 1;
  85 module_param(vmm_exclusive, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 110 #define KVM_VM_CR0_ALWAYS_ON                                            \
 111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 115
 116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 118
 119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 120
 121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 122
 123 /*
 124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 125  * ple_gap:    upper bound on the amount of time between two successive
 126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 127  *             According to test, this time is usually smaller than 128 cycles.
 128  * ple_window: upper bound on the amount of time a guest is allowed to execute
 129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 130  *             less than 2^12 cycles
 131  * Time is measured based on a counter that runs at the same rate as the TSC,
 132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 133  */
 134 #define KVM_VMX_DEFAULT_PLE_GAP           128
 135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 140
 141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 142 module_param(ple_gap, int, S_IRUGO);
 143
 144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 145 module_param(ple_window, int, S_IRUGO);
 146
 147 /* Default doubles per-vcpu window every exit. */
 148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 149 module_param(ple_window_grow, int, S_IRUGO);
 150
 151 /* Default resets per-vcpu window every exit to ple_window. */
 152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 153 module_param(ple_window_shrink, int, S_IRUGO);
 154
 155 /* Default is to compute the maximum so we can never overflow. */
 156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 158 module_param(ple_window_max, int, S_IRUGO);
 159
 160 extern const ulong vmx_return;
 161
 162 #define NR_AUTOLOAD_MSRS 8
 163 #define VMCS02_POOL_SIZE 1
 164
 165 struct vmcs {
 166         u32 revision_id;
 167         u32 abort;
 168         char data[0];
 169 };
 170
 171 /*
 172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 174  * loaded on this CPU (so we can clear them if the CPU goes down).
 175  */
 176 struct loaded_vmcs {
 177         struct vmcs *vmcs;
 178         int cpu;
 179         int launched;
 180         struct list_head loaded_vmcss_on_cpu_link;
 181 };
 182
 183 struct shared_msr_entry {
 184         unsigned index;
 185         u64 data;
 186         u64 mask;
 187 };
 188
 189 /*
 190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 197  * underlying hardware which will be used to run L2.
 198  * This structure is packed to ensure that its layout is identical across
 199  * machines (necessary for live migration).
 200  * If there are changes in this struct, VMCS12_REVISION must be changed.
 201  */
 202 typedef u64 natural_width;
 203 struct __packed vmcs12 {
 204         /* According to the Intel spec, a VMCS region must start with the
 205          * following two fields. Then follow implementation-specific data.
 206          */
 207         u32 revision_id;
 208         u32 abort;
 209
 210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 211         u32 padding[7]; /* room for future expansion */
 212
 213         u64 io_bitmap_a;
 214         u64 io_bitmap_b;
 215         u64 msr_bitmap;
 216         u64 vm_exit_msr_store_addr;
 217         u64 vm_exit_msr_load_addr;
 218         u64 vm_entry_msr_load_addr;
 219         u64 tsc_offset;
 220         u64 virtual_apic_page_addr;
 221         u64 apic_access_addr;
 222         u64 posted_intr_desc_addr;
 223         u64 ept_pointer;
 224         u64 eoi_exit_bitmap0;
 225         u64 eoi_exit_bitmap1;
 226         u64 eoi_exit_bitmap2;
 227         u64 eoi_exit_bitmap3;
 228         u64 xss_exit_bitmap;
 229         u64 guest_physical_address;
 230         u64 vmcs_link_pointer;
 231         u64 guest_ia32_debugctl;
 232         u64 guest_ia32_pat;
 233         u64 guest_ia32_efer;
 234         u64 guest_ia32_perf_global_ctrl;
 235         u64 guest_pdptr0;
 236         u64 guest_pdptr1;
 237         u64 guest_pdptr2;
 238         u64 guest_pdptr3;
 239         u64 guest_bndcfgs;
 240         u64 host_ia32_pat;
 241         u64 host_ia32_efer;
 242         u64 host_ia32_perf_global_ctrl;
 243         u64 padding64[8]; /* room for future expansion */
 244         /*
 245          * To allow migration of L1 (complete with its L2 guests) between
 246          * machines of different natural widths (32 or 64 bit), we cannot have
 247          * unsigned long fields with no explict size. We use u64 (aliased
 248          * natural_width) instead. Luckily, x86 is little-endian.
 249          */
 250         natural_width cr0_guest_host_mask;
 251         natural_width cr4_guest_host_mask;
 252         natural_width cr0_read_shadow;
 253         natural_width cr4_read_shadow;
 254         natural_width cr3_target_value0;
 255         natural_width cr3_target_value1;
 256         natural_width cr3_target_value2;
 257         natural_width cr3_target_value3;
 258         natural_width exit_qualification;
 259         natural_width guest_linear_address;
 260         natural_width guest_cr0;
 261         natural_width guest_cr3;
 262         natural_width guest_cr4;
 263         natural_width guest_es_base;
 264         natural_width guest_cs_base;
 265         natural_width guest_ss_base;
 266         natural_width guest_ds_base;
 267         natural_width guest_fs_base;
 268         natural_width guest_gs_base;
 269         natural_width guest_ldtr_base;
 270         natural_width guest_tr_base;
 271         natural_width guest_gdtr_base;
 272         natural_width guest_idtr_base;
 273         natural_width guest_dr7;
 274         natural_width guest_rsp;
 275         natural_width guest_rip;
 276         natural_width guest_rflags;
 277         natural_width guest_pending_dbg_exceptions;
 278         natural_width guest_sysenter_esp;
 279         natural_width guest_sysenter_eip;
 280         natural_width host_cr0;
 281         natural_width host_cr3;
 282         natural_width host_cr4;
 283         natural_width host_fs_base;
 284         natural_width host_gs_base;
 285         natural_width host_tr_base;
 286         natural_width host_gdtr_base;
 287         natural_width host_idtr_base;
 288         natural_width host_ia32_sysenter_esp;
 289         natural_width host_ia32_sysenter_eip;
 290         natural_width host_rsp;
 291         natural_width host_rip;
 292         natural_width paddingl[8]; /* room for future expansion */
 293         u32 pin_based_vm_exec_control;
 294         u32 cpu_based_vm_exec_control;
 295         u32 exception_bitmap;
 296         u32 page_fault_error_code_mask;
 297         u32 page_fault_error_code_match;
 298         u32 cr3_target_count;
 299         u32 vm_exit_controls;
 300         u32 vm_exit_msr_store_count;
 301         u32 vm_exit_msr_load_count;
 302         u32 vm_entry_controls;
 303         u32 vm_entry_msr_load_count;
 304         u32 vm_entry_intr_info_field;
 305         u32 vm_entry_exception_error_code;
 306         u32 vm_entry_instruction_len;
 307         u32 tpr_threshold;
 308         u32 secondary_vm_exec_control;
 309         u32 vm_instruction_error;
 310         u32 vm_exit_reason;
 311         u32 vm_exit_intr_info;
 312         u32 vm_exit_intr_error_code;
 313         u32 idt_vectoring_info_field;
 314         u32 idt_vectoring_error_code;
 315         u32 vm_exit_instruction_len;
 316         u32 vmx_instruction_info;
 317         u32 guest_es_limit;
 318         u32 guest_cs_limit;
 319         u32 guest_ss_limit;
 320         u32 guest_ds_limit;
 321         u32 guest_fs_limit;
 322         u32 guest_gs_limit;
 323         u32 guest_ldtr_limit;
 324         u32 guest_tr_limit;
 325         u32 guest_gdtr_limit;
 326         u32 guest_idtr_limit;
 327         u32 guest_es_ar_bytes;
 328         u32 guest_cs_ar_bytes;
 329         u32 guest_ss_ar_bytes;
 330         u32 guest_ds_ar_bytes;
 331         u32 guest_fs_ar_bytes;
 332         u32 guest_gs_ar_bytes;
 333         u32 guest_ldtr_ar_bytes;
 334         u32 guest_tr_ar_bytes;
 335         u32 guest_interruptibility_info;
 336         u32 guest_activity_state;
 337         u32 guest_sysenter_cs;
 338         u32 host_ia32_sysenter_cs;
 339         u32 vmx_preemption_timer_value;
 340         u32 padding32[7]; /* room for future expansion */
 341         u16 virtual_processor_id;
 342         u16 posted_intr_nv;
 343         u16 guest_es_selector;
 344         u16 guest_cs_selector;
 345         u16 guest_ss_selector;
 346         u16 guest_ds_selector;
 347         u16 guest_fs_selector;
 348         u16 guest_gs_selector;
 349         u16 guest_ldtr_selector;
 350         u16 guest_tr_selector;
 351         u16 guest_intr_status;
 352         u16 host_es_selector;
 353         u16 host_cs_selector;
 354         u16 host_ss_selector;
 355         u16 host_ds_selector;
 356         u16 host_fs_selector;
 357         u16 host_gs_selector;
 358         u16 host_tr_selector;
 359 };
 360
 361 /*
 362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 365  */
 366 #define VMCS12_REVISION 0x11e57ed0
 367
 368 /*
 369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 371  * current implementation, 4K are reserved to avoid future complications.
 372  */
 373 #define VMCS12_SIZE 0x1000
 374
 375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 376 struct vmcs02_list {
 377         struct list_head list;
 378         gpa_t vmptr;
 379         struct loaded_vmcs vmcs02;
 380 };
 381
 382 /*
 383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 385  */
 386 struct nested_vmx {
 387         /* Has the level1 guest done vmxon? */
 388         bool vmxon;
 389         gpa_t vmxon_ptr;
 390
 391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 392         gpa_t current_vmptr;
 393         /* The host-usable pointer to the above */
 394         struct page *current_vmcs12_page;
 395         struct vmcs12 *current_vmcs12;
 396         struct vmcs *current_shadow_vmcs;
 397         /*
 398          * Indicates if the shadow vmcs must be updated with the
 399          * data hold by vmcs12
 400          */
 401         bool sync_shadow_vmcs;
 402
 403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 404         struct list_head vmcs02_pool;
 405         int vmcs02_num;
 406         u64 vmcs01_tsc_offset;
 407         /* L2 must run next, and mustn't decide to exit to L1. */
 408         bool nested_run_pending;
 409         /*
 410          * Guest pages referred to in vmcs02 with host-physical pointers, so
 411          * we must keep them pinned while L2 runs.
 412          */
 413         struct page *apic_access_page;
 414         struct page *virtual_apic_page;
 415         struct page *pi_desc_page;
 416         struct pi_desc *pi_desc;
 417         bool pi_pending;
 418         u16 posted_intr_nv;
 419         u64 msr_ia32_feature_control;
 420
 421         struct hrtimer preemption_timer;
 422         bool preemption_timer_expired;
 423
 424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 425         u64 vmcs01_debugctl;
 426
 427         u32 nested_vmx_procbased_ctls_low;
 428         u32 nested_vmx_procbased_ctls_high;
 429         u32 nested_vmx_true_procbased_ctls_low;
 430         u32 nested_vmx_secondary_ctls_low;
 431         u32 nested_vmx_secondary_ctls_high;
 432         u32 nested_vmx_pinbased_ctls_low;
 433         u32 nested_vmx_pinbased_ctls_high;
 434         u32 nested_vmx_exit_ctls_low;
 435         u32 nested_vmx_exit_ctls_high;
 436         u32 nested_vmx_true_exit_ctls_low;
 437         u32 nested_vmx_entry_ctls_low;
 438         u32 nested_vmx_entry_ctls_high;
 439         u32 nested_vmx_true_entry_ctls_low;
 440         u32 nested_vmx_misc_low;
 441         u32 nested_vmx_misc_high;
 442         u32 nested_vmx_ept_caps;
 443 };
 444
 445 #define POSTED_INTR_ON  0
 446 /* Posted-Interrupt Descriptor */
 447 struct pi_desc {
 448         u32 pir[8];     /* Posted interrupt requested */
 449         u32 control;    /* bit 0 of control is outstanding notification bit */
 450         u32 rsvd[7];
 451 } __aligned(64);
 452
 453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 454 {
 455         return test_and_set_bit(POSTED_INTR_ON,
 456                         (unsigned long *)&pi_desc->control);
 457 }
 458
 459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 460 {
 461         return test_and_clear_bit(POSTED_INTR_ON,
 462                         (unsigned long *)&pi_desc->control);
 463 }
 464
 465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 466 {
 467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 468 }
 469
 470 struct vcpu_vmx {
 471         struct kvm_vcpu       vcpu;
 472         unsigned long         host_rsp;
 473         u8                    fail;
 474         bool                  nmi_known_unmasked;
 475         u32                   exit_intr_info;
 476         u32                   idt_vectoring_info;
 477         ulong                 rflags;
 478         struct shared_msr_entry *guest_msrs;
 479         int                   nmsrs;
 480         int                   save_nmsrs;
 481         unsigned long         host_idt_base;
 482 #ifdef CONFIG_X86_64
 483         u64                   msr_host_kernel_gs_base;
 484         u64                   msr_guest_kernel_gs_base;
 485 #endif
 486         u32 vm_entry_controls_shadow;
 487         u32 vm_exit_controls_shadow;
 488         /*
 489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 490          * non-nested (L1) guest, it always points to vmcs01. For a nested
 491          * guest (L2), it points to a different VMCS.
 492          */
 493         struct loaded_vmcs    vmcs01;
 494         struct loaded_vmcs   *loaded_vmcs;
 495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 496         struct msr_autoload {
 497                 unsigned nr;
 498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 500         } msr_autoload;
 501         struct {
 502                 int           loaded;
 503                 u16           fs_sel, gs_sel, ldt_sel;
 504 #ifdef CONFIG_X86_64
 505                 u16           ds_sel, es_sel;
 506 #endif
 507                 int           gs_ldt_reload_needed;
 508                 int           fs_reload_needed;
 509                 u64           msr_host_bndcfgs;
 510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 511         } host_state;
 512         struct {
 513                 int vm86_active;
 514                 ulong save_rflags;
 515                 struct kvm_segment segs[8];
 516         } rmode;
 517         struct {
 518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 519                 struct kvm_save_segment {
 520                         u16 selector;
 521                         unsigned long base;
 522                         u32 limit;
 523                         u32 ar;
 524                 } seg[8];
 525         } segment_cache;
 526         int vpid;
 527         bool emulation_required;
 528
 529         /* Support for vnmi-less CPUs */
 530         int soft_vnmi_blocked;
 531         ktime_t entry_time;
 532         s64 vnmi_blocked_time;
 533         u32 exit_reason;
 534
 535         bool rdtscp_enabled;
 536
 537         /* Posted interrupt descriptor */
 538         struct pi_desc pi_desc;
 539
 540         /* Support for a guest hypervisor (nested VMX) */
 541         struct nested_vmx nested;
 542
 543         /* Dynamic PLE window. */
 544         int ple_window;
 545         bool ple_window_dirty;
 546
 547         /* Support for PML */
 548 #define PML_ENTITY_NUM          512
 549         struct page *pml_pg;
 550 };
 551
 552 enum segment_cache_field {
 553         SEG_FIELD_SEL = 0,
 554         SEG_FIELD_BASE = 1,
 555         SEG_FIELD_LIMIT = 2,
 556         SEG_FIELD_AR = 3,
 557
 558         SEG_FIELD_NR = 4
 559 };
 560
 561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 562 {
 563         return container_of(vcpu, struct vcpu_vmx, vcpu);
 564 }
 565
 566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 570
 571
 572 static unsigned long shadow_read_only_fields[] = {
 573         /*
 574          * We do NOT shadow fields that are modified when L0
 575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 576          * VMXON...) executed by L1.
 577          * For example, VM_INSTRUCTION_ERROR is read
 578          * by L1 if a vmx instruction fails (part of the error path).
 579          * Note the code assumes this logic. If for some reason
 580          * we start shadowing these fields then we need to
 581          * force a shadow sync when L0 emulates vmx instructions
 582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 583          * by nested_vmx_failValid)
 584          */
 585         VM_EXIT_REASON,
 586         VM_EXIT_INTR_INFO,
 587         VM_EXIT_INSTRUCTION_LEN,
 588         IDT_VECTORING_INFO_FIELD,
 589         IDT_VECTORING_ERROR_CODE,
 590         VM_EXIT_INTR_ERROR_CODE,
 591         EXIT_QUALIFICATION,
 592         GUEST_LINEAR_ADDRESS,
 593         GUEST_PHYSICAL_ADDRESS
 594 };
 595 static int max_shadow_read_only_fields =
 596         ARRAY_SIZE(shadow_read_only_fields);
 597
 598 static unsigned long shadow_read_write_fields[] = {
 599         TPR_THRESHOLD,
 600         GUEST_RIP,
 601         GUEST_RSP,
 602         GUEST_CR0,
 603         GUEST_CR3,
 604         GUEST_CR4,
 605         GUEST_INTERRUPTIBILITY_INFO,
 606         GUEST_RFLAGS,
 607         GUEST_CS_SELECTOR,
 608         GUEST_CS_AR_BYTES,
 609         GUEST_CS_LIMIT,
 610         GUEST_CS_BASE,
 611         GUEST_ES_BASE,
 612         GUEST_BNDCFGS,
 613         CR0_GUEST_HOST_MASK,
 614         CR0_READ_SHADOW,
 615         CR4_READ_SHADOW,
 616         TSC_OFFSET,
 617         EXCEPTION_BITMAP,
 618         CPU_BASED_VM_EXEC_CONTROL,
 619         VM_ENTRY_EXCEPTION_ERROR_CODE,
 620         VM_ENTRY_INTR_INFO_FIELD,
 621         VM_ENTRY_INSTRUCTION_LEN,
 622         VM_ENTRY_EXCEPTION_ERROR_CODE,
 623         HOST_FS_BASE,
 624         HOST_GS_BASE,
 625         HOST_FS_SELECTOR,
 626         HOST_GS_SELECTOR
 627 };
 628 static int max_shadow_read_write_fields =
 629         ARRAY_SIZE(shadow_read_write_fields);
 630
 631 static const unsigned short vmcs_field_to_offset_table[] = {
 632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 633         FIELD(POSTED_INTR_NV, posted_intr_nv),
 634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 643         FIELD(HOST_ES_SELECTOR, host_es_selector),
 644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 650         FIELD64(IO_BITMAP_A, io_bitmap_a),
 651         FIELD64(IO_BITMAP_B, io_bitmap_b),
 652         FIELD64(MSR_BITMAP, msr_bitmap),
 653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 656         FIELD64(TSC_OFFSET, tsc_offset),
 657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 660         FIELD64(EPT_POINTER, ept_pointer),
 661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 694         FIELD(TPR_THRESHOLD, tpr_threshold),
 695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 697         FIELD(VM_EXIT_REASON, vm_exit_reason),
 698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 735         FIELD(EXIT_QUALIFICATION, exit_qualification),
 736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 737         FIELD(GUEST_CR0, guest_cr0),
 738         FIELD(GUEST_CR3, guest_cr3),
 739         FIELD(GUEST_CR4, guest_cr4),
 740         FIELD(GUEST_ES_BASE, guest_es_base),
 741         FIELD(GUEST_CS_BASE, guest_cs_base),
 742         FIELD(GUEST_SS_BASE, guest_ss_base),
 743         FIELD(GUEST_DS_BASE, guest_ds_base),
 744         FIELD(GUEST_FS_BASE, guest_fs_base),
 745         FIELD(GUEST_GS_BASE, guest_gs_base),
 746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 747         FIELD(GUEST_TR_BASE, guest_tr_base),
 748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 750         FIELD(GUEST_DR7, guest_dr7),
 751         FIELD(GUEST_RSP, guest_rsp),
 752         FIELD(GUEST_RIP, guest_rip),
 753         FIELD(GUEST_RFLAGS, guest_rflags),
 754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 757         FIELD(HOST_CR0, host_cr0),
 758         FIELD(HOST_CR3, host_cr3),
 759         FIELD(HOST_CR4, host_cr4),
 760         FIELD(HOST_FS_BASE, host_fs_base),
 761         FIELD(HOST_GS_BASE, host_gs_base),
 762         FIELD(HOST_TR_BASE, host_tr_base),
 763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 764         FIELD(HOST_IDTR_BASE, host_idtr_base),
 765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 767         FIELD(HOST_RSP, host_rsp),
 768         FIELD(HOST_RIP, host_rip),
 769 };
 770
 771 static inline short vmcs_field_to_offset(unsigned long field)
 772 {
 773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 774
 775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 776             vmcs_field_to_offset_table[field] == 0)
 777                 return -ENOENT;
 778
 779         return vmcs_field_to_offset_table[field];
 780 }
 781
 782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 783 {
 784         return to_vmx(vcpu)->nested.current_vmcs12;
 785 }
 786
 787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 788 {
 789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 790         if (is_error_page(page))
 791                 return NULL;
 792
 793         return page;
 794 }
 795
 796 static void nested_release_page(struct page *page)
 797 {
 798         kvm_release_page_dirty(page);
 799 }
 800
 801 static void nested_release_page_clean(struct page *page)
 802 {
 803         kvm_release_page_clean(page);
 804 }
 805
 806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 807 static u64 construct_eptp(unsigned long root_hpa);
 808 static void kvm_cpu_vmxon(u64 addr);
 809 static void kvm_cpu_vmxoff(void);
 810 static bool vmx_mpx_supported(void);
 811 static bool vmx_xsaves_supported(void);
 812 static int vmx_vm_has_apicv(struct kvm *kvm);
 813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 815                             struct kvm_segment *var, int seg);
 816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 817                             struct kvm_segment *var, int seg);
 818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 823 static int alloc_identity_pagetable(struct kvm *kvm);
 824
 825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 827 /*
 828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 830  */
 831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 833
 834 static unsigned long *vmx_io_bitmap_a;
 835 static unsigned long *vmx_io_bitmap_b;
 836 static unsigned long *vmx_msr_bitmap_legacy;
 837 static unsigned long *vmx_msr_bitmap_longmode;
 838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 840 static unsigned long *vmx_msr_bitmap_nested;
 841 static unsigned long *vmx_vmread_bitmap;
 842 static unsigned long *vmx_vmwrite_bitmap;
 843
 844 static bool cpu_has_load_ia32_efer;
 845 static bool cpu_has_load_perf_global_ctrl;
 846
 847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 848 static DEFINE_SPINLOCK(vmx_vpid_lock);
 849
 850 static struct vmcs_config {
 851         int size;
 852         int order;
 853         u32 revision_id;
 854         u32 pin_based_exec_ctrl;
 855         u32 cpu_based_exec_ctrl;
 856         u32 cpu_based_2nd_exec_ctrl;
 857         u32 vmexit_ctrl;
 858         u32 vmentry_ctrl;
 859 } vmcs_config;
 860
 861 static struct vmx_capability {
 862         u32 ept;
 863         u32 vpid;
 864 } vmx_capability;
 865
 866 #define VMX_SEGMENT_FIELD(seg)                                  \
 867         [VCPU_SREG_##seg] = {                                   \
 868                 .selector = GUEST_##seg##_SELECTOR,             \
 869                 .base = GUEST_##seg##_BASE,                     \
 870                 .limit = GUEST_##seg##_LIMIT,                   \
 871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 872         }
 873
 874 static const struct kvm_vmx_segment_field {
 875         unsigned selector;
 876         unsigned base;
 877         unsigned limit;
 878         unsigned ar_bytes;
 879 } kvm_vmx_segment_fields[] = {
 880         VMX_SEGMENT_FIELD(CS),
 881         VMX_SEGMENT_FIELD(DS),
 882         VMX_SEGMENT_FIELD(ES),
 883         VMX_SEGMENT_FIELD(FS),
 884         VMX_SEGMENT_FIELD(GS),
 885         VMX_SEGMENT_FIELD(SS),
 886         VMX_SEGMENT_FIELD(TR),
 887         VMX_SEGMENT_FIELD(LDTR),
 888 };
 889
 890 static u64 host_efer;
 891
 892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 893
 894 /*
 895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 896  * away by decrementing the array size.
 897  */
 898 static const u32 vmx_msr_index[] = {
 899 #ifdef CONFIG_X86_64
 900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 901 #endif
 902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 903 };
 904
 905 static inline bool is_page_fault(u32 intr_info)
 906 {
 907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 908                              INTR_INFO_VALID_MASK)) ==
 909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 910 }
 911
 912 static inline bool is_no_device(u32 intr_info)
 913 {
 914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 915                              INTR_INFO_VALID_MASK)) ==
 916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 917 }
 918
 919 static inline bool is_invalid_opcode(u32 intr_info)
 920 {
 921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 922                              INTR_INFO_VALID_MASK)) ==
 923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 924 }
 925
 926 static inline bool is_external_interrupt(u32 intr_info)
 927 {
 928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 930 }
 931
 932 static inline bool is_machine_check(u32 intr_info)
 933 {
 934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 935                              INTR_INFO_VALID_MASK)) ==
 936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 937 }
 938
 939 static inline bool cpu_has_vmx_msr_bitmap(void)
 940 {
 941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 942 }
 943
 944 static inline bool cpu_has_vmx_tpr_shadow(void)
 945 {
 946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 947 }
 948
 949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 950 {
 951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 952 }
 953
 954 static inline bool cpu_has_secondary_exec_ctrls(void)
 955 {
 956         return vmcs_config.cpu_based_exec_ctrl &
 957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 958 }
 959
 960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 961 {
 962         return vmcs_config.cpu_based_2nd_exec_ctrl &
 963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 964 }
 965
 966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 967 {
 968         return vmcs_config.cpu_based_2nd_exec_ctrl &
 969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 970 }
 971
 972 static inline bool cpu_has_vmx_apic_register_virt(void)
 973 {
 974         return vmcs_config.cpu_based_2nd_exec_ctrl &
 975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 976 }
 977
 978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 979 {
 980         return vmcs_config.cpu_based_2nd_exec_ctrl &
 981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 982 }
 983
 984 static inline bool cpu_has_vmx_posted_intr(void)
 985 {
 986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 987 }
 988
 989 static inline bool cpu_has_vmx_apicv(void)
 990 {
 991         return cpu_has_vmx_apic_register_virt() &&
 992                 cpu_has_vmx_virtual_intr_delivery() &&
 993                 cpu_has_vmx_posted_intr();
 994 }
 995
 996 static inline bool cpu_has_vmx_flexpriority(void)
 997 {
 998         return cpu_has_vmx_tpr_shadow() &&
 999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469
1470
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497
1498
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716
1717         guest_efer = vmx->vcpu.arch.efer;
1718
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762
1763         if (!(selector & ~3))
1764                 return 0;
1765
1766         table_base = gdt->address;
1767
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796
1797         if (vmx->host_state.loaded)
1798                 return;
1799
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061
2062         return ret;
2063 }
2064
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170
2171         if (is_guest_mode(vcpu))
2172                 msr_bitmap = vmx_msr_bitmap_nested;
2173         else if (irqchip_in_kernel(vcpu->kvm) &&
2174                 apic_x2apic_mode(vcpu->arch.apic)) {
2175                 if (is_long_mode(vcpu))
2176                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177                 else
2178                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179         } else {
2180                 if (is_long_mode(vcpu))
2181                         msr_bitmap = vmx_msr_bitmap_longmode;
2182                 else
2183                         msr_bitmap = vmx_msr_bitmap_legacy;
2184         }
2185
2186         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187 }
2188
2189 /*
2190  * Set up the vmcs to automatically save and restore system
2191  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2192  * mode, as fiddling with msrs is very expensive.
2193  */
2194 static void setup_msrs(struct vcpu_vmx *vmx)
2195 {
2196         int save_nmsrs, index;
2197
2198         save_nmsrs = 0;
2199 #ifdef CONFIG_X86_64
2200         if (is_long_mode(&vmx->vcpu)) {
2201                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2202                 if (index >= 0)
2203                         move_msr_up(vmx, index, save_nmsrs++);
2204                 index = __find_msr_index(vmx, MSR_LSTAR);
2205                 if (index >= 0)
2206                         move_msr_up(vmx, index, save_nmsrs++);
2207                 index = __find_msr_index(vmx, MSR_CSTAR);
2208                 if (index >= 0)
2209                         move_msr_up(vmx, index, save_nmsrs++);
2210                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211                 if (index >= 0 && vmx->rdtscp_enabled)
2212                         move_msr_up(vmx, index, save_nmsrs++);
2213                 /*
2214                  * MSR_STAR is only needed on long mode guests, and only
2215                  * if efer.sce is enabled.
2216                  */
2217                 index = __find_msr_index(vmx, MSR_STAR);
2218                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2219                         move_msr_up(vmx, index, save_nmsrs++);
2220         }
2221 #endif
2222         index = __find_msr_index(vmx, MSR_EFER);
2223         if (index >= 0 && update_transition_efer(vmx, index))
2224                 move_msr_up(vmx, index, save_nmsrs++);
2225
2226         vmx->save_nmsrs = save_nmsrs;
2227
2228         if (cpu_has_vmx_msr_bitmap())
2229                 vmx_set_msr_bitmap(&vmx->vcpu);
2230 }
2231
2232 /*
2233  * reads and returns guest's timestamp counter "register"
2234  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2235  */
2236 static u64 guest_read_tsc(void)
2237 {
2238         u64 host_tsc, tsc_offset;
2239
2240         rdtscll(host_tsc);
2241         tsc_offset = vmcs_read64(TSC_OFFSET);
2242         return host_tsc + tsc_offset;
2243 }
2244
2245 /*
2246  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247  * counter, even if a nested guest (L2) is currently running.
2248  */
2249 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2250 {
2251         u64 tsc_offset;
2252
2253         tsc_offset = is_guest_mode(vcpu) ?
2254                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255                 vmcs_read64(TSC_OFFSET);
2256         return host_tsc + tsc_offset;
2257 }
2258
2259 /*
2260  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2261  * software catchup for faster rates on slower CPUs.
2262  */
2263 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2264 {
2265         if (!scale)
2266                 return;
2267
2268         if (user_tsc_khz > tsc_khz) {
2269                 vcpu->arch.tsc_catchup = 1;
2270                 vcpu->arch.tsc_always_catchup = 1;
2271         } else
2272                 WARN(1, "user requested TSC rate below hardware speed\n");
2273 }
2274
2275 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276 {
2277         return vmcs_read64(TSC_OFFSET);
2278 }
2279
2280 /*
2281  * writes 'offset' into guest's timestamp counter offset register
2282  */
2283 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2284 {
2285         if (is_guest_mode(vcpu)) {
2286                 /*
2287                  * We're here if L1 chose not to trap WRMSR to TSC. According
2288                  * to the spec, this should set L1's TSC; The offset that L1
2289                  * set for L2 remains unchanged, and still needs to be added
2290                  * to the newly set TSC to get L2's TSC.
2291                  */
2292                 struct vmcs12 *vmcs12;
2293                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294                 /* recalculate vmcs02.TSC_OFFSET: */
2295                 vmcs12 = get_vmcs12(vcpu);
2296                 vmcs_write64(TSC_OFFSET, offset +
2297                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298                          vmcs12->tsc_offset : 0));
2299         } else {
2300                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301                                            vmcs_read64(TSC_OFFSET), offset);
2302                 vmcs_write64(TSC_OFFSET, offset);
2303         }
2304 }
2305
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2307 {
2308         u64 offset = vmcs_read64(TSC_OFFSET);
2309
2310         vmcs_write64(TSC_OFFSET, offset + adjustment);
2311         if (is_guest_mode(vcpu)) {
2312                 /* Even when running L2, the adjustment needs to apply to L1 */
2313                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2314         } else
2315                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316                                            offset + adjustment);
2317 }
2318
2319 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320 {
2321         return target_tsc - native_read_tsc();
2322 }
2323
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325 {
2326         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328 }
2329
2330 /*
2331  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333  * all guests if the "nested" module option is off, and can also be disabled
2334  * for a single guest by disabling its VMX cpuid bit.
2335  */
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337 {
2338         return nested && guest_cpuid_has_vmx(vcpu);
2339 }
2340
2341 /*
2342  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343  * returned for the various VMX controls MSRs when nested VMX is enabled.
2344  * The same values should also be used to verify that vmcs12 control fields are
2345  * valid during nested entry from L1 to L2.
2346  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348  * bit in the high half is on if the corresponding bit in the control field
2349  * may be on. See also vmx_control_verify().
2350  */
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2352 {
2353         /*
2354          * Note that as a general rule, the high half of the MSRs (bits in
2355          * the control fields which may be 1) should be initialized by the
2356          * intersection of the underlying hardware's MSR (i.e., features which
2357          * can be supported) and the list of features we want to expose -
2358          * because they are known to be properly supported in our code.
2359          * Also, usually, the low half of the MSRs (bits which must be 1) can
2360          * be set to 0, meaning that L1 may turn off any of these bits. The
2361          * reason is that if one of these bits is necessary, it will appear
2362          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363          * fields of vmcs01 and vmcs02, will turn these bits off - and
2364          * nested_vmx_exit_handled() will not pass related exits to L1.
2365          * These rules have exceptions below.
2366          */
2367
2368         /* pin-based controls */
2369         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2370                 vmx->nested.nested_vmx_pinbased_ctls_low,
2371                 vmx->nested.nested_vmx_pinbased_ctls_high);
2372         vmx->nested.nested_vmx_pinbased_ctls_low |=
2373                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374         vmx->nested.nested_vmx_pinbased_ctls_high &=
2375                 PIN_BASED_EXT_INTR_MASK |
2376                 PIN_BASED_NMI_EXITING |
2377                 PIN_BASED_VIRTUAL_NMIS;
2378         vmx->nested.nested_vmx_pinbased_ctls_high |=
2379                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2380                 PIN_BASED_VMX_PREEMPTION_TIMER;
2381         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383                         PIN_BASED_POSTED_INTR;
2384
2385         /* exit controls */
2386         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2387                 vmx->nested.nested_vmx_exit_ctls_low,
2388                 vmx->nested.nested_vmx_exit_ctls_high);
2389         vmx->nested.nested_vmx_exit_ctls_low =
2390                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2391
2392         vmx->nested.nested_vmx_exit_ctls_high &=
2393 #ifdef CONFIG_X86_64
2394                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2395 #endif
2396                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2397         vmx->nested.nested_vmx_exit_ctls_high |=
2398                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2399                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2400                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
2402         if (vmx_mpx_supported())
2403                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2404
2405         /* We support free control of debug control saving. */
2406         vmx->nested.nested_vmx_true_exit_ctls_low =
2407                 vmx->nested.nested_vmx_exit_ctls_low &
2408                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
2410         /* entry controls */
2411         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2412                 vmx->nested.nested_vmx_entry_ctls_low,
2413                 vmx->nested.nested_vmx_entry_ctls_high);
2414         vmx->nested.nested_vmx_entry_ctls_low =
2415                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416         vmx->nested.nested_vmx_entry_ctls_high &=
2417 #ifdef CONFIG_X86_64
2418                 VM_ENTRY_IA32E_MODE |
2419 #endif
2420                 VM_ENTRY_LOAD_IA32_PAT;
2421         vmx->nested.nested_vmx_entry_ctls_high |=
2422                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2423         if (vmx_mpx_supported())
2424                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2425
2426         /* We support free control of debug control loading. */
2427         vmx->nested.nested_vmx_true_entry_ctls_low =
2428                 vmx->nested.nested_vmx_entry_ctls_low &
2429                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
2431         /* cpu-based controls */
2432         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2433                 vmx->nested.nested_vmx_procbased_ctls_low,
2434                 vmx->nested.nested_vmx_procbased_ctls_high);
2435         vmx->nested.nested_vmx_procbased_ctls_low =
2436                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437         vmx->nested.nested_vmx_procbased_ctls_high &=
2438                 CPU_BASED_VIRTUAL_INTR_PENDING |
2439                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2440                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442                 CPU_BASED_CR3_STORE_EXITING |
2443 #ifdef CONFIG_X86_64
2444                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445 #endif
2446                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2448                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2449                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2450                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451         /*
2452          * We can allow some features even when not supported by the
2453          * hardware. For example, L1 can specify an MSR bitmap - and we
2454          * can use it to avoid exits to L1 - even when L0 runs L2
2455          * without MSR bitmaps.
2456          */
2457         vmx->nested.nested_vmx_procbased_ctls_high |=
2458                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2459                 CPU_BASED_USE_MSR_BITMAPS;
2460
2461         /* We support free control of CR3 access interception. */
2462         vmx->nested.nested_vmx_true_procbased_ctls_low =
2463                 vmx->nested.nested_vmx_procbased_ctls_low &
2464                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
2466         /* secondary cpu-based controls */
2467         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2468                 vmx->nested.nested_vmx_secondary_ctls_low,
2469                 vmx->nested.nested_vmx_secondary_ctls_high);
2470         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471         vmx->nested.nested_vmx_secondary_ctls_high &=
2472                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2473                 SECONDARY_EXEC_RDTSCP |
2474                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2475                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2476                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2477                 SECONDARY_EXEC_WBINVD_EXITING |
2478                 SECONDARY_EXEC_XSAVES;
2479
2480         if (enable_ept) {
2481                 /* nested EPT: emulate EPT also to L1 */
2482                 vmx->nested.nested_vmx_secondary_ctls_high |=
2483                         SECONDARY_EXEC_ENABLE_EPT;
2484                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2485                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486                          VMX_EPT_INVEPT_BIT;
2487                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2488                 /*
2489                  * For nested guests, we don't do anything specific
2490                  * for single context invalidation. Hence, only advertise
2491                  * support for global context invalidation.
2492                  */
2493                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2494         } else
2495                 vmx->nested.nested_vmx_ept_caps = 0;
2496
2497         if (enable_unrestricted_guest)
2498                 vmx->nested.nested_vmx_secondary_ctls_high |=
2499                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500
2501         /* miscellaneous data */
2502         rdmsr(MSR_IA32_VMX_MISC,
2503                 vmx->nested.nested_vmx_misc_low,
2504                 vmx->nested.nested_vmx_misc_high);
2505         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506         vmx->nested.nested_vmx_misc_low |=
2507                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2508                 VMX_MISC_ACTIVITY_HLT;
2509         vmx->nested.nested_vmx_misc_high = 0;
2510 }
2511
2512 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2513 {
2514         /*
2515          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516          */
2517         return ((control & high) | low) == control;
2518 }
2519
2520 static inline u64 vmx_control_msr(u32 low, u32 high)
2521 {
2522         return low | ((u64)high << 32);
2523 }
2524
2525 /* Returns 0 on success, non-0 otherwise. */
2526 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527 {
2528         struct vcpu_vmx *vmx = to_vmx(vcpu);
2529
2530         switch (msr_index) {
2531         case MSR_IA32_VMX_BASIC:
2532                 /*
2533                  * This MSR reports some information about VMX support. We
2534                  * should return information about the VMX we emulate for the
2535                  * guest, and the VMCS structure we give it - not about the
2536                  * VMX support of the underlying hardware.
2537                  */
2538                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2539                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541                 break;
2542         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543         case MSR_IA32_VMX_PINBASED_CTLS:
2544                 *pdata = vmx_control_msr(
2545                         vmx->nested.nested_vmx_pinbased_ctls_low,
2546                         vmx->nested.nested_vmx_pinbased_ctls_high);
2547                 break;
2548         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2549                 *pdata = vmx_control_msr(
2550                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2551                         vmx->nested.nested_vmx_procbased_ctls_high);
2552                 break;
2553         case MSR_IA32_VMX_PROCBASED_CTLS:
2554                 *pdata = vmx_control_msr(
2555                         vmx->nested.nested_vmx_procbased_ctls_low,
2556                         vmx->nested.nested_vmx_procbased_ctls_high);
2557                 break;
2558         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2559                 *pdata = vmx_control_msr(
2560                         vmx->nested.nested_vmx_true_exit_ctls_low,
2561                         vmx->nested.nested_vmx_exit_ctls_high);
2562                 break;
2563         case MSR_IA32_VMX_EXIT_CTLS:
2564                 *pdata = vmx_control_msr(
2565                         vmx->nested.nested_vmx_exit_ctls_low,
2566                         vmx->nested.nested_vmx_exit_ctls_high);
2567                 break;
2568         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2569                 *pdata = vmx_control_msr(
2570                         vmx->nested.nested_vmx_true_entry_ctls_low,
2571                         vmx->nested.nested_vmx_entry_ctls_high);
2572                 break;
2573         case MSR_IA32_VMX_ENTRY_CTLS:
2574                 *pdata = vmx_control_msr(
2575                         vmx->nested.nested_vmx_entry_ctls_low,
2576                         vmx->nested.nested_vmx_entry_ctls_high);
2577                 break;
2578         case MSR_IA32_VMX_MISC:
2579                 *pdata = vmx_control_msr(
2580                         vmx->nested.nested_vmx_misc_low,
2581                         vmx->nested.nested_vmx_misc_high);
2582                 break;
2583         /*
2584          * These MSRs specify bits which the guest must keep fixed (on or off)
2585          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586          * We picked the standard core2 setting.
2587          */
2588 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2590         case MSR_IA32_VMX_CR0_FIXED0:
2591                 *pdata = VMXON_CR0_ALWAYSON;
2592                 break;
2593         case MSR_IA32_VMX_CR0_FIXED1:
2594                 *pdata = -1ULL;
2595                 break;
2596         case MSR_IA32_VMX_CR4_FIXED0:
2597                 *pdata = VMXON_CR4_ALWAYSON;
2598                 break;
2599         case MSR_IA32_VMX_CR4_FIXED1:
2600                 *pdata = -1ULL;
2601                 break;
2602         case MSR_IA32_VMX_VMCS_ENUM:
2603                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2604                 break;
2605         case MSR_IA32_VMX_PROCBASED_CTLS2:
2606                 *pdata = vmx_control_msr(
2607                         vmx->nested.nested_vmx_secondary_ctls_low,
2608                         vmx->nested.nested_vmx_secondary_ctls_high);
2609                 break;
2610         case MSR_IA32_VMX_EPT_VPID_CAP:
2611                 /* Currently, no nested vpid support */
2612                 *pdata = vmx->nested.nested_vmx_ept_caps;
2613                 break;
2614         default:
2615                 return 1;
2616         }
2617
2618         return 0;
2619 }
2620
2621 /*
2622  * Reads an msr value (of 'msr_index') into 'pdata'.
2623  * Returns 0 on success, non-0 otherwise.
2624  * Assumes vcpu_load() was already called.
2625  */
2626 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2627 {
2628         u64 data;
2629         struct shared_msr_entry *msr;
2630
2631         if (!pdata) {
2632                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2633                 return -EINVAL;
2634         }
2635
2636         switch (msr_index) {
2637 #ifdef CONFIG_X86_64
2638         case MSR_FS_BASE:
2639                 data = vmcs_readl(GUEST_FS_BASE);
2640                 break;
2641         case MSR_GS_BASE:
2642                 data = vmcs_readl(GUEST_GS_BASE);
2643                 break;
2644         case MSR_KERNEL_GS_BASE:
2645                 vmx_load_host_state(to_vmx(vcpu));
2646                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2647                 break;
2648 #endif
2649         case MSR_EFER:
2650                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2651         case MSR_IA32_TSC:
2652                 data = guest_read_tsc();
2653                 break;
2654         case MSR_IA32_SYSENTER_CS:
2655                 data = vmcs_read32(GUEST_SYSENTER_CS);
2656                 break;
2657         case MSR_IA32_SYSENTER_EIP:
2658                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2659                 break;
2660         case MSR_IA32_SYSENTER_ESP:
2661                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2662                 break;
2663         case MSR_IA32_BNDCFGS:
2664                 if (!vmx_mpx_supported())
2665                         return 1;
2666                 data = vmcs_read64(GUEST_BNDCFGS);
2667                 break;
2668         case MSR_IA32_FEATURE_CONTROL:
2669                 if (!nested_vmx_allowed(vcpu))
2670                         return 1;
2671                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2672                 break;
2673         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2674                 if (!nested_vmx_allowed(vcpu))
2675                         return 1;
2676                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2677         case MSR_IA32_XSS:
2678                 if (!vmx_xsaves_supported())
2679                         return 1;
2680                 data = vcpu->arch.ia32_xss;
2681                 break;
2682         case MSR_TSC_AUX:
2683                 if (!to_vmx(vcpu)->rdtscp_enabled)
2684                         return 1;
2685                 /* Otherwise falls through */
2686         default:
2687                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2688                 if (msr) {
2689                         data = msr->data;
2690                         break;
2691                 }
2692                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2693         }
2694
2695         *pdata = data;
2696         return 0;
2697 }
2698
2699 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2700
2701 /*
2702  * Writes msr value into into the appropriate "register".
2703  * Returns 0 on success, non-0 otherwise.
2704  * Assumes vcpu_load() was already called.
2705  */
2706 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2707 {
2708         struct vcpu_vmx *vmx = to_vmx(vcpu);
2709         struct shared_msr_entry *msr;
2710         int ret = 0;
2711         u32 msr_index = msr_info->index;
2712         u64 data = msr_info->data;
2713
2714         switch (msr_index) {
2715         case MSR_EFER:
2716                 ret = kvm_set_msr_common(vcpu, msr_info);
2717                 break;
2718 #ifdef CONFIG_X86_64
2719         case MSR_FS_BASE:
2720                 vmx_segment_cache_clear(vmx);
2721                 vmcs_writel(GUEST_FS_BASE, data);
2722                 break;
2723         case MSR_GS_BASE:
2724                 vmx_segment_cache_clear(vmx);
2725                 vmcs_writel(GUEST_GS_BASE, data);
2726                 break;
2727         case MSR_KERNEL_GS_BASE:
2728                 vmx_load_host_state(vmx);
2729                 vmx->msr_guest_kernel_gs_base = data;
2730                 break;
2731 #endif
2732         case MSR_IA32_SYSENTER_CS:
2733                 vmcs_write32(GUEST_SYSENTER_CS, data);
2734                 break;
2735         case MSR_IA32_SYSENTER_EIP:
2736                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2737                 break;
2738         case MSR_IA32_SYSENTER_ESP:
2739                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2740                 break;
2741         case MSR_IA32_BNDCFGS:
2742                 if (!vmx_mpx_supported())
2743                         return 1;
2744                 vmcs_write64(GUEST_BNDCFGS, data);
2745                 break;
2746         case MSR_IA32_TSC:
2747                 kvm_write_tsc(vcpu, msr_info);
2748                 break;
2749         case MSR_IA32_CR_PAT:
2750                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2751                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2752                                 return 1;
2753                         vmcs_write64(GUEST_IA32_PAT, data);
2754                         vcpu->arch.pat = data;
2755                         break;
2756                 }
2757                 ret = kvm_set_msr_common(vcpu, msr_info);
2758                 break;
2759         case MSR_IA32_TSC_ADJUST:
2760                 ret = kvm_set_msr_common(vcpu, msr_info);
2761                 break;
2762         case MSR_IA32_FEATURE_CONTROL:
2763                 if (!nested_vmx_allowed(vcpu) ||
2764                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2765                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2766                         return 1;
2767                 vmx->nested.msr_ia32_feature_control = data;
2768                 if (msr_info->host_initiated && data == 0)
2769                         vmx_leave_nested(vcpu);
2770                 break;
2771         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2772                 return 1; /* they are read-only */
2773         case MSR_IA32_XSS:
2774                 if (!vmx_xsaves_supported())
2775                         return 1;
2776                 /*
2777                  * The only supported bit as of Skylake is bit 8, but
2778                  * it is not supported on KVM.
2779                  */
2780                 if (data != 0)
2781                         return 1;
2782                 vcpu->arch.ia32_xss = data;
2783                 if (vcpu->arch.ia32_xss != host_xss)
2784                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2785                                 vcpu->arch.ia32_xss, host_xss);
2786                 else
2787                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2788                 break;
2789         case MSR_TSC_AUX:
2790                 if (!vmx->rdtscp_enabled)
2791                         return 1;
2792                 /* Check reserved bit, higher 32 bits should be zero */
2793                 if ((data >> 32) != 0)
2794                         return 1;
2795                 /* Otherwise falls through */
2796         default:
2797                 msr = find_msr_entry(vmx, msr_index);
2798                 if (msr) {
2799                         u64 old_msr_data = msr->data;
2800                         msr->data = data;
2801                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2802                                 preempt_disable();
2803                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2804                                                          msr->mask);
2805                                 preempt_enable();
2806                                 if (ret)
2807                                         msr->data = old_msr_data;
2808                         }
2809                         break;
2810                 }
2811                 ret = kvm_set_msr_common(vcpu, msr_info);
2812         }
2813
2814         return ret;
2815 }
2816
2817 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2818 {
2819         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2820         switch (reg) {
2821         case VCPU_REGS_RSP:
2822                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2823                 break;
2824         case VCPU_REGS_RIP:
2825                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2826                 break;
2827         case VCPU_EXREG_PDPTR:
2828                 if (enable_ept)
2829                         ept_save_pdptrs(vcpu);
2830                 break;
2831         default:
2832                 break;
2833         }
2834 }
2835
2836 static __init int cpu_has_kvm_support(void)
2837 {
2838         return cpu_has_vmx();
2839 }
2840
2841 static __init int vmx_disabled_by_bios(void)
2842 {
2843         u64 msr;
2844
2845         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2846         if (msr & FEATURE_CONTROL_LOCKED) {
2847                 /* launched w/ TXT and VMX disabled */
2848                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2849                         && tboot_enabled())
2850                         return 1;
2851                 /* launched w/o TXT and VMX only enabled w/ TXT */
2852                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2853                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2854                         && !tboot_enabled()) {
2855                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2856                                 "activate TXT before enabling KVM\n");
2857                         return 1;
2858                 }
2859                 /* launched w/o TXT and VMX disabled */
2860                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2861                         && !tboot_enabled())
2862                         return 1;
2863         }
2864
2865         return 0;
2866 }
2867
2868 static void kvm_cpu_vmxon(u64 addr)
2869 {
2870         asm volatile (ASM_VMX_VMXON_RAX
2871                         : : "a"(&addr), "m"(addr)
2872                         : "memory", "cc");
2873 }
2874
2875 static int hardware_enable(void)
2876 {
2877         int cpu = raw_smp_processor_id();
2878         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2879         u64 old, test_bits;
2880
2881         if (cr4_read_shadow() & X86_CR4_VMXE)
2882                 return -EBUSY;
2883
2884         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2885
2886         /*
2887          * Now we can enable the vmclear operation in kdump
2888          * since the loaded_vmcss_on_cpu list on this cpu
2889          * has been initialized.
2890          *
2891          * Though the cpu is not in VMX operation now, there
2892          * is no problem to enable the vmclear operation
2893          * for the loaded_vmcss_on_cpu list is empty!
2894          */
2895         crash_enable_local_vmclear(cpu);
2896
2897         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2898
2899         test_bits = FEATURE_CONTROL_LOCKED;
2900         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2901         if (tboot_enabled())
2902                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2903
2904         if ((old & test_bits) != test_bits) {
2905                 /* enable and lock */
2906                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2907         }
2908         cr4_set_bits(X86_CR4_VMXE);
2909
2910         if (vmm_exclusive) {
2911                 kvm_cpu_vmxon(phys_addr);
2912                 ept_sync_global();
2913         }
2914
2915         native_store_gdt(this_cpu_ptr(&host_gdt));
2916
2917         return 0;
2918 }
2919
2920 static void vmclear_local_loaded_vmcss(void)
2921 {
2922         int cpu = raw_smp_processor_id();
2923         struct loaded_vmcs *v, *n;
2924
2925         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2926                                  loaded_vmcss_on_cpu_link)
2927                 __loaded_vmcs_clear(v);
2928 }
2929
2930
2931 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2932  * tricks.
2933  */
2934 static void kvm_cpu_vmxoff(void)
2935 {
2936         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2937 }
2938
2939 static void hardware_disable(void)
2940 {
2941         if (vmm_exclusive) {
2942                 vmclear_local_loaded_vmcss();
2943                 kvm_cpu_vmxoff();
2944         }
2945         cr4_clear_bits(X86_CR4_VMXE);
2946 }
2947
2948 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2949                                       u32 msr, u32 *result)
2950 {
2951         u32 vmx_msr_low, vmx_msr_high;
2952         u32 ctl = ctl_min | ctl_opt;
2953
2954         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2955
2956         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2957         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2958
2959         /* Ensure minimum (required) set of control bits are supported. */
2960         if (ctl_min & ~ctl)
2961                 return -EIO;
2962
2963         *result = ctl;
2964         return 0;
2965 }
2966
2967 static __init bool allow_1_setting(u32 msr, u32 ctl)
2968 {
2969         u32 vmx_msr_low, vmx_msr_high;
2970
2971         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2972         return vmx_msr_high & ctl;
2973 }
2974
2975 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2976 {
2977         u32 vmx_msr_low, vmx_msr_high;
2978         u32 min, opt, min2, opt2;
2979         u32 _pin_based_exec_control = 0;
2980         u32 _cpu_based_exec_control = 0;
2981         u32 _cpu_based_2nd_exec_control = 0;
2982         u32 _vmexit_control = 0;
2983         u32 _vmentry_control = 0;
2984
2985         min = CPU_BASED_HLT_EXITING |
2986 #ifdef CONFIG_X86_64
2987               CPU_BASED_CR8_LOAD_EXITING |
2988               CPU_BASED_CR8_STORE_EXITING |
2989 #endif
2990               CPU_BASED_CR3_LOAD_EXITING |
2991               CPU_BASED_CR3_STORE_EXITING |
2992               CPU_BASED_USE_IO_BITMAPS |
2993               CPU_BASED_MOV_DR_EXITING |
2994               CPU_BASED_USE_TSC_OFFSETING |
2995               CPU_BASED_MWAIT_EXITING |
2996               CPU_BASED_MONITOR_EXITING |
2997               CPU_BASED_INVLPG_EXITING |
2998               CPU_BASED_RDPMC_EXITING;
2999
3000         opt = CPU_BASED_TPR_SHADOW |
3001               CPU_BASED_USE_MSR_BITMAPS |
3002               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3003         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3004                                 &_cpu_based_exec_control) < 0)
3005                 return -EIO;
3006 #ifdef CONFIG_X86_64
3007         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3008                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3009                                            ~CPU_BASED_CR8_STORE_EXITING;
3010 #endif
3011         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3012                 min2 = 0;
3013                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3014                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3015                         SECONDARY_EXEC_WBINVD_EXITING |
3016                         SECONDARY_EXEC_ENABLE_VPID |
3017                         SECONDARY_EXEC_ENABLE_EPT |
3018                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3019                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3020                         SECONDARY_EXEC_RDTSCP |
3021                         SECONDARY_EXEC_ENABLE_INVPCID |
3022                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3023                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3024                         SECONDARY_EXEC_SHADOW_VMCS |
3025                         SECONDARY_EXEC_XSAVES |
3026                         SECONDARY_EXEC_ENABLE_PML;
3027                 if (adjust_vmx_controls(min2, opt2,
3028                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3029                                         &_cpu_based_2nd_exec_control) < 0)
3030                         return -EIO;
3031         }
3032 #ifndef CONFIG_X86_64
3033         if (!(_cpu_based_2nd_exec_control &
3034                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3035                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3036 #endif
3037
3038         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3039                 _cpu_based_2nd_exec_control &= ~(
3040                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3041                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3042                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3043
3044         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3045                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3046                    enabled */
3047                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3048                                              CPU_BASED_CR3_STORE_EXITING |
3049                                              CPU_BASED_INVLPG_EXITING);
3050                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3051                       vmx_capability.ept, vmx_capability.vpid);
3052         }
3053
3054         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3055 #ifdef CONFIG_X86_64
3056         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3057 #endif
3058         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3059                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3060         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3061                                 &_vmexit_control) < 0)
3062                 return -EIO;
3063
3064         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3065         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3066         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3067                                 &_pin_based_exec_control) < 0)
3068                 return -EIO;
3069
3070         if (!(_cpu_based_2nd_exec_control &
3071                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3072                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3073                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3074
3075         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3076         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3077         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3078                                 &_vmentry_control) < 0)
3079                 return -EIO;
3080
3081         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3082
3083         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3085                 return -EIO;
3086
3087 #ifdef CONFIG_X86_64
3088         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089         if (vmx_msr_high & (1u<<16))
3090                 return -EIO;
3091 #endif
3092
3093         /* Require Write-Back (WB) memory type for VMCS accesses. */
3094         if (((vmx_msr_high >> 18) & 15) != 6)
3095                 return -EIO;
3096
3097         vmcs_conf->size = vmx_msr_high & 0x1fff;
3098         vmcs_conf->order = get_order(vmcs_config.size);
3099         vmcs_conf->revision_id = vmx_msr_low;
3100
3101         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3102         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3103         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3104         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3105         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3106
3107         cpu_has_load_ia32_efer =
3108                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109                                 VM_ENTRY_LOAD_IA32_EFER)
3110                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111                                    VM_EXIT_LOAD_IA32_EFER);
3112
3113         cpu_has_load_perf_global_ctrl =
3114                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3115                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3116                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3117                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3118
3119         /*
3120          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121          * but due to arrata below it can't be used. Workaround is to use
3122          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3123          *
3124          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3125          *
3126          * AAK155             (model 26)
3127          * AAP115             (model 30)
3128          * AAT100             (model 37)
3129          * BC86,AAY89,BD102   (model 44)
3130          * BA97               (model 46)
3131          *
3132          */
3133         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3134                 switch (boot_cpu_data.x86_model) {
3135                 case 26:
3136                 case 30:
3137                 case 37:
3138                 case 44:
3139                 case 46:
3140                         cpu_has_load_perf_global_ctrl = false;
3141                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142                                         "does not work properly. Using workaround\n");
3143                         break;
3144                 default:
3145                         break;
3146                 }
3147         }
3148
3149         if (cpu_has_xsaves)
3150                 rdmsrl(MSR_IA32_XSS, host_xss);
3151
3152         return 0;
3153 }
3154
3155 static struct vmcs *alloc_vmcs_cpu(int cpu)
3156 {
3157         int node = cpu_to_node(cpu);
3158         struct page *pages;
3159         struct vmcs *vmcs;
3160
3161         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3162         if (!pages)
3163                 return NULL;
3164         vmcs = page_address(pages);
3165         memset(vmcs, 0, vmcs_config.size);
3166         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3167         return vmcs;
3168 }
3169
3170 static struct vmcs *alloc_vmcs(void)
3171 {
3172         return alloc_vmcs_cpu(raw_smp_processor_id());
3173 }
3174
3175 static void free_vmcs(struct vmcs *vmcs)
3176 {
3177         free_pages((unsigned long)vmcs, vmcs_config.order);
3178 }
3179
3180 /*
3181  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3182  */
3183 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3184 {
3185         if (!loaded_vmcs->vmcs)
3186                 return;
3187         loaded_vmcs_clear(loaded_vmcs);
3188         free_vmcs(loaded_vmcs->vmcs);
3189         loaded_vmcs->vmcs = NULL;
3190 }
3191
3192 static void free_kvm_area(void)
3193 {
3194         int cpu;
3195
3196         for_each_possible_cpu(cpu) {
3197                 free_vmcs(per_cpu(vmxarea, cpu));
3198                 per_cpu(vmxarea, cpu) = NULL;
3199         }
3200 }
3201
3202 static void init_vmcs_shadow_fields(void)
3203 {
3204         int i, j;
3205
3206         /* No checks for read only fields yet */
3207
3208         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3209                 switch (shadow_read_write_fields[i]) {
3210                 case GUEST_BNDCFGS:
3211                         if (!vmx_mpx_supported())
3212                                 continue;
3213                         break;
3214                 default:
3215                         break;
3216                 }
3217
3218                 if (j < i)
3219                         shadow_read_write_fields[j] =
3220                                 shadow_read_write_fields[i];
3221                 j++;
3222         }
3223         max_shadow_read_write_fields = j;
3224
3225         /* shadowed fields guest access without vmexit */
3226         for (i = 0; i < max_shadow_read_write_fields; i++) {
3227                 clear_bit(shadow_read_write_fields[i],
3228                           vmx_vmwrite_bitmap);
3229                 clear_bit(shadow_read_write_fields[i],
3230                           vmx_vmread_bitmap);
3231         }
3232         for (i = 0; i < max_shadow_read_only_fields; i++)
3233                 clear_bit(shadow_read_only_fields[i],
3234                           vmx_vmread_bitmap);
3235 }
3236
3237 static __init int alloc_kvm_area(void)
3238 {
3239         int cpu;
3240
3241         for_each_possible_cpu(cpu) {
3242                 struct vmcs *vmcs;
3243
3244                 vmcs = alloc_vmcs_cpu(cpu);
3245                 if (!vmcs) {
3246                         free_kvm_area();
3247                         return -ENOMEM;
3248                 }
3249
3250                 per_cpu(vmxarea, cpu) = vmcs;
3251         }
3252         return 0;
3253 }
3254
3255 static bool emulation_required(struct kvm_vcpu *vcpu)
3256 {
3257         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3258 }
3259
3260 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3261                 struct kvm_segment *save)
3262 {
3263         if (!emulate_invalid_guest_state) {
3264                 /*
3265                  * CS and SS RPL should be equal during guest entry according
3266                  * to VMX spec, but in reality it is not always so. Since vcpu
3267                  * is in the middle of the transition from real mode to
3268                  * protected mode it is safe to assume that RPL 0 is a good
3269                  * default value.
3270                  */
3271                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3272                         save->selector &= ~SEGMENT_RPL_MASK;
3273                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3274                 save->s = 1;
3275         }
3276         vmx_set_segment(vcpu, save, seg);
3277 }
3278
3279 static void enter_pmode(struct kvm_vcpu *vcpu)
3280 {
3281         unsigned long flags;
3282         struct vcpu_vmx *vmx = to_vmx(vcpu);
3283
3284         /*
3285          * Update real mode segment cache. It may be not up-to-date if sement
3286          * register was written while vcpu was in a guest mode.
3287          */
3288         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3289         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3290         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3291         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3292         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3293         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3294
3295         vmx->rmode.vm86_active = 0;
3296
3297         vmx_segment_cache_clear(vmx);
3298
3299         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3300
3301         flags = vmcs_readl(GUEST_RFLAGS);
3302         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3303         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3304         vmcs_writel(GUEST_RFLAGS, flags);
3305
3306         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3307                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3308
3309         update_exception_bitmap(vcpu);
3310
3311         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3312         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3313         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3314         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3315         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3316         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3317 }
3318
3319 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3320 {
3321         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3322         struct kvm_segment var = *save;
3323
3324         var.dpl = 0x3;
3325         if (seg == VCPU_SREG_CS)
3326                 var.type = 0x3;
3327
3328         if (!emulate_invalid_guest_state) {
3329                 var.selector = var.base >> 4;
3330                 var.base = var.base & 0xffff0;
3331                 var.limit = 0xffff;
3332                 var.g = 0;
3333                 var.db = 0;
3334                 var.present = 1;
3335                 var.s = 1;
3336                 var.l = 0;
3337                 var.unusable = 0;
3338                 var.type = 0x3;
3339                 var.avl = 0;
3340                 if (save->base & 0xf)
3341                         printk_once(KERN_WARNING "kvm: segment base is not "
3342                                         "paragraph aligned when entering "
3343                                         "protected mode (seg=%d)", seg);
3344         }
3345
3346         vmcs_write16(sf->selector, var.selector);
3347         vmcs_write32(sf->base, var.base);
3348         vmcs_write32(sf->limit, var.limit);
3349         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3350 }
3351
3352 static void enter_rmode(struct kvm_vcpu *vcpu)
3353 {
3354         unsigned long flags;
3355         struct vcpu_vmx *vmx = to_vmx(vcpu);
3356
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3358         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3359         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3360         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3361         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3363         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3364
3365         vmx->rmode.vm86_active = 1;
3366
3367         /*
3368          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3369          * vcpu. Warn the user that an update is overdue.
3370          */
3371         if (!vcpu->kvm->arch.tss_addr)
3372                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3373                              "called before entering vcpu\n");
3374
3375         vmx_segment_cache_clear(vmx);
3376
3377         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3378         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3379         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3380
3381         flags = vmcs_readl(GUEST_RFLAGS);
3382         vmx->rmode.save_rflags = flags;
3383
3384         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3385
3386         vmcs_writel(GUEST_RFLAGS, flags);
3387         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3388         update_exception_bitmap(vcpu);
3389
3390         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3391         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3392         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3393         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3394         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3395         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3396
3397         kvm_mmu_reset_context(vcpu);
3398 }
3399
3400 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3401 {
3402         struct vcpu_vmx *vmx = to_vmx(vcpu);
3403         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3404
3405         if (!msr)
3406                 return;
3407
3408         /*
3409          * Force kernel_gs_base reloading before EFER changes, as control
3410          * of this msr depends on is_long_mode().
3411          */
3412         vmx_load_host_state(to_vmx(vcpu));
3413         vcpu->arch.efer = efer;
3414         if (efer & EFER_LMA) {
3415                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3416                 msr->data = efer;
3417         } else {
3418                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3419
3420                 msr->data = efer & ~EFER_LME;
3421         }
3422         setup_msrs(vmx);
3423 }
3424
3425 #ifdef CONFIG_X86_64
3426
3427 static void enter_lmode(struct kvm_vcpu *vcpu)
3428 {
3429         u32 guest_tr_ar;
3430
3431         vmx_segment_cache_clear(to_vmx(vcpu));
3432
3433         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3434         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3435                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3436                                      __func__);
3437                 vmcs_write32(GUEST_TR_AR_BYTES,
3438                              (guest_tr_ar & ~AR_TYPE_MASK)
3439                              | AR_TYPE_BUSY_64_TSS);
3440         }
3441         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3442 }
3443
3444 static void exit_lmode(struct kvm_vcpu *vcpu)
3445 {
3446         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3447         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3448 }
3449
3450 #endif
3451
3452 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3453 {
3454         vpid_sync_context(to_vmx(vcpu));
3455         if (enable_ept) {
3456                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3457                         return;
3458                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3459         }
3460 }
3461
3462 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3463 {
3464         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3465
3466         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3467         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3468 }
3469
3470 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3471 {
3472         if (enable_ept && is_paging(vcpu))
3473                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3474         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3475 }
3476
3477 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3478 {
3479         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3480
3481         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3482         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3483 }
3484
3485 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3486 {
3487         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3488
3489         if (!test_bit(VCPU_EXREG_PDPTR,
3490                       (unsigned long *)&vcpu->arch.regs_dirty))
3491                 return;
3492
3493         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3494                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3495                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3496                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3497                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3498         }
3499 }
3500
3501 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3502 {
3503         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3504
3505         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3506                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3507                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3508                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3509                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3510         }
3511
3512         __set_bit(VCPU_EXREG_PDPTR,
3513                   (unsigned long *)&vcpu->arch.regs_avail);
3514         __set_bit(VCPU_EXREG_PDPTR,
3515                   (unsigned long *)&vcpu->arch.regs_dirty);
3516 }
3517
3518 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3519
3520 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3521                                         unsigned long cr0,
3522                                         struct kvm_vcpu *vcpu)
3523 {
3524         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3525                 vmx_decache_cr3(vcpu);
3526         if (!(cr0 & X86_CR0_PG)) {
3527                 /* From paging/starting to nonpaging */
3528                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3529                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3530                              (CPU_BASED_CR3_LOAD_EXITING |
3531                               CPU_BASED_CR3_STORE_EXITING));
3532                 vcpu->arch.cr0 = cr0;
3533                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3534         } else if (!is_paging(vcpu)) {
3535                 /* From nonpaging to paging */
3536                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3537                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3538                              ~(CPU_BASED_CR3_LOAD_EXITING |
3539                                CPU_BASED_CR3_STORE_EXITING));
3540                 vcpu->arch.cr0 = cr0;
3541                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3542         }
3543
3544         if (!(cr0 & X86_CR0_WP))
3545                 *hw_cr0 &= ~X86_CR0_WP;
3546 }
3547
3548 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3549 {
3550         struct vcpu_vmx *vmx = to_vmx(vcpu);
3551         unsigned long hw_cr0;
3552
3553         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3554         if (enable_unrestricted_guest)
3555                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3556         else {
3557                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3558
3559                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3560                         enter_pmode(vcpu);
3561
3562                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3563                         enter_rmode(vcpu);
3564         }
3565
3566 #ifdef CONFIG_X86_64
3567         if (vcpu->arch.efer & EFER_LME) {
3568                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3569                         enter_lmode(vcpu);
3570                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3571                         exit_lmode(vcpu);
3572         }
3573 #endif
3574
3575         if (enable_ept)
3576                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3577
3578         if (!vcpu->fpu_active)
3579                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3580
3581         vmcs_writel(CR0_READ_SHADOW, cr0);
3582         vmcs_writel(GUEST_CR0, hw_cr0);
3583         vcpu->arch.cr0 = cr0;
3584
3585         /* depends on vcpu->arch.cr0 to be set to a new value */
3586         vmx->emulation_required = emulation_required(vcpu);
3587 }
3588
3589 static u64 construct_eptp(unsigned long root_hpa)
3590 {
3591         u64 eptp;
3592
3593         /* TODO write the value reading from MSR */
3594         eptp = VMX_EPT_DEFAULT_MT |
3595                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3596         if (enable_ept_ad_bits)
3597                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3598         eptp |= (root_hpa & PAGE_MASK);
3599
3600         return eptp;
3601 }
3602
3603 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3604 {
3605         unsigned long guest_cr3;
3606         u64 eptp;
3607
3608         guest_cr3 = cr3;
3609         if (enable_ept) {
3610                 eptp = construct_eptp(cr3);
3611                 vmcs_write64(EPT_POINTER, eptp);
3612                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3613                         guest_cr3 = kvm_read_cr3(vcpu);
3614                 else
3615                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3616                 ept_load_pdptrs(vcpu);
3617         }
3618
3619         vmx_flush_tlb(vcpu);
3620         vmcs_writel(GUEST_CR3, guest_cr3);
3621 }
3622
3623 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3624 {
3625         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3626                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3627
3628         if (cr4 & X86_CR4_VMXE) {
3629                 /*
3630                  * To use VMXON (and later other VMX instructions), a guest
3631                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3632                  * So basically the check on whether to allow nested VMX
3633                  * is here.
3634                  */
3635                 if (!nested_vmx_allowed(vcpu))
3636                         return 1;
3637         }
3638         if (to_vmx(vcpu)->nested.vmxon &&
3639             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3640                 return 1;
3641
3642         vcpu->arch.cr4 = cr4;
3643         if (enable_ept) {
3644                 if (!is_paging(vcpu)) {
3645                         hw_cr4 &= ~X86_CR4_PAE;
3646                         hw_cr4 |= X86_CR4_PSE;
3647                         /*
3648                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3649                          * in hardware. However KVM always uses paging mode to
3650                          * emulate guest non-paging mode with TDP.
3651                          * To emulate this behavior, SMEP/SMAP needs to be
3652                          * manually disabled when guest switches to non-paging
3653                          * mode.
3654                          */
3655                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3656                 } else if (!(cr4 & X86_CR4_PAE)) {
3657                         hw_cr4 &= ~X86_CR4_PAE;
3658                 }
3659         }
3660
3661         vmcs_writel(CR4_READ_SHADOW, cr4);
3662         vmcs_writel(GUEST_CR4, hw_cr4);
3663         return 0;
3664 }
3665
3666 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3667                             struct kvm_segment *var, int seg)
3668 {
3669         struct vcpu_vmx *vmx = to_vmx(vcpu);
3670         u32 ar;
3671
3672         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3673                 *var = vmx->rmode.segs[seg];
3674                 if (seg == VCPU_SREG_TR
3675                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3676                         return;
3677                 var->base = vmx_read_guest_seg_base(vmx, seg);
3678                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3679                 return;
3680         }
3681         var->base = vmx_read_guest_seg_base(vmx, seg);
3682         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3683         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3684         ar = vmx_read_guest_seg_ar(vmx, seg);
3685         var->unusable = (ar >> 16) & 1;
3686         var->type = ar & 15;
3687         var->s = (ar >> 4) & 1;
3688         var->dpl = (ar >> 5) & 3;
3689         /*
3690          * Some userspaces do not preserve unusable property. Since usable
3691          * segment has to be present according to VMX spec we can use present
3692          * property to amend userspace bug by making unusable segment always
3693          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3694          * segment as unusable.
3695          */
3696         var->present = !var->unusable;
3697         var->avl = (ar >> 12) & 1;
3698         var->l = (ar >> 13) & 1;
3699         var->db = (ar >> 14) & 1;
3700         var->g = (ar >> 15) & 1;
3701 }
3702
3703 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3704 {
3705         struct kvm_segment s;
3706
3707         if (to_vmx(vcpu)->rmode.vm86_active) {
3708                 vmx_get_segment(vcpu, &s, seg);
3709                 return s.base;
3710         }
3711         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3712 }
3713
3714 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3715 {
3716         struct vcpu_vmx *vmx = to_vmx(vcpu);
3717
3718         if (unlikely(vmx->rmode.vm86_active))
3719                 return 0;
3720         else {
3721                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3722                 return AR_DPL(ar);
3723         }
3724 }
3725
3726 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3727 {
3728         u32 ar;
3729
3730         if (var->unusable || !var->present)
3731                 ar = 1 << 16;
3732         else {
3733                 ar = var->type & 15;
3734                 ar |= (var->s & 1) << 4;
3735                 ar |= (var->dpl & 3) << 5;
3736                 ar |= (var->present & 1) << 7;
3737                 ar |= (var->avl & 1) << 12;
3738                 ar |= (var->l & 1) << 13;
3739                 ar |= (var->db & 1) << 14;
3740                 ar |= (var->g & 1) << 15;
3741         }
3742
3743         return ar;
3744 }
3745
3746 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3747                             struct kvm_segment *var, int seg)
3748 {
3749         struct vcpu_vmx *vmx = to_vmx(vcpu);
3750         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3751
3752         vmx_segment_cache_clear(vmx);
3753
3754         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3755                 vmx->rmode.segs[seg] = *var;
3756                 if (seg == VCPU_SREG_TR)
3757                         vmcs_write16(sf->selector, var->selector);
3758                 else if (var->s)
3759                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3760                 goto out;
3761         }
3762
3763         vmcs_writel(sf->base, var->base);
3764         vmcs_write32(sf->limit, var->limit);
3765         vmcs_write16(sf->selector, var->selector);
3766
3767         /*
3768          *   Fix the "Accessed" bit in AR field of segment registers for older
3769          * qemu binaries.
3770          *   IA32 arch specifies that at the time of processor reset the
3771          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3772          * is setting it to 0 in the userland code. This causes invalid guest
3773          * state vmexit when "unrestricted guest" mode is turned on.
3774          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3775          * tree. Newer qemu binaries with that qemu fix would not need this
3776          * kvm hack.
3777          */
3778         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3779                 var->type |= 0x1; /* Accessed */
3780
3781         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3782
3783 out:
3784         vmx->emulation_required = emulation_required(vcpu);
3785 }
3786
3787 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3788 {
3789         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3790
3791         *db = (ar >> 14) & 1;
3792         *l = (ar >> 13) & 1;
3793 }
3794
3795 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3796 {
3797         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3798         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3799 }
3800
3801 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3802 {
3803         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3804         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3805 }
3806
3807 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3808 {
3809         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3810         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3811 }
3812
3813 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3814 {
3815         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3816         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3817 }
3818
3819 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3820 {
3821         struct kvm_segment var;
3822         u32 ar;
3823
3824         vmx_get_segment(vcpu, &var, seg);
3825         var.dpl = 0x3;
3826         if (seg == VCPU_SREG_CS)
3827                 var.type = 0x3;
3828         ar = vmx_segment_access_rights(&var);
3829
3830         if (var.base != (var.selector << 4))
3831                 return false;
3832         if (var.limit != 0xffff)
3833                 return false;
3834         if (ar != 0xf3)
3835                 return false;
3836
3837         return true;
3838 }
3839
3840 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3841 {
3842         struct kvm_segment cs;
3843         unsigned int cs_rpl;
3844
3845         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3846         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3847
3848         if (cs.unusable)
3849                 return false;
3850         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3851                 return false;
3852         if (!cs.s)
3853                 return false;
3854         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3855                 if (cs.dpl > cs_rpl)
3856                         return false;
3857         } else {
3858                 if (cs.dpl != cs_rpl)
3859                         return false;
3860         }
3861         if (!cs.present)
3862                 return false;
3863
3864         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3865         return true;
3866 }
3867
3868 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3869 {
3870         struct kvm_segment ss;
3871         unsigned int ss_rpl;
3872
3873         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3874         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3875
3876         if (ss.unusable)
3877                 return true;
3878         if (ss.type != 3 && ss.type != 7)
3879                 return false;
3880         if (!ss.s)
3881                 return false;
3882         if (ss.dpl != ss_rpl) /* DPL != RPL */
3883                 return false;
3884         if (!ss.present)
3885                 return false;
3886
3887         return true;
3888 }
3889
3890 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3891 {
3892         struct kvm_segment var;
3893         unsigned int rpl;
3894
3895         vmx_get_segment(vcpu, &var, seg);
3896         rpl = var.selector & SEGMENT_RPL_MASK;
3897
3898         if (var.unusable)
3899                 return true;
3900         if (!var.s)
3901                 return false;
3902         if (!var.present)
3903                 return false;
3904         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3905                 if (var.dpl < rpl) /* DPL < RPL */
3906                         return false;
3907         }
3908
3909         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3910          * rights flags
3911          */
3912         return true;
3913 }
3914
3915 static bool tr_valid(struct kvm_vcpu *vcpu)
3916 {
3917         struct kvm_segment tr;
3918
3919         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3920
3921         if (tr.unusable)
3922                 return false;
3923         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3924                 return false;
3925         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3926                 return false;
3927         if (!tr.present)
3928                 return false;
3929
3930         return true;
3931 }
3932
3933 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3934 {
3935         struct kvm_segment ldtr;
3936
3937         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3938
3939         if (ldtr.unusable)
3940                 return true;
3941         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3942                 return false;
3943         if (ldtr.type != 2)
3944                 return false;
3945         if (!ldtr.present)
3946                 return false;
3947
3948         return true;
3949 }
3950
3951 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3952 {
3953         struct kvm_segment cs, ss;
3954
3955         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3956         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3957
3958         return ((cs.selector & SEGMENT_RPL_MASK) ==
3959                  (ss.selector & SEGMENT_RPL_MASK));
3960 }
3961
3962 /*
3963  * Check if guest state is valid. Returns true if valid, false if
3964  * not.
3965  * We assume that registers are always usable
3966  */
3967 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3968 {
3969         if (enable_unrestricted_guest)
3970                 return true;
3971
3972         /* real mode guest state checks */
3973         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3974                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3975                         return false;
3976                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3977                         return false;
3978                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3979                         return false;
3980                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3981                         return false;
3982                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3983                         return false;
3984                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3985                         return false;
3986         } else {
3987         /* protected mode guest state checks */
3988                 if (!cs_ss_rpl_check(vcpu))
3989                         return false;
3990                 if (!code_segment_valid(vcpu))
3991                         return false;
3992                 if (!stack_segment_valid(vcpu))
3993                         return false;
3994                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3995                         return false;
3996                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3997                         return false;
3998                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3999                         return false;
4000                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4001                         return false;
4002                 if (!tr_valid(vcpu))
4003                         return false;
4004                 if (!ldtr_valid(vcpu))
4005                         return false;
4006         }
4007         /* TODO:
4008          * - Add checks on RIP
4009          * - Add checks on RFLAGS
4010          */
4011
4012         return true;
4013 }
4014
4015 static int init_rmode_tss(struct kvm *kvm)
4016 {
4017         gfn_t fn;
4018         u16 data = 0;
4019         int idx, r;
4020
4021         idx = srcu_read_lock(&kvm->srcu);
4022         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4023         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4024         if (r < 0)
4025                 goto out;
4026         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4027         r = kvm_write_guest_page(kvm, fn++, &data,
4028                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4029         if (r < 0)
4030                 goto out;
4031         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4032         if (r < 0)
4033                 goto out;
4034         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4035         if (r < 0)
4036                 goto out;
4037         data = ~0;
4038         r = kvm_write_guest_page(kvm, fn, &data,
4039                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4040                                  sizeof(u8));
4041 out:
4042         srcu_read_unlock(&kvm->srcu, idx);
4043         return r;
4044 }
4045
4046 static int init_rmode_identity_map(struct kvm *kvm)
4047 {
4048         int i, idx, r = 0;
4049         pfn_t identity_map_pfn;
4050         u32 tmp;
4051
4052         if (!enable_ept)
4053                 return 0;
4054
4055         /* Protect kvm->arch.ept_identity_pagetable_done. */
4056         mutex_lock(&kvm->slots_lock);
4057
4058         if (likely(kvm->arch.ept_identity_pagetable_done))
4059                 goto out2;
4060
4061         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4062
4063         r = alloc_identity_pagetable(kvm);
4064         if (r < 0)
4065                 goto out2;
4066
4067         idx = srcu_read_lock(&kvm->srcu);
4068         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4069         if (r < 0)
4070                 goto out;
4071         /* Set up identity-mapping pagetable for EPT in real mode */
4072         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4073                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4074                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4075                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4076                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4077                 if (r < 0)
4078                         goto out;
4079         }
4080         kvm->arch.ept_identity_pagetable_done = true;
4081
4082 out:
4083         srcu_read_unlock(&kvm->srcu, idx);
4084
4085 out2:
4086         mutex_unlock(&kvm->slots_lock);
4087         return r;
4088 }
4089
4090 static void seg_setup(int seg)
4091 {
4092         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4093         unsigned int ar;
4094
4095         vmcs_write16(sf->selector, 0);
4096         vmcs_writel(sf->base, 0);
4097         vmcs_write32(sf->limit, 0xffff);
4098         ar = 0x93;
4099         if (seg == VCPU_SREG_CS)
4100                 ar |= 0x08; /* code segment */
4101
4102         vmcs_write32(sf->ar_bytes, ar);
4103 }
4104
4105 static int alloc_apic_access_page(struct kvm *kvm)
4106 {
4107         struct page *page;
4108         struct kvm_userspace_memory_region kvm_userspace_mem;
4109         int r = 0;
4110
4111         mutex_lock(&kvm->slots_lock);
4112         if (kvm->arch.apic_access_page_done)
4113                 goto out;
4114         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4115         kvm_userspace_mem.flags = 0;
4116         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4117         kvm_userspace_mem.memory_size = PAGE_SIZE;
4118         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4119         if (r)
4120                 goto out;
4121
4122         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4123         if (is_error_page(page)) {
4124                 r = -EFAULT;
4125                 goto out;
4126         }
4127
4128         /*
4129          * Do not pin the page in memory, so that memory hot-unplug
4130          * is able to migrate it.
4131          */
4132         put_page(page);
4133         kvm->arch.apic_access_page_done = true;
4134 out:
4135         mutex_unlock(&kvm->slots_lock);
4136         return r;
4137 }
4138
4139 static int alloc_identity_pagetable(struct kvm *kvm)
4140 {
4141         /* Called with kvm->slots_lock held. */
4142
4143         struct kvm_userspace_memory_region kvm_userspace_mem;
4144         int r = 0;
4145
4146         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4147
4148         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4149         kvm_userspace_mem.flags = 0;
4150         kvm_userspace_mem.guest_phys_addr =
4151                 kvm->arch.ept_identity_map_addr;
4152         kvm_userspace_mem.memory_size = PAGE_SIZE;
4153         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4154
4155         return r;
4156 }
4157
4158 static void allocate_vpid(struct vcpu_vmx *vmx)
4159 {
4160         int vpid;
4161
4162         vmx->vpid = 0;
4163         if (!enable_vpid)
4164                 return;
4165         spin_lock(&vmx_vpid_lock);
4166         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4167         if (vpid < VMX_NR_VPIDS) {
4168                 vmx->vpid = vpid;
4169                 __set_bit(vpid, vmx_vpid_bitmap);
4170         }
4171         spin_unlock(&vmx_vpid_lock);
4172 }
4173
4174 static void free_vpid(struct vcpu_vmx *vmx)
4175 {
4176         if (!enable_vpid)
4177                 return;
4178         spin_lock(&vmx_vpid_lock);
4179         if (vmx->vpid != 0)
4180                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4181         spin_unlock(&vmx_vpid_lock);
4182 }
4183
4184 #define MSR_TYPE_R      1
4185 #define MSR_TYPE_W      2
4186 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4187                                                 u32 msr, int type)
4188 {
4189         int f = sizeof(unsigned long);
4190
4191         if (!cpu_has_vmx_msr_bitmap())
4192                 return;
4193
4194         /*
4195          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4196          * have the write-low and read-high bitmap offsets the wrong way round.
4197          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4198          */
4199         if (msr <= 0x1fff) {
4200                 if (type & MSR_TYPE_R)
4201                         /* read-low */
4202                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4203
4204                 if (type & MSR_TYPE_W)
4205                         /* write-low */
4206                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4207
4208         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4209                 msr &= 0x1fff;
4210                 if (type & MSR_TYPE_R)
4211                         /* read-high */
4212                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4213
4214                 if (type & MSR_TYPE_W)
4215                         /* write-high */
4216                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4217
4218         }
4219 }
4220
4221 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4222                                                 u32 msr, int type)
4223 {
4224         int f = sizeof(unsigned long);
4225
4226         if (!cpu_has_vmx_msr_bitmap())
4227                 return;
4228
4229         /*
4230          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4231          * have the write-low and read-high bitmap offsets the wrong way round.
4232          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4233          */
4234         if (msr <= 0x1fff) {
4235                 if (type & MSR_TYPE_R)
4236                         /* read-low */
4237                         __set_bit(msr, msr_bitmap + 0x000 / f);
4238
4239                 if (type & MSR_TYPE_W)
4240                         /* write-low */
4241                         __set_bit(msr, msr_bitmap + 0x800 / f);
4242
4243         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4244                 msr &= 0x1fff;
4245                 if (type & MSR_TYPE_R)
4246                         /* read-high */
4247                         __set_bit(msr, msr_bitmap + 0x400 / f);
4248
4249                 if (type & MSR_TYPE_W)
4250                         /* write-high */
4251                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4252
4253         }
4254 }
4255
4256 /*
4257  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4258  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4259  */
4260 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4261                                                unsigned long *msr_bitmap_nested,
4262                                                u32 msr, int type)
4263 {
4264         int f = sizeof(unsigned long);
4265
4266         if (!cpu_has_vmx_msr_bitmap()) {
4267                 WARN_ON(1);
4268                 return;
4269         }
4270
4271         /*
4272          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4273          * have the write-low and read-high bitmap offsets the wrong way round.
4274          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4275          */
4276         if (msr <= 0x1fff) {
4277                 if (type & MSR_TYPE_R &&
4278                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4279                         /* read-low */
4280                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4281
4282                 if (type & MSR_TYPE_W &&
4283                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4284                         /* write-low */
4285                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4286
4287         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4288                 msr &= 0x1fff;
4289                 if (type & MSR_TYPE_R &&
4290                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4291                         /* read-high */
4292                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4293
4294                 if (type & MSR_TYPE_W &&
4295                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4296                         /* write-high */
4297                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4298
4299         }
4300 }
4301
4302 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4303 {
4304         if (!longmode_only)
4305                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4306                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4307         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4308                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4309 }
4310
4311 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4312 {
4313         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4314                         msr, MSR_TYPE_R);
4315         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4316                         msr, MSR_TYPE_R);
4317 }
4318
4319 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4320 {
4321         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4322                         msr, MSR_TYPE_R);
4323         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4324                         msr, MSR_TYPE_R);
4325 }
4326
4327 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4328 {
4329         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4330                         msr, MSR_TYPE_W);
4331         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4332                         msr, MSR_TYPE_W);
4333 }
4334
4335 static int vmx_vm_has_apicv(struct kvm *kvm)
4336 {
4337         return enable_apicv && irqchip_in_kernel(kvm);
4338 }
4339
4340 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4341 {
4342         struct vcpu_vmx *vmx = to_vmx(vcpu);
4343         int max_irr;
4344         void *vapic_page;
4345         u16 status;
4346
4347         if (vmx->nested.pi_desc &&
4348             vmx->nested.pi_pending) {
4349                 vmx->nested.pi_pending = false;
4350                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4351                         return 0;
4352
4353                 max_irr = find_last_bit(
4354                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4355
4356                 if (max_irr == 256)
4357                         return 0;
4358
4359                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4360                 if (!vapic_page) {
4361                         WARN_ON(1);
4362                         return -ENOMEM;
4363                 }
4364                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4365                 kunmap(vmx->nested.virtual_apic_page);
4366
4367                 status = vmcs_read16(GUEST_INTR_STATUS);
4368                 if ((u8)max_irr > ((u8)status & 0xff)) {
4369                         status &= ~0xff;
4370                         status |= (u8)max_irr;
4371                         vmcs_write16(GUEST_INTR_STATUS, status);
4372                 }
4373         }
4374         return 0;
4375 }
4376
4377 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4378 {
4379 #ifdef CONFIG_SMP
4380         if (vcpu->mode == IN_GUEST_MODE) {
4381                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4382                                 POSTED_INTR_VECTOR);
4383                 return true;
4384         }
4385 #endif
4386         return false;
4387 }
4388
4389 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4390                                                 int vector)
4391 {
4392         struct vcpu_vmx *vmx = to_vmx(vcpu);
4393
4394         if (is_guest_mode(vcpu) &&
4395             vector == vmx->nested.posted_intr_nv) {
4396                 /* the PIR and ON have been set by L1. */
4397                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4398                 /*
4399                  * If a posted intr is not recognized by hardware,
4400                  * we will accomplish it in the next vmentry.
4401                  */
4402                 vmx->nested.pi_pending = true;
4403                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4404                 return 0;
4405         }
4406         return -1;
4407 }
4408 /*
4409  * Send interrupt to vcpu via posted interrupt way.
4410  * 1. If target vcpu is running(non-root mode), send posted interrupt
4411  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4412  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4413  * interrupt from PIR in next vmentry.
4414  */
4415 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4416 {
4417         struct vcpu_vmx *vmx = to_vmx(vcpu);
4418         int r;
4419
4420         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4421         if (!r)
4422                 return;
4423
4424         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4425                 return;
4426
4427         r = pi_test_and_set_on(&vmx->pi_desc);
4428         kvm_make_request(KVM_REQ_EVENT, vcpu);
4429         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4430                 kvm_vcpu_kick(vcpu);
4431 }
4432
4433 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4434 {
4435         struct vcpu_vmx *vmx = to_vmx(vcpu);
4436
4437         if (!pi_test_and_clear_on(&vmx->pi_desc))
4438                 return;
4439
4440         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4441 }
4442
4443 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4444 {
4445         return;
4446 }
4447
4448 /*
4449  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4450  * will not change in the lifetime of the guest.
4451  * Note that host-state that does change is set elsewhere. E.g., host-state
4452  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4453  */
4454 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4455 {
4456         u32 low32, high32;
4457         unsigned long tmpl;
4458         struct desc_ptr dt;
4459         unsigned long cr4;
4460
4461         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4462         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4463
4464         /* Save the most likely value for this task's CR4 in the VMCS. */
4465         cr4 = cr4_read_shadow();
4466         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4467         vmx->host_state.vmcs_host_cr4 = cr4;
4468
4469         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4470 #ifdef CONFIG_X86_64
4471         /*
4472          * Load null selectors, so we can avoid reloading them in
4473          * __vmx_load_host_state(), in case userspace uses the null selectors
4474          * too (the expected case).
4475          */
4476         vmcs_write16(HOST_DS_SELECTOR, 0);
4477         vmcs_write16(HOST_ES_SELECTOR, 0);
4478 #else
4479         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4480         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4481 #endif
4482         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4483         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4484
4485         native_store_idt(&dt);
4486         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4487         vmx->host_idt_base = dt.address;
4488
4489         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4490
4491         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4492         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4493         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4494         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4495
4496         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4497                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4498                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4499         }
4500 }
4501
4502 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4503 {
4504         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4505         if (enable_ept)
4506                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4507         if (is_guest_mode(&vmx->vcpu))
4508                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4509                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4510         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4511 }
4512
4513 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4514 {
4515         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4516
4517         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4518                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4519         return pin_based_exec_ctrl;
4520 }
4521
4522 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4523 {
4524         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4525
4526         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4527                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4528
4529         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4530                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4531 #ifdef CONFIG_X86_64
4532                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4533                                 CPU_BASED_CR8_LOAD_EXITING;
4534 #endif
4535         }
4536         if (!enable_ept)
4537                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4538                                 CPU_BASED_CR3_LOAD_EXITING  |
4539                                 CPU_BASED_INVLPG_EXITING;
4540         return exec_control;
4541 }
4542
4543 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4544 {
4545         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4546         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4547                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4548         if (vmx->vpid == 0)
4549                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4550         if (!enable_ept) {
4551                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4552                 enable_unrestricted_guest = 0;
4553                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4554                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4555         }
4556         if (!enable_unrestricted_guest)
4557                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4558         if (!ple_gap)
4559                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4560         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4561                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4562                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4563         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4564         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4565            (handle_vmptrld).
4566            We can NOT enable shadow_vmcs here because we don't have yet
4567            a current VMCS12
4568         */
4569         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4570         /* PML is enabled/disabled in creating/destorying vcpu */
4571         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4572
4573         return exec_control;
4574 }
4575
4576 static void ept_set_mmio_spte_mask(void)
4577 {
4578         /*
4579          * EPT Misconfigurations can be generated if the value of bits 2:0
4580          * of an EPT paging-structure entry is 110b (write/execute).
4581          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4582          * spte.
4583          */
4584         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4585 }
4586
4587 #define VMX_XSS_EXIT_BITMAP 0
4588 /*
4589  * Sets up the vmcs for emulated real mode.
4590  */
4591 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4592 {
4593 #ifdef CONFIG_X86_64
4594         unsigned long a;
4595 #endif
4596         int i;
4597
4598         /* I/O */
4599         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4600         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4601
4602         if (enable_shadow_vmcs) {
4603                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4604                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4605         }
4606         if (cpu_has_vmx_msr_bitmap())
4607                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4608
4609         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4610
4611         /* Control */
4612         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4613
4614         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4615
4616         if (cpu_has_secondary_exec_ctrls()) {
4617                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4618                                 vmx_secondary_exec_control(vmx));
4619         }
4620
4621         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4622                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4623                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4624                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4625                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4626
4627                 vmcs_write16(GUEST_INTR_STATUS, 0);
4628
4629                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4630                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4631         }
4632
4633         if (ple_gap) {
4634                 vmcs_write32(PLE_GAP, ple_gap);
4635                 vmx->ple_window = ple_window;
4636                 vmx->ple_window_dirty = true;
4637         }
4638
4639         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4640         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4641         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4642
4643         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4644         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4645         vmx_set_constant_host_state(vmx);
4646 #ifdef CONFIG_X86_64
4647         rdmsrl(MSR_FS_BASE, a);
4648         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4649         rdmsrl(MSR_GS_BASE, a);
4650         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4651 #else
4652         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4653         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4654 #endif
4655
4656         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4657         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4658         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4659         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4660         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4661
4662         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4663                 u32 msr_low, msr_high;
4664                 u64 host_pat;
4665                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4666                 host_pat = msr_low | ((u64) msr_high << 32);
4667                 /* Write the default value follow host pat */
4668                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4669                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4670                 vmx->vcpu.arch.pat = host_pat;
4671         }
4672
4673         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4674                 u32 index = vmx_msr_index[i];
4675                 u32 data_low, data_high;
4676                 int j = vmx->nmsrs;
4677
4678                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4679                         continue;
4680                 if (wrmsr_safe(index, data_low, data_high) < 0)
4681                         continue;
4682                 vmx->guest_msrs[j].index = i;
4683                 vmx->guest_msrs[j].data = 0;
4684                 vmx->guest_msrs[j].mask = -1ull;
4685                 ++vmx->nmsrs;
4686         }
4687
4688
4689         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4690
4691         /* 22.2.1, 20.8.1 */
4692         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4693
4694         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4695         set_cr4_guest_host_mask(vmx);
4696
4697         if (vmx_xsaves_supported())
4698                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4699
4700         return 0;
4701 }
4702
4703 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4704 {
4705         struct vcpu_vmx *vmx = to_vmx(vcpu);
4706         struct msr_data apic_base_msr;
4707
4708         vmx->rmode.vm86_active = 0;
4709
4710         vmx->soft_vnmi_blocked = 0;
4711
4712         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4713         kvm_set_cr8(&vmx->vcpu, 0);
4714         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4715         if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
4716                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4717         apic_base_msr.host_initiated = true;
4718         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4719
4720         vmx_segment_cache_clear(vmx);
4721
4722         seg_setup(VCPU_SREG_CS);
4723         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4724         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4725
4726         seg_setup(VCPU_SREG_DS);
4727         seg_setup(VCPU_SREG_ES);
4728         seg_setup(VCPU_SREG_FS);
4729         seg_setup(VCPU_SREG_GS);
4730         seg_setup(VCPU_SREG_SS);
4731
4732         vmcs_write16(GUEST_TR_SELECTOR, 0);
4733         vmcs_writel(GUEST_TR_BASE, 0);
4734         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4735         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4736
4737         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4738         vmcs_writel(GUEST_LDTR_BASE, 0);
4739         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4740         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4741
4742         vmcs_write32(GUEST_SYSENTER_CS, 0);
4743         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4744         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4745
4746         vmcs_writel(GUEST_RFLAGS, 0x02);
4747         kvm_rip_write(vcpu, 0xfff0);
4748
4749         vmcs_writel(GUEST_GDTR_BASE, 0);
4750         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4751
4752         vmcs_writel(GUEST_IDTR_BASE, 0);
4753         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4754
4755         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4756         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4757         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4758
4759         /* Special registers */
4760         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4761
4762         setup_msrs(vmx);
4763
4764         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4765
4766         if (cpu_has_vmx_tpr_shadow()) {
4767                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4768                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4769                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4770                                      __pa(vmx->vcpu.arch.apic->regs));
4771                 vmcs_write32(TPR_THRESHOLD, 0);
4772         }
4773
4774         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4775
4776         if (vmx_vm_has_apicv(vcpu->kvm))
4777                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4778
4779         if (vmx->vpid != 0)
4780                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4781
4782         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4783         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4784         vmx_set_cr4(&vmx->vcpu, 0);
4785         vmx_set_efer(&vmx->vcpu, 0);
4786         vmx_fpu_activate(&vmx->vcpu);
4787         update_exception_bitmap(&vmx->vcpu);
4788
4789         vpid_sync_context(vmx);
4790 }
4791
4792 /*
4793  * In nested virtualization, check if L1 asked to exit on external interrupts.
4794  * For most existing hypervisors, this will always return true.
4795  */
4796 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4797 {
4798         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4799                 PIN_BASED_EXT_INTR_MASK;
4800 }
4801
4802 /*
4803  * In nested virtualization, check if L1 has set
4804  * VM_EXIT_ACK_INTR_ON_EXIT
4805  */
4806 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4807 {
4808         return get_vmcs12(vcpu)->vm_exit_controls &
4809                 VM_EXIT_ACK_INTR_ON_EXIT;
4810 }
4811
4812 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4813 {
4814         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4815                 PIN_BASED_NMI_EXITING;
4816 }
4817
4818 static void enable_irq_window(struct kvm_vcpu *vcpu)
4819 {
4820         u32 cpu_based_vm_exec_control;
4821
4822         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4823         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4824         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4825 }
4826
4827 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4828 {
4829         u32 cpu_based_vm_exec_control;
4830
4831         if (!cpu_has_virtual_nmis() ||
4832             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4833                 enable_irq_window(vcpu);
4834                 return;
4835         }
4836
4837         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4838         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4839         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4840 }
4841
4842 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4843 {
4844         struct vcpu_vmx *vmx = to_vmx(vcpu);
4845         uint32_t intr;
4846         int irq = vcpu->arch.interrupt.nr;
4847
4848         trace_kvm_inj_virq(irq);
4849
4850         ++vcpu->stat.irq_injections;
4851         if (vmx->rmode.vm86_active) {
4852                 int inc_eip = 0;
4853                 if (vcpu->arch.interrupt.soft)
4854                         inc_eip = vcpu->arch.event_exit_inst_len;
4855                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4856                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4857                 return;
4858         }
4859         intr = irq | INTR_INFO_VALID_MASK;
4860         if (vcpu->arch.interrupt.soft) {
4861                 intr |= INTR_TYPE_SOFT_INTR;
4862                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4863                              vmx->vcpu.arch.event_exit_inst_len);
4864         } else
4865                 intr |= INTR_TYPE_EXT_INTR;
4866         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4867 }
4868
4869 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4870 {
4871         struct vcpu_vmx *vmx = to_vmx(vcpu);
4872
4873         if (is_guest_mode(vcpu))
4874                 return;
4875
4876         if (!cpu_has_virtual_nmis()) {
4877                 /*
4878                  * Tracking the NMI-blocked state in software is built upon
4879                  * finding the next open IRQ window. This, in turn, depends on
4880                  * well-behaving guests: They have to keep IRQs disabled at
4881                  * least as long as the NMI handler runs. Otherwise we may
4882                  * cause NMI nesting, maybe breaking the guest. But as this is
4883                  * highly unlikely, we can live with the residual risk.
4884                  */
4885                 vmx->soft_vnmi_blocked = 1;
4886                 vmx->vnmi_blocked_time = 0;
4887         }
4888
4889         ++vcpu->stat.nmi_injections;
4890         vmx->nmi_known_unmasked = false;
4891         if (vmx->rmode.vm86_active) {
4892                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4893                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4894                 return;
4895         }
4896         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4897                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4898 }
4899
4900 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4901 {
4902         if (!cpu_has_virtual_nmis())
4903                 return to_vmx(vcpu)->soft_vnmi_blocked;
4904         if (to_vmx(vcpu)->nmi_known_unmasked)
4905                 return false;
4906         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4907 }
4908
4909 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4910 {
4911         struct vcpu_vmx *vmx = to_vmx(vcpu);
4912
4913         if (!cpu_has_virtual_nmis()) {
4914                 if (vmx->soft_vnmi_blocked != masked) {
4915                         vmx->soft_vnmi_blocked = masked;
4916                         vmx->vnmi_blocked_time = 0;
4917                 }
4918         } else {
4919                 vmx->nmi_known_unmasked = !masked;
4920                 if (masked)
4921                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4922                                       GUEST_INTR_STATE_NMI);
4923                 else
4924                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4925                                         GUEST_INTR_STATE_NMI);
4926         }
4927 }
4928
4929 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4930 {
4931         if (to_vmx(vcpu)->nested.nested_run_pending)
4932                 return 0;
4933
4934         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4935                 return 0;
4936
4937         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4938                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4939                    | GUEST_INTR_STATE_NMI));
4940 }
4941
4942 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4943 {
4944         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4945                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4946                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4947                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4948 }
4949
4950 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4951 {
4952         int ret;
4953         struct kvm_userspace_memory_region tss_mem = {
4954                 .slot = TSS_PRIVATE_MEMSLOT,
4955                 .guest_phys_addr = addr,
4956                 .memory_size = PAGE_SIZE * 3,
4957                 .flags = 0,
4958         };
4959
4960         ret = kvm_set_memory_region(kvm, &tss_mem);
4961         if (ret)
4962                 return ret;
4963         kvm->arch.tss_addr = addr;
4964         return init_rmode_tss(kvm);
4965 }
4966
4967 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4968 {
4969         switch (vec) {
4970         case BP_VECTOR:
4971                 /*
4972                  * Update instruction length as we may reinject the exception
4973                  * from user space while in guest debugging mode.
4974                  */
4975                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4976                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4977                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4978                         return false;
4979                 /* fall through */
4980         case DB_VECTOR:
4981                 if (vcpu->guest_debug &
4982                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4983                         return false;
4984                 /* fall through */
4985         case DE_VECTOR:
4986         case OF_VECTOR:
4987         case BR_VECTOR:
4988         case UD_VECTOR:
4989         case DF_VECTOR:
4990         case SS_VECTOR:
4991         case GP_VECTOR:
4992         case MF_VECTOR:
4993                 return true;
4994         break;
4995         }
4996         return false;
4997 }
4998
4999 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5000                                   int vec, u32 err_code)
5001 {
5002         /*
5003          * Instruction with address size override prefix opcode 0x67
5004          * Cause the #SS fault with 0 error code in VM86 mode.
5005          */
5006         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5007                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5008                         if (vcpu->arch.halt_request) {
5009                                 vcpu->arch.halt_request = 0;
5010                                 return kvm_vcpu_halt(vcpu);
5011                         }
5012                         return 1;
5013                 }
5014                 return 0;
5015         }
5016
5017         /*
5018          * Forward all other exceptions that are valid in real mode.
5019          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5020          *        the required debugging infrastructure rework.
5021          */
5022         kvm_queue_exception(vcpu, vec);
5023         return 1;
5024 }
5025
5026 /*
5027  * Trigger machine check on the host. We assume all the MSRs are already set up
5028  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5029  * We pass a fake environment to the machine check handler because we want
5030  * the guest to be always treated like user space, no matter what context
5031  * it used internally.
5032  */
5033 static void kvm_machine_check(void)
5034 {
5035 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5036         struct pt_regs regs = {
5037                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5038                 .flags = X86_EFLAGS_IF,
5039         };
5040
5041         do_machine_check(&regs, 0);
5042 #endif
5043 }
5044
5045 static int handle_machine_check(struct kvm_vcpu *vcpu)
5046 {
5047         /* already handled by vcpu_run */
5048         return 1;
5049 }
5050
5051 static int handle_exception(struct kvm_vcpu *vcpu)
5052 {
5053         struct vcpu_vmx *vmx = to_vmx(vcpu);
5054         struct kvm_run *kvm_run = vcpu->run;
5055         u32 intr_info, ex_no, error_code;
5056         unsigned long cr2, rip, dr6;
5057         u32 vect_info;
5058         enum emulation_result er;
5059
5060         vect_info = vmx->idt_vectoring_info;
5061         intr_info = vmx->exit_intr_info;
5062
5063         if (is_machine_check(intr_info))
5064                 return handle_machine_check(vcpu);
5065
5066         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5067                 return 1;  /* already handled by vmx_vcpu_run() */
5068
5069         if (is_no_device(intr_info)) {
5070                 vmx_fpu_activate(vcpu);
5071                 return 1;
5072         }
5073
5074         if (is_invalid_opcode(intr_info)) {
5075                 if (is_guest_mode(vcpu)) {
5076                         kvm_queue_exception(vcpu, UD_VECTOR);
5077                         return 1;
5078                 }
5079                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5080                 if (er != EMULATE_DONE)
5081                         kvm_queue_exception(vcpu, UD_VECTOR);
5082                 return 1;
5083         }
5084
5085         error_code = 0;
5086         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5087                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5088
5089         /*
5090          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5091          * MMIO, it is better to report an internal error.
5092          * See the comments in vmx_handle_exit.
5093          */
5094         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5095             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5096                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5097                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5098                 vcpu->run->internal.ndata = 3;
5099                 vcpu->run->internal.data[0] = vect_info;
5100                 vcpu->run->internal.data[1] = intr_info;
5101                 vcpu->run->internal.data[2] = error_code;
5102                 return 0;
5103         }
5104
5105         if (is_page_fault(intr_info)) {
5106                 /* EPT won't cause page fault directly */
5107                 BUG_ON(enable_ept);
5108                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5109                 trace_kvm_page_fault(cr2, error_code);
5110
5111                 if (kvm_event_needs_reinjection(vcpu))
5112                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5113                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5114         }
5115
5116         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5117
5118         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5119                 return handle_rmode_exception(vcpu, ex_no, error_code);
5120
5121         switch (ex_no) {
5122         case DB_VECTOR:
5123                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5124                 if (!(vcpu->guest_debug &
5125                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5126                         vcpu->arch.dr6 &= ~15;
5127                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5128                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5129                                 skip_emulated_instruction(vcpu);
5130
5131                         kvm_queue_exception(vcpu, DB_VECTOR);
5132                         return 1;
5133                 }
5134                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5135                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5136                 /* fall through */
5137         case BP_VECTOR:
5138                 /*
5139                  * Update instruction length as we may reinject #BP from
5140                  * user space while in guest debugging mode. Reading it for
5141                  * #DB as well causes no harm, it is not used in that case.
5142                  */
5143                 vmx->vcpu.arch.event_exit_inst_len =
5144                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5145                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5146                 rip = kvm_rip_read(vcpu);
5147                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5148                 kvm_run->debug.arch.exception = ex_no;
5149                 break;
5150         default:
5151                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5152                 kvm_run->ex.exception = ex_no;
5153                 kvm_run->ex.error_code = error_code;
5154                 break;
5155         }
5156         return 0;
5157 }
5158
5159 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5160 {
5161         ++vcpu->stat.irq_exits;
5162         return 1;
5163 }
5164
5165 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5166 {
5167         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5168         return 0;
5169 }
5170
5171 static int handle_io(struct kvm_vcpu *vcpu)
5172 {
5173         unsigned long exit_qualification;
5174         int size, in, string;
5175         unsigned port;
5176
5177         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5178         string = (exit_qualification & 16) != 0;
5179         in = (exit_qualification & 8) != 0;
5180
5181         ++vcpu->stat.io_exits;
5182
5183         if (string || in)
5184                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5185
5186         port = exit_qualification >> 16;
5187         size = (exit_qualification & 7) + 1;
5188         skip_emulated_instruction(vcpu);
5189
5190         return kvm_fast_pio_out(vcpu, size, port);
5191 }
5192
5193 static void
5194 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5195 {
5196         /*
5197          * Patch in the VMCALL instruction:
5198          */
5199         hypercall[0] = 0x0f;
5200         hypercall[1] = 0x01;
5201         hypercall[2] = 0xc1;
5202 }
5203
5204 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5205 {
5206         unsigned long always_on = VMXON_CR0_ALWAYSON;
5207         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5208
5209         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5210                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5211             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5212                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5213         return (val & always_on) == always_on;
5214 }
5215
5216 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5217 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5218 {
5219         if (is_guest_mode(vcpu)) {
5220                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5221                 unsigned long orig_val = val;
5222
5223                 /*
5224                  * We get here when L2 changed cr0 in a way that did not change
5225                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5226                  * but did change L0 shadowed bits. So we first calculate the
5227                  * effective cr0 value that L1 would like to write into the
5228                  * hardware. It consists of the L2-owned bits from the new
5229                  * value combined with the L1-owned bits from L1's guest_cr0.
5230                  */
5231                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5232                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5233
5234                 if (!nested_cr0_valid(vcpu, val))
5235                         return 1;
5236
5237                 if (kvm_set_cr0(vcpu, val))
5238                         return 1;
5239                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5240                 return 0;
5241         } else {
5242                 if (to_vmx(vcpu)->nested.vmxon &&
5243                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5244                         return 1;
5245                 return kvm_set_cr0(vcpu, val);
5246         }
5247 }
5248
5249 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5250 {
5251         if (is_guest_mode(vcpu)) {
5252                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5253                 unsigned long orig_val = val;
5254
5255                 /* analogously to handle_set_cr0 */
5256                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5257                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5258                 if (kvm_set_cr4(vcpu, val))
5259                         return 1;
5260                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5261                 return 0;
5262         } else
5263                 return kvm_set_cr4(vcpu, val);
5264 }
5265
5266 /* called to set cr0 as approriate for clts instruction exit. */
5267 static void handle_clts(struct kvm_vcpu *vcpu)
5268 {
5269         if (is_guest_mode(vcpu)) {
5270                 /*
5271                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5272                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5273                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5274                  */
5275                 vmcs_writel(CR0_READ_SHADOW,
5276                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5277                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5278         } else
5279                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5280 }
5281
5282 static int handle_cr(struct kvm_vcpu *vcpu)
5283 {
5284         unsigned long exit_qualification, val;
5285         int cr;
5286         int reg;
5287         int err;
5288
5289         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5290         cr = exit_qualification & 15;
5291         reg = (exit_qualification >> 8) & 15;
5292         switch ((exit_qualification >> 4) & 3) {
5293         case 0: /* mov to cr */
5294                 val = kvm_register_readl(vcpu, reg);
5295                 trace_kvm_cr_write(cr, val);
5296                 switch (cr) {
5297                 case 0:
5298                         err = handle_set_cr0(vcpu, val);
5299                         kvm_complete_insn_gp(vcpu, err);
5300                         return 1;
5301                 case 3:
5302                         err = kvm_set_cr3(vcpu, val);
5303                         kvm_complete_insn_gp(vcpu, err);
5304                         return 1;
5305                 case 4:
5306                         err = handle_set_cr4(vcpu, val);
5307                         kvm_complete_insn_gp(vcpu, err);
5308                         return 1;
5309                 case 8: {
5310                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5311                                 u8 cr8 = (u8)val;
5312                                 err = kvm_set_cr8(vcpu, cr8);
5313                                 kvm_complete_insn_gp(vcpu, err);
5314                                 if (irqchip_in_kernel(vcpu->kvm))
5315                                         return 1;
5316                                 if (cr8_prev <= cr8)
5317                                         return 1;
5318                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5319                                 return 0;
5320                         }
5321                 }
5322                 break;
5323         case 2: /* clts */
5324                 handle_clts(vcpu);
5325                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5326                 skip_emulated_instruction(vcpu);
5327                 vmx_fpu_activate(vcpu);
5328                 return 1;
5329         case 1: /*mov from cr*/
5330                 switch (cr) {
5331                 case 3:
5332                         val = kvm_read_cr3(vcpu);
5333                         kvm_register_write(vcpu, reg, val);
5334                         trace_kvm_cr_read(cr, val);
5335                         skip_emulated_instruction(vcpu);
5336                         return 1;
5337                 case 8:
5338                         val = kvm_get_cr8(vcpu);
5339                         kvm_register_write(vcpu, reg, val);
5340                         trace_kvm_cr_read(cr, val);
5341                         skip_emulated_instruction(vcpu);
5342                         return 1;
5343                 }
5344                 break;
5345         case 3: /* lmsw */
5346                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5347                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5348                 kvm_lmsw(vcpu, val);
5349
5350                 skip_emulated_instruction(vcpu);
5351                 return 1;
5352         default:
5353                 break;
5354         }
5355         vcpu->run->exit_reason = 0;
5356         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5357                (int)(exit_qualification >> 4) & 3, cr);
5358         return 0;
5359 }
5360
5361 static int handle_dr(struct kvm_vcpu *vcpu)
5362 {
5363         unsigned long exit_qualification;
5364         int dr, dr7, reg;
5365
5366         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5367         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5368
5369         /* First, if DR does not exist, trigger UD */
5370         if (!kvm_require_dr(vcpu, dr))
5371                 return 1;
5372
5373         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5374         if (!kvm_require_cpl(vcpu, 0))
5375                 return 1;
5376         dr7 = vmcs_readl(GUEST_DR7);
5377         if (dr7 & DR7_GD) {
5378                 /*
5379                  * As the vm-exit takes precedence over the debug trap, we
5380                  * need to emulate the latter, either for the host or the
5381                  * guest debugging itself.
5382                  */
5383                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5384                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5385                         vcpu->run->debug.arch.dr7 = dr7;
5386                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5387                         vcpu->run->debug.arch.exception = DB_VECTOR;
5388                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5389                         return 0;
5390                 } else {
5391                         vcpu->arch.dr6 &= ~15;
5392                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5393                         kvm_queue_exception(vcpu, DB_VECTOR);
5394                         return 1;
5395                 }
5396         }
5397
5398         if (vcpu->guest_debug == 0) {
5399                 u32 cpu_based_vm_exec_control;
5400
5401                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5402                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5403                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5404
5405                 /*
5406                  * No more DR vmexits; force a reload of the debug registers
5407                  * and reenter on this instruction.  The next vmexit will
5408                  * retrieve the full state of the debug registers.
5409                  */
5410                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5411                 return 1;
5412         }
5413
5414         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5415         if (exit_qualification & TYPE_MOV_FROM_DR) {
5416                 unsigned long val;
5417
5418                 if (kvm_get_dr(vcpu, dr, &val))
5419                         return 1;
5420                 kvm_register_write(vcpu, reg, val);
5421         } else
5422                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5423                         return 1;
5424
5425         skip_emulated_instruction(vcpu);
5426         return 1;
5427 }
5428
5429 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5430 {
5431         return vcpu->arch.dr6;
5432 }
5433
5434 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5435 {
5436 }
5437
5438 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5439 {
5440         u32 cpu_based_vm_exec_control;
5441
5442         get_debugreg(vcpu->arch.db[0], 0);
5443         get_debugreg(vcpu->arch.db[1], 1);
5444         get_debugreg(vcpu->arch.db[2], 2);
5445         get_debugreg(vcpu->arch.db[3], 3);
5446         get_debugreg(vcpu->arch.dr6, 6);
5447         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5448
5449         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5450
5451         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5452         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5453         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5454 }
5455
5456 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5457 {
5458         vmcs_writel(GUEST_DR7, val);
5459 }
5460
5461 static int handle_cpuid(struct kvm_vcpu *vcpu)
5462 {
5463         kvm_emulate_cpuid(vcpu);
5464         return 1;
5465 }
5466
5467 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5468 {
5469         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5470         u64 data;
5471
5472         if (vmx_get_msr(vcpu, ecx, &data)) {
5473                 trace_kvm_msr_read_ex(ecx);
5474                 kvm_inject_gp(vcpu, 0);
5475                 return 1;
5476         }
5477
5478         trace_kvm_msr_read(ecx, data);
5479
5480         /* FIXME: handling of bits 32:63 of rax, rdx */
5481         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5482         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5483         skip_emulated_instruction(vcpu);
5484         return 1;
5485 }
5486
5487 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5488 {
5489         struct msr_data msr;
5490         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5491         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5492                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5493
5494         msr.data = data;
5495         msr.index = ecx;
5496         msr.host_initiated = false;
5497         if (kvm_set_msr(vcpu, &msr) != 0) {
5498                 trace_kvm_msr_write_ex(ecx, data);
5499                 kvm_inject_gp(vcpu, 0);
5500                 return 1;
5501         }
5502
5503         trace_kvm_msr_write(ecx, data);
5504         skip_emulated_instruction(vcpu);
5505         return 1;
5506 }
5507
5508 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5509 {
5510         kvm_make_request(KVM_REQ_EVENT, vcpu);
5511         return 1;
5512 }
5513
5514 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5515 {
5516         u32 cpu_based_vm_exec_control;
5517
5518         /* clear pending irq */
5519         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5520         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5521         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5522
5523         kvm_make_request(KVM_REQ_EVENT, vcpu);
5524
5525         ++vcpu->stat.irq_window_exits;
5526
5527         /*
5528          * If the user space waits to inject interrupts, exit as soon as
5529          * possible
5530          */
5531         if (!irqchip_in_kernel(vcpu->kvm) &&
5532             vcpu->run->request_interrupt_window &&
5533             !kvm_cpu_has_interrupt(vcpu)) {
5534                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5535                 return 0;
5536         }
5537         return 1;
5538 }
5539
5540 static int handle_halt(struct kvm_vcpu *vcpu)
5541 {
5542         return kvm_emulate_halt(vcpu);
5543 }
5544
5545 static int handle_vmcall(struct kvm_vcpu *vcpu)
5546 {
5547         kvm_emulate_hypercall(vcpu);
5548         return 1;
5549 }
5550
5551 static int handle_invd(struct kvm_vcpu *vcpu)
5552 {
5553         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5554 }
5555
5556 static int handle_invlpg(struct kvm_vcpu *vcpu)
5557 {
5558         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5559
5560         kvm_mmu_invlpg(vcpu, exit_qualification);
5561         skip_emulated_instruction(vcpu);
5562         return 1;
5563 }
5564
5565 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5566 {
5567         int err;
5568
5569         err = kvm_rdpmc(vcpu);
5570         kvm_complete_insn_gp(vcpu, err);
5571
5572         return 1;
5573 }
5574
5575 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5576 {
5577         kvm_emulate_wbinvd(vcpu);
5578         return 1;
5579 }
5580
5581 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5582 {
5583         u64 new_bv = kvm_read_edx_eax(vcpu);
5584         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5585
5586         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5587                 skip_emulated_instruction(vcpu);
5588         return 1;
5589 }
5590
5591 static int handle_xsaves(struct kvm_vcpu *vcpu)
5592 {
5593         skip_emulated_instruction(vcpu);
5594         WARN(1, "this should never happen\n");
5595         return 1;
5596 }
5597
5598 static int handle_xrstors(struct kvm_vcpu *vcpu)
5599 {
5600         skip_emulated_instruction(vcpu);
5601         WARN(1, "this should never happen\n");
5602         return 1;
5603 }
5604
5605 static int handle_apic_access(struct kvm_vcpu *vcpu)
5606 {
5607         if (likely(fasteoi)) {
5608                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5609                 int access_type, offset;
5610
5611                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5612                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5613                 /*
5614                  * Sane guest uses MOV to write EOI, with written value
5615                  * not cared. So make a short-circuit here by avoiding
5616                  * heavy instruction emulation.
5617                  */
5618                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5619                     (offset == APIC_EOI)) {
5620                         kvm_lapic_set_eoi(vcpu);
5621                         skip_emulated_instruction(vcpu);
5622                         return 1;
5623                 }
5624         }
5625         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5626 }
5627
5628 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5629 {
5630         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5631         int vector = exit_qualification & 0xff;
5632
5633         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5634         kvm_apic_set_eoi_accelerated(vcpu, vector);
5635         return 1;
5636 }
5637
5638 static int handle_apic_write(struct kvm_vcpu *vcpu)
5639 {
5640         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5641         u32 offset = exit_qualification & 0xfff;
5642
5643         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5644         kvm_apic_write_nodecode(vcpu, offset);
5645         return 1;
5646 }
5647
5648 static int handle_task_switch(struct kvm_vcpu *vcpu)
5649 {
5650         struct vcpu_vmx *vmx = to_vmx(vcpu);
5651         unsigned long exit_qualification;
5652         bool has_error_code = false;
5653         u32 error_code = 0;
5654         u16 tss_selector;
5655         int reason, type, idt_v, idt_index;
5656
5657         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5658         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5659         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5660
5661         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5662
5663         reason = (u32)exit_qualification >> 30;
5664         if (reason == TASK_SWITCH_GATE && idt_v) {
5665                 switch (type) {
5666                 case INTR_TYPE_NMI_INTR:
5667                         vcpu->arch.nmi_injected = false;
5668                         vmx_set_nmi_mask(vcpu, true);
5669                         break;
5670                 case INTR_TYPE_EXT_INTR:
5671                 case INTR_TYPE_SOFT_INTR:
5672                         kvm_clear_interrupt_queue(vcpu);
5673                         break;
5674                 case INTR_TYPE_HARD_EXCEPTION:
5675                         if (vmx->idt_vectoring_info &
5676                             VECTORING_INFO_DELIVER_CODE_MASK) {
5677                                 has_error_code = true;
5678                                 error_code =
5679                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5680                         }
5681                         /* fall through */
5682                 case INTR_TYPE_SOFT_EXCEPTION:
5683                         kvm_clear_exception_queue(vcpu);
5684                         break;
5685                 default:
5686                         break;
5687                 }
5688         }
5689         tss_selector = exit_qualification;
5690
5691         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5692                        type != INTR_TYPE_EXT_INTR &&
5693                        type != INTR_TYPE_NMI_INTR))
5694                 skip_emulated_instruction(vcpu);
5695
5696         if (kvm_task_switch(vcpu, tss_selector,
5697                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5698                             has_error_code, error_code) == EMULATE_FAIL) {
5699                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5700                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5701                 vcpu->run->internal.ndata = 0;
5702                 return 0;
5703         }
5704
5705         /* clear all local breakpoint enable flags */
5706         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5707
5708         /*
5709          * TODO: What about debug traps on tss switch?
5710          *       Are we supposed to inject them and update dr6?
5711          */
5712
5713         return 1;
5714 }
5715
5716 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5717 {
5718         unsigned long exit_qualification;
5719         gpa_t gpa;
5720         u32 error_code;
5721         int gla_validity;
5722
5723         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5724
5725         gla_validity = (exit_qualification >> 7) & 0x3;
5726         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5727                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5728                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5729                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5730                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5731                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5732                         (long unsigned int)exit_qualification);
5733                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5734                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5735                 return 0;
5736         }
5737
5738         /*
5739          * EPT violation happened while executing iret from NMI,
5740          * "blocked by NMI" bit has to be set before next VM entry.
5741          * There are errata that may cause this bit to not be set:
5742          * AAK134, BY25.
5743          */
5744         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5745                         cpu_has_virtual_nmis() &&
5746                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5747                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5748
5749         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5750         trace_kvm_page_fault(gpa, exit_qualification);
5751
5752         /* It is a write fault? */
5753         error_code = exit_qualification & PFERR_WRITE_MASK;
5754         /* It is a fetch fault? */
5755         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5756         /* ept page table is present? */
5757         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5758
5759         vcpu->arch.exit_qualification = exit_qualification;
5760
5761         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5762 }
5763
5764 static u64 ept_rsvd_mask(u64 spte, int level)
5765 {
5766         int i;
5767         u64 mask = 0;
5768
5769         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5770                 mask |= (1ULL << i);
5771
5772         if (level == 4)
5773                 /* bits 7:3 reserved */
5774                 mask |= 0xf8;
5775         else if (spte & (1ULL << 7))
5776                 /*
5777                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5778                  * level == 1 if the hypervisor is using the ignored bit 7.
5779                  */
5780                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5781         else if (level > 1)
5782                 /* bits 6:3 reserved */
5783                 mask |= 0x78;
5784
5785         return mask;
5786 }
5787
5788 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5789                                        int level)
5790 {
5791         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5792
5793         /* 010b (write-only) */
5794         WARN_ON((spte & 0x7) == 0x2);
5795
5796         /* 110b (write/execute) */
5797         WARN_ON((spte & 0x7) == 0x6);
5798
5799         /* 100b (execute-only) and value not supported by logical processor */
5800         if (!cpu_has_vmx_ept_execute_only())
5801                 WARN_ON((spte & 0x7) == 0x4);
5802
5803         /* not 000b */
5804         if ((spte & 0x7)) {
5805                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5806
5807                 if (rsvd_bits != 0) {
5808                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5809                                          __func__, rsvd_bits);
5810                         WARN_ON(1);
5811                 }
5812
5813                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5814                 if ((rsvd_bits & 0x38) == 0) {
5815                         u64 ept_mem_type = (spte & 0x38) >> 3;
5816
5817                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5818                             ept_mem_type == 7) {
5819                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5820                                                 __func__, ept_mem_type);
5821                                 WARN_ON(1);
5822                         }
5823                 }
5824         }
5825 }
5826
5827 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5828 {
5829         u64 sptes[4];
5830         int nr_sptes, i, ret;
5831         gpa_t gpa;
5832
5833         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5834         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5835                 skip_emulated_instruction(vcpu);
5836                 return 1;
5837         }
5838
5839         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5840         if (likely(ret == RET_MMIO_PF_EMULATE))
5841                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5842                                               EMULATE_DONE;
5843
5844         if (unlikely(ret == RET_MMIO_PF_INVALID))
5845                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5846
5847         if (unlikely(ret == RET_MMIO_PF_RETRY))
5848                 return 1;
5849
5850         /* It is the real ept misconfig */
5851         printk(KERN_ERR "EPT: Misconfiguration.\n");
5852         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5853
5854         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5855
5856         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5857                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5858
5859         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5860         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5861
5862         return 0;
5863 }
5864
5865 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5866 {
5867         u32 cpu_based_vm_exec_control;
5868
5869         /* clear pending NMI */
5870         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5871         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5872         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5873         ++vcpu->stat.nmi_window_exits;
5874         kvm_make_request(KVM_REQ_EVENT, vcpu);
5875
5876         return 1;
5877 }
5878
5879 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5880 {
5881         struct vcpu_vmx *vmx = to_vmx(vcpu);
5882         enum emulation_result err = EMULATE_DONE;
5883         int ret = 1;
5884         u32 cpu_exec_ctrl;
5885         bool intr_window_requested;
5886         unsigned count = 130;
5887
5888         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5889         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5890
5891         while (vmx->emulation_required && count-- != 0) {
5892                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5893                         return handle_interrupt_window(&vmx->vcpu);
5894
5895                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5896                         return 1;
5897
5898                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5899
5900                 if (err == EMULATE_USER_EXIT) {
5901                         ++vcpu->stat.mmio_exits;
5902                         ret = 0;
5903                         goto out;
5904                 }
5905
5906                 if (err != EMULATE_DONE) {
5907                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5908                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5909                         vcpu->run->internal.ndata = 0;
5910                         return 0;
5911                 }
5912
5913                 if (vcpu->arch.halt_request) {
5914                         vcpu->arch.halt_request = 0;
5915                         ret = kvm_vcpu_halt(vcpu);
5916                         goto out;
5917                 }
5918
5919                 if (signal_pending(current))
5920                         goto out;
5921                 if (need_resched())
5922                         schedule();
5923         }
5924
5925 out:
5926         return ret;
5927 }
5928
5929 static int __grow_ple_window(int val)
5930 {
5931         if (ple_window_grow < 1)
5932                 return ple_window;
5933
5934         val = min(val, ple_window_actual_max);
5935
5936         if (ple_window_grow < ple_window)
5937                 val *= ple_window_grow;
5938         else
5939                 val += ple_window_grow;
5940
5941         return val;
5942 }
5943
5944 static int __shrink_ple_window(int val, int modifier, int minimum)
5945 {
5946         if (modifier < 1)
5947                 return ple_window;
5948
5949         if (modifier < ple_window)
5950                 val /= modifier;
5951         else
5952                 val -= modifier;
5953
5954         return max(val, minimum);
5955 }
5956
5957 static void grow_ple_window(struct kvm_vcpu *vcpu)
5958 {
5959         struct vcpu_vmx *vmx = to_vmx(vcpu);
5960         int old = vmx->ple_window;
5961
5962         vmx->ple_window = __grow_ple_window(old);
5963
5964         if (vmx->ple_window != old)
5965                 vmx->ple_window_dirty = true;
5966
5967         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5968 }
5969
5970 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5971 {
5972         struct vcpu_vmx *vmx = to_vmx(vcpu);
5973         int old = vmx->ple_window;
5974
5975         vmx->ple_window = __shrink_ple_window(old,
5976                                               ple_window_shrink, ple_window);
5977
5978         if (vmx->ple_window != old)
5979                 vmx->ple_window_dirty = true;
5980
5981         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5982 }
5983
5984 /*
5985  * ple_window_actual_max is computed to be one grow_ple_window() below
5986  * ple_window_max. (See __grow_ple_window for the reason.)
5987  * This prevents overflows, because ple_window_max is int.
5988  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5989  * this process.
5990  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5991  */
5992 static void update_ple_window_actual_max(void)
5993 {
5994         ple_window_actual_max =
5995                         __shrink_ple_window(max(ple_window_max, ple_window),
5996                                             ple_window_grow, INT_MIN);
5997 }
5998
5999 static __init int hardware_setup(void)
6000 {
6001         int r = -ENOMEM, i, msr;
6002
6003         rdmsrl_safe(MSR_EFER, &host_efer);
6004
6005         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6006                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6007
6008         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6009         if (!vmx_io_bitmap_a)
6010                 return r;
6011
6012         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6013         if (!vmx_io_bitmap_b)
6014                 goto out;
6015
6016         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6017         if (!vmx_msr_bitmap_legacy)
6018                 goto out1;
6019
6020         vmx_msr_bitmap_legacy_x2apic =
6021                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6022         if (!vmx_msr_bitmap_legacy_x2apic)
6023                 goto out2;
6024
6025         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6026         if (!vmx_msr_bitmap_longmode)
6027                 goto out3;
6028
6029         vmx_msr_bitmap_longmode_x2apic =
6030                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6031         if (!vmx_msr_bitmap_longmode_x2apic)
6032                 goto out4;
6033
6034         if (nested) {
6035                 vmx_msr_bitmap_nested =
6036                         (unsigned long *)__get_free_page(GFP_KERNEL);
6037                 if (!vmx_msr_bitmap_nested)
6038                         goto out5;
6039         }
6040
6041         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6042         if (!vmx_vmread_bitmap)
6043                 goto out6;
6044
6045         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6046         if (!vmx_vmwrite_bitmap)
6047                 goto out7;
6048
6049         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6050         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6051
6052         /*
6053          * Allow direct access to the PC debug port (it is often used for I/O
6054          * delays, but the vmexits simply slow things down).
6055          */
6056         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6057         clear_bit(0x80, vmx_io_bitmap_a);
6058
6059         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6060
6061         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6062         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6063         if (nested)
6064                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6065
6066         if (setup_vmcs_config(&vmcs_config) < 0) {
6067                 r = -EIO;
6068                 goto out8;
6069         }
6070
6071         if (boot_cpu_has(X86_FEATURE_NX))
6072                 kvm_enable_efer_bits(EFER_NX);
6073
6074         if (!cpu_has_vmx_vpid())
6075                 enable_vpid = 0;
6076         if (!cpu_has_vmx_shadow_vmcs())
6077                 enable_shadow_vmcs = 0;
6078         if (enable_shadow_vmcs)
6079                 init_vmcs_shadow_fields();
6080
6081         if (!cpu_has_vmx_ept() ||
6082             !cpu_has_vmx_ept_4levels()) {
6083                 enable_ept = 0;
6084                 enable_unrestricted_guest = 0;
6085                 enable_ept_ad_bits = 0;
6086         }
6087
6088         if (!cpu_has_vmx_ept_ad_bits())
6089                 enable_ept_ad_bits = 0;
6090
6091         if (!cpu_has_vmx_unrestricted_guest())
6092                 enable_unrestricted_guest = 0;
6093
6094         if (!cpu_has_vmx_flexpriority())
6095                 flexpriority_enabled = 0;
6096
6097         /*
6098          * set_apic_access_page_addr() is used to reload apic access
6099          * page upon invalidation.  No need to do anything if not
6100          * using the APIC_ACCESS_ADDR VMCS field.
6101          */
6102         if (!flexpriority_enabled)
6103                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6104
6105         if (!cpu_has_vmx_tpr_shadow())
6106                 kvm_x86_ops->update_cr8_intercept = NULL;
6107
6108         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6109                 kvm_disable_largepages();
6110
6111         if (!cpu_has_vmx_ple())
6112                 ple_gap = 0;
6113
6114         if (!cpu_has_vmx_apicv())
6115                 enable_apicv = 0;
6116
6117         if (enable_apicv)
6118                 kvm_x86_ops->update_cr8_intercept = NULL;
6119         else {
6120                 kvm_x86_ops->hwapic_irr_update = NULL;
6121                 kvm_x86_ops->hwapic_isr_update = NULL;
6122                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6123                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6124         }
6125
6126         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6127         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6128         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6129         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6130         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6131         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6132         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6133
6134         memcpy(vmx_msr_bitmap_legacy_x2apic,
6135                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6136         memcpy(vmx_msr_bitmap_longmode_x2apic,
6137                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6138
6139         if (enable_apicv) {
6140                 for (msr = 0x800; msr <= 0x8ff; msr++)
6141                         vmx_disable_intercept_msr_read_x2apic(msr);
6142
6143                 /* According SDM, in x2apic mode, the whole id reg is used.
6144                  * But in KVM, it only use the highest eight bits. Need to
6145                  * intercept it */
6146                 vmx_enable_intercept_msr_read_x2apic(0x802);
6147                 /* TMCCT */
6148                 vmx_enable_intercept_msr_read_x2apic(0x839);
6149                 /* TPR */
6150                 vmx_disable_intercept_msr_write_x2apic(0x808);
6151                 /* EOI */
6152                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6153                 /* SELF-IPI */
6154                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6155         }
6156
6157         if (enable_ept) {
6158                 kvm_mmu_set_mask_ptes(0ull,
6159                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6160                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6161                         0ull, VMX_EPT_EXECUTABLE_MASK);
6162                 ept_set_mmio_spte_mask();
6163                 kvm_enable_tdp();
6164         } else
6165                 kvm_disable_tdp();
6166
6167         update_ple_window_actual_max();
6168
6169         /*
6170          * Only enable PML when hardware supports PML feature, and both EPT
6171          * and EPT A/D bit features are enabled -- PML depends on them to work.
6172          */
6173         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6174                 enable_pml = 0;
6175
6176         if (!enable_pml) {
6177                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6178                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6179                 kvm_x86_ops->flush_log_dirty = NULL;
6180                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6181         }
6182
6183         return alloc_kvm_area();
6184
6185 out8:
6186         free_page((unsigned long)vmx_vmwrite_bitmap);
6187 out7:
6188         free_page((unsigned long)vmx_vmread_bitmap);
6189 out6:
6190         if (nested)
6191                 free_page((unsigned long)vmx_msr_bitmap_nested);
6192 out5:
6193         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6194 out4:
6195         free_page((unsigned long)vmx_msr_bitmap_longmode);
6196 out3:
6197         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6198 out2:
6199         free_page((unsigned long)vmx_msr_bitmap_legacy);
6200 out1:
6201         free_page((unsigned long)vmx_io_bitmap_b);
6202 out:
6203         free_page((unsigned long)vmx_io_bitmap_a);
6204
6205     return r;
6206 }
6207
6208 static __exit void hardware_unsetup(void)
6209 {
6210         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6211         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6212         free_page((unsigned long)vmx_msr_bitmap_legacy);
6213         free_page((unsigned long)vmx_msr_bitmap_longmode);
6214         free_page((unsigned long)vmx_io_bitmap_b);
6215         free_page((unsigned long)vmx_io_bitmap_a);
6216         free_page((unsigned long)vmx_vmwrite_bitmap);
6217         free_page((unsigned long)vmx_vmread_bitmap);
6218         if (nested)
6219                 free_page((unsigned long)vmx_msr_bitmap_nested);
6220
6221         free_kvm_area();
6222 }
6223
6224 /*
6225  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6226  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6227  */
6228 static int handle_pause(struct kvm_vcpu *vcpu)
6229 {
6230         if (ple_gap)
6231                 grow_ple_window(vcpu);
6232
6233         skip_emulated_instruction(vcpu);
6234         kvm_vcpu_on_spin(vcpu);
6235
6236         return 1;
6237 }
6238
6239 static int handle_nop(struct kvm_vcpu *vcpu)
6240 {
6241         skip_emulated_instruction(vcpu);
6242         return 1;
6243 }
6244
6245 static int handle_mwait(struct kvm_vcpu *vcpu)
6246 {
6247         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6248         return handle_nop(vcpu);
6249 }
6250
6251 static int handle_monitor(struct kvm_vcpu *vcpu)
6252 {
6253         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6254         return handle_nop(vcpu);
6255 }
6256
6257 /*
6258  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6259  * We could reuse a single VMCS for all the L2 guests, but we also want the
6260  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6261  * allows keeping them loaded on the processor, and in the future will allow
6262  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6263  * every entry if they never change.
6264  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6265  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6266  *
6267  * The following functions allocate and free a vmcs02 in this pool.
6268  */
6269
6270 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6271 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6272 {
6273         struct vmcs02_list *item;
6274         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6275                 if (item->vmptr == vmx->nested.current_vmptr) {
6276                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6277                         return &item->vmcs02;
6278                 }
6279
6280         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6281                 /* Recycle the least recently used VMCS. */
6282                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6283                         struct vmcs02_list, list);
6284                 item->vmptr = vmx->nested.current_vmptr;
6285                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6286                 return &item->vmcs02;
6287         }
6288
6289         /* Create a new VMCS */
6290         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6291         if (!item)
6292                 return NULL;
6293         item->vmcs02.vmcs = alloc_vmcs();
6294         if (!item->vmcs02.vmcs) {
6295                 kfree(item);
6296                 return NULL;
6297         }
6298         loaded_vmcs_init(&item->vmcs02);
6299         item->vmptr = vmx->nested.current_vmptr;
6300         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6301         vmx->nested.vmcs02_num++;
6302         return &item->vmcs02;
6303 }
6304
6305 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6306 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6307 {
6308         struct vmcs02_list *item;
6309         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6310                 if (item->vmptr == vmptr) {
6311                         free_loaded_vmcs(&item->vmcs02);
6312                         list_del(&item->list);
6313                         kfree(item);
6314                         vmx->nested.vmcs02_num--;
6315                         return;
6316                 }
6317 }
6318
6319 /*
6320  * Free all VMCSs saved for this vcpu, except the one pointed by
6321  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6322  * must be &vmx->vmcs01.
6323  */
6324 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6325 {
6326         struct vmcs02_list *item, *n;
6327
6328         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6329         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6330                 /*
6331                  * Something will leak if the above WARN triggers.  Better than
6332                  * a use-after-free.
6333                  */
6334                 if (vmx->loaded_vmcs == &item->vmcs02)
6335                         continue;
6336
6337                 free_loaded_vmcs(&item->vmcs02);
6338                 list_del(&item->list);
6339                 kfree(item);
6340                 vmx->nested.vmcs02_num--;
6341         }
6342 }
6343
6344 /*
6345  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6346  * set the success or error code of an emulated VMX instruction, as specified
6347  * by Vol 2B, VMX Instruction Reference, "Conventions".
6348  */
6349 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6350 {
6351         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6352                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6353                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6354 }
6355
6356 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6357 {
6358         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6359                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6360                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6361                         | X86_EFLAGS_CF);
6362 }
6363
6364 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6365                                         u32 vm_instruction_error)
6366 {
6367         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6368                 /*
6369                  * failValid writes the error number to the current VMCS, which
6370                  * can't be done there isn't a current VMCS.
6371                  */
6372                 nested_vmx_failInvalid(vcpu);
6373                 return;
6374         }
6375         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6376                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6377                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6378                         | X86_EFLAGS_ZF);
6379         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6380         /*
6381          * We don't need to force a shadow sync because
6382          * VM_INSTRUCTION_ERROR is not shadowed
6383          */
6384 }
6385
6386 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6387 {
6388         /* TODO: not to reset guest simply here. */
6389         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6390         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6391 }
6392
6393 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6394 {
6395         struct vcpu_vmx *vmx =
6396                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6397
6398         vmx->nested.preemption_timer_expired = true;
6399         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6400         kvm_vcpu_kick(&vmx->vcpu);
6401
6402         return HRTIMER_NORESTART;
6403 }
6404
6405 /*
6406  * Decode the memory-address operand of a vmx instruction, as recorded on an
6407  * exit caused by such an instruction (run by a guest hypervisor).
6408  * On success, returns 0. When the operand is invalid, returns 1 and throws
6409  * #UD or #GP.
6410  */
6411 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6412                                  unsigned long exit_qualification,
6413                                  u32 vmx_instruction_info, gva_t *ret)
6414 {
6415         /*
6416          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6417          * Execution", on an exit, vmx_instruction_info holds most of the
6418          * addressing components of the operand. Only the displacement part
6419          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6420          * For how an actual address is calculated from all these components,
6421          * refer to Vol. 1, "Operand Addressing".
6422          */
6423         int  scaling = vmx_instruction_info & 3;
6424         int  addr_size = (vmx_instruction_info >> 7) & 7;
6425         bool is_reg = vmx_instruction_info & (1u << 10);
6426         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6427         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6428         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6429         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6430         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6431
6432         if (is_reg) {
6433                 kvm_queue_exception(vcpu, UD_VECTOR);
6434                 return 1;
6435         }
6436
6437         /* Addr = segment_base + offset */
6438         /* offset = base + [index * scale] + displacement */
6439         *ret = vmx_get_segment_base(vcpu, seg_reg);
6440         if (base_is_valid)
6441                 *ret += kvm_register_read(vcpu, base_reg);
6442         if (index_is_valid)
6443                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6444         *ret += exit_qualification; /* holds the displacement */
6445
6446         if (addr_size == 1) /* 32 bit */
6447                 *ret &= 0xffffffff;
6448
6449         /*
6450          * TODO: throw #GP (and return 1) in various cases that the VM*
6451          * instructions require it - e.g., offset beyond segment limit,
6452          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6453          * address, and so on. Currently these are not checked.
6454          */
6455         return 0;
6456 }
6457
6458 /*
6459  * This function performs the various checks including
6460  * - if it's 4KB aligned
6461  * - No bits beyond the physical address width are set
6462  * - Returns 0 on success or else 1
6463  * (Intel SDM Section 30.3)
6464  */
6465 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6466                                   gpa_t *vmpointer)
6467 {
6468         gva_t gva;
6469         gpa_t vmptr;
6470         struct x86_exception e;
6471         struct page *page;
6472         struct vcpu_vmx *vmx = to_vmx(vcpu);
6473         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6474
6475         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6476                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6477                 return 1;
6478
6479         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6480                                 sizeof(vmptr), &e)) {
6481                 kvm_inject_page_fault(vcpu, &e);
6482                 return 1;
6483         }
6484
6485         switch (exit_reason) {
6486         case EXIT_REASON_VMON:
6487                 /*
6488                  * SDM 3: 24.11.5
6489                  * The first 4 bytes of VMXON region contain the supported
6490                  * VMCS revision identifier
6491                  *
6492                  * Note - IA32_VMX_BASIC[48] will never be 1
6493                  * for the nested case;
6494                  * which replaces physical address width with 32
6495                  *
6496                  */
6497                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6498                         nested_vmx_failInvalid(vcpu);
6499                         skip_emulated_instruction(vcpu);
6500                         return 1;
6501                 }
6502
6503                 page = nested_get_page(vcpu, vmptr);
6504                 if (page == NULL ||
6505                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6506                         nested_vmx_failInvalid(vcpu);
6507                         kunmap(page);
6508                         skip_emulated_instruction(vcpu);
6509                         return 1;
6510                 }
6511                 kunmap(page);
6512                 vmx->nested.vmxon_ptr = vmptr;
6513                 break;
6514         case EXIT_REASON_VMCLEAR:
6515                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6516                         nested_vmx_failValid(vcpu,
6517                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6518                         skip_emulated_instruction(vcpu);
6519                         return 1;
6520                 }
6521
6522                 if (vmptr == vmx->nested.vmxon_ptr) {
6523                         nested_vmx_failValid(vcpu,
6524                                              VMXERR_VMCLEAR_VMXON_POINTER);
6525                         skip_emulated_instruction(vcpu);
6526                         return 1;
6527                 }
6528                 break;
6529         case EXIT_REASON_VMPTRLD:
6530                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6531                         nested_vmx_failValid(vcpu,
6532                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6533                         skip_emulated_instruction(vcpu);
6534                         return 1;
6535                 }
6536
6537                 if (vmptr == vmx->nested.vmxon_ptr) {
6538                         nested_vmx_failValid(vcpu,
6539                                              VMXERR_VMCLEAR_VMXON_POINTER);
6540                         skip_emulated_instruction(vcpu);
6541                         return 1;
6542                 }
6543                 break;
6544         default:
6545                 return 1; /* shouldn't happen */
6546         }
6547
6548         if (vmpointer)
6549                 *vmpointer = vmptr;
6550         return 0;
6551 }
6552
6553 /*
6554  * Emulate the VMXON instruction.
6555  * Currently, we just remember that VMX is active, and do not save or even
6556  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6557  * do not currently need to store anything in that guest-allocated memory
6558  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6559  * argument is different from the VMXON pointer (which the spec says they do).
6560  */
6561 static int handle_vmon(struct kvm_vcpu *vcpu)
6562 {
6563         struct kvm_segment cs;
6564         struct vcpu_vmx *vmx = to_vmx(vcpu);
6565         struct vmcs *shadow_vmcs;
6566         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6567                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6568
6569         /* The Intel VMX Instruction Reference lists a bunch of bits that
6570          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6571          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6572          * Otherwise, we should fail with #UD. We test these now:
6573          */
6574         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6575             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6576             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6577                 kvm_queue_exception(vcpu, UD_VECTOR);
6578                 return 1;
6579         }
6580
6581         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6582         if (is_long_mode(vcpu) && !cs.l) {
6583                 kvm_queue_exception(vcpu, UD_VECTOR);
6584                 return 1;
6585         }
6586
6587         if (vmx_get_cpl(vcpu)) {
6588                 kvm_inject_gp(vcpu, 0);
6589                 return 1;
6590         }
6591
6592         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6593                 return 1;
6594
6595         if (vmx->nested.vmxon) {
6596                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6597                 skip_emulated_instruction(vcpu);
6598                 return 1;
6599         }
6600
6601         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6602                         != VMXON_NEEDED_FEATURES) {
6603                 kvm_inject_gp(vcpu, 0);
6604                 return 1;
6605         }
6606
6607         if (enable_shadow_vmcs) {
6608                 shadow_vmcs = alloc_vmcs();
6609                 if (!shadow_vmcs)
6610                         return -ENOMEM;
6611                 /* mark vmcs as shadow */
6612                 shadow_vmcs->revision_id |= (1u << 31);
6613                 /* init shadow vmcs */
6614                 vmcs_clear(shadow_vmcs);
6615                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6616         }
6617
6618         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6619         vmx->nested.vmcs02_num = 0;
6620
6621         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6622                      HRTIMER_MODE_REL);
6623         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6624
6625         vmx->nested.vmxon = true;
6626
6627         skip_emulated_instruction(vcpu);
6628         nested_vmx_succeed(vcpu);
6629         return 1;
6630 }
6631
6632 /*
6633  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6634  * for running VMX instructions (except VMXON, whose prerequisites are
6635  * slightly different). It also specifies what exception to inject otherwise.
6636  */
6637 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6638 {
6639         struct kvm_segment cs;
6640         struct vcpu_vmx *vmx = to_vmx(vcpu);
6641
6642         if (!vmx->nested.vmxon) {
6643                 kvm_queue_exception(vcpu, UD_VECTOR);
6644                 return 0;
6645         }
6646
6647         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6648         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6649             (is_long_mode(vcpu) && !cs.l)) {
6650                 kvm_queue_exception(vcpu, UD_VECTOR);
6651                 return 0;
6652         }
6653
6654         if (vmx_get_cpl(vcpu)) {
6655                 kvm_inject_gp(vcpu, 0);
6656                 return 0;
6657         }
6658
6659         return 1;
6660 }
6661
6662 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6663 {
6664         u32 exec_control;
6665         if (vmx->nested.current_vmptr == -1ull)
6666                 return;
6667
6668         /* current_vmptr and current_vmcs12 are always set/reset together */
6669         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6670                 return;
6671
6672         if (enable_shadow_vmcs) {
6673                 /* copy to memory all shadowed fields in case
6674                    they were modified */
6675                 copy_shadow_to_vmcs12(vmx);
6676                 vmx->nested.sync_shadow_vmcs = false;
6677                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6678                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6679                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6680                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6681         }
6682         vmx->nested.posted_intr_nv = -1;
6683         kunmap(vmx->nested.current_vmcs12_page);
6684         nested_release_page(vmx->nested.current_vmcs12_page);
6685         vmx->nested.current_vmptr = -1ull;
6686         vmx->nested.current_vmcs12 = NULL;
6687 }
6688
6689 /*
6690  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6691  * just stops using VMX.
6692  */
6693 static void free_nested(struct vcpu_vmx *vmx)
6694 {
6695         if (!vmx->nested.vmxon)
6696                 return;
6697
6698         vmx->nested.vmxon = false;
6699         nested_release_vmcs12(vmx);
6700         if (enable_shadow_vmcs)
6701                 free_vmcs(vmx->nested.current_shadow_vmcs);
6702         /* Unpin physical memory we referred to in current vmcs02 */
6703         if (vmx->nested.apic_access_page) {
6704                 nested_release_page(vmx->nested.apic_access_page);
6705                 vmx->nested.apic_access_page = NULL;
6706         }
6707         if (vmx->nested.virtual_apic_page) {
6708                 nested_release_page(vmx->nested.virtual_apic_page);
6709                 vmx->nested.virtual_apic_page = NULL;
6710         }
6711         if (vmx->nested.pi_desc_page) {
6712                 kunmap(vmx->nested.pi_desc_page);
6713                 nested_release_page(vmx->nested.pi_desc_page);
6714                 vmx->nested.pi_desc_page = NULL;
6715                 vmx->nested.pi_desc = NULL;
6716         }
6717
6718         nested_free_all_saved_vmcss(vmx);
6719 }
6720
6721 /* Emulate the VMXOFF instruction */
6722 static int handle_vmoff(struct kvm_vcpu *vcpu)
6723 {
6724         if (!nested_vmx_check_permission(vcpu))
6725                 return 1;
6726         free_nested(to_vmx(vcpu));
6727         skip_emulated_instruction(vcpu);
6728         nested_vmx_succeed(vcpu);
6729         return 1;
6730 }
6731
6732 /* Emulate the VMCLEAR instruction */
6733 static int handle_vmclear(struct kvm_vcpu *vcpu)
6734 {
6735         struct vcpu_vmx *vmx = to_vmx(vcpu);
6736         gpa_t vmptr;
6737         struct vmcs12 *vmcs12;
6738         struct page *page;
6739
6740         if (!nested_vmx_check_permission(vcpu))
6741                 return 1;
6742
6743         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6744                 return 1;
6745
6746         if (vmptr == vmx->nested.current_vmptr)
6747                 nested_release_vmcs12(vmx);
6748
6749         page = nested_get_page(vcpu, vmptr);
6750         if (page == NULL) {
6751                 /*
6752                  * For accurate processor emulation, VMCLEAR beyond available
6753                  * physical memory should do nothing at all. However, it is
6754                  * possible that a nested vmx bug, not a guest hypervisor bug,
6755                  * resulted in this case, so let's shut down before doing any
6756                  * more damage:
6757                  */
6758                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6759                 return 1;
6760         }
6761         vmcs12 = kmap(page);
6762         vmcs12->launch_state = 0;
6763         kunmap(page);
6764         nested_release_page(page);
6765
6766         nested_free_vmcs02(vmx, vmptr);
6767
6768         skip_emulated_instruction(vcpu);
6769         nested_vmx_succeed(vcpu);
6770         return 1;
6771 }
6772
6773 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6774
6775 /* Emulate the VMLAUNCH instruction */
6776 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6777 {
6778         return nested_vmx_run(vcpu, true);
6779 }
6780
6781 /* Emulate the VMRESUME instruction */
6782 static int handle_vmresume(struct kvm_vcpu *vcpu)
6783 {
6784
6785         return nested_vmx_run(vcpu, false);
6786 }
6787
6788 enum vmcs_field_type {
6789         VMCS_FIELD_TYPE_U16 = 0,
6790         VMCS_FIELD_TYPE_U64 = 1,
6791         VMCS_FIELD_TYPE_U32 = 2,
6792         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6793 };
6794
6795 static inline int vmcs_field_type(unsigned long field)
6796 {
6797         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6798                 return VMCS_FIELD_TYPE_U32;
6799         return (field >> 13) & 0x3 ;
6800 }
6801
6802 static inline int vmcs_field_readonly(unsigned long field)
6803 {
6804         return (((field >> 10) & 0x3) == 1);
6805 }
6806
6807 /*
6808  * Read a vmcs12 field. Since these can have varying lengths and we return
6809  * one type, we chose the biggest type (u64) and zero-extend the return value
6810  * to that size. Note that the caller, handle_vmread, might need to use only
6811  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6812  * 64-bit fields are to be returned).
6813  */
6814 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6815                                   unsigned long field, u64 *ret)
6816 {
6817         short offset = vmcs_field_to_offset(field);
6818         char *p;
6819
6820         if (offset < 0)
6821                 return offset;
6822
6823         p = ((char *)(get_vmcs12(vcpu))) + offset;
6824
6825         switch (vmcs_field_type(field)) {
6826         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6827                 *ret = *((natural_width *)p);
6828                 return 0;
6829         case VMCS_FIELD_TYPE_U16:
6830                 *ret = *((u16 *)p);
6831                 return 0;
6832         case VMCS_FIELD_TYPE_U32:
6833                 *ret = *((u32 *)p);
6834                 return 0;
6835         case VMCS_FIELD_TYPE_U64:
6836                 *ret = *((u64 *)p);
6837                 return 0;
6838         default:
6839                 WARN_ON(1);
6840                 return -ENOENT;
6841         }
6842 }
6843
6844
6845 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6846                                    unsigned long field, u64 field_value){
6847         short offset = vmcs_field_to_offset(field);
6848         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6849         if (offset < 0)
6850                 return offset;
6851
6852         switch (vmcs_field_type(field)) {
6853         case VMCS_FIELD_TYPE_U16:
6854                 *(u16 *)p = field_value;
6855                 return 0;
6856         case VMCS_FIELD_TYPE_U32:
6857                 *(u32 *)p = field_value;
6858                 return 0;
6859         case VMCS_FIELD_TYPE_U64:
6860                 *(u64 *)p = field_value;
6861                 return 0;
6862         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6863                 *(natural_width *)p = field_value;
6864                 return 0;
6865         default:
6866                 WARN_ON(1);
6867                 return -ENOENT;
6868         }
6869
6870 }
6871
6872 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6873 {
6874         int i;
6875         unsigned long field;
6876         u64 field_value;
6877         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6878         const unsigned long *fields = shadow_read_write_fields;
6879         const int num_fields = max_shadow_read_write_fields;
6880
6881         preempt_disable();
6882
6883         vmcs_load(shadow_vmcs);
6884
6885         for (i = 0; i < num_fields; i++) {
6886                 field = fields[i];
6887                 switch (vmcs_field_type(field)) {
6888                 case VMCS_FIELD_TYPE_U16:
6889                         field_value = vmcs_read16(field);
6890                         break;
6891                 case VMCS_FIELD_TYPE_U32:
6892                         field_value = vmcs_read32(field);
6893                         break;
6894                 case VMCS_FIELD_TYPE_U64:
6895                         field_value = vmcs_read64(field);
6896                         break;
6897                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6898                         field_value = vmcs_readl(field);
6899                         break;
6900                 default:
6901                         WARN_ON(1);
6902                         continue;
6903                 }
6904                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6905         }
6906
6907         vmcs_clear(shadow_vmcs);
6908         vmcs_load(vmx->loaded_vmcs->vmcs);
6909
6910         preempt_enable();
6911 }
6912
6913 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6914 {
6915         const unsigned long *fields[] = {
6916                 shadow_read_write_fields,
6917                 shadow_read_only_fields
6918         };
6919         const int max_fields[] = {
6920                 max_shadow_read_write_fields,
6921                 max_shadow_read_only_fields
6922         };
6923         int i, q;
6924         unsigned long field;
6925         u64 field_value = 0;
6926         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6927
6928         vmcs_load(shadow_vmcs);
6929
6930         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6931                 for (i = 0; i < max_fields[q]; i++) {
6932                         field = fields[q][i];
6933                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6934
6935                         switch (vmcs_field_type(field)) {
6936                         case VMCS_FIELD_TYPE_U16:
6937                                 vmcs_write16(field, (u16)field_value);
6938                                 break;
6939                         case VMCS_FIELD_TYPE_U32:
6940                                 vmcs_write32(field, (u32)field_value);
6941                                 break;
6942                         case VMCS_FIELD_TYPE_U64:
6943                                 vmcs_write64(field, (u64)field_value);
6944                                 break;
6945                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6946                                 vmcs_writel(field, (long)field_value);
6947                                 break;
6948                         default:
6949                                 WARN_ON(1);
6950                                 break;
6951                         }
6952                 }
6953         }
6954
6955         vmcs_clear(shadow_vmcs);
6956         vmcs_load(vmx->loaded_vmcs->vmcs);
6957 }
6958
6959 /*
6960  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6961  * used before) all generate the same failure when it is missing.
6962  */
6963 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6964 {
6965         struct vcpu_vmx *vmx = to_vmx(vcpu);
6966         if (vmx->nested.current_vmptr == -1ull) {
6967                 nested_vmx_failInvalid(vcpu);
6968                 skip_emulated_instruction(vcpu);
6969                 return 0;
6970         }
6971         return 1;
6972 }
6973
6974 static int handle_vmread(struct kvm_vcpu *vcpu)
6975 {
6976         unsigned long field;
6977         u64 field_value;
6978         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6979         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6980         gva_t gva = 0;
6981
6982         if (!nested_vmx_check_permission(vcpu) ||
6983             !nested_vmx_check_vmcs12(vcpu))
6984                 return 1;
6985
6986         /* Decode instruction info and find the field to read */
6987         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6988         /* Read the field, zero-extended to a u64 field_value */
6989         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6990                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6991                 skip_emulated_instruction(vcpu);
6992                 return 1;
6993         }
6994         /*
6995          * Now copy part of this value to register or memory, as requested.
6996          * Note that the number of bits actually copied is 32 or 64 depending
6997          * on the guest's mode (32 or 64 bit), not on the given field's length.
6998          */
6999         if (vmx_instruction_info & (1u << 10)) {
7000                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7001                         field_value);
7002         } else {
7003                 if (get_vmx_mem_address(vcpu, exit_qualification,
7004                                 vmx_instruction_info, &gva))
7005                         return 1;
7006                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7007                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7008                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7009         }
7010
7011         nested_vmx_succeed(vcpu);
7012         skip_emulated_instruction(vcpu);
7013         return 1;
7014 }
7015
7016
7017 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7018 {
7019         unsigned long field;
7020         gva_t gva;
7021         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7022         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7023         /* The value to write might be 32 or 64 bits, depending on L1's long
7024          * mode, and eventually we need to write that into a field of several
7025          * possible lengths. The code below first zero-extends the value to 64
7026          * bit (field_value), and then copies only the approriate number of
7027          * bits into the vmcs12 field.
7028          */
7029         u64 field_value = 0;
7030         struct x86_exception e;
7031
7032         if (!nested_vmx_check_permission(vcpu) ||
7033             !nested_vmx_check_vmcs12(vcpu))
7034                 return 1;
7035
7036         if (vmx_instruction_info & (1u << 10))
7037                 field_value = kvm_register_readl(vcpu,
7038                         (((vmx_instruction_info) >> 3) & 0xf));
7039         else {
7040                 if (get_vmx_mem_address(vcpu, exit_qualification,
7041                                 vmx_instruction_info, &gva))
7042                         return 1;
7043                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7044                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7045                         kvm_inject_page_fault(vcpu, &e);
7046                         return 1;
7047                 }
7048         }
7049
7050
7051         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7052         if (vmcs_field_readonly(field)) {
7053                 nested_vmx_failValid(vcpu,
7054                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7055                 skip_emulated_instruction(vcpu);
7056                 return 1;
7057         }
7058
7059         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7060                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7061                 skip_emulated_instruction(vcpu);
7062                 return 1;
7063         }
7064
7065         nested_vmx_succeed(vcpu);
7066         skip_emulated_instruction(vcpu);
7067         return 1;
7068 }
7069
7070 /* Emulate the VMPTRLD instruction */
7071 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7072 {
7073         struct vcpu_vmx *vmx = to_vmx(vcpu);
7074         gpa_t vmptr;
7075         u32 exec_control;
7076
7077         if (!nested_vmx_check_permission(vcpu))
7078                 return 1;
7079
7080         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7081                 return 1;
7082
7083         if (vmx->nested.current_vmptr != vmptr) {
7084                 struct vmcs12 *new_vmcs12;
7085                 struct page *page;
7086                 page = nested_get_page(vcpu, vmptr);
7087                 if (page == NULL) {
7088                         nested_vmx_failInvalid(vcpu);
7089                         skip_emulated_instruction(vcpu);
7090                         return 1;
7091                 }
7092                 new_vmcs12 = kmap(page);
7093                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7094                         kunmap(page);
7095                         nested_release_page_clean(page);
7096                         nested_vmx_failValid(vcpu,
7097                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7098                         skip_emulated_instruction(vcpu);
7099                         return 1;
7100                 }
7101
7102                 nested_release_vmcs12(vmx);
7103                 vmx->nested.current_vmptr = vmptr;
7104                 vmx->nested.current_vmcs12 = new_vmcs12;
7105                 vmx->nested.current_vmcs12_page = page;
7106                 if (enable_shadow_vmcs) {
7107                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7108                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7109                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7110                         vmcs_write64(VMCS_LINK_POINTER,
7111                                      __pa(vmx->nested.current_shadow_vmcs));
7112                         vmx->nested.sync_shadow_vmcs = true;
7113                 }
7114         }
7115
7116         nested_vmx_succeed(vcpu);
7117         skip_emulated_instruction(vcpu);
7118         return 1;
7119 }
7120
7121 /* Emulate the VMPTRST instruction */
7122 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7123 {
7124         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7125         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7126         gva_t vmcs_gva;
7127         struct x86_exception e;
7128
7129         if (!nested_vmx_check_permission(vcpu))
7130                 return 1;
7131
7132         if (get_vmx_mem_address(vcpu, exit_qualification,
7133                         vmx_instruction_info, &vmcs_gva))
7134                 return 1;
7135         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7136         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7137                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7138                                  sizeof(u64), &e)) {
7139                 kvm_inject_page_fault(vcpu, &e);
7140                 return 1;
7141         }
7142         nested_vmx_succeed(vcpu);
7143         skip_emulated_instruction(vcpu);
7144         return 1;
7145 }
7146
7147 /* Emulate the INVEPT instruction */
7148 static int handle_invept(struct kvm_vcpu *vcpu)
7149 {
7150         struct vcpu_vmx *vmx = to_vmx(vcpu);
7151         u32 vmx_instruction_info, types;
7152         unsigned long type;
7153         gva_t gva;
7154         struct x86_exception e;
7155         struct {
7156                 u64 eptp, gpa;
7157         } operand;
7158
7159         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7160               SECONDARY_EXEC_ENABLE_EPT) ||
7161             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7162                 kvm_queue_exception(vcpu, UD_VECTOR);
7163                 return 1;
7164         }
7165
7166         if (!nested_vmx_check_permission(vcpu))
7167                 return 1;
7168
7169         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7170                 kvm_queue_exception(vcpu, UD_VECTOR);
7171                 return 1;
7172         }
7173
7174         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7175         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7176
7177         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7178
7179         if (!(types & (1UL << type))) {
7180                 nested_vmx_failValid(vcpu,
7181                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7182                 return 1;
7183         }
7184
7185         /* According to the Intel VMX instruction reference, the memory
7186          * operand is read even if it isn't needed (e.g., for type==global)
7187          */
7188         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7189                         vmx_instruction_info, &gva))
7190                 return 1;
7191         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7192                                 sizeof(operand), &e)) {
7193                 kvm_inject_page_fault(vcpu, &e);
7194                 return 1;
7195         }
7196
7197         switch (type) {
7198         case VMX_EPT_EXTENT_GLOBAL:
7199                 kvm_mmu_sync_roots(vcpu);
7200                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7201                 nested_vmx_succeed(vcpu);
7202                 break;
7203         default:
7204                 /* Trap single context invalidation invept calls */
7205                 BUG_ON(1);
7206                 break;
7207         }
7208
7209         skip_emulated_instruction(vcpu);
7210         return 1;
7211 }
7212
7213 static int handle_invvpid(struct kvm_vcpu *vcpu)
7214 {
7215         kvm_queue_exception(vcpu, UD_VECTOR);
7216         return 1;
7217 }
7218
7219 static int handle_pml_full(struct kvm_vcpu *vcpu)
7220 {
7221         unsigned long exit_qualification;
7222
7223         trace_kvm_pml_full(vcpu->vcpu_id);
7224
7225         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7226
7227         /*
7228          * PML buffer FULL happened while executing iret from NMI,
7229          * "blocked by NMI" bit has to be set before next VM entry.
7230          */
7231         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7232                         cpu_has_virtual_nmis() &&
7233                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7234                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7235                                 GUEST_INTR_STATE_NMI);
7236
7237         /*
7238          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7239          * here.., and there's no userspace involvement needed for PML.
7240          */
7241         return 1;
7242 }
7243
7244 /*
7245  * The exit handlers return 1 if the exit was handled fully and guest execution
7246  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7247  * to be done to userspace and return 0.
7248  */
7249 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7250         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7251         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7252         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7253         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7254         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7255         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7256         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7257         [EXIT_REASON_CPUID]                   = handle_cpuid,
7258         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7259         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7260         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7261         [EXIT_REASON_HLT]                     = handle_halt,
7262         [EXIT_REASON_INVD]                    = handle_invd,
7263         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7264         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7265         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7266         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7267         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7268         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7269         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7270         [EXIT_REASON_VMREAD]                  = handle_vmread,
7271         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7272         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7273         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7274         [EXIT_REASON_VMON]                    = handle_vmon,
7275         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7276         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7277         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7278         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7279         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7280         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7281         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7282         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7283         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7284         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7285         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7286         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7287         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7288         [EXIT_REASON_INVEPT]                  = handle_invept,
7289         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7290         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7291         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7292         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7293 };
7294
7295 static const int kvm_vmx_max_exit_handlers =
7296         ARRAY_SIZE(kvm_vmx_exit_handlers);
7297
7298 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7299                                        struct vmcs12 *vmcs12)
7300 {
7301         unsigned long exit_qualification;
7302         gpa_t bitmap, last_bitmap;
7303         unsigned int port;
7304         int size;
7305         u8 b;
7306
7307         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7308                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7309
7310         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7311
7312         port = exit_qualification >> 16;
7313         size = (exit_qualification & 7) + 1;
7314
7315         last_bitmap = (gpa_t)-1;
7316         b = -1;
7317
7318         while (size > 0) {
7319                 if (port < 0x8000)
7320                         bitmap = vmcs12->io_bitmap_a;
7321                 else if (port < 0x10000)
7322                         bitmap = vmcs12->io_bitmap_b;
7323                 else
7324                         return true;
7325                 bitmap += (port & 0x7fff) / 8;
7326
7327                 if (last_bitmap != bitmap)
7328                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7329                                 return true;
7330                 if (b & (1 << (port & 7)))
7331                         return true;
7332
7333                 port++;
7334                 size--;
7335                 last_bitmap = bitmap;
7336         }
7337
7338         return false;
7339 }
7340
7341 /*
7342  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7343  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7344  * disinterest in the current event (read or write a specific MSR) by using an
7345  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7346  */
7347 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7348         struct vmcs12 *vmcs12, u32 exit_reason)
7349 {
7350         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7351         gpa_t bitmap;
7352
7353         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7354                 return true;
7355
7356         /*
7357          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7358          * for the four combinations of read/write and low/high MSR numbers.
7359          * First we need to figure out which of the four to use:
7360          */
7361         bitmap = vmcs12->msr_bitmap;
7362         if (exit_reason == EXIT_REASON_MSR_WRITE)
7363                 bitmap += 2048;
7364         if (msr_index >= 0xc0000000) {
7365                 msr_index -= 0xc0000000;
7366                 bitmap += 1024;
7367         }
7368
7369         /* Then read the msr_index'th bit from this bitmap: */
7370         if (msr_index < 1024*8) {
7371                 unsigned char b;
7372                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7373                         return true;
7374                 return 1 & (b >> (msr_index & 7));
7375         } else
7376                 return true; /* let L1 handle the wrong parameter */
7377 }
7378
7379 /*
7380  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7381  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7382  * intercept (via guest_host_mask etc.) the current event.
7383  */
7384 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7385         struct vmcs12 *vmcs12)
7386 {
7387         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7388         int cr = exit_qualification & 15;
7389         int reg = (exit_qualification >> 8) & 15;
7390         unsigned long val = kvm_register_readl(vcpu, reg);
7391
7392         switch ((exit_qualification >> 4) & 3) {
7393         case 0: /* mov to cr */
7394                 switch (cr) {
7395                 case 0:
7396                         if (vmcs12->cr0_guest_host_mask &
7397                             (val ^ vmcs12->cr0_read_shadow))
7398                                 return true;
7399                         break;
7400                 case 3:
7401                         if ((vmcs12->cr3_target_count >= 1 &&
7402                                         vmcs12->cr3_target_value0 == val) ||
7403                                 (vmcs12->cr3_target_count >= 2 &&
7404                                         vmcs12->cr3_target_value1 == val) ||
7405                                 (vmcs12->cr3_target_count >= 3 &&
7406                                         vmcs12->cr3_target_value2 == val) ||
7407                                 (vmcs12->cr3_target_count >= 4 &&
7408                                         vmcs12->cr3_target_value3 == val))
7409                                 return false;
7410                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7411                                 return true;
7412                         break;
7413                 case 4:
7414                         if (vmcs12->cr4_guest_host_mask &
7415                             (vmcs12->cr4_read_shadow ^ val))
7416                                 return true;
7417                         break;
7418                 case 8:
7419                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7420                                 return true;
7421                         break;
7422                 }
7423                 break;
7424         case 2: /* clts */
7425                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7426                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7427                         return true;
7428                 break;
7429         case 1: /* mov from cr */
7430                 switch (cr) {
7431                 case 3:
7432                         if (vmcs12->cpu_based_vm_exec_control &
7433                             CPU_BASED_CR3_STORE_EXITING)
7434                                 return true;
7435                         break;
7436                 case 8:
7437                         if (vmcs12->cpu_based_vm_exec_control &
7438                             CPU_BASED_CR8_STORE_EXITING)
7439                                 return true;
7440                         break;
7441                 }
7442                 break;
7443         case 3: /* lmsw */
7444                 /*
7445                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7446                  * cr0. Other attempted changes are ignored, with no exit.
7447                  */
7448                 if (vmcs12->cr0_guest_host_mask & 0xe &
7449                     (val ^ vmcs12->cr0_read_shadow))
7450                         return true;
7451                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7452                     !(vmcs12->cr0_read_shadow & 0x1) &&
7453                     (val & 0x1))
7454                         return true;
7455                 break;
7456         }
7457         return false;
7458 }
7459
7460 /*
7461  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7462  * should handle it ourselves in L0 (and then continue L2). Only call this
7463  * when in is_guest_mode (L2).
7464  */
7465 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7466 {
7467         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7468         struct vcpu_vmx *vmx = to_vmx(vcpu);
7469         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7470         u32 exit_reason = vmx->exit_reason;
7471
7472         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7473                                 vmcs_readl(EXIT_QUALIFICATION),
7474                                 vmx->idt_vectoring_info,
7475                                 intr_info,
7476                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7477                                 KVM_ISA_VMX);
7478
7479         if (vmx->nested.nested_run_pending)
7480                 return false;
7481
7482         if (unlikely(vmx->fail)) {
7483                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7484                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7485                 return true;
7486         }
7487
7488         switch (exit_reason) {
7489         case EXIT_REASON_EXCEPTION_NMI:
7490                 if (!is_exception(intr_info))
7491                         return false;
7492                 else if (is_page_fault(intr_info))
7493                         return enable_ept;
7494                 else if (is_no_device(intr_info) &&
7495                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7496                         return false;
7497                 return vmcs12->exception_bitmap &
7498                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7499         case EXIT_REASON_EXTERNAL_INTERRUPT:
7500                 return false;
7501         case EXIT_REASON_TRIPLE_FAULT:
7502                 return true;
7503         case EXIT_REASON_PENDING_INTERRUPT:
7504                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7505         case EXIT_REASON_NMI_WINDOW:
7506                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7507         case EXIT_REASON_TASK_SWITCH:
7508                 return true;
7509         case EXIT_REASON_CPUID:
7510                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7511                         return false;
7512                 return true;
7513         case EXIT_REASON_HLT:
7514                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7515         case EXIT_REASON_INVD:
7516                 return true;
7517         case EXIT_REASON_INVLPG:
7518                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7519         case EXIT_REASON_RDPMC:
7520                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7521         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7522                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7523         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7524         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7525         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7526         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7527         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7528         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7529                 /*
7530                  * VMX instructions trap unconditionally. This allows L1 to
7531                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7532                  */
7533                 return true;
7534         case EXIT_REASON_CR_ACCESS:
7535                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7536         case EXIT_REASON_DR_ACCESS:
7537                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7538         case EXIT_REASON_IO_INSTRUCTION:
7539                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7540         case EXIT_REASON_MSR_READ:
7541         case EXIT_REASON_MSR_WRITE:
7542                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7543         case EXIT_REASON_INVALID_STATE:
7544                 return true;
7545         case EXIT_REASON_MWAIT_INSTRUCTION:
7546                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7547         case EXIT_REASON_MONITOR_INSTRUCTION:
7548                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7549         case EXIT_REASON_PAUSE_INSTRUCTION:
7550                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7551                         nested_cpu_has2(vmcs12,
7552                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7553         case EXIT_REASON_MCE_DURING_VMENTRY:
7554                 return false;
7555         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7556                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7557         case EXIT_REASON_APIC_ACCESS:
7558                 return nested_cpu_has2(vmcs12,
7559                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7560         case EXIT_REASON_APIC_WRITE:
7561         case EXIT_REASON_EOI_INDUCED:
7562                 /* apic_write and eoi_induced should exit unconditionally. */
7563                 return true;
7564         case EXIT_REASON_EPT_VIOLATION:
7565                 /*
7566                  * L0 always deals with the EPT violation. If nested EPT is
7567                  * used, and the nested mmu code discovers that the address is
7568                  * missing in the guest EPT table (EPT12), the EPT violation
7569                  * will be injected with nested_ept_inject_page_fault()
7570                  */
7571                 return false;
7572         case EXIT_REASON_EPT_MISCONFIG:
7573                 /*
7574                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7575                  * table (shadow on EPT) or a merged EPT table that L0 built
7576                  * (EPT on EPT). So any problems with the structure of the
7577                  * table is L0's fault.
7578                  */
7579                 return false;
7580         case EXIT_REASON_WBINVD:
7581                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7582         case EXIT_REASON_XSETBV:
7583                 return true;
7584         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7585                 /*
7586                  * This should never happen, since it is not possible to
7587                  * set XSS to a non-zero value---neither in L1 nor in L2.
7588                  * If if it were, XSS would have to be checked against
7589                  * the XSS exit bitmap in vmcs12.
7590                  */
7591                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7592         default:
7593                 return true;
7594         }
7595 }
7596
7597 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7598 {
7599         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7600         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7601 }
7602
7603 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7604 {
7605         struct page *pml_pg;
7606         u32 exec_control;
7607
7608         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7609         if (!pml_pg)
7610                 return -ENOMEM;
7611
7612         vmx->pml_pg = pml_pg;
7613
7614         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7615         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7616
7617         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7618         exec_control |= SECONDARY_EXEC_ENABLE_PML;
7619         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7620
7621         return 0;
7622 }
7623
7624 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7625 {
7626         u32 exec_control;
7627
7628         ASSERT(vmx->pml_pg);
7629         __free_page(vmx->pml_pg);
7630         vmx->pml_pg = NULL;
7631
7632         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7633         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7634         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7635 }
7636
7637 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7638 {
7639         struct kvm *kvm = vmx->vcpu.kvm;
7640         u64 *pml_buf;
7641         u16 pml_idx;
7642
7643         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7644
7645         /* Do nothing if PML buffer is empty */
7646         if (pml_idx == (PML_ENTITY_NUM - 1))
7647                 return;
7648
7649         /* PML index always points to next available PML buffer entity */
7650         if (pml_idx >= PML_ENTITY_NUM)
7651                 pml_idx = 0;
7652         else
7653                 pml_idx++;
7654
7655         pml_buf = page_address(vmx->pml_pg);
7656         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7657                 u64 gpa;
7658
7659                 gpa = pml_buf[pml_idx];
7660                 WARN_ON(gpa & (PAGE_SIZE - 1));
7661                 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7662         }
7663
7664         /* reset PML index */
7665         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7666 }
7667
7668 /*
7669  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7670  * Called before reporting dirty_bitmap to userspace.
7671  */
7672 static void kvm_flush_pml_buffers(struct kvm *kvm)
7673 {
7674         int i;
7675         struct kvm_vcpu *vcpu;
7676         /*
7677          * We only need to kick vcpu out of guest mode here, as PML buffer
7678          * is flushed at beginning of all VMEXITs, and it's obvious that only
7679          * vcpus running in guest are possible to have unflushed GPAs in PML
7680          * buffer.
7681          */
7682         kvm_for_each_vcpu(i, vcpu, kvm)
7683                 kvm_vcpu_kick(vcpu);
7684 }
7685
7686 /*
7687  * The guest has exited.  See if we can fix it or if we need userspace
7688  * assistance.
7689  */
7690 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7691 {
7692         struct vcpu_vmx *vmx = to_vmx(vcpu);
7693         u32 exit_reason = vmx->exit_reason;
7694         u32 vectoring_info = vmx->idt_vectoring_info;
7695
7696         /*
7697          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7698          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7699          * querying dirty_bitmap, we only need to kick all vcpus out of guest
7700          * mode as if vcpus is in root mode, the PML buffer must has been
7701          * flushed already.
7702          */
7703         if (enable_pml)
7704                 vmx_flush_pml_buffer(vmx);
7705
7706         /* If guest state is invalid, start emulating */
7707         if (vmx->emulation_required)
7708                 return handle_invalid_guest_state(vcpu);
7709
7710         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7711                 nested_vmx_vmexit(vcpu, exit_reason,
7712                                   vmcs_read32(VM_EXIT_INTR_INFO),
7713                                   vmcs_readl(EXIT_QUALIFICATION));
7714                 return 1;
7715         }
7716
7717         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7718                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7719                 vcpu->run->fail_entry.hardware_entry_failure_reason
7720                         = exit_reason;
7721                 return 0;
7722         }
7723
7724         if (unlikely(vmx->fail)) {
7725                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7726                 vcpu->run->fail_entry.hardware_entry_failure_reason
7727                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7728                 return 0;
7729         }
7730
7731         /*
7732          * Note:
7733          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7734          * delivery event since it indicates guest is accessing MMIO.
7735          * The vm-exit can be triggered again after return to guest that
7736          * will cause infinite loop.
7737          */
7738         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7739                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7740                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7741                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7742                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7743                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7744                 vcpu->run->internal.ndata = 2;
7745                 vcpu->run->internal.data[0] = vectoring_info;
7746                 vcpu->run->internal.data[1] = exit_reason;
7747                 return 0;
7748         }
7749
7750         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7751             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7752                                         get_vmcs12(vcpu))))) {
7753                 if (vmx_interrupt_allowed(vcpu)) {
7754                         vmx->soft_vnmi_blocked = 0;
7755                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7756                            vcpu->arch.nmi_pending) {
7757                         /*
7758                          * This CPU don't support us in finding the end of an
7759                          * NMI-blocked window if the guest runs with IRQs
7760                          * disabled. So we pull the trigger after 1 s of
7761                          * futile waiting, but inform the user about this.
7762                          */
7763                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7764                                "state on VCPU %d after 1 s timeout\n",
7765                                __func__, vcpu->vcpu_id);
7766                         vmx->soft_vnmi_blocked = 0;
7767                 }
7768         }
7769
7770         if (exit_reason < kvm_vmx_max_exit_handlers
7771             && kvm_vmx_exit_handlers[exit_reason])
7772                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7773         else {
7774                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7775                 kvm_queue_exception(vcpu, UD_VECTOR);
7776                 return 1;
7777         }
7778 }
7779
7780 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7781 {
7782         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7783
7784         if (is_guest_mode(vcpu) &&
7785                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7786                 return;
7787
7788         if (irr == -1 || tpr < irr) {
7789                 vmcs_write32(TPR_THRESHOLD, 0);
7790                 return;
7791         }
7792
7793         vmcs_write32(TPR_THRESHOLD, irr);
7794 }
7795
7796 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7797 {
7798         u32 sec_exec_control;
7799
7800         /*
7801          * There is not point to enable virtualize x2apic without enable
7802          * apicv
7803          */
7804         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7805                                 !vmx_vm_has_apicv(vcpu->kvm))
7806                 return;
7807
7808         if (!vm_need_tpr_shadow(vcpu->kvm))
7809                 return;
7810
7811         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7812
7813         if (set) {
7814                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7815                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7816         } else {
7817                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7818                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7819         }
7820         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7821
7822         vmx_set_msr_bitmap(vcpu);
7823 }
7824
7825 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7826 {
7827         struct vcpu_vmx *vmx = to_vmx(vcpu);
7828
7829         /*
7830          * Currently we do not handle the nested case where L2 has an
7831          * APIC access page of its own; that page is still pinned.
7832          * Hence, we skip the case where the VCPU is in guest mode _and_
7833          * L1 prepared an APIC access page for L2.
7834          *
7835          * For the case where L1 and L2 share the same APIC access page
7836          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7837          * in the vmcs12), this function will only update either the vmcs01
7838          * or the vmcs02.  If the former, the vmcs02 will be updated by
7839          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7840          * the next L2->L1 exit.
7841          */
7842         if (!is_guest_mode(vcpu) ||
7843             !nested_cpu_has2(vmx->nested.current_vmcs12,
7844                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7845                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7846 }
7847
7848 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7849 {
7850         u16 status;
7851         u8 old;
7852
7853         if (isr == -1)
7854                 isr = 0;
7855
7856         status = vmcs_read16(GUEST_INTR_STATUS);
7857         old = status >> 8;
7858         if (isr != old) {
7859                 status &= 0xff;
7860                 status |= isr << 8;
7861                 vmcs_write16(GUEST_INTR_STATUS, status);
7862         }
7863 }
7864
7865 static void vmx_set_rvi(int vector)
7866 {
7867         u16 status;
7868         u8 old;
7869
7870         if (vector == -1)
7871                 vector = 0;
7872
7873         status = vmcs_read16(GUEST_INTR_STATUS);
7874         old = (u8)status & 0xff;
7875         if ((u8)vector != old) {
7876                 status &= ~0xff;
7877                 status |= (u8)vector;
7878                 vmcs_write16(GUEST_INTR_STATUS, status);
7879         }
7880 }
7881
7882 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7883 {
7884         if (!is_guest_mode(vcpu)) {
7885                 vmx_set_rvi(max_irr);
7886                 return;
7887         }
7888
7889         if (max_irr == -1)
7890                 return;
7891
7892         /*
7893          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7894          * handles it.
7895          */
7896         if (nested_exit_on_intr(vcpu))
7897                 return;
7898
7899         /*
7900          * Else, fall back to pre-APICv interrupt injection since L2
7901          * is run without virtual interrupt delivery.
7902          */
7903         if (!kvm_event_needs_reinjection(vcpu) &&
7904             vmx_interrupt_allowed(vcpu)) {
7905                 kvm_queue_interrupt(vcpu, max_irr, false);
7906                 vmx_inject_irq(vcpu);
7907         }
7908 }
7909
7910 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7911 {
7912         if (!vmx_vm_has_apicv(vcpu->kvm))
7913                 return;
7914
7915         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7916         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7917         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7918         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7919 }
7920
7921 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7922 {
7923         u32 exit_intr_info;
7924
7925         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7926               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7927                 return;
7928
7929         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7930         exit_intr_info = vmx->exit_intr_info;
7931
7932         /* Handle machine checks before interrupts are enabled */
7933         if (is_machine_check(exit_intr_info))
7934                 kvm_machine_check();
7935
7936         /* We need to handle NMIs before interrupts are enabled */
7937         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7938             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7939                 kvm_before_handle_nmi(&vmx->vcpu);
7940                 asm("int $2");
7941                 kvm_after_handle_nmi(&vmx->vcpu);
7942         }
7943 }
7944
7945 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7946 {
7947         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7948
7949         /*
7950          * If external interrupt exists, IF bit is set in rflags/eflags on the
7951          * interrupt stack frame, and interrupt will be enabled on a return
7952          * from interrupt handler.
7953          */
7954         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7955                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7956                 unsigned int vector;
7957                 unsigned long entry;
7958                 gate_desc *desc;
7959                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7960 #ifdef CONFIG_X86_64
7961                 unsigned long tmp;
7962 #endif
7963
7964                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7965                 desc = (gate_desc *)vmx->host_idt_base + vector;
7966                 entry = gate_offset(*desc);
7967                 asm volatile(
7968 #ifdef CONFIG_X86_64
7969                         "mov %%" _ASM_SP ", %[sp]\n\t"
7970                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7971                         "push $%c[ss]\n\t"
7972                         "push %[sp]\n\t"
7973 #endif
7974                         "pushf\n\t"
7975                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7976                         __ASM_SIZE(push) " $%c[cs]\n\t"
7977                         "call *%[entry]\n\t"
7978                         :
7979 #ifdef CONFIG_X86_64
7980                         [sp]"=&r"(tmp)
7981 #endif
7982                         :
7983                         [entry]"r"(entry),
7984                         [ss]"i"(__KERNEL_DS),
7985                         [cs]"i"(__KERNEL_CS)
7986                         );
7987         } else
7988                 local_irq_enable();
7989 }
7990
7991 static bool vmx_mpx_supported(void)
7992 {
7993         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7994                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7995 }
7996
7997 static bool vmx_xsaves_supported(void)
7998 {
7999         return vmcs_config.cpu_based_2nd_exec_ctrl &
8000                 SECONDARY_EXEC_XSAVES;
8001 }
8002
8003 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8004 {
8005         u32 exit_intr_info;
8006         bool unblock_nmi;
8007         u8 vector;
8008         bool idtv_info_valid;
8009
8010         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8011
8012         if (cpu_has_virtual_nmis()) {
8013                 if (vmx->nmi_known_unmasked)
8014                         return;
8015                 /*
8016                  * Can't use vmx->exit_intr_info since we're not sure what
8017                  * the exit reason is.
8018                  */
8019                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8020                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8021                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8022                 /*
8023                  * SDM 3: 27.7.1.2 (September 2008)
8024                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8025                  * a guest IRET fault.
8026                  * SDM 3: 23.2.2 (September 2008)
8027                  * Bit 12 is undefined in any of the following cases:
8028                  *  If the VM exit sets the valid bit in the IDT-vectoring
8029                  *   information field.
8030                  *  If the VM exit is due to a double fault.
8031                  */
8032                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8033                     vector != DF_VECTOR && !idtv_info_valid)
8034                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8035                                       GUEST_INTR_STATE_NMI);
8036                 else
8037                         vmx->nmi_known_unmasked =
8038                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8039                                   & GUEST_INTR_STATE_NMI);
8040         } else if (unlikely(vmx->soft_vnmi_blocked))
8041                 vmx->vnmi_blocked_time +=
8042                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8043 }
8044
8045 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8046                                       u32 idt_vectoring_info,
8047                                       int instr_len_field,
8048                                       int error_code_field)
8049 {
8050         u8 vector;
8051         int type;
8052         bool idtv_info_valid;
8053
8054         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8055
8056         vcpu->arch.nmi_injected = false;
8057         kvm_clear_exception_queue(vcpu);
8058         kvm_clear_interrupt_queue(vcpu);
8059
8060         if (!idtv_info_valid)
8061                 return;
8062
8063         kvm_make_request(KVM_REQ_EVENT, vcpu);
8064
8065         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8066         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8067
8068         switch (type) {
8069         case INTR_TYPE_NMI_INTR:
8070                 vcpu->arch.nmi_injected = true;
8071                 /*
8072                  * SDM 3: 27.7.1.2 (September 2008)
8073                  * Clear bit "block by NMI" before VM entry if a NMI
8074                  * delivery faulted.
8075                  */
8076                 vmx_set_nmi_mask(vcpu, false);
8077                 break;
8078         case INTR_TYPE_SOFT_EXCEPTION:
8079                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8080                 /* fall through */
8081         case INTR_TYPE_HARD_EXCEPTION:
8082                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8083                         u32 err = vmcs_read32(error_code_field);
8084                         kvm_requeue_exception_e(vcpu, vector, err);
8085                 } else
8086                         kvm_requeue_exception(vcpu, vector);
8087                 break;
8088         case INTR_TYPE_SOFT_INTR:
8089                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8090                 /* fall through */
8091         case INTR_TYPE_EXT_INTR:
8092                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8093                 break;
8094         default:
8095                 break;
8096         }
8097 }
8098
8099 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8100 {
8101         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8102                                   VM_EXIT_INSTRUCTION_LEN,
8103                                   IDT_VECTORING_ERROR_CODE);
8104 }
8105
8106 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8107 {
8108         __vmx_complete_interrupts(vcpu,
8109                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8110                                   VM_ENTRY_INSTRUCTION_LEN,
8111                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8112
8113         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8114 }
8115
8116 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8117 {
8118         int i, nr_msrs;
8119         struct perf_guest_switch_msr *msrs;
8120
8121         msrs = perf_guest_get_msrs(&nr_msrs);
8122
8123         if (!msrs)
8124                 return;
8125
8126         for (i = 0; i < nr_msrs; i++)
8127                 if (msrs[i].host == msrs[i].guest)
8128                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8129                 else
8130                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8131                                         msrs[i].host);
8132 }
8133
8134 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8135 {
8136         struct vcpu_vmx *vmx = to_vmx(vcpu);
8137         unsigned long debugctlmsr, cr4;
8138
8139         /* Record the guest's net vcpu time for enforced NMI injections. */
8140         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8141                 vmx->entry_time = ktime_get();
8142
8143         /* Don't enter VMX if guest state is invalid, let the exit handler
8144            start emulation until we arrive back to a valid state */
8145         if (vmx->emulation_required)
8146                 return;
8147
8148         if (vmx->ple_window_dirty) {
8149                 vmx->ple_window_dirty = false;
8150                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8151         }
8152
8153         if (vmx->nested.sync_shadow_vmcs) {
8154                 copy_vmcs12_to_shadow(vmx);
8155                 vmx->nested.sync_shadow_vmcs = false;
8156         }
8157
8158         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8159                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8160         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8161                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8162
8163         cr4 = cr4_read_shadow();
8164         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8165                 vmcs_writel(HOST_CR4, cr4);
8166                 vmx->host_state.vmcs_host_cr4 = cr4;
8167         }
8168
8169         /* When single-stepping over STI and MOV SS, we must clear the
8170          * corresponding interruptibility bits in the guest state. Otherwise
8171          * vmentry fails as it then expects bit 14 (BS) in pending debug
8172          * exceptions being set, but that's not correct for the guest debugging
8173          * case. */
8174         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8175                 vmx_set_interrupt_shadow(vcpu, 0);
8176
8177         atomic_switch_perf_msrs(vmx);
8178         debugctlmsr = get_debugctlmsr();
8179
8180         vmx->__launched = vmx->loaded_vmcs->launched;
8181         asm(
8182                 /* Store host registers */
8183                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8184                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8185                 "push %%" _ASM_CX " \n\t"
8186                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8187                 "je 1f \n\t"
8188                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8189                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8190                 "1: \n\t"
8191                 /* Reload cr2 if changed */
8192                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8193                 "mov %%cr2, %%" _ASM_DX " \n\t"
8194                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8195                 "je 2f \n\t"
8196                 "mov %%" _ASM_AX", %%cr2 \n\t"
8197                 "2: \n\t"
8198                 /* Check if vmlaunch of vmresume is needed */
8199                 "cmpl $0, %c[launched](%0) \n\t"
8200                 /* Load guest registers.  Don't clobber flags. */
8201                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8202                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8203                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8204                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8205                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8206                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8207 #ifdef CONFIG_X86_64
8208                 "mov %c[r8](%0),  %%r8  \n\t"
8209                 "mov %c[r9](%0),  %%r9  \n\t"
8210                 "mov %c[r10](%0), %%r10 \n\t"
8211                 "mov %c[r11](%0), %%r11 \n\t"
8212                 "mov %c[r12](%0), %%r12 \n\t"
8213                 "mov %c[r13](%0), %%r13 \n\t"
8214                 "mov %c[r14](%0), %%r14 \n\t"
8215                 "mov %c[r15](%0), %%r15 \n\t"
8216 #endif
8217                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8218
8219                 /* Enter guest mode */
8220                 "jne 1f \n\t"
8221                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8222                 "jmp 2f \n\t"
8223                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8224                 "2: "
8225                 /* Save guest registers, load host registers, keep flags */
8226                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8227                 "pop %0 \n\t"
8228                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8229                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8230                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8231                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8232                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8233                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8234                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8235 #ifdef CONFIG_X86_64
8236                 "mov %%r8,  %c[r8](%0) \n\t"
8237                 "mov %%r9,  %c[r9](%0) \n\t"
8238                 "mov %%r10, %c[r10](%0) \n\t"
8239                 "mov %%r11, %c[r11](%0) \n\t"
8240                 "mov %%r12, %c[r12](%0) \n\t"
8241                 "mov %%r13, %c[r13](%0) \n\t"
8242                 "mov %%r14, %c[r14](%0) \n\t"
8243                 "mov %%r15, %c[r15](%0) \n\t"
8244 #endif
8245                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8246                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8247
8248                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8249                 "setbe %c[fail](%0) \n\t"
8250                 ".pushsection .rodata \n\t"
8251                 ".global vmx_return \n\t"
8252                 "vmx_return: " _ASM_PTR " 2b \n\t"
8253                 ".popsection"
8254               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8255                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8256                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8257                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8258                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8259                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8260                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8261                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8262                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8263                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8264                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8265 #ifdef CONFIG_X86_64
8266                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8267                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8268                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8269                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8270                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8271                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8272                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8273                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8274 #endif
8275                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8276                 [wordsize]"i"(sizeof(ulong))
8277               : "cc", "memory"
8278 #ifdef CONFIG_X86_64
8279                 , "rax", "rbx", "rdi", "rsi"
8280                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8281 #else
8282                 , "eax", "ebx", "edi", "esi"
8283 #endif
8284               );
8285
8286         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8287         if (debugctlmsr)
8288                 update_debugctlmsr(debugctlmsr);
8289
8290 #ifndef CONFIG_X86_64
8291         /*
8292          * The sysexit path does not restore ds/es, so we must set them to
8293          * a reasonable value ourselves.
8294          *
8295          * We can't defer this to vmx_load_host_state() since that function
8296          * may be executed in interrupt context, which saves and restore segments
8297          * around it, nullifying its effect.
8298          */
8299         loadsegment(ds, __USER_DS);
8300         loadsegment(es, __USER_DS);
8301 #endif
8302
8303         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8304                                   | (1 << VCPU_EXREG_RFLAGS)
8305                                   | (1 << VCPU_EXREG_PDPTR)
8306                                   | (1 << VCPU_EXREG_SEGMENTS)
8307                                   | (1 << VCPU_EXREG_CR3));
8308         vcpu->arch.regs_dirty = 0;
8309
8310         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8311
8312         vmx->loaded_vmcs->launched = 1;
8313
8314         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8315         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8316
8317         /*
8318          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8319          * we did not inject a still-pending event to L1 now because of
8320          * nested_run_pending, we need to re-enable this bit.
8321          */
8322         if (vmx->nested.nested_run_pending)
8323                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8324
8325         vmx->nested.nested_run_pending = 0;
8326
8327         vmx_complete_atomic_exit(vmx);
8328         vmx_recover_nmi_blocking(vmx);
8329         vmx_complete_interrupts(vmx);
8330 }
8331
8332 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8333 {
8334         struct vcpu_vmx *vmx = to_vmx(vcpu);
8335         int cpu;
8336
8337         if (vmx->loaded_vmcs == &vmx->vmcs01)
8338                 return;
8339
8340         cpu = get_cpu();
8341         vmx->loaded_vmcs = &vmx->vmcs01;
8342         vmx_vcpu_put(vcpu);
8343         vmx_vcpu_load(vcpu, cpu);
8344         vcpu->cpu = cpu;
8345         put_cpu();
8346 }
8347
8348 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8349 {
8350         struct vcpu_vmx *vmx = to_vmx(vcpu);
8351
8352         if (enable_pml)
8353                 vmx_disable_pml(vmx);
8354         free_vpid(vmx);
8355         leave_guest_mode(vcpu);
8356         vmx_load_vmcs01(vcpu);
8357         free_nested(vmx);
8358         free_loaded_vmcs(vmx->loaded_vmcs);
8359         kfree(vmx->guest_msrs);
8360         kvm_vcpu_uninit(vcpu);
8361         kmem_cache_free(kvm_vcpu_cache, vmx);
8362 }
8363
8364 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8365 {
8366         int err;
8367         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8368         int cpu;
8369
8370         if (!vmx)
8371                 return ERR_PTR(-ENOMEM);
8372
8373         allocate_vpid(vmx);
8374
8375         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8376         if (err)
8377                 goto free_vcpu;
8378
8379         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8380         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8381                      > PAGE_SIZE);
8382
8383         err = -ENOMEM;
8384         if (!vmx->guest_msrs) {
8385                 goto uninit_vcpu;
8386         }
8387
8388         vmx->loaded_vmcs = &vmx->vmcs01;
8389         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8390         if (!vmx->loaded_vmcs->vmcs)
8391                 goto free_msrs;
8392         if (!vmm_exclusive)
8393                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8394         loaded_vmcs_init(vmx->loaded_vmcs);
8395         if (!vmm_exclusive)
8396                 kvm_cpu_vmxoff();
8397
8398         cpu = get_cpu();
8399         vmx_vcpu_load(&vmx->vcpu, cpu);
8400         vmx->vcpu.cpu = cpu;
8401         err = vmx_vcpu_setup(vmx);
8402         vmx_vcpu_put(&vmx->vcpu);
8403         put_cpu();
8404         if (err)
8405                 goto free_vmcs;
8406         if (vm_need_virtualize_apic_accesses(kvm)) {
8407                 err = alloc_apic_access_page(kvm);
8408                 if (err)
8409                         goto free_vmcs;
8410         }
8411
8412         if (enable_ept) {
8413                 if (!kvm->arch.ept_identity_map_addr)
8414                         kvm->arch.ept_identity_map_addr =
8415                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8416                 err = init_rmode_identity_map(kvm);
8417                 if (err)
8418                         goto free_vmcs;
8419         }
8420
8421         if (nested)
8422                 nested_vmx_setup_ctls_msrs(vmx);
8423
8424         vmx->nested.posted_intr_nv = -1;
8425         vmx->nested.current_vmptr = -1ull;
8426         vmx->nested.current_vmcs12 = NULL;
8427
8428         /*
8429          * If PML is turned on, failure on enabling PML just results in failure
8430          * of creating the vcpu, therefore we can simplify PML logic (by
8431          * avoiding dealing with cases, such as enabling PML partially on vcpus
8432          * for the guest, etc.
8433          */
8434         if (enable_pml) {
8435                 err = vmx_enable_pml(vmx);
8436                 if (err)
8437                         goto free_vmcs;
8438         }
8439
8440         return &vmx->vcpu;
8441
8442 free_vmcs:
8443         free_loaded_vmcs(vmx->loaded_vmcs);
8444 free_msrs:
8445         kfree(vmx->guest_msrs);
8446 uninit_vcpu:
8447         kvm_vcpu_uninit(&vmx->vcpu);
8448 free_vcpu:
8449         free_vpid(vmx);
8450         kmem_cache_free(kvm_vcpu_cache, vmx);
8451         return ERR_PTR(err);
8452 }
8453
8454 static void __init vmx_check_processor_compat(void *rtn)
8455 {
8456         struct vmcs_config vmcs_conf;
8457
8458         *(int *)rtn = 0;
8459         if (setup_vmcs_config(&vmcs_conf) < 0)
8460                 *(int *)rtn = -EIO;
8461         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8462                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8463                                 smp_processor_id());
8464                 *(int *)rtn = -EIO;
8465         }
8466 }
8467
8468 static int get_ept_level(void)
8469 {
8470         return VMX_EPT_DEFAULT_GAW + 1;
8471 }
8472
8473 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8474 {
8475         u64 ret;
8476
8477         /* For VT-d and EPT combination
8478          * 1. MMIO: always map as UC
8479          * 2. EPT with VT-d:
8480          *   a. VT-d without snooping control feature: can't guarantee the
8481          *      result, try to trust guest.
8482          *   b. VT-d with snooping control feature: snooping control feature of
8483          *      VT-d engine can guarantee the cache correctness. Just set it
8484          *      to WB to keep consistent with host. So the same as item 3.
8485          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8486          *    consistent with host MTRR
8487          */
8488         if (is_mmio)
8489                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8490         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8491                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8492                       VMX_EPT_MT_EPTE_SHIFT;
8493         else
8494                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8495                         | VMX_EPT_IPAT_BIT;
8496
8497         return ret;
8498 }
8499
8500 static int vmx_get_lpage_level(void)
8501 {
8502         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8503                 return PT_DIRECTORY_LEVEL;
8504         else
8505                 /* For shadow and EPT supported 1GB page */
8506                 return PT_PDPE_LEVEL;
8507 }
8508
8509 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8510 {
8511         struct kvm_cpuid_entry2 *best;
8512         struct vcpu_vmx *vmx = to_vmx(vcpu);
8513         u32 exec_control;
8514
8515         vmx->rdtscp_enabled = false;
8516         if (vmx_rdtscp_supported()) {
8517                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8518                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8519                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8520                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8521                                 vmx->rdtscp_enabled = true;
8522                         else {
8523                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8524                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8525                                                 exec_control);
8526                         }
8527                 }
8528                 if (nested && !vmx->rdtscp_enabled)
8529                         vmx->nested.nested_vmx_secondary_ctls_high &=
8530                                 ~SECONDARY_EXEC_RDTSCP;
8531         }
8532
8533         /* Exposing INVPCID only when PCID is exposed */
8534         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8535         if (vmx_invpcid_supported() &&
8536             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8537             guest_cpuid_has_pcid(vcpu)) {
8538                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8539                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8540                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8541                              exec_control);
8542         } else {
8543                 if (cpu_has_secondary_exec_ctrls()) {
8544                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8545                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8546                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8547                                      exec_control);
8548                 }
8549                 if (best)
8550                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8551         }
8552 }
8553
8554 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8555 {
8556         if (func == 1 && nested)
8557                 entry->ecx |= bit(X86_FEATURE_VMX);
8558 }
8559
8560 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8561                 struct x86_exception *fault)
8562 {
8563         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8564         u32 exit_reason;
8565
8566         if (fault->error_code & PFERR_RSVD_MASK)
8567                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8568         else
8569                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8570         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8571         vmcs12->guest_physical_address = fault->address;
8572 }
8573
8574 /* Callbacks for nested_ept_init_mmu_context: */
8575
8576 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8577 {
8578         /* return the page table to be shadowed - in our case, EPT12 */
8579         return get_vmcs12(vcpu)->ept_pointer;
8580 }
8581
8582 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8583 {
8584         WARN_ON(mmu_is_nested(vcpu));
8585         kvm_init_shadow_ept_mmu(vcpu,
8586                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8587                         VMX_EPT_EXECUTE_ONLY_BIT);
8588         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8589         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8590         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8591
8592         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8593 }
8594
8595 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8596 {
8597         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8598 }
8599
8600 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8601                                             u16 error_code)
8602 {
8603         bool inequality, bit;
8604
8605         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8606         inequality =
8607                 (error_code & vmcs12->page_fault_error_code_mask) !=
8608                  vmcs12->page_fault_error_code_match;
8609         return inequality ^ bit;
8610 }
8611
8612 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8613                 struct x86_exception *fault)
8614 {
8615         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8616
8617         WARN_ON(!is_guest_mode(vcpu));
8618
8619         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8620                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8621                                   vmcs_read32(VM_EXIT_INTR_INFO),
8622                                   vmcs_readl(EXIT_QUALIFICATION));
8623         else
8624                 kvm_inject_page_fault(vcpu, fault);
8625 }
8626
8627 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8628                                         struct vmcs12 *vmcs12)
8629 {
8630         struct vcpu_vmx *vmx = to_vmx(vcpu);
8631         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8632
8633         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8634                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8635                     vmcs12->apic_access_addr >> maxphyaddr)
8636                         return false;
8637
8638                 /*
8639                  * Translate L1 physical address to host physical
8640                  * address for vmcs02. Keep the page pinned, so this
8641                  * physical address remains valid. We keep a reference
8642                  * to it so we can release it later.
8643                  */
8644                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8645                         nested_release_page(vmx->nested.apic_access_page);
8646                 vmx->nested.apic_access_page =
8647                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8648         }
8649
8650         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8651                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8652                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
8653                         return false;
8654
8655                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8656                         nested_release_page(vmx->nested.virtual_apic_page);
8657                 vmx->nested.virtual_apic_page =
8658                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8659
8660                 /*
8661                  * Failing the vm entry is _not_ what the processor does
8662                  * but it's basically the only possibility we have.
8663                  * We could still enter the guest if CR8 load exits are
8664                  * enabled, CR8 store exits are enabled, and virtualize APIC
8665                  * access is disabled; in this case the processor would never
8666                  * use the TPR shadow and we could simply clear the bit from
8667                  * the execution control.  But such a configuration is useless,
8668                  * so let's keep the code simple.
8669                  */
8670                 if (!vmx->nested.virtual_apic_page)
8671                         return false;
8672         }
8673
8674         if (nested_cpu_has_posted_intr(vmcs12)) {
8675                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8676                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
8677                         return false;
8678
8679                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8680                         kunmap(vmx->nested.pi_desc_page);
8681                         nested_release_page(vmx->nested.pi_desc_page);
8682                 }
8683                 vmx->nested.pi_desc_page =
8684                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8685                 if (!vmx->nested.pi_desc_page)
8686                         return false;
8687
8688                 vmx->nested.pi_desc =
8689                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8690                 if (!vmx->nested.pi_desc) {
8691                         nested_release_page_clean(vmx->nested.pi_desc_page);
8692                         return false;
8693                 }
8694                 vmx->nested.pi_desc =
8695                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
8696                         (unsigned long)(vmcs12->posted_intr_desc_addr &
8697                         (PAGE_SIZE - 1)));
8698         }
8699
8700         return true;
8701 }
8702
8703 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8704 {
8705         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8706         struct vcpu_vmx *vmx = to_vmx(vcpu);
8707
8708         if (vcpu->arch.virtual_tsc_khz == 0)
8709                 return;
8710
8711         /* Make sure short timeouts reliably trigger an immediate vmexit.
8712          * hrtimer_start does not guarantee this. */
8713         if (preemption_timeout <= 1) {
8714                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8715                 return;
8716         }
8717
8718         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8719         preemption_timeout *= 1000000;
8720         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8721         hrtimer_start(&vmx->nested.preemption_timer,
8722                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8723 }
8724
8725 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8726                                                 struct vmcs12 *vmcs12)
8727 {
8728         int maxphyaddr;
8729         u64 addr;
8730
8731         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8732                 return 0;
8733
8734         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8735                 WARN_ON(1);
8736                 return -EINVAL;
8737         }
8738         maxphyaddr = cpuid_maxphyaddr(vcpu);
8739
8740         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8741            ((addr + PAGE_SIZE) >> maxphyaddr))
8742                 return -EINVAL;
8743
8744         return 0;
8745 }
8746
8747 /*
8748  * Merge L0's and L1's MSR bitmap, return false to indicate that
8749  * we do not use the hardware.
8750  */
8751 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8752                                                struct vmcs12 *vmcs12)
8753 {
8754         int msr;
8755         struct page *page;
8756         unsigned long *msr_bitmap;
8757
8758         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8759                 return false;
8760
8761         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8762         if (!page) {
8763                 WARN_ON(1);
8764                 return false;
8765         }
8766         msr_bitmap = (unsigned long *)kmap(page);
8767         if (!msr_bitmap) {
8768                 nested_release_page_clean(page);
8769                 WARN_ON(1);
8770                 return false;
8771         }
8772
8773         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8774                 if (nested_cpu_has_apic_reg_virt(vmcs12))
8775                         for (msr = 0x800; msr <= 0x8ff; msr++)
8776                                 nested_vmx_disable_intercept_for_msr(
8777                                         msr_bitmap,
8778                                         vmx_msr_bitmap_nested,
8779                                         msr, MSR_TYPE_R);
8780                 /* TPR is allowed */
8781                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8782                                 vmx_msr_bitmap_nested,
8783                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8784                                 MSR_TYPE_R | MSR_TYPE_W);
8785                 if (nested_cpu_has_vid(vmcs12)) {
8786                         /* EOI and self-IPI are allowed */
8787                         nested_vmx_disable_intercept_for_msr(
8788                                 msr_bitmap,
8789                                 vmx_msr_bitmap_nested,
8790                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8791                                 MSR_TYPE_W);
8792                         nested_vmx_disable_intercept_for_msr(
8793                                 msr_bitmap,
8794                                 vmx_msr_bitmap_nested,
8795                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8796                                 MSR_TYPE_W);
8797                 }
8798         } else {
8799                 /*
8800                  * Enable reading intercept of all the x2apic
8801                  * MSRs. We should not rely on vmcs12 to do any
8802                  * optimizations here, it may have been modified
8803                  * by L1.
8804                  */
8805                 for (msr = 0x800; msr <= 0x8ff; msr++)
8806                         __vmx_enable_intercept_for_msr(
8807                                 vmx_msr_bitmap_nested,
8808                                 msr,
8809                                 MSR_TYPE_R);
8810
8811                 __vmx_enable_intercept_for_msr(
8812                                 vmx_msr_bitmap_nested,
8813                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8814                                 MSR_TYPE_W);
8815                 __vmx_enable_intercept_for_msr(
8816                                 vmx_msr_bitmap_nested,
8817                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8818                                 MSR_TYPE_W);
8819                 __vmx_enable_intercept_for_msr(
8820                                 vmx_msr_bitmap_nested,
8821                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8822                                 MSR_TYPE_W);
8823         }
8824         kunmap(page);
8825         nested_release_page_clean(page);
8826
8827         return true;
8828 }
8829
8830 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8831                                            struct vmcs12 *vmcs12)
8832 {
8833         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8834             !nested_cpu_has_apic_reg_virt(vmcs12) &&
8835             !nested_cpu_has_vid(vmcs12) &&
8836             !nested_cpu_has_posted_intr(vmcs12))
8837                 return 0;
8838
8839         /*
8840          * If virtualize x2apic mode is enabled,
8841          * virtualize apic access must be disabled.
8842          */
8843         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8844             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8845                 return -EINVAL;
8846
8847         /*
8848          * If virtual interrupt delivery is enabled,
8849          * we must exit on external interrupts.
8850          */
8851         if (nested_cpu_has_vid(vmcs12) &&
8852            !nested_exit_on_intr(vcpu))
8853                 return -EINVAL;
8854
8855         /*
8856          * bits 15:8 should be zero in posted_intr_nv,
8857          * the descriptor address has been already checked
8858          * in nested_get_vmcs12_pages.
8859          */
8860         if (nested_cpu_has_posted_intr(vmcs12) &&
8861            (!nested_cpu_has_vid(vmcs12) ||
8862             !nested_exit_intr_ack_set(vcpu) ||
8863             vmcs12->posted_intr_nv & 0xff00))
8864                 return -EINVAL;
8865
8866         /* tpr shadow is needed by all apicv features. */
8867         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8868                 return -EINVAL;
8869
8870         return 0;
8871 }
8872
8873 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8874                                        unsigned long count_field,
8875                                        unsigned long addr_field)
8876 {
8877         int maxphyaddr;
8878         u64 count, addr;
8879
8880         if (vmcs12_read_any(vcpu, count_field, &count) ||
8881             vmcs12_read_any(vcpu, addr_field, &addr)) {
8882                 WARN_ON(1);
8883                 return -EINVAL;
8884         }
8885         if (count == 0)
8886                 return 0;
8887         maxphyaddr = cpuid_maxphyaddr(vcpu);
8888         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8889             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8890                 pr_warn_ratelimited(
8891                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8892                         addr_field, maxphyaddr, count, addr);
8893                 return -EINVAL;
8894         }
8895         return 0;
8896 }
8897
8898 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8899                                                 struct vmcs12 *vmcs12)
8900 {
8901         if (vmcs12->vm_exit_msr_load_count == 0 &&
8902             vmcs12->vm_exit_msr_store_count == 0 &&
8903             vmcs12->vm_entry_msr_load_count == 0)
8904                 return 0; /* Fast path */
8905         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8906                                         VM_EXIT_MSR_LOAD_ADDR) ||
8907             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8908                                         VM_EXIT_MSR_STORE_ADDR) ||
8909             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8910                                         VM_ENTRY_MSR_LOAD_ADDR))
8911                 return -EINVAL;
8912         return 0;
8913 }
8914
8915 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8916                                        struct vmx_msr_entry *e)
8917 {
8918         /* x2APIC MSR accesses are not allowed */
8919         if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8920                 return -EINVAL;
8921         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8922             e->index == MSR_IA32_UCODE_REV)
8923                 return -EINVAL;
8924         if (e->reserved != 0)
8925                 return -EINVAL;
8926         return 0;
8927 }
8928
8929 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8930                                      struct vmx_msr_entry *e)
8931 {
8932         if (e->index == MSR_FS_BASE ||
8933             e->index == MSR_GS_BASE ||
8934             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8935             nested_vmx_msr_check_common(vcpu, e))
8936                 return -EINVAL;
8937         return 0;
8938 }
8939
8940 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8941                                       struct vmx_msr_entry *e)
8942 {
8943         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8944             nested_vmx_msr_check_common(vcpu, e))
8945                 return -EINVAL;
8946         return 0;
8947 }
8948
8949 /*
8950  * Load guest's/host's msr at nested entry/exit.
8951  * return 0 for success, entry index for failure.
8952  */
8953 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8954 {
8955         u32 i;
8956         struct vmx_msr_entry e;
8957         struct msr_data msr;
8958
8959         msr.host_initiated = false;
8960         for (i = 0; i < count; i++) {
8961                 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8962                                    &e, sizeof(e))) {
8963                         pr_warn_ratelimited(
8964                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8965                                 __func__, i, gpa + i * sizeof(e));
8966                         goto fail;
8967                 }
8968                 if (nested_vmx_load_msr_check(vcpu, &e)) {
8969                         pr_warn_ratelimited(
8970                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8971                                 __func__, i, e.index, e.reserved);
8972                         goto fail;
8973                 }
8974                 msr.index = e.index;
8975                 msr.data = e.value;
8976                 if (kvm_set_msr(vcpu, &msr)) {
8977                         pr_warn_ratelimited(
8978                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8979                                 __func__, i, e.index, e.value);
8980                         goto fail;
8981                 }
8982         }
8983         return 0;
8984 fail:
8985         return i + 1;
8986 }
8987
8988 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8989 {
8990         u32 i;
8991         struct vmx_msr_entry e;
8992
8993         for (i = 0; i < count; i++) {
8994                 if (kvm_read_guest(vcpu->kvm,
8995                                    gpa + i * sizeof(e),
8996                                    &e, 2 * sizeof(u32))) {
8997                         pr_warn_ratelimited(
8998                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8999                                 __func__, i, gpa + i * sizeof(e));
9000                         return -EINVAL;
9001                 }
9002                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9003                         pr_warn_ratelimited(
9004                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9005                                 __func__, i, e.index, e.reserved);
9006                         return -EINVAL;
9007                 }
9008                 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9009                         pr_warn_ratelimited(
9010                                 "%s cannot read MSR (%u, 0x%x)\n",
9011                                 __func__, i, e.index);
9012                         return -EINVAL;
9013                 }
9014                 if (kvm_write_guest(vcpu->kvm,
9015                                     gpa + i * sizeof(e) +
9016                                         offsetof(struct vmx_msr_entry, value),
9017                                     &e.value, sizeof(e.value))) {
9018                         pr_warn_ratelimited(
9019                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9020                                 __func__, i, e.index, e.value);
9021                         return -EINVAL;
9022                 }
9023         }
9024         return 0;
9025 }
9026
9027 /*
9028  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9029  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9030  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9031  * guest in a way that will both be appropriate to L1's requests, and our
9032  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9033  * function also has additional necessary side-effects, like setting various
9034  * vcpu->arch fields.
9035  */
9036 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9037 {
9038         struct vcpu_vmx *vmx = to_vmx(vcpu);
9039         u32 exec_control;
9040
9041         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9042         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9043         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9044         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9045         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9046         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9047         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9048         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9049         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9050         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9051         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9052         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9053         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9054         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9055         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9056         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9057         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9058         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9059         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9060         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9061         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9062         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9063         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9064         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9065         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9066         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9067         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9068         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9069         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9070         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9071         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9072         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9073         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9074         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9075         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9076         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9077
9078         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9079                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9080                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9081         } else {
9082                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9083                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9084         }
9085         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9086                 vmcs12->vm_entry_intr_info_field);
9087         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9088                 vmcs12->vm_entry_exception_error_code);
9089         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9090                 vmcs12->vm_entry_instruction_len);
9091         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9092                 vmcs12->guest_interruptibility_info);
9093         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9094         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9095         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9096                 vmcs12->guest_pending_dbg_exceptions);
9097         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9098         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9099
9100         if (nested_cpu_has_xsaves(vmcs12))
9101                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9102         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9103
9104         exec_control = vmcs12->pin_based_vm_exec_control;
9105         exec_control |= vmcs_config.pin_based_exec_ctrl;
9106         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9107
9108         if (nested_cpu_has_posted_intr(vmcs12)) {
9109                 /*
9110                  * Note that we use L0's vector here and in
9111                  * vmx_deliver_nested_posted_interrupt.
9112                  */
9113                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9114                 vmx->nested.pi_pending = false;
9115                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9116                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9117                         page_to_phys(vmx->nested.pi_desc_page) +
9118                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9119                         (PAGE_SIZE - 1)));
9120         } else
9121                 exec_control &= ~PIN_BASED_POSTED_INTR;
9122
9123         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9124
9125         vmx->nested.preemption_timer_expired = false;
9126         if (nested_cpu_has_preemption_timer(vmcs12))
9127                 vmx_start_preemption_timer(vcpu);
9128
9129         /*
9130          * Whether page-faults are trapped is determined by a combination of
9131          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9132          * If enable_ept, L0 doesn't care about page faults and we should
9133          * set all of these to L1's desires. However, if !enable_ept, L0 does
9134          * care about (at least some) page faults, and because it is not easy
9135          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9136          * to exit on each and every L2 page fault. This is done by setting
9137          * MASK=MATCH=0 and (see below) EB.PF=1.
9138          * Note that below we don't need special code to set EB.PF beyond the
9139          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9140          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9141          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9142          *
9143          * A problem with this approach (when !enable_ept) is that L1 may be
9144          * injected with more page faults than it asked for. This could have
9145          * caused problems, but in practice existing hypervisors don't care.
9146          * To fix this, we will need to emulate the PFEC checking (on the L1
9147          * page tables), using walk_addr(), when injecting PFs to L1.
9148          */
9149         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9150                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9151         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9152                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9153
9154         if (cpu_has_secondary_exec_ctrls()) {
9155                 exec_control = vmx_secondary_exec_control(vmx);
9156                 if (!vmx->rdtscp_enabled)
9157                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
9158                 /* Take the following fields only from vmcs12 */
9159                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9160                                   SECONDARY_EXEC_RDTSCP |
9161                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9162                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9163                 if (nested_cpu_has(vmcs12,
9164                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9165                         exec_control |= vmcs12->secondary_vm_exec_control;
9166
9167                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9168                         /*
9169                          * If translation failed, no matter: This feature asks
9170                          * to exit when accessing the given address, and if it
9171                          * can never be accessed, this feature won't do
9172                          * anything anyway.
9173                          */
9174                         if (!vmx->nested.apic_access_page)
9175                                 exec_control &=
9176                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9177                         else
9178                                 vmcs_write64(APIC_ACCESS_ADDR,
9179                                   page_to_phys(vmx->nested.apic_access_page));
9180                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9181                             (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9182                         exec_control |=
9183                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9184                         kvm_vcpu_reload_apic_access_page(vcpu);
9185                 }
9186
9187                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9188                         vmcs_write64(EOI_EXIT_BITMAP0,
9189                                 vmcs12->eoi_exit_bitmap0);
9190                         vmcs_write64(EOI_EXIT_BITMAP1,
9191                                 vmcs12->eoi_exit_bitmap1);
9192                         vmcs_write64(EOI_EXIT_BITMAP2,
9193                                 vmcs12->eoi_exit_bitmap2);
9194                         vmcs_write64(EOI_EXIT_BITMAP3,
9195                                 vmcs12->eoi_exit_bitmap3);
9196                         vmcs_write16(GUEST_INTR_STATUS,
9197                                 vmcs12->guest_intr_status);
9198                 }
9199
9200                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9201         }
9202
9203
9204         /*
9205          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9206          * Some constant fields are set here by vmx_set_constant_host_state().
9207          * Other fields are different per CPU, and will be set later when
9208          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9209          */
9210         vmx_set_constant_host_state(vmx);
9211
9212         /*
9213          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9214          * entry, but only if the current (host) sp changed from the value
9215          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9216          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9217          * here we just force the write to happen on entry.
9218          */
9219         vmx->host_rsp = 0;
9220
9221         exec_control = vmx_exec_control(vmx); /* L0's desires */
9222         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9223         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9224         exec_control &= ~CPU_BASED_TPR_SHADOW;
9225         exec_control |= vmcs12->cpu_based_vm_exec_control;
9226
9227         if (exec_control & CPU_BASED_TPR_SHADOW) {
9228                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9229                                 page_to_phys(vmx->nested.virtual_apic_page));
9230                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9231         }
9232
9233         if (cpu_has_vmx_msr_bitmap() &&
9234             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9235                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9236                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9237         } else
9238                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9239
9240         /*
9241          * Merging of IO bitmap not currently supported.
9242          * Rather, exit every time.
9243          */
9244         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9245         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9246
9247         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9248
9249         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9250          * bitwise-or of what L1 wants to trap for L2, and what we want to
9251          * trap. Note that CR0.TS also needs updating - we do this later.
9252          */
9253         update_exception_bitmap(vcpu);
9254         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9255         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9256
9257         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9258          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9259          * bits are further modified by vmx_set_efer() below.
9260          */
9261         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9262
9263         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9264          * emulated by vmx_set_efer(), below.
9265          */
9266         vm_entry_controls_init(vmx,
9267                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9268                         ~VM_ENTRY_IA32E_MODE) |
9269                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9270
9271         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9272                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9273                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9274         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9275                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9276
9277
9278         set_cr4_guest_host_mask(vmx);
9279
9280         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9281                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9282
9283         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9284                 vmcs_write64(TSC_OFFSET,
9285                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9286         else
9287                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9288
9289         if (enable_vpid) {
9290                 /*
9291                  * Trivially support vpid by letting L2s share their parent
9292                  * L1's vpid. TODO: move to a more elaborate solution, giving
9293                  * each L2 its own vpid and exposing the vpid feature to L1.
9294                  */
9295                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9296                 vmx_flush_tlb(vcpu);
9297         }
9298
9299         if (nested_cpu_has_ept(vmcs12)) {
9300                 kvm_mmu_unload(vcpu);
9301                 nested_ept_init_mmu_context(vcpu);
9302         }
9303
9304         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9305                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9306         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9307                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9308         else
9309                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9310         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9311         vmx_set_efer(vcpu, vcpu->arch.efer);
9312
9313         /*
9314          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9315          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9316          * The CR0_READ_SHADOW is what L2 should have expected to read given
9317          * the specifications by L1; It's not enough to take
9318          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9319          * have more bits than L1 expected.
9320          */
9321         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9322         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9323
9324         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9325         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9326
9327         /* shadow page tables on either EPT or shadow page tables */
9328         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9329         kvm_mmu_reset_context(vcpu);
9330
9331         if (!enable_ept)
9332                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9333
9334         /*
9335          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9336          */
9337         if (enable_ept) {
9338                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9339                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9340                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9341                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9342         }
9343
9344         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9345         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9346 }
9347
9348 /*
9349  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9350  * for running an L2 nested guest.
9351  */
9352 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9353 {
9354         struct vmcs12 *vmcs12;
9355         struct vcpu_vmx *vmx = to_vmx(vcpu);
9356         int cpu;
9357         struct loaded_vmcs *vmcs02;
9358         bool ia32e;
9359         u32 msr_entry_idx;
9360
9361         if (!nested_vmx_check_permission(vcpu) ||
9362             !nested_vmx_check_vmcs12(vcpu))
9363                 return 1;
9364
9365         skip_emulated_instruction(vcpu);
9366         vmcs12 = get_vmcs12(vcpu);
9367
9368         if (enable_shadow_vmcs)
9369                 copy_shadow_to_vmcs12(vmx);
9370
9371         /*
9372          * The nested entry process starts with enforcing various prerequisites
9373          * on vmcs12 as required by the Intel SDM, and act appropriately when
9374          * they fail: As the SDM explains, some conditions should cause the
9375          * instruction to fail, while others will cause the instruction to seem
9376          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9377          * To speed up the normal (success) code path, we should avoid checking
9378          * for misconfigurations which will anyway be caught by the processor
9379          * when using the merged vmcs02.
9380          */
9381         if (vmcs12->launch_state == launch) {
9382                 nested_vmx_failValid(vcpu,
9383                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9384                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9385                 return 1;
9386         }
9387
9388         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9389             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9390                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9391                 return 1;
9392         }
9393
9394         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9395                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9396                 return 1;
9397         }
9398
9399         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9400                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9401                 return 1;
9402         }
9403
9404         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9405                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9406                 return 1;
9407         }
9408
9409         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9410                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9411                 return 1;
9412         }
9413
9414         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9415                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9416                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9417             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9418                                 vmx->nested.nested_vmx_secondary_ctls_low,
9419                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9420             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9421                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9422                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9423             !vmx_control_verify(vmcs12->vm_exit_controls,
9424                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9425                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9426             !vmx_control_verify(vmcs12->vm_entry_controls,
9427                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9428                                 vmx->nested.nested_vmx_entry_ctls_high))
9429         {
9430                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9431                 return 1;
9432         }
9433
9434         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9435             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9436                 nested_vmx_failValid(vcpu,
9437                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9438                 return 1;
9439         }
9440
9441         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9442             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9443                 nested_vmx_entry_failure(vcpu, vmcs12,
9444                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9445                 return 1;
9446         }
9447         if (vmcs12->vmcs_link_pointer != -1ull) {
9448                 nested_vmx_entry_failure(vcpu, vmcs12,
9449                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9450                 return 1;
9451         }
9452
9453         /*
9454          * If the load IA32_EFER VM-entry control is 1, the following checks
9455          * are performed on the field for the IA32_EFER MSR:
9456          * - Bits reserved in the IA32_EFER MSR must be 0.
9457          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9458          *   the IA-32e mode guest VM-exit control. It must also be identical
9459          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9460          *   CR0.PG) is 1.
9461          */
9462         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9463                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9464                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9465                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9466                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9467                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9468                         nested_vmx_entry_failure(vcpu, vmcs12,
9469                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9470                         return 1;
9471                 }
9472         }
9473
9474         /*
9475          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9476          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9477          * the values of the LMA and LME bits in the field must each be that of
9478          * the host address-space size VM-exit control.
9479          */
9480         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9481                 ia32e = (vmcs12->vm_exit_controls &
9482                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9483                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9484                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9485                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9486                         nested_vmx_entry_failure(vcpu, vmcs12,
9487                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9488                         return 1;
9489                 }
9490         }
9491
9492         /*
9493          * We're finally done with prerequisite checking, and can start with
9494          * the nested entry.
9495          */
9496
9497         vmcs02 = nested_get_current_vmcs02(vmx);
9498         if (!vmcs02)
9499                 return -ENOMEM;
9500
9501         enter_guest_mode(vcpu);
9502
9503         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9504
9505         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9506                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9507
9508         cpu = get_cpu();
9509         vmx->loaded_vmcs = vmcs02;
9510         vmx_vcpu_put(vcpu);
9511         vmx_vcpu_load(vcpu, cpu);
9512         vcpu->cpu = cpu;
9513         put_cpu();
9514
9515         vmx_segment_cache_clear(vmx);
9516
9517         prepare_vmcs02(vcpu, vmcs12);
9518
9519         msr_entry_idx = nested_vmx_load_msr(vcpu,
9520                                             vmcs12->vm_entry_msr_load_addr,
9521                                             vmcs12->vm_entry_msr_load_count);
9522         if (msr_entry_idx) {
9523                 leave_guest_mode(vcpu);
9524                 vmx_load_vmcs01(vcpu);
9525                 nested_vmx_entry_failure(vcpu, vmcs12,
9526                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9527                 return 1;
9528         }
9529
9530         vmcs12->launch_state = 1;
9531
9532         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9533                 return kvm_vcpu_halt(vcpu);
9534
9535         vmx->nested.nested_run_pending = 1;
9536
9537         /*
9538          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9539          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9540          * returned as far as L1 is concerned. It will only return (and set
9541          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9542          */
9543         return 1;
9544 }
9545
9546 /*
9547  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9548  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9549  * This function returns the new value we should put in vmcs12.guest_cr0.
9550  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9551  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9552  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9553  *     didn't trap the bit, because if L1 did, so would L0).
9554  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9555  *     been modified by L2, and L1 knows it. So just leave the old value of
9556  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9557  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9558  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9559  *     changed these bits, and therefore they need to be updated, but L0
9560  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9561  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9562  */
9563 static inline unsigned long
9564 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9565 {
9566         return
9567         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9568         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9569         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9570                         vcpu->arch.cr0_guest_owned_bits));
9571 }
9572
9573 static inline unsigned long
9574 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9575 {
9576         return
9577         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9578         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9579         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9580                         vcpu->arch.cr4_guest_owned_bits));
9581 }
9582
9583 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9584                                        struct vmcs12 *vmcs12)
9585 {
9586         u32 idt_vectoring;
9587         unsigned int nr;
9588
9589         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9590                 nr = vcpu->arch.exception.nr;
9591                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9592
9593                 if (kvm_exception_is_soft(nr)) {
9594                         vmcs12->vm_exit_instruction_len =
9595                                 vcpu->arch.event_exit_inst_len;
9596                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9597                 } else
9598                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9599
9600                 if (vcpu->arch.exception.has_error_code) {
9601                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9602                         vmcs12->idt_vectoring_error_code =
9603                                 vcpu->arch.exception.error_code;
9604                 }
9605
9606                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9607         } else if (vcpu->arch.nmi_injected) {
9608                 vmcs12->idt_vectoring_info_field =
9609                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9610         } else if (vcpu->arch.interrupt.pending) {
9611                 nr = vcpu->arch.interrupt.nr;
9612                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9613
9614                 if (vcpu->arch.interrupt.soft) {
9615                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9616                         vmcs12->vm_entry_instruction_len =
9617                                 vcpu->arch.event_exit_inst_len;
9618                 } else
9619                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9620
9621                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9622         }
9623 }
9624
9625 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9626 {
9627         struct vcpu_vmx *vmx = to_vmx(vcpu);
9628
9629         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9630             vmx->nested.preemption_timer_expired) {
9631                 if (vmx->nested.nested_run_pending)
9632                         return -EBUSY;
9633                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9634                 return 0;
9635         }
9636
9637         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9638                 if (vmx->nested.nested_run_pending ||
9639                     vcpu->arch.interrupt.pending)
9640                         return -EBUSY;
9641                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9642                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
9643                                   INTR_INFO_VALID_MASK, 0);
9644                 /*
9645                  * The NMI-triggered VM exit counts as injection:
9646                  * clear this one and block further NMIs.
9647                  */
9648                 vcpu->arch.nmi_pending = 0;
9649                 vmx_set_nmi_mask(vcpu, true);
9650                 return 0;
9651         }
9652
9653         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9654             nested_exit_on_intr(vcpu)) {
9655                 if (vmx->nested.nested_run_pending)
9656                         return -EBUSY;
9657                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9658                 return 0;
9659         }
9660
9661         return vmx_complete_nested_posted_interrupt(vcpu);
9662 }
9663
9664 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9665 {
9666         ktime_t remaining =
9667                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9668         u64 value;
9669
9670         if (ktime_to_ns(remaining) <= 0)
9671                 return 0;
9672
9673         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9674         do_div(value, 1000000);
9675         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9676 }
9677
9678 /*
9679  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9680  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9681  * and this function updates it to reflect the changes to the guest state while
9682  * L2 was running (and perhaps made some exits which were handled directly by L0
9683  * without going back to L1), and to reflect the exit reason.
9684  * Note that we do not have to copy here all VMCS fields, just those that
9685  * could have changed by the L2 guest or the exit - i.e., the guest-state and
9686  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9687  * which already writes to vmcs12 directly.
9688  */
9689 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9690                            u32 exit_reason, u32 exit_intr_info,
9691                            unsigned long exit_qualification)
9692 {
9693         /* update guest state fields: */
9694         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9695         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9696
9697         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9698         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9699         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9700
9701         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9702         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9703         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9704         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9705         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9706         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9707         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9708         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9709         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9710         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9711         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9712         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9713         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9714         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9715         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9716         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9717         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9718         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9719         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9720         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9721         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9722         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9723         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9724         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9725         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9726         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9727         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9728         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9729         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9730         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9731         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9732         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9733         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9734         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9735         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9736         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9737
9738         vmcs12->guest_interruptibility_info =
9739                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9740         vmcs12->guest_pending_dbg_exceptions =
9741                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9742         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9743                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9744         else
9745                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9746
9747         if (nested_cpu_has_preemption_timer(vmcs12)) {
9748                 if (vmcs12->vm_exit_controls &
9749                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9750                         vmcs12->vmx_preemption_timer_value =
9751                                 vmx_get_preemption_timer_value(vcpu);
9752                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9753         }
9754
9755         /*
9756          * In some cases (usually, nested EPT), L2 is allowed to change its
9757          * own CR3 without exiting. If it has changed it, we must keep it.
9758          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9759          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9760          *
9761          * Additionally, restore L2's PDPTR to vmcs12.
9762          */
9763         if (enable_ept) {
9764                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9765                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9766                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9767                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9768                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9769         }
9770
9771         if (nested_cpu_has_vid(vmcs12))
9772                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9773
9774         vmcs12->vm_entry_controls =
9775                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9776                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9777
9778         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9779                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9780                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9781         }
9782
9783         /* TODO: These cannot have changed unless we have MSR bitmaps and
9784          * the relevant bit asks not to trap the change */
9785         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9786                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9787         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9788                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9789         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9790         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9791         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9792         if (vmx_mpx_supported())
9793                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9794         if (nested_cpu_has_xsaves(vmcs12))
9795                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9796
9797         /* update exit information fields: */
9798
9799         vmcs12->vm_exit_reason = exit_reason;
9800         vmcs12->exit_qualification = exit_qualification;
9801
9802         vmcs12->vm_exit_intr_info = exit_intr_info;
9803         if ((vmcs12->vm_exit_intr_info &
9804              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9805             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9806                 vmcs12->vm_exit_intr_error_code =
9807                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9808         vmcs12->idt_vectoring_info_field = 0;
9809         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9810         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9811
9812         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9813                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9814                  * instead of reading the real value. */
9815                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9816
9817                 /*
9818                  * Transfer the event that L0 or L1 may wanted to inject into
9819                  * L2 to IDT_VECTORING_INFO_FIELD.
9820                  */
9821                 vmcs12_save_pending_event(vcpu, vmcs12);
9822         }
9823
9824         /*
9825          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9826          * preserved above and would only end up incorrectly in L1.
9827          */
9828         vcpu->arch.nmi_injected = false;
9829         kvm_clear_exception_queue(vcpu);
9830         kvm_clear_interrupt_queue(vcpu);
9831 }
9832
9833 /*
9834  * A part of what we need to when the nested L2 guest exits and we want to
9835  * run its L1 parent, is to reset L1's guest state to the host state specified
9836  * in vmcs12.
9837  * This function is to be called not only on normal nested exit, but also on
9838  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9839  * Failures During or After Loading Guest State").
9840  * This function should be called when the active VMCS is L1's (vmcs01).
9841  */
9842 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9843                                    struct vmcs12 *vmcs12)
9844 {
9845         struct kvm_segment seg;
9846
9847         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9848                 vcpu->arch.efer = vmcs12->host_ia32_efer;
9849         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9850                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9851         else
9852                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9853         vmx_set_efer(vcpu, vcpu->arch.efer);
9854
9855         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9856         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9857         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9858         /*
9859          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9860          * actually changed, because it depends on the current state of
9861          * fpu_active (which may have changed).
9862          * Note that vmx_set_cr0 refers to efer set above.
9863          */
9864         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9865         /*
9866          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9867          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9868          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9869          */
9870         update_exception_bitmap(vcpu);
9871         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9872         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9873
9874         /*
9875          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9876          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9877          */
9878         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9879         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9880
9881         nested_ept_uninit_mmu_context(vcpu);
9882
9883         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9884         kvm_mmu_reset_context(vcpu);
9885
9886         if (!enable_ept)
9887                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9888
9889         if (enable_vpid) {
9890                 /*
9891                  * Trivially support vpid by letting L2s share their parent
9892                  * L1's vpid. TODO: move to a more elaborate solution, giving
9893                  * each L2 its own vpid and exposing the vpid feature to L1.
9894                  */
9895                 vmx_flush_tlb(vcpu);
9896         }
9897
9898
9899         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9900         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9901         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9902         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9903         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9904
9905         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9906         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9907                 vmcs_write64(GUEST_BNDCFGS, 0);
9908
9909         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9910                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9911                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9912         }
9913         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9914                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9915                         vmcs12->host_ia32_perf_global_ctrl);
9916
9917         /* Set L1 segment info according to Intel SDM
9918             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9919         seg = (struct kvm_segment) {
9920                 .base = 0,
9921                 .limit = 0xFFFFFFFF,
9922                 .selector = vmcs12->host_cs_selector,
9923                 .type = 11,
9924                 .present = 1,
9925                 .s = 1,
9926                 .g = 1
9927         };
9928         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9929                 seg.l = 1;
9930         else
9931                 seg.db = 1;
9932         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9933         seg = (struct kvm_segment) {
9934                 .base = 0,
9935                 .limit = 0xFFFFFFFF,
9936                 .type = 3,
9937                 .present = 1,
9938                 .s = 1,
9939                 .db = 1,
9940                 .g = 1
9941         };
9942         seg.selector = vmcs12->host_ds_selector;
9943         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9944         seg.selector = vmcs12->host_es_selector;
9945         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9946         seg.selector = vmcs12->host_ss_selector;
9947         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9948         seg.selector = vmcs12->host_fs_selector;
9949         seg.base = vmcs12->host_fs_base;
9950         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9951         seg.selector = vmcs12->host_gs_selector;
9952         seg.base = vmcs12->host_gs_base;
9953         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9954         seg = (struct kvm_segment) {
9955                 .base = vmcs12->host_tr_base,
9956                 .limit = 0x67,
9957                 .selector = vmcs12->host_tr_selector,
9958                 .type = 11,
9959                 .present = 1
9960         };
9961         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9962
9963         kvm_set_dr(vcpu, 7, 0x400);
9964         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9965
9966         if (cpu_has_vmx_msr_bitmap())
9967                 vmx_set_msr_bitmap(vcpu);
9968
9969         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9970                                 vmcs12->vm_exit_msr_load_count))
9971                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9972 }
9973
9974 /*
9975  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9976  * and modify vmcs12 to make it see what it would expect to see there if
9977  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9978  */
9979 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9980                               u32 exit_intr_info,
9981                               unsigned long exit_qualification)
9982 {
9983         struct vcpu_vmx *vmx = to_vmx(vcpu);
9984         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9985
9986         /* trying to cancel vmlaunch/vmresume is a bug */
9987         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9988
9989         leave_guest_mode(vcpu);
9990         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9991                        exit_qualification);
9992
9993         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9994                                  vmcs12->vm_exit_msr_store_count))
9995                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9996
9997         vmx_load_vmcs01(vcpu);
9998
9999         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10000             && nested_exit_intr_ack_set(vcpu)) {
10001                 int irq = kvm_cpu_get_interrupt(vcpu);
10002                 WARN_ON(irq < 0);
10003                 vmcs12->vm_exit_intr_info = irq |
10004                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10005         }
10006
10007         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10008                                        vmcs12->exit_qualification,
10009                                        vmcs12->idt_vectoring_info_field,
10010                                        vmcs12->vm_exit_intr_info,
10011                                        vmcs12->vm_exit_intr_error_code,
10012                                        KVM_ISA_VMX);
10013
10014         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10015         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10016         vmx_segment_cache_clear(vmx);
10017
10018         /* if no vmcs02 cache requested, remove the one we used */
10019         if (VMCS02_POOL_SIZE == 0)
10020                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10021
10022         load_vmcs12_host_state(vcpu, vmcs12);
10023
10024         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10025         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10026
10027         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10028         vmx->host_rsp = 0;
10029
10030         /* Unpin physical memory we referred to in vmcs02 */
10031         if (vmx->nested.apic_access_page) {
10032                 nested_release_page(vmx->nested.apic_access_page);
10033                 vmx->nested.apic_access_page = NULL;
10034         }
10035         if (vmx->nested.virtual_apic_page) {
10036                 nested_release_page(vmx->nested.virtual_apic_page);
10037                 vmx->nested.virtual_apic_page = NULL;
10038         }
10039         if (vmx->nested.pi_desc_page) {
10040                 kunmap(vmx->nested.pi_desc_page);
10041                 nested_release_page(vmx->nested.pi_desc_page);
10042                 vmx->nested.pi_desc_page = NULL;
10043                 vmx->nested.pi_desc = NULL;
10044         }
10045
10046         /*
10047          * We are now running in L2, mmu_notifier will force to reload the
10048          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10049          */
10050         kvm_vcpu_reload_apic_access_page(vcpu);
10051
10052         /*
10053          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10054          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10055          * success or failure flag accordingly.
10056          */
10057         if (unlikely(vmx->fail)) {
10058                 vmx->fail = 0;
10059                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10060         } else
10061                 nested_vmx_succeed(vcpu);
10062         if (enable_shadow_vmcs)
10063                 vmx->nested.sync_shadow_vmcs = true;
10064
10065         /* in case we halted in L2 */
10066         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10067 }
10068
10069 /*
10070  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10071  */
10072 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10073 {
10074         if (is_guest_mode(vcpu))
10075                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10076         free_nested(to_vmx(vcpu));
10077 }
10078
10079 /*
10080  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10081  * 23.7 "VM-entry failures during or after loading guest state" (this also
10082  * lists the acceptable exit-reason and exit-qualification parameters).
10083  * It should only be called before L2 actually succeeded to run, and when
10084  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10085  */
10086 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10087                         struct vmcs12 *vmcs12,
10088                         u32 reason, unsigned long qualification)
10089 {
10090         load_vmcs12_host_state(vcpu, vmcs12);
10091         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10092         vmcs12->exit_qualification = qualification;
10093         nested_vmx_succeed(vcpu);
10094         if (enable_shadow_vmcs)
10095                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10096 }
10097
10098 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10099                                struct x86_instruction_info *info,
10100                                enum x86_intercept_stage stage)
10101 {
10102         return X86EMUL_CONTINUE;
10103 }
10104
10105 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10106 {
10107         if (ple_gap)
10108                 shrink_ple_window(vcpu);
10109 }
10110
10111 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10112                                      struct kvm_memory_slot *slot)
10113 {
10114         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10115         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10116 }
10117
10118 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10119                                        struct kvm_memory_slot *slot)
10120 {
10121         kvm_mmu_slot_set_dirty(kvm, slot);
10122 }
10123
10124 static void vmx_flush_log_dirty(struct kvm *kvm)
10125 {
10126         kvm_flush_pml_buffers(kvm);
10127 }
10128
10129 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10130                                            struct kvm_memory_slot *memslot,
10131                                            gfn_t offset, unsigned long mask)
10132 {
10133         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10134 }
10135
10136 static struct kvm_x86_ops vmx_x86_ops = {
10137         .cpu_has_kvm_support = cpu_has_kvm_support,
10138         .disabled_by_bios = vmx_disabled_by_bios,
10139         .hardware_setup = hardware_setup,
10140         .hardware_unsetup = hardware_unsetup,
10141         .check_processor_compatibility = vmx_check_processor_compat,
10142         .hardware_enable = hardware_enable,
10143         .hardware_disable = hardware_disable,
10144         .cpu_has_accelerated_tpr = report_flexpriority,
10145
10146         .vcpu_create = vmx_create_vcpu,
10147         .vcpu_free = vmx_free_vcpu,
10148         .vcpu_reset = vmx_vcpu_reset,
10149
10150         .prepare_guest_switch = vmx_save_host_state,
10151         .vcpu_load = vmx_vcpu_load,
10152         .vcpu_put = vmx_vcpu_put,
10153
10154         .update_db_bp_intercept = update_exception_bitmap,
10155         .get_msr = vmx_get_msr,
10156         .set_msr = vmx_set_msr,
10157         .get_segment_base = vmx_get_segment_base,
10158         .get_segment = vmx_get_segment,
10159         .set_segment = vmx_set_segment,
10160         .get_cpl = vmx_get_cpl,
10161         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10162         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10163         .decache_cr3 = vmx_decache_cr3,
10164         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10165         .set_cr0 = vmx_set_cr0,
10166         .set_cr3 = vmx_set_cr3,
10167         .set_cr4 = vmx_set_cr4,
10168         .set_efer = vmx_set_efer,
10169         .get_idt = vmx_get_idt,
10170         .set_idt = vmx_set_idt,
10171         .get_gdt = vmx_get_gdt,
10172         .set_gdt = vmx_set_gdt,
10173         .get_dr6 = vmx_get_dr6,
10174         .set_dr6 = vmx_set_dr6,
10175         .set_dr7 = vmx_set_dr7,
10176         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10177         .cache_reg = vmx_cache_reg,
10178         .get_rflags = vmx_get_rflags,
10179         .set_rflags = vmx_set_rflags,
10180         .fpu_deactivate = vmx_fpu_deactivate,
10181
10182         .tlb_flush = vmx_flush_tlb,
10183
10184         .run = vmx_vcpu_run,
10185         .handle_exit = vmx_handle_exit,
10186         .skip_emulated_instruction = skip_emulated_instruction,
10187         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10188         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10189         .patch_hypercall = vmx_patch_hypercall,
10190         .set_irq = vmx_inject_irq,
10191         .set_nmi = vmx_inject_nmi,
10192         .queue_exception = vmx_queue_exception,
10193         .cancel_injection = vmx_cancel_injection,
10194         .interrupt_allowed = vmx_interrupt_allowed,
10195         .nmi_allowed = vmx_nmi_allowed,
10196         .get_nmi_mask = vmx_get_nmi_mask,
10197         .set_nmi_mask = vmx_set_nmi_mask,
10198         .enable_nmi_window = enable_nmi_window,
10199         .enable_irq_window = enable_irq_window,
10200         .update_cr8_intercept = update_cr8_intercept,
10201         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10202         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10203         .vm_has_apicv = vmx_vm_has_apicv,
10204         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10205         .hwapic_irr_update = vmx_hwapic_irr_update,
10206         .hwapic_isr_update = vmx_hwapic_isr_update,
10207         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10208         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10209
10210         .set_tss_addr = vmx_set_tss_addr,
10211         .get_tdp_level = get_ept_level,
10212         .get_mt_mask = vmx_get_mt_mask,
10213
10214         .get_exit_info = vmx_get_exit_info,
10215
10216         .get_lpage_level = vmx_get_lpage_level,
10217
10218         .cpuid_update = vmx_cpuid_update,
10219
10220         .rdtscp_supported = vmx_rdtscp_supported,
10221         .invpcid_supported = vmx_invpcid_supported,
10222
10223         .set_supported_cpuid = vmx_set_supported_cpuid,
10224
10225         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10226
10227         .set_tsc_khz = vmx_set_tsc_khz,
10228         .read_tsc_offset = vmx_read_tsc_offset,
10229         .write_tsc_offset = vmx_write_tsc_offset,
10230         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10231         .compute_tsc_offset = vmx_compute_tsc_offset,
10232         .read_l1_tsc = vmx_read_l1_tsc,
10233
10234         .set_tdp_cr3 = vmx_set_cr3,
10235
10236         .check_intercept = vmx_check_intercept,
10237         .handle_external_intr = vmx_handle_external_intr,
10238         .mpx_supported = vmx_mpx_supported,
10239         .xsaves_supported = vmx_xsaves_supported,
10240
10241         .check_nested_events = vmx_check_nested_events,
10242
10243         .sched_in = vmx_sched_in,
10244
10245         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10246         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10247         .flush_log_dirty = vmx_flush_log_dirty,
10248         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10249 };
10250
10251 static int __init vmx_init(void)
10252 {
10253         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10254                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10255         if (r)
10256                 return r;
10257
10258 #ifdef CONFIG_KEXEC
10259         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10260                            crash_vmclear_local_loaded_vmcss);
10261 #endif
10262
10263         return 0;
10264 }
10265
10266 static void __exit vmx_exit(void)
10267 {
10268 #ifdef CONFIG_KEXEC
10269         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10270         synchronize_rcu();
10271 #endif
10272
10273         kvm_exit();
10274 }
10275
10276 module_init(vmx_init)
10277 module_exit(vmx_exit)