arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly emulate_invalid_guest_state = 0;
  75 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  76
  77 static bool __read_mostly vmm_exclusive = 1;
  78 module_param(vmm_exclusive, bool, S_IRUGO);
  79
  80 static bool __read_mostly fasteoi = 1;
  81 module_param(fasteoi, bool, S_IRUGO);
  82
  83 /*
  84  * If nested=1, nested virtualization is supported, i.e., guests may use
  85  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  86  * use VMX instructions.
  87  */
  88 static bool __read_mostly nested = 0;
  89 module_param(nested, bool, S_IRUGO);
  90
  91 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  92         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  93 #define KVM_GUEST_CR0_MASK                                              \
  94         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  95 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  96         (X86_CR0_WP | X86_CR0_NE)
  97 #define KVM_VM_CR0_ALWAYS_ON                                            \
  98         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  99 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 100         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 101          | X86_CR4_OSXMMEXCPT)
 102
 103 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 104 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 105
 106 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 107
 108 /*
 109  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 110  * ple_gap:    upper bound on the amount of time between two successive
 111  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 112  *             According to test, this time is usually smaller than 128 cycles.
 113  * ple_window: upper bound on the amount of time a guest is allowed to execute
 114  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 115  *             less than 2^12 cycles
 116  * Time is measured based on a counter that runs at the same rate as the TSC,
 117  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 118  */
 119 #define KVM_VMX_DEFAULT_PLE_GAP    128
 120 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 121 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 122 module_param(ple_gap, int, S_IRUGO);
 123
 124 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 125 module_param(ple_window, int, S_IRUGO);
 126
 127 #define NR_AUTOLOAD_MSRS 8
 128 #define VMCS02_POOL_SIZE 1
 129
 130 struct vmcs {
 131         u32 revision_id;
 132         u32 abort;
 133         char data[0];
 134 };
 135
 136 /*
 137  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 138  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 139  * loaded on this CPU (so we can clear them if the CPU goes down).
 140  */
 141 struct loaded_vmcs {
 142         struct vmcs *vmcs;
 143         int cpu;
 144         int launched;
 145         struct list_head loaded_vmcss_on_cpu_link;
 146 };
 147
 148 struct shared_msr_entry {
 149         unsigned index;
 150         u64 data;
 151         u64 mask;
 152 };
 153
 154 /*
 155  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 156  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 157  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 158  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 159  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 160  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 161  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 162  * underlying hardware which will be used to run L2.
 163  * This structure is packed to ensure that its layout is identical across
 164  * machines (necessary for live migration).
 165  * If there are changes in this struct, VMCS12_REVISION must be changed.
 166  */
 167 typedef u64 natural_width;
 168 struct __packed vmcs12 {
 169         /* According to the Intel spec, a VMCS region must start with the
 170          * following two fields. Then follow implementation-specific data.
 171          */
 172         u32 revision_id;
 173         u32 abort;
 174
 175         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 176         u32 padding[7]; /* room for future expansion */
 177
 178         u64 io_bitmap_a;
 179         u64 io_bitmap_b;
 180         u64 msr_bitmap;
 181         u64 vm_exit_msr_store_addr;
 182         u64 vm_exit_msr_load_addr;
 183         u64 vm_entry_msr_load_addr;
 184         u64 tsc_offset;
 185         u64 virtual_apic_page_addr;
 186         u64 apic_access_addr;
 187         u64 ept_pointer;
 188         u64 guest_physical_address;
 189         u64 vmcs_link_pointer;
 190         u64 guest_ia32_debugctl;
 191         u64 guest_ia32_pat;
 192         u64 guest_ia32_efer;
 193         u64 guest_ia32_perf_global_ctrl;
 194         u64 guest_pdptr0;
 195         u64 guest_pdptr1;
 196         u64 guest_pdptr2;
 197         u64 guest_pdptr3;
 198         u64 host_ia32_pat;
 199         u64 host_ia32_efer;
 200         u64 host_ia32_perf_global_ctrl;
 201         u64 padding64[8]; /* room for future expansion */
 202         /*
 203          * To allow migration of L1 (complete with its L2 guests) between
 204          * machines of different natural widths (32 or 64 bit), we cannot have
 205          * unsigned long fields with no explict size. We use u64 (aliased
 206          * natural_width) instead. Luckily, x86 is little-endian.
 207          */
 208         natural_width cr0_guest_host_mask;
 209         natural_width cr4_guest_host_mask;
 210         natural_width cr0_read_shadow;
 211         natural_width cr4_read_shadow;
 212         natural_width cr3_target_value0;
 213         natural_width cr3_target_value1;
 214         natural_width cr3_target_value2;
 215         natural_width cr3_target_value3;
 216         natural_width exit_qualification;
 217         natural_width guest_linear_address;
 218         natural_width guest_cr0;
 219         natural_width guest_cr3;
 220         natural_width guest_cr4;
 221         natural_width guest_es_base;
 222         natural_width guest_cs_base;
 223         natural_width guest_ss_base;
 224         natural_width guest_ds_base;
 225         natural_width guest_fs_base;
 226         natural_width guest_gs_base;
 227         natural_width guest_ldtr_base;
 228         natural_width guest_tr_base;
 229         natural_width guest_gdtr_base;
 230         natural_width guest_idtr_base;
 231         natural_width guest_dr7;
 232         natural_width guest_rsp;
 233         natural_width guest_rip;
 234         natural_width guest_rflags;
 235         natural_width guest_pending_dbg_exceptions;
 236         natural_width guest_sysenter_esp;
 237         natural_width guest_sysenter_eip;
 238         natural_width host_cr0;
 239         natural_width host_cr3;
 240         natural_width host_cr4;
 241         natural_width host_fs_base;
 242         natural_width host_gs_base;
 243         natural_width host_tr_base;
 244         natural_width host_gdtr_base;
 245         natural_width host_idtr_base;
 246         natural_width host_ia32_sysenter_esp;
 247         natural_width host_ia32_sysenter_eip;
 248         natural_width host_rsp;
 249         natural_width host_rip;
 250         natural_width paddingl[8]; /* room for future expansion */
 251         u32 pin_based_vm_exec_control;
 252         u32 cpu_based_vm_exec_control;
 253         u32 exception_bitmap;
 254         u32 page_fault_error_code_mask;
 255         u32 page_fault_error_code_match;
 256         u32 cr3_target_count;
 257         u32 vm_exit_controls;
 258         u32 vm_exit_msr_store_count;
 259         u32 vm_exit_msr_load_count;
 260         u32 vm_entry_controls;
 261         u32 vm_entry_msr_load_count;
 262         u32 vm_entry_intr_info_field;
 263         u32 vm_entry_exception_error_code;
 264         u32 vm_entry_instruction_len;
 265         u32 tpr_threshold;
 266         u32 secondary_vm_exec_control;
 267         u32 vm_instruction_error;
 268         u32 vm_exit_reason;
 269         u32 vm_exit_intr_info;
 270         u32 vm_exit_intr_error_code;
 271         u32 idt_vectoring_info_field;
 272         u32 idt_vectoring_error_code;
 273         u32 vm_exit_instruction_len;
 274         u32 vmx_instruction_info;
 275         u32 guest_es_limit;
 276         u32 guest_cs_limit;
 277         u32 guest_ss_limit;
 278         u32 guest_ds_limit;
 279         u32 guest_fs_limit;
 280         u32 guest_gs_limit;
 281         u32 guest_ldtr_limit;
 282         u32 guest_tr_limit;
 283         u32 guest_gdtr_limit;
 284         u32 guest_idtr_limit;
 285         u32 guest_es_ar_bytes;
 286         u32 guest_cs_ar_bytes;
 287         u32 guest_ss_ar_bytes;
 288         u32 guest_ds_ar_bytes;
 289         u32 guest_fs_ar_bytes;
 290         u32 guest_gs_ar_bytes;
 291         u32 guest_ldtr_ar_bytes;
 292         u32 guest_tr_ar_bytes;
 293         u32 guest_interruptibility_info;
 294         u32 guest_activity_state;
 295         u32 guest_sysenter_cs;
 296         u32 host_ia32_sysenter_cs;
 297         u32 padding32[8]; /* room for future expansion */
 298         u16 virtual_processor_id;
 299         u16 guest_es_selector;
 300         u16 guest_cs_selector;
 301         u16 guest_ss_selector;
 302         u16 guest_ds_selector;
 303         u16 guest_fs_selector;
 304         u16 guest_gs_selector;
 305         u16 guest_ldtr_selector;
 306         u16 guest_tr_selector;
 307         u16 host_es_selector;
 308         u16 host_cs_selector;
 309         u16 host_ss_selector;
 310         u16 host_ds_selector;
 311         u16 host_fs_selector;
 312         u16 host_gs_selector;
 313         u16 host_tr_selector;
 314 };
 315
 316 /*
 317  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 318  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 319  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 320  */
 321 #define VMCS12_REVISION 0x11e57ed0
 322
 323 /*
 324  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 325  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 326  * current implementation, 4K are reserved to avoid future complications.
 327  */
 328 #define VMCS12_SIZE 0x1000
 329
 330 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 331 struct vmcs02_list {
 332         struct list_head list;
 333         gpa_t vmptr;
 334         struct loaded_vmcs vmcs02;
 335 };
 336
 337 /*
 338  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 339  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 340  */
 341 struct nested_vmx {
 342         /* Has the level1 guest done vmxon? */
 343         bool vmxon;
 344
 345         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 346         gpa_t current_vmptr;
 347         /* The host-usable pointer to the above */
 348         struct page *current_vmcs12_page;
 349         struct vmcs12 *current_vmcs12;
 350
 351         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 352         struct list_head vmcs02_pool;
 353         int vmcs02_num;
 354         u64 vmcs01_tsc_offset;
 355         /* L2 must run next, and mustn't decide to exit to L1. */
 356         bool nested_run_pending;
 357         /*
 358          * Guest pages referred to in vmcs02 with host-physical pointers, so
 359          * we must keep them pinned while L2 runs.
 360          */
 361         struct page *apic_access_page;
 362 };
 363
 364 struct vcpu_vmx {
 365         struct kvm_vcpu       vcpu;
 366         unsigned long         host_rsp;
 367         u8                    fail;
 368         u8                    cpl;
 369         bool                  nmi_known_unmasked;
 370         u32                   exit_intr_info;
 371         u32                   idt_vectoring_info;
 372         ulong                 rflags;
 373         struct shared_msr_entry *guest_msrs;
 374         int                   nmsrs;
 375         int                   save_nmsrs;
 376 #ifdef CONFIG_X86_64
 377         u64                   msr_host_kernel_gs_base;
 378         u64                   msr_guest_kernel_gs_base;
 379 #endif
 380         /*
 381          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 382          * non-nested (L1) guest, it always points to vmcs01. For a nested
 383          * guest (L2), it points to a different VMCS.
 384          */
 385         struct loaded_vmcs    vmcs01;
 386         struct loaded_vmcs   *loaded_vmcs;
 387         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 388         struct msr_autoload {
 389                 unsigned nr;
 390                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 391                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 392         } msr_autoload;
 393         struct {
 394                 int           loaded;
 395                 u16           fs_sel, gs_sel, ldt_sel;
 396                 int           gs_ldt_reload_needed;
 397                 int           fs_reload_needed;
 398         } host_state;
 399         struct {
 400                 int vm86_active;
 401                 ulong save_rflags;
 402                 struct kvm_save_segment {
 403                         u16 selector;
 404                         unsigned long base;
 405                         u32 limit;
 406                         u32 ar;
 407                 } tr, es, ds, fs, gs;
 408         } rmode;
 409         struct {
 410                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 411                 struct kvm_save_segment seg[8];
 412         } segment_cache;
 413         int vpid;
 414         bool emulation_required;
 415
 416         /* Support for vnmi-less CPUs */
 417         int soft_vnmi_blocked;
 418         ktime_t entry_time;
 419         s64 vnmi_blocked_time;
 420         u32 exit_reason;
 421
 422         bool rdtscp_enabled;
 423
 424         /* Support for a guest hypervisor (nested VMX) */
 425         struct nested_vmx nested;
 426 };
 427
 428 enum segment_cache_field {
 429         SEG_FIELD_SEL = 0,
 430         SEG_FIELD_BASE = 1,
 431         SEG_FIELD_LIMIT = 2,
 432         SEG_FIELD_AR = 3,
 433
 434         SEG_FIELD_NR = 4
 435 };
 436
 437 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 438 {
 439         return container_of(vcpu, struct vcpu_vmx, vcpu);
 440 }
 441
 442 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 443 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 444 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 445                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 446
 447 static unsigned short vmcs_field_to_offset_table[] = {
 448         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 449         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 450         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 451         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 452         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 453         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 454         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 455         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 456         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 457         FIELD(HOST_ES_SELECTOR, host_es_selector),
 458         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 459         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 460         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 461         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 462         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 463         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 464         FIELD64(IO_BITMAP_A, io_bitmap_a),
 465         FIELD64(IO_BITMAP_B, io_bitmap_b),
 466         FIELD64(MSR_BITMAP, msr_bitmap),
 467         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 468         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 469         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 470         FIELD64(TSC_OFFSET, tsc_offset),
 471         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 472         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 473         FIELD64(EPT_POINTER, ept_pointer),
 474         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 475         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 476         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 477         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 478         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 479         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 480         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 481         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 482         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 483         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 484         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 485         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 486         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 487         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 488         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 489         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 490         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 491         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 492         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 493         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 494         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 495         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 496         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 497         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 498         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 499         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 500         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 501         FIELD(TPR_THRESHOLD, tpr_threshold),
 502         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 503         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 504         FIELD(VM_EXIT_REASON, vm_exit_reason),
 505         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 506         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 507         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 508         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 509         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 510         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 511         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 512         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 513         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 514         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 515         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 516         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 517         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 518         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 519         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 520         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 521         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 522         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 523         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 524         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 525         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 526         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 527         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 528         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 529         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 530         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 531         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 532         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 533         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 534         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 535         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 536         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 537         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 538         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 539         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 540         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 541         FIELD(EXIT_QUALIFICATION, exit_qualification),
 542         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 543         FIELD(GUEST_CR0, guest_cr0),
 544         FIELD(GUEST_CR3, guest_cr3),
 545         FIELD(GUEST_CR4, guest_cr4),
 546         FIELD(GUEST_ES_BASE, guest_es_base),
 547         FIELD(GUEST_CS_BASE, guest_cs_base),
 548         FIELD(GUEST_SS_BASE, guest_ss_base),
 549         FIELD(GUEST_DS_BASE, guest_ds_base),
 550         FIELD(GUEST_FS_BASE, guest_fs_base),
 551         FIELD(GUEST_GS_BASE, guest_gs_base),
 552         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 553         FIELD(GUEST_TR_BASE, guest_tr_base),
 554         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 555         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 556         FIELD(GUEST_DR7, guest_dr7),
 557         FIELD(GUEST_RSP, guest_rsp),
 558         FIELD(GUEST_RIP, guest_rip),
 559         FIELD(GUEST_RFLAGS, guest_rflags),
 560         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 561         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 562         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 563         FIELD(HOST_CR0, host_cr0),
 564         FIELD(HOST_CR3, host_cr3),
 565         FIELD(HOST_CR4, host_cr4),
 566         FIELD(HOST_FS_BASE, host_fs_base),
 567         FIELD(HOST_GS_BASE, host_gs_base),
 568         FIELD(HOST_TR_BASE, host_tr_base),
 569         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 570         FIELD(HOST_IDTR_BASE, host_idtr_base),
 571         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 572         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 573         FIELD(HOST_RSP, host_rsp),
 574         FIELD(HOST_RIP, host_rip),
 575 };
 576 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 577
 578 static inline short vmcs_field_to_offset(unsigned long field)
 579 {
 580         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 581                 return -1;
 582         return vmcs_field_to_offset_table[field];
 583 }
 584
 585 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 586 {
 587         return to_vmx(vcpu)->nested.current_vmcs12;
 588 }
 589
 590 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 591 {
 592         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 593         if (is_error_page(page)) {
 594                 kvm_release_page_clean(page);
 595                 return NULL;
 596         }
 597         return page;
 598 }
 599
 600 static void nested_release_page(struct page *page)
 601 {
 602         kvm_release_page_dirty(page);
 603 }
 604
 605 static void nested_release_page_clean(struct page *page)
 606 {
 607         kvm_release_page_clean(page);
 608 }
 609
 610 static u64 construct_eptp(unsigned long root_hpa);
 611 static void kvm_cpu_vmxon(u64 addr);
 612 static void kvm_cpu_vmxoff(void);
 613 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 614 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 615
 616 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 617 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 618 /*
 619  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 620  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 621  */
 622 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 623 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 624
 625 static unsigned long *vmx_io_bitmap_a;
 626 static unsigned long *vmx_io_bitmap_b;
 627 static unsigned long *vmx_msr_bitmap_legacy;
 628 static unsigned long *vmx_msr_bitmap_longmode;
 629
 630 static bool cpu_has_load_ia32_efer;
 631 static bool cpu_has_load_perf_global_ctrl;
 632
 633 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 634 static DEFINE_SPINLOCK(vmx_vpid_lock);
 635
 636 static struct vmcs_config {
 637         int size;
 638         int order;
 639         u32 revision_id;
 640         u32 pin_based_exec_ctrl;
 641         u32 cpu_based_exec_ctrl;
 642         u32 cpu_based_2nd_exec_ctrl;
 643         u32 vmexit_ctrl;
 644         u32 vmentry_ctrl;
 645 } vmcs_config;
 646
 647 static struct vmx_capability {
 648         u32 ept;
 649         u32 vpid;
 650 } vmx_capability;
 651
 652 #define VMX_SEGMENT_FIELD(seg)                                  \
 653         [VCPU_SREG_##seg] = {                                   \
 654                 .selector = GUEST_##seg##_SELECTOR,             \
 655                 .base = GUEST_##seg##_BASE,                     \
 656                 .limit = GUEST_##seg##_LIMIT,                   \
 657                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 658         }
 659
 660 static struct kvm_vmx_segment_field {
 661         unsigned selector;
 662         unsigned base;
 663         unsigned limit;
 664         unsigned ar_bytes;
 665 } kvm_vmx_segment_fields[] = {
 666         VMX_SEGMENT_FIELD(CS),
 667         VMX_SEGMENT_FIELD(DS),
 668         VMX_SEGMENT_FIELD(ES),
 669         VMX_SEGMENT_FIELD(FS),
 670         VMX_SEGMENT_FIELD(GS),
 671         VMX_SEGMENT_FIELD(SS),
 672         VMX_SEGMENT_FIELD(TR),
 673         VMX_SEGMENT_FIELD(LDTR),
 674 };
 675
 676 static u64 host_efer;
 677
 678 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 679
 680 /*
 681  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 682  * away by decrementing the array size.
 683  */
 684 static const u32 vmx_msr_index[] = {
 685 #ifdef CONFIG_X86_64
 686         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 687 #endif
 688         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 689 };
 690 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 691
 692 static inline bool is_page_fault(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_no_device(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_invalid_opcode(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 709                              INTR_INFO_VALID_MASK)) ==
 710                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 711 }
 712
 713 static inline bool is_external_interrupt(u32 intr_info)
 714 {
 715         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 716                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool is_machine_check(u32 intr_info)
 720 {
 721         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 722                              INTR_INFO_VALID_MASK)) ==
 723                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 724 }
 725
 726 static inline bool cpu_has_vmx_msr_bitmap(void)
 727 {
 728         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 729 }
 730
 731 static inline bool cpu_has_vmx_tpr_shadow(void)
 732 {
 733         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 734 }
 735
 736 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 737 {
 738         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 739 }
 740
 741 static inline bool cpu_has_secondary_exec_ctrls(void)
 742 {
 743         return vmcs_config.cpu_based_exec_ctrl &
 744                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 745 }
 746
 747 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 748 {
 749         return vmcs_config.cpu_based_2nd_exec_ctrl &
 750                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 751 }
 752
 753 static inline bool cpu_has_vmx_flexpriority(void)
 754 {
 755         return cpu_has_vmx_tpr_shadow() &&
 756                 cpu_has_vmx_virtualize_apic_accesses();
 757 }
 758
 759 static inline bool cpu_has_vmx_ept_execute_only(void)
 760 {
 761         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 762 }
 763
 764 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 765 {
 766         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 767 }
 768
 769 static inline bool cpu_has_vmx_eptp_writeback(void)
 770 {
 771         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_ept_2m_page(void)
 775 {
 776         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_ept_1g_page(void)
 780 {
 781         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_ept_4levels(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_invept_individual_addr(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_invept_context(void)
 795 {
 796         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_invept_global(void)
 800 {
 801         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_invvpid_single(void)
 805 {
 806         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 807 }
 808
 809 static inline bool cpu_has_vmx_invvpid_global(void)
 810 {
 811         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 812 }
 813
 814 static inline bool cpu_has_vmx_ept(void)
 815 {
 816         return vmcs_config.cpu_based_2nd_exec_ctrl &
 817                 SECONDARY_EXEC_ENABLE_EPT;
 818 }
 819
 820 static inline bool cpu_has_vmx_unrestricted_guest(void)
 821 {
 822         return vmcs_config.cpu_based_2nd_exec_ctrl &
 823                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 824 }
 825
 826 static inline bool cpu_has_vmx_ple(void)
 827 {
 828         return vmcs_config.cpu_based_2nd_exec_ctrl &
 829                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 830 }
 831
 832 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 833 {
 834         return flexpriority_enabled && irqchip_in_kernel(kvm);
 835 }
 836
 837 static inline bool cpu_has_vmx_vpid(void)
 838 {
 839         return vmcs_config.cpu_based_2nd_exec_ctrl &
 840                 SECONDARY_EXEC_ENABLE_VPID;
 841 }
 842
 843 static inline bool cpu_has_vmx_rdtscp(void)
 844 {
 845         return vmcs_config.cpu_based_2nd_exec_ctrl &
 846                 SECONDARY_EXEC_RDTSCP;
 847 }
 848
 849 static inline bool cpu_has_virtual_nmis(void)
 850 {
 851         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 852 }
 853
 854 static inline bool cpu_has_vmx_wbinvd_exit(void)
 855 {
 856         return vmcs_config.cpu_based_2nd_exec_ctrl &
 857                 SECONDARY_EXEC_WBINVD_EXITING;
 858 }
 859
 860 static inline bool report_flexpriority(void)
 861 {
 862         return flexpriority_enabled;
 863 }
 864
 865 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 866 {
 867         return vmcs12->cpu_based_vm_exec_control & bit;
 868 }
 869
 870 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 871 {
 872         return (vmcs12->cpu_based_vm_exec_control &
 873                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 874                 (vmcs12->secondary_vm_exec_control & bit);
 875 }
 876
 877 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 878         struct kvm_vcpu *vcpu)
 879 {
 880         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 881 }
 882
 883 static inline bool is_exception(u32 intr_info)
 884 {
 885         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 886                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 887 }
 888
 889 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 890 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 891                         struct vmcs12 *vmcs12,
 892                         u32 reason, unsigned long qualification);
 893
 894 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 895 {
 896         int i;
 897
 898         for (i = 0; i < vmx->nmsrs; ++i)
 899                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 900                         return i;
 901         return -1;
 902 }
 903
 904 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 905 {
 906     struct {
 907         u64 vpid : 16;
 908         u64 rsvd : 48;
 909         u64 gva;
 910     } operand = { vpid, 0, gva };
 911
 912     asm volatile (__ex(ASM_VMX_INVVPID)
 913                   /* CF==1 or ZF==1 --> rc = -1 */
 914                   "; ja 1f ; ud2 ; 1:"
 915                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 916 }
 917
 918 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 919 {
 920         struct {
 921                 u64 eptp, gpa;
 922         } operand = {eptp, gpa};
 923
 924         asm volatile (__ex(ASM_VMX_INVEPT)
 925                         /* CF==1 or ZF==1 --> rc = -1 */
 926                         "; ja 1f ; ud2 ; 1:\n"
 927                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 928 }
 929
 930 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 931 {
 932         int i;
 933
 934         i = __find_msr_index(vmx, msr);
 935         if (i >= 0)
 936                 return &vmx->guest_msrs[i];
 937         return NULL;
 938 }
 939
 940 static void vmcs_clear(struct vmcs *vmcs)
 941 {
 942         u64 phys_addr = __pa(vmcs);
 943         u8 error;
 944
 945         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 946                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 947                       : "cc", "memory");
 948         if (error)
 949                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 950                        vmcs, phys_addr);
 951 }
 952
 953 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 954 {
 955         vmcs_clear(loaded_vmcs->vmcs);
 956         loaded_vmcs->cpu = -1;
 957         loaded_vmcs->launched = 0;
 958 }
 959
 960 static void vmcs_load(struct vmcs *vmcs)
 961 {
 962         u64 phys_addr = __pa(vmcs);
 963         u8 error;
 964
 965         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 966                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 967                         : "cc", "memory");
 968         if (error)
 969                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 970                        vmcs, phys_addr);
 971 }
 972
 973 static void __loaded_vmcs_clear(void *arg)
 974 {
 975         struct loaded_vmcs *loaded_vmcs = arg;
 976         int cpu = raw_smp_processor_id();
 977
 978         if (loaded_vmcs->cpu != cpu)
 979                 return; /* vcpu migration can race with cpu offline */
 980         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 981                 per_cpu(current_vmcs, cpu) = NULL;
 982         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 983         loaded_vmcs_init(loaded_vmcs);
 984 }
 985
 986 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 987 {
 988         if (loaded_vmcs->cpu != -1)
 989                 smp_call_function_single(
 990                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 991 }
 992
 993 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 994 {
 995         if (vmx->vpid == 0)
 996                 return;
 997
 998         if (cpu_has_vmx_invvpid_single())
 999                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1000 }
1001
1002 static inline void vpid_sync_vcpu_global(void)
1003 {
1004         if (cpu_has_vmx_invvpid_global())
1005                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1006 }
1007
1008 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1009 {
1010         if (cpu_has_vmx_invvpid_single())
1011                 vpid_sync_vcpu_single(vmx);
1012         else
1013                 vpid_sync_vcpu_global();
1014 }
1015
1016 static inline void ept_sync_global(void)
1017 {
1018         if (cpu_has_vmx_invept_global())
1019                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1020 }
1021
1022 static inline void ept_sync_context(u64 eptp)
1023 {
1024         if (enable_ept) {
1025                 if (cpu_has_vmx_invept_context())
1026                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1027                 else
1028                         ept_sync_global();
1029         }
1030 }
1031
1032 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1033 {
1034         if (enable_ept) {
1035                 if (cpu_has_vmx_invept_individual_addr())
1036                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1037                                         eptp, gpa);
1038                 else
1039                         ept_sync_context(eptp);
1040         }
1041 }
1042
1043 static __always_inline unsigned long vmcs_readl(unsigned long field)
1044 {
1045         unsigned long value;
1046
1047         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1048                       : "=a"(value) : "d"(field) : "cc");
1049         return value;
1050 }
1051
1052 static __always_inline u16 vmcs_read16(unsigned long field)
1053 {
1054         return vmcs_readl(field);
1055 }
1056
1057 static __always_inline u32 vmcs_read32(unsigned long field)
1058 {
1059         return vmcs_readl(field);
1060 }
1061
1062 static __always_inline u64 vmcs_read64(unsigned long field)
1063 {
1064 #ifdef CONFIG_X86_64
1065         return vmcs_readl(field);
1066 #else
1067         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1068 #endif
1069 }
1070
1071 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1072 {
1073         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1074                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1075         dump_stack();
1076 }
1077
1078 static void vmcs_writel(unsigned long field, unsigned long value)
1079 {
1080         u8 error;
1081
1082         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1083                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1084         if (unlikely(error))
1085                 vmwrite_error(field, value);
1086 }
1087
1088 static void vmcs_write16(unsigned long field, u16 value)
1089 {
1090         vmcs_writel(field, value);
1091 }
1092
1093 static void vmcs_write32(unsigned long field, u32 value)
1094 {
1095         vmcs_writel(field, value);
1096 }
1097
1098 static void vmcs_write64(unsigned long field, u64 value)
1099 {
1100         vmcs_writel(field, value);
1101 #ifndef CONFIG_X86_64
1102         asm volatile ("");
1103         vmcs_writel(field+1, value >> 32);
1104 #endif
1105 }
1106
1107 static void vmcs_clear_bits(unsigned long field, u32 mask)
1108 {
1109         vmcs_writel(field, vmcs_readl(field) & ~mask);
1110 }
1111
1112 static void vmcs_set_bits(unsigned long field, u32 mask)
1113 {
1114         vmcs_writel(field, vmcs_readl(field) | mask);
1115 }
1116
1117 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1118 {
1119         vmx->segment_cache.bitmask = 0;
1120 }
1121
1122 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1123                                        unsigned field)
1124 {
1125         bool ret;
1126         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1127
1128         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1129                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1130                 vmx->segment_cache.bitmask = 0;
1131         }
1132         ret = vmx->segment_cache.bitmask & mask;
1133         vmx->segment_cache.bitmask |= mask;
1134         return ret;
1135 }
1136
1137 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1138 {
1139         u16 *p = &vmx->segment_cache.seg[seg].selector;
1140
1141         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1142                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1143         return *p;
1144 }
1145
1146 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1147 {
1148         ulong *p = &vmx->segment_cache.seg[seg].base;
1149
1150         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1151                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1152         return *p;
1153 }
1154
1155 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1156 {
1157         u32 *p = &vmx->segment_cache.seg[seg].limit;
1158
1159         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1160                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1161         return *p;
1162 }
1163
1164 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1165 {
1166         u32 *p = &vmx->segment_cache.seg[seg].ar;
1167
1168         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1169                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1170         return *p;
1171 }
1172
1173 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1174 {
1175         u32 eb;
1176
1177         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1178              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1179         if ((vcpu->guest_debug &
1180              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1181             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1182                 eb |= 1u << BP_VECTOR;
1183         if (to_vmx(vcpu)->rmode.vm86_active)
1184                 eb = ~0;
1185         if (enable_ept)
1186                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1187         if (vcpu->fpu_active)
1188                 eb &= ~(1u << NM_VECTOR);
1189
1190         /* When we are running a nested L2 guest and L1 specified for it a
1191          * certain exception bitmap, we must trap the same exceptions and pass
1192          * them to L1. When running L2, we will only handle the exceptions
1193          * specified above if L1 did not want them.
1194          */
1195         if (is_guest_mode(vcpu))
1196                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1197
1198         vmcs_write32(EXCEPTION_BITMAP, eb);
1199 }
1200
1201 static void clear_atomic_switch_msr_special(unsigned long entry,
1202                 unsigned long exit)
1203 {
1204         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1205         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1206 }
1207
1208 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1209 {
1210         unsigned i;
1211         struct msr_autoload *m = &vmx->msr_autoload;
1212
1213         switch (msr) {
1214         case MSR_EFER:
1215                 if (cpu_has_load_ia32_efer) {
1216                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1217                                         VM_EXIT_LOAD_IA32_EFER);
1218                         return;
1219                 }
1220                 break;
1221         case MSR_CORE_PERF_GLOBAL_CTRL:
1222                 if (cpu_has_load_perf_global_ctrl) {
1223                         clear_atomic_switch_msr_special(
1224                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1225                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1226                         return;
1227                 }
1228                 break;
1229         }
1230
1231         for (i = 0; i < m->nr; ++i)
1232                 if (m->guest[i].index == msr)
1233                         break;
1234
1235         if (i == m->nr)
1236                 return;
1237         --m->nr;
1238         m->guest[i] = m->guest[m->nr];
1239         m->host[i] = m->host[m->nr];
1240         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1241         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1242 }
1243
1244 static void add_atomic_switch_msr_special(unsigned long entry,
1245                 unsigned long exit, unsigned long guest_val_vmcs,
1246                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1247 {
1248         vmcs_write64(guest_val_vmcs, guest_val);
1249         vmcs_write64(host_val_vmcs, host_val);
1250         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1251         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1252 }
1253
1254 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1255                                   u64 guest_val, u64 host_val)
1256 {
1257         unsigned i;
1258         struct msr_autoload *m = &vmx->msr_autoload;
1259
1260         switch (msr) {
1261         case MSR_EFER:
1262                 if (cpu_has_load_ia32_efer) {
1263                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1264                                         VM_EXIT_LOAD_IA32_EFER,
1265                                         GUEST_IA32_EFER,
1266                                         HOST_IA32_EFER,
1267                                         guest_val, host_val);
1268                         return;
1269                 }
1270                 break;
1271         case MSR_CORE_PERF_GLOBAL_CTRL:
1272                 if (cpu_has_load_perf_global_ctrl) {
1273                         add_atomic_switch_msr_special(
1274                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1275                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1276                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1277                                         HOST_IA32_PERF_GLOBAL_CTRL,
1278                                         guest_val, host_val);
1279                         return;
1280                 }
1281                 break;
1282         }
1283
1284         for (i = 0; i < m->nr; ++i)
1285                 if (m->guest[i].index == msr)
1286                         break;
1287
1288         if (i == NR_AUTOLOAD_MSRS) {
1289                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1290                                 "Can't add msr %x\n", msr);
1291                 return;
1292         } else if (i == m->nr) {
1293                 ++m->nr;
1294                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1295                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1296         }
1297
1298         m->guest[i].index = msr;
1299         m->guest[i].value = guest_val;
1300         m->host[i].index = msr;
1301         m->host[i].value = host_val;
1302 }
1303
1304 static void reload_tss(void)
1305 {
1306         /*
1307          * VT restores TR but not its size.  Useless.
1308          */
1309         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1310         struct desc_struct *descs;
1311
1312         descs = (void *)gdt->address;
1313         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1314         load_TR_desc();
1315 }
1316
1317 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1318 {
1319         u64 guest_efer;
1320         u64 ignore_bits;
1321
1322         guest_efer = vmx->vcpu.arch.efer;
1323
1324         /*
1325          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1326          * outside long mode
1327          */
1328         ignore_bits = EFER_NX | EFER_SCE;
1329 #ifdef CONFIG_X86_64
1330         ignore_bits |= EFER_LMA | EFER_LME;
1331         /* SCE is meaningful only in long mode on Intel */
1332         if (guest_efer & EFER_LMA)
1333                 ignore_bits &= ~(u64)EFER_SCE;
1334 #endif
1335         guest_efer &= ~ignore_bits;
1336         guest_efer |= host_efer & ignore_bits;
1337         vmx->guest_msrs[efer_offset].data = guest_efer;
1338         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1339
1340         clear_atomic_switch_msr(vmx, MSR_EFER);
1341         /* On ept, can't emulate nx, and must switch nx atomically */
1342         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1343                 guest_efer = vmx->vcpu.arch.efer;
1344                 if (!(guest_efer & EFER_LMA))
1345                         guest_efer &= ~EFER_LME;
1346                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1347                 return false;
1348         }
1349
1350         return true;
1351 }
1352
1353 static unsigned long segment_base(u16 selector)
1354 {
1355         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1356         struct desc_struct *d;
1357         unsigned long table_base;
1358         unsigned long v;
1359
1360         if (!(selector & ~3))
1361                 return 0;
1362
1363         table_base = gdt->address;
1364
1365         if (selector & 4) {           /* from ldt */
1366                 u16 ldt_selector = kvm_read_ldt();
1367
1368                 if (!(ldt_selector & ~3))
1369                         return 0;
1370
1371                 table_base = segment_base(ldt_selector);
1372         }
1373         d = (struct desc_struct *)(table_base + (selector & ~7));
1374         v = get_desc_base(d);
1375 #ifdef CONFIG_X86_64
1376        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1377                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1378 #endif
1379         return v;
1380 }
1381
1382 static inline unsigned long kvm_read_tr_base(void)
1383 {
1384         u16 tr;
1385         asm("str %0" : "=g"(tr));
1386         return segment_base(tr);
1387 }
1388
1389 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1390 {
1391         struct vcpu_vmx *vmx = to_vmx(vcpu);
1392         int i;
1393
1394         if (vmx->host_state.loaded)
1395                 return;
1396
1397         vmx->host_state.loaded = 1;
1398         /*
1399          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1400          * allow segment selectors with cpl > 0 or ti == 1.
1401          */
1402         vmx->host_state.ldt_sel = kvm_read_ldt();
1403         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1404         savesegment(fs, vmx->host_state.fs_sel);
1405         if (!(vmx->host_state.fs_sel & 7)) {
1406                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1407                 vmx->host_state.fs_reload_needed = 0;
1408         } else {
1409                 vmcs_write16(HOST_FS_SELECTOR, 0);
1410                 vmx->host_state.fs_reload_needed = 1;
1411         }
1412         savesegment(gs, vmx->host_state.gs_sel);
1413         if (!(vmx->host_state.gs_sel & 7))
1414                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1415         else {
1416                 vmcs_write16(HOST_GS_SELECTOR, 0);
1417                 vmx->host_state.gs_ldt_reload_needed = 1;
1418         }
1419
1420 #ifdef CONFIG_X86_64
1421         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1422         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1423 #else
1424         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1425         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1426 #endif
1427
1428 #ifdef CONFIG_X86_64
1429         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1430         if (is_long_mode(&vmx->vcpu))
1431                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1432 #endif
1433         for (i = 0; i < vmx->save_nmsrs; ++i)
1434                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1435                                    vmx->guest_msrs[i].data,
1436                                    vmx->guest_msrs[i].mask);
1437 }
1438
1439 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1440 {
1441         if (!vmx->host_state.loaded)
1442                 return;
1443
1444         ++vmx->vcpu.stat.host_state_reload;
1445         vmx->host_state.loaded = 0;
1446 #ifdef CONFIG_X86_64
1447         if (is_long_mode(&vmx->vcpu))
1448                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1449 #endif
1450         if (vmx->host_state.gs_ldt_reload_needed) {
1451                 kvm_load_ldt(vmx->host_state.ldt_sel);
1452 #ifdef CONFIG_X86_64
1453                 load_gs_index(vmx->host_state.gs_sel);
1454 #else
1455                 loadsegment(gs, vmx->host_state.gs_sel);
1456 #endif
1457         }
1458         if (vmx->host_state.fs_reload_needed)
1459                 loadsegment(fs, vmx->host_state.fs_sel);
1460         reload_tss();
1461 #ifdef CONFIG_X86_64
1462         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1463 #endif
1464         if (user_has_fpu())
1465                 clts();
1466         load_gdt(&__get_cpu_var(host_gdt));
1467 }
1468
1469 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1470 {
1471         preempt_disable();
1472         __vmx_load_host_state(vmx);
1473         preempt_enable();
1474 }
1475
1476 /*
1477  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1478  * vcpu mutex is already taken.
1479  */
1480 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1481 {
1482         struct vcpu_vmx *vmx = to_vmx(vcpu);
1483         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1484
1485         if (!vmm_exclusive)
1486                 kvm_cpu_vmxon(phys_addr);
1487         else if (vmx->loaded_vmcs->cpu != cpu)
1488                 loaded_vmcs_clear(vmx->loaded_vmcs);
1489
1490         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1491                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1492                 vmcs_load(vmx->loaded_vmcs->vmcs);
1493         }
1494
1495         if (vmx->loaded_vmcs->cpu != cpu) {
1496                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1497                 unsigned long sysenter_esp;
1498
1499                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1500                 local_irq_disable();
1501                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1502                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1503                 local_irq_enable();
1504
1505                 /*
1506                  * Linux uses per-cpu TSS and GDT, so set these when switching
1507                  * processors.
1508                  */
1509                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1510                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1511
1512                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1513                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1514                 vmx->loaded_vmcs->cpu = cpu;
1515         }
1516 }
1517
1518 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1519 {
1520         __vmx_load_host_state(to_vmx(vcpu));
1521         if (!vmm_exclusive) {
1522                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1523                 vcpu->cpu = -1;
1524                 kvm_cpu_vmxoff();
1525         }
1526 }
1527
1528 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1529 {
1530         ulong cr0;
1531
1532         if (vcpu->fpu_active)
1533                 return;
1534         vcpu->fpu_active = 1;
1535         cr0 = vmcs_readl(GUEST_CR0);
1536         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1537         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1538         vmcs_writel(GUEST_CR0, cr0);
1539         update_exception_bitmap(vcpu);
1540         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1541         if (is_guest_mode(vcpu))
1542                 vcpu->arch.cr0_guest_owned_bits &=
1543                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1544         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1545 }
1546
1547 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1548
1549 /*
1550  * Return the cr0 value that a nested guest would read. This is a combination
1551  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1552  * its hypervisor (cr0_read_shadow).
1553  */
1554 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1555 {
1556         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1557                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1558 }
1559 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1560 {
1561         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1562                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1563 }
1564
1565 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1566 {
1567         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1568          * set this *before* calling this function.
1569          */
1570         vmx_decache_cr0_guest_bits(vcpu);
1571         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1572         update_exception_bitmap(vcpu);
1573         vcpu->arch.cr0_guest_owned_bits = 0;
1574         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1575         if (is_guest_mode(vcpu)) {
1576                 /*
1577                  * L1's specified read shadow might not contain the TS bit,
1578                  * so now that we turned on shadowing of this bit, we need to
1579                  * set this bit of the shadow. Like in nested_vmx_run we need
1580                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1581                  * up-to-date here because we just decached cr0.TS (and we'll
1582                  * only update vmcs12->guest_cr0 on nested exit).
1583                  */
1584                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1585                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1586                         (vcpu->arch.cr0 & X86_CR0_TS);
1587                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1588         } else
1589                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1590 }
1591
1592 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1593 {
1594         unsigned long rflags, save_rflags;
1595
1596         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1597                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1598                 rflags = vmcs_readl(GUEST_RFLAGS);
1599                 if (to_vmx(vcpu)->rmode.vm86_active) {
1600                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1601                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1602                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1603                 }
1604                 to_vmx(vcpu)->rflags = rflags;
1605         }
1606         return to_vmx(vcpu)->rflags;
1607 }
1608
1609 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1610 {
1611         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1612         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1613         to_vmx(vcpu)->rflags = rflags;
1614         if (to_vmx(vcpu)->rmode.vm86_active) {
1615                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1616                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1617         }
1618         vmcs_writel(GUEST_RFLAGS, rflags);
1619 }
1620
1621 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1622 {
1623         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1624         int ret = 0;
1625
1626         if (interruptibility & GUEST_INTR_STATE_STI)
1627                 ret |= KVM_X86_SHADOW_INT_STI;
1628         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1629                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1630
1631         return ret & mask;
1632 }
1633
1634 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1635 {
1636         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1637         u32 interruptibility = interruptibility_old;
1638
1639         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1640
1641         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1642                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1643         else if (mask & KVM_X86_SHADOW_INT_STI)
1644                 interruptibility |= GUEST_INTR_STATE_STI;
1645
1646         if ((interruptibility != interruptibility_old))
1647                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1648 }
1649
1650 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1651 {
1652         unsigned long rip;
1653
1654         rip = kvm_rip_read(vcpu);
1655         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1656         kvm_rip_write(vcpu, rip);
1657
1658         /* skipping an emulated instruction also counts */
1659         vmx_set_interrupt_shadow(vcpu, 0);
1660 }
1661
1662 /*
1663  * KVM wants to inject page-faults which it got to the guest. This function
1664  * checks whether in a nested guest, we need to inject them to L1 or L2.
1665  * This function assumes it is called with the exit reason in vmcs02 being
1666  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1667  * is running).
1668  */
1669 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1670 {
1671         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1672
1673         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1674         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1675                 return 0;
1676
1677         nested_vmx_vmexit(vcpu);
1678         return 1;
1679 }
1680
1681 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1682                                 bool has_error_code, u32 error_code,
1683                                 bool reinject)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1687
1688         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1689                 nested_pf_handled(vcpu))
1690                 return;
1691
1692         if (has_error_code) {
1693                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1694                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1695         }
1696
1697         if (vmx->rmode.vm86_active) {
1698                 int inc_eip = 0;
1699                 if (kvm_exception_is_soft(nr))
1700                         inc_eip = vcpu->arch.event_exit_inst_len;
1701                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1702                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1703                 return;
1704         }
1705
1706         if (kvm_exception_is_soft(nr)) {
1707                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1708                              vmx->vcpu.arch.event_exit_inst_len);
1709                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1710         } else
1711                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1712
1713         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1714 }
1715
1716 static bool vmx_rdtscp_supported(void)
1717 {
1718         return cpu_has_vmx_rdtscp();
1719 }
1720
1721 /*
1722  * Swap MSR entry in host/guest MSR entry array.
1723  */
1724 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1725 {
1726         struct shared_msr_entry tmp;
1727
1728         tmp = vmx->guest_msrs[to];
1729         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1730         vmx->guest_msrs[from] = tmp;
1731 }
1732
1733 /*
1734  * Set up the vmcs to automatically save and restore system
1735  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1736  * mode, as fiddling with msrs is very expensive.
1737  */
1738 static void setup_msrs(struct vcpu_vmx *vmx)
1739 {
1740         int save_nmsrs, index;
1741         unsigned long *msr_bitmap;
1742
1743         save_nmsrs = 0;
1744 #ifdef CONFIG_X86_64
1745         if (is_long_mode(&vmx->vcpu)) {
1746                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1747                 if (index >= 0)
1748                         move_msr_up(vmx, index, save_nmsrs++);
1749                 index = __find_msr_index(vmx, MSR_LSTAR);
1750                 if (index >= 0)
1751                         move_msr_up(vmx, index, save_nmsrs++);
1752                 index = __find_msr_index(vmx, MSR_CSTAR);
1753                 if (index >= 0)
1754                         move_msr_up(vmx, index, save_nmsrs++);
1755                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1756                 if (index >= 0 && vmx->rdtscp_enabled)
1757                         move_msr_up(vmx, index, save_nmsrs++);
1758                 /*
1759                  * MSR_STAR is only needed on long mode guests, and only
1760                  * if efer.sce is enabled.
1761                  */
1762                 index = __find_msr_index(vmx, MSR_STAR);
1763                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1764                         move_msr_up(vmx, index, save_nmsrs++);
1765         }
1766 #endif
1767         index = __find_msr_index(vmx, MSR_EFER);
1768         if (index >= 0 && update_transition_efer(vmx, index))
1769                 move_msr_up(vmx, index, save_nmsrs++);
1770
1771         vmx->save_nmsrs = save_nmsrs;
1772
1773         if (cpu_has_vmx_msr_bitmap()) {
1774                 if (is_long_mode(&vmx->vcpu))
1775                         msr_bitmap = vmx_msr_bitmap_longmode;
1776                 else
1777                         msr_bitmap = vmx_msr_bitmap_legacy;
1778
1779                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1780         }
1781 }
1782
1783 /*
1784  * reads and returns guest's timestamp counter "register"
1785  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1786  */
1787 static u64 guest_read_tsc(void)
1788 {
1789         u64 host_tsc, tsc_offset;
1790
1791         rdtscll(host_tsc);
1792         tsc_offset = vmcs_read64(TSC_OFFSET);
1793         return host_tsc + tsc_offset;
1794 }
1795
1796 /*
1797  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1798  * counter, even if a nested guest (L2) is currently running.
1799  */
1800 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1801 {
1802         u64 host_tsc, tsc_offset;
1803
1804         rdtscll(host_tsc);
1805         tsc_offset = is_guest_mode(vcpu) ?
1806                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1807                 vmcs_read64(TSC_OFFSET);
1808         return host_tsc + tsc_offset;
1809 }
1810
1811 /*
1812  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1813  * software catchup for faster rates on slower CPUs.
1814  */
1815 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1816 {
1817         if (!scale)
1818                 return;
1819
1820         if (user_tsc_khz > tsc_khz) {
1821                 vcpu->arch.tsc_catchup = 1;
1822                 vcpu->arch.tsc_always_catchup = 1;
1823         } else
1824                 WARN(1, "user requested TSC rate below hardware speed\n");
1825 }
1826
1827 /*
1828  * writes 'offset' into guest's timestamp counter offset register
1829  */
1830 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1831 {
1832         if (is_guest_mode(vcpu)) {
1833                 /*
1834                  * We're here if L1 chose not to trap WRMSR to TSC. According
1835                  * to the spec, this should set L1's TSC; The offset that L1
1836                  * set for L2 remains unchanged, and still needs to be added
1837                  * to the newly set TSC to get L2's TSC.
1838                  */
1839                 struct vmcs12 *vmcs12;
1840                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1841                 /* recalculate vmcs02.TSC_OFFSET: */
1842                 vmcs12 = get_vmcs12(vcpu);
1843                 vmcs_write64(TSC_OFFSET, offset +
1844                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1845                          vmcs12->tsc_offset : 0));
1846         } else {
1847                 vmcs_write64(TSC_OFFSET, offset);
1848         }
1849 }
1850
1851 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1852 {
1853         u64 offset = vmcs_read64(TSC_OFFSET);
1854         vmcs_write64(TSC_OFFSET, offset + adjustment);
1855         if (is_guest_mode(vcpu)) {
1856                 /* Even when running L2, the adjustment needs to apply to L1 */
1857                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1858         }
1859 }
1860
1861 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1862 {
1863         return target_tsc - native_read_tsc();
1864 }
1865
1866 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1867 {
1868         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1869         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1870 }
1871
1872 /*
1873  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1874  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1875  * all guests if the "nested" module option is off, and can also be disabled
1876  * for a single guest by disabling its VMX cpuid bit.
1877  */
1878 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1879 {
1880         return nested && guest_cpuid_has_vmx(vcpu);
1881 }
1882
1883 /*
1884  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1885  * returned for the various VMX controls MSRs when nested VMX is enabled.
1886  * The same values should also be used to verify that vmcs12 control fields are
1887  * valid during nested entry from L1 to L2.
1888  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1889  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1890  * bit in the high half is on if the corresponding bit in the control field
1891  * may be on. See also vmx_control_verify().
1892  * TODO: allow these variables to be modified (downgraded) by module options
1893  * or other means.
1894  */
1895 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1896 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1897 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1898 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1899 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1900 static __init void nested_vmx_setup_ctls_msrs(void)
1901 {
1902         /*
1903          * Note that as a general rule, the high half of the MSRs (bits in
1904          * the control fields which may be 1) should be initialized by the
1905          * intersection of the underlying hardware's MSR (i.e., features which
1906          * can be supported) and the list of features we want to expose -
1907          * because they are known to be properly supported in our code.
1908          * Also, usually, the low half of the MSRs (bits which must be 1) can
1909          * be set to 0, meaning that L1 may turn off any of these bits. The
1910          * reason is that if one of these bits is necessary, it will appear
1911          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1912          * fields of vmcs01 and vmcs02, will turn these bits off - and
1913          * nested_vmx_exit_handled() will not pass related exits to L1.
1914          * These rules have exceptions below.
1915          */
1916
1917         /* pin-based controls */
1918         /*
1919          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1920          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1921          */
1922         nested_vmx_pinbased_ctls_low = 0x16 ;
1923         nested_vmx_pinbased_ctls_high = 0x16 |
1924                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1925                 PIN_BASED_VIRTUAL_NMIS;
1926
1927         /* exit controls */
1928         nested_vmx_exit_ctls_low = 0;
1929         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1930 #ifdef CONFIG_X86_64
1931         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1932 #else
1933         nested_vmx_exit_ctls_high = 0;
1934 #endif
1935
1936         /* entry controls */
1937         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1938                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1939         nested_vmx_entry_ctls_low = 0;
1940         nested_vmx_entry_ctls_high &=
1941                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1942
1943         /* cpu-based controls */
1944         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1945                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1946         nested_vmx_procbased_ctls_low = 0;
1947         nested_vmx_procbased_ctls_high &=
1948                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1949                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1950                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1951                 CPU_BASED_CR3_STORE_EXITING |
1952 #ifdef CONFIG_X86_64
1953                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1954 #endif
1955                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1956                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1957                 CPU_BASED_RDPMC_EXITING |
1958                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1959         /*
1960          * We can allow some features even when not supported by the
1961          * hardware. For example, L1 can specify an MSR bitmap - and we
1962          * can use it to avoid exits to L1 - even when L0 runs L2
1963          * without MSR bitmaps.
1964          */
1965         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1966
1967         /* secondary cpu-based controls */
1968         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1969                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1970         nested_vmx_secondary_ctls_low = 0;
1971         nested_vmx_secondary_ctls_high &=
1972                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1973 }
1974
1975 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1976 {
1977         /*
1978          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1979          */
1980         return ((control & high) | low) == control;
1981 }
1982
1983 static inline u64 vmx_control_msr(u32 low, u32 high)
1984 {
1985         return low | ((u64)high << 32);
1986 }
1987
1988 /*
1989  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1990  * also let it use VMX-specific MSRs.
1991  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1992  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1993  * like all other MSRs).
1994  */
1995 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1996 {
1997         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1998                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1999                 /*
2000                  * According to the spec, processors which do not support VMX
2001                  * should throw a #GP(0) when VMX capability MSRs are read.
2002                  */
2003                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2004                 return 1;
2005         }
2006
2007         switch (msr_index) {
2008         case MSR_IA32_FEATURE_CONTROL:
2009                 *pdata = 0;
2010                 break;
2011         case MSR_IA32_VMX_BASIC:
2012                 /*
2013                  * This MSR reports some information about VMX support. We
2014                  * should return information about the VMX we emulate for the
2015                  * guest, and the VMCS structure we give it - not about the
2016                  * VMX support of the underlying hardware.
2017                  */
2018                 *pdata = VMCS12_REVISION |
2019                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2020                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2021                 break;
2022         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2023         case MSR_IA32_VMX_PINBASED_CTLS:
2024                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2025                                         nested_vmx_pinbased_ctls_high);
2026                 break;
2027         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2028         case MSR_IA32_VMX_PROCBASED_CTLS:
2029                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2030                                         nested_vmx_procbased_ctls_high);
2031                 break;
2032         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2033         case MSR_IA32_VMX_EXIT_CTLS:
2034                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2035                                         nested_vmx_exit_ctls_high);
2036                 break;
2037         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2038         case MSR_IA32_VMX_ENTRY_CTLS:
2039                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2040                                         nested_vmx_entry_ctls_high);
2041                 break;
2042         case MSR_IA32_VMX_MISC:
2043                 *pdata = 0;
2044                 break;
2045         /*
2046          * These MSRs specify bits which the guest must keep fixed (on or off)
2047          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2048          * We picked the standard core2 setting.
2049          */
2050 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2051 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2052         case MSR_IA32_VMX_CR0_FIXED0:
2053                 *pdata = VMXON_CR0_ALWAYSON;
2054                 break;
2055         case MSR_IA32_VMX_CR0_FIXED1:
2056                 *pdata = -1ULL;
2057                 break;
2058         case MSR_IA32_VMX_CR4_FIXED0:
2059                 *pdata = VMXON_CR4_ALWAYSON;
2060                 break;
2061         case MSR_IA32_VMX_CR4_FIXED1:
2062                 *pdata = -1ULL;
2063                 break;
2064         case MSR_IA32_VMX_VMCS_ENUM:
2065                 *pdata = 0x1f;
2066                 break;
2067         case MSR_IA32_VMX_PROCBASED_CTLS2:
2068                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2069                                         nested_vmx_secondary_ctls_high);
2070                 break;
2071         case MSR_IA32_VMX_EPT_VPID_CAP:
2072                 /* Currently, no nested ept or nested vpid */
2073                 *pdata = 0;
2074                 break;
2075         default:
2076                 return 0;
2077         }
2078
2079         return 1;
2080 }
2081
2082 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2083 {
2084         if (!nested_vmx_allowed(vcpu))
2085                 return 0;
2086
2087         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2088                 /* TODO: the right thing. */
2089                 return 1;
2090         /*
2091          * No need to treat VMX capability MSRs specially: If we don't handle
2092          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2093          */
2094         return 0;
2095 }
2096
2097 /*
2098  * Reads an msr value (of 'msr_index') into 'pdata'.
2099  * Returns 0 on success, non-0 otherwise.
2100  * Assumes vcpu_load() was already called.
2101  */
2102 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2103 {
2104         u64 data;
2105         struct shared_msr_entry *msr;
2106
2107         if (!pdata) {
2108                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2109                 return -EINVAL;
2110         }
2111
2112         switch (msr_index) {
2113 #ifdef CONFIG_X86_64
2114         case MSR_FS_BASE:
2115                 data = vmcs_readl(GUEST_FS_BASE);
2116                 break;
2117         case MSR_GS_BASE:
2118                 data = vmcs_readl(GUEST_GS_BASE);
2119                 break;
2120         case MSR_KERNEL_GS_BASE:
2121                 vmx_load_host_state(to_vmx(vcpu));
2122                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2123                 break;
2124 #endif
2125         case MSR_EFER:
2126                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2127         case MSR_IA32_TSC:
2128                 data = guest_read_tsc();
2129                 break;
2130         case MSR_IA32_SYSENTER_CS:
2131                 data = vmcs_read32(GUEST_SYSENTER_CS);
2132                 break;
2133         case MSR_IA32_SYSENTER_EIP:
2134                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2135                 break;
2136         case MSR_IA32_SYSENTER_ESP:
2137                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2138                 break;
2139         case MSR_TSC_AUX:
2140                 if (!to_vmx(vcpu)->rdtscp_enabled)
2141                         return 1;
2142                 /* Otherwise falls through */
2143         default:
2144                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2145                         return 0;
2146                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2147                 if (msr) {
2148                         data = msr->data;
2149                         break;
2150                 }
2151                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2152         }
2153
2154         *pdata = data;
2155         return 0;
2156 }
2157
2158 /*
2159  * Writes msr value into into the appropriate "register".
2160  * Returns 0 on success, non-0 otherwise.
2161  * Assumes vcpu_load() was already called.
2162  */
2163 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2164 {
2165         struct vcpu_vmx *vmx = to_vmx(vcpu);
2166         struct shared_msr_entry *msr;
2167         int ret = 0;
2168
2169         switch (msr_index) {
2170         case MSR_EFER:
2171                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2172                 break;
2173 #ifdef CONFIG_X86_64
2174         case MSR_FS_BASE:
2175                 vmx_segment_cache_clear(vmx);
2176                 vmcs_writel(GUEST_FS_BASE, data);
2177                 break;
2178         case MSR_GS_BASE:
2179                 vmx_segment_cache_clear(vmx);
2180                 vmcs_writel(GUEST_GS_BASE, data);
2181                 break;
2182         case MSR_KERNEL_GS_BASE:
2183                 vmx_load_host_state(vmx);
2184                 vmx->msr_guest_kernel_gs_base = data;
2185                 break;
2186 #endif
2187         case MSR_IA32_SYSENTER_CS:
2188                 vmcs_write32(GUEST_SYSENTER_CS, data);
2189                 break;
2190         case MSR_IA32_SYSENTER_EIP:
2191                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2192                 break;
2193         case MSR_IA32_SYSENTER_ESP:
2194                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2195                 break;
2196         case MSR_IA32_TSC:
2197                 kvm_write_tsc(vcpu, data);
2198                 break;
2199         case MSR_IA32_CR_PAT:
2200                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201                         vmcs_write64(GUEST_IA32_PAT, data);
2202                         vcpu->arch.pat = data;
2203                         break;
2204                 }
2205                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2206                 break;
2207         case MSR_TSC_AUX:
2208                 if (!vmx->rdtscp_enabled)
2209                         return 1;
2210                 /* Check reserved bit, higher 32 bits should be zero */
2211                 if ((data >> 32) != 0)
2212                         return 1;
2213                 /* Otherwise falls through */
2214         default:
2215                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2216                         break;
2217                 msr = find_msr_entry(vmx, msr_index);
2218                 if (msr) {
2219                         msr->data = data;
2220                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2221                                 preempt_disable();
2222                                 kvm_set_shared_msr(msr->index, msr->data,
2223                                                    msr->mask);
2224                                 preempt_enable();
2225                         }
2226                         break;
2227                 }
2228                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2229         }
2230
2231         return ret;
2232 }
2233
2234 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2235 {
2236         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2237         switch (reg) {
2238         case VCPU_REGS_RSP:
2239                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2240                 break;
2241         case VCPU_REGS_RIP:
2242                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2243                 break;
2244         case VCPU_EXREG_PDPTR:
2245                 if (enable_ept)
2246                         ept_save_pdptrs(vcpu);
2247                 break;
2248         default:
2249                 break;
2250         }
2251 }
2252
2253 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2254 {
2255         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2256                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2257         else
2258                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2259
2260         update_exception_bitmap(vcpu);
2261 }
2262
2263 static __init int cpu_has_kvm_support(void)
2264 {
2265         return cpu_has_vmx();
2266 }
2267
2268 static __init int vmx_disabled_by_bios(void)
2269 {
2270         u64 msr;
2271
2272         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2273         if (msr & FEATURE_CONTROL_LOCKED) {
2274                 /* launched w/ TXT and VMX disabled */
2275                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2276                         && tboot_enabled())
2277                         return 1;
2278                 /* launched w/o TXT and VMX only enabled w/ TXT */
2279                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2280                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2281                         && !tboot_enabled()) {
2282                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2283                                 "activate TXT before enabling KVM\n");
2284                         return 1;
2285                 }
2286                 /* launched w/o TXT and VMX disabled */
2287                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2288                         && !tboot_enabled())
2289                         return 1;
2290         }
2291
2292         return 0;
2293 }
2294
2295 static void kvm_cpu_vmxon(u64 addr)
2296 {
2297         asm volatile (ASM_VMX_VMXON_RAX
2298                         : : "a"(&addr), "m"(addr)
2299                         : "memory", "cc");
2300 }
2301
2302 static int hardware_enable(void *garbage)
2303 {
2304         int cpu = raw_smp_processor_id();
2305         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2306         u64 old, test_bits;
2307
2308         if (read_cr4() & X86_CR4_VMXE)
2309                 return -EBUSY;
2310
2311         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2312         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2313
2314         test_bits = FEATURE_CONTROL_LOCKED;
2315         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2316         if (tboot_enabled())
2317                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2318
2319         if ((old & test_bits) != test_bits) {
2320                 /* enable and lock */
2321                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2322         }
2323         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2324
2325         if (vmm_exclusive) {
2326                 kvm_cpu_vmxon(phys_addr);
2327                 ept_sync_global();
2328         }
2329
2330         store_gdt(&__get_cpu_var(host_gdt));
2331
2332         return 0;
2333 }
2334
2335 static void vmclear_local_loaded_vmcss(void)
2336 {
2337         int cpu = raw_smp_processor_id();
2338         struct loaded_vmcs *v, *n;
2339
2340         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2341                                  loaded_vmcss_on_cpu_link)
2342                 __loaded_vmcs_clear(v);
2343 }
2344
2345
2346 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2347  * tricks.
2348  */
2349 static void kvm_cpu_vmxoff(void)
2350 {
2351         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2352 }
2353
2354 static void hardware_disable(void *garbage)
2355 {
2356         if (vmm_exclusive) {
2357                 vmclear_local_loaded_vmcss();
2358                 kvm_cpu_vmxoff();
2359         }
2360         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2361 }
2362
2363 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2364                                       u32 msr, u32 *result)
2365 {
2366         u32 vmx_msr_low, vmx_msr_high;
2367         u32 ctl = ctl_min | ctl_opt;
2368
2369         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2370
2371         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2372         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2373
2374         /* Ensure minimum (required) set of control bits are supported. */
2375         if (ctl_min & ~ctl)
2376                 return -EIO;
2377
2378         *result = ctl;
2379         return 0;
2380 }
2381
2382 static __init bool allow_1_setting(u32 msr, u32 ctl)
2383 {
2384         u32 vmx_msr_low, vmx_msr_high;
2385
2386         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2387         return vmx_msr_high & ctl;
2388 }
2389
2390 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2391 {
2392         u32 vmx_msr_low, vmx_msr_high;
2393         u32 min, opt, min2, opt2;
2394         u32 _pin_based_exec_control = 0;
2395         u32 _cpu_based_exec_control = 0;
2396         u32 _cpu_based_2nd_exec_control = 0;
2397         u32 _vmexit_control = 0;
2398         u32 _vmentry_control = 0;
2399
2400         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2401         opt = PIN_BASED_VIRTUAL_NMIS;
2402         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2403                                 &_pin_based_exec_control) < 0)
2404                 return -EIO;
2405
2406         min = CPU_BASED_HLT_EXITING |
2407 #ifdef CONFIG_X86_64
2408               CPU_BASED_CR8_LOAD_EXITING |
2409               CPU_BASED_CR8_STORE_EXITING |
2410 #endif
2411               CPU_BASED_CR3_LOAD_EXITING |
2412               CPU_BASED_CR3_STORE_EXITING |
2413               CPU_BASED_USE_IO_BITMAPS |
2414               CPU_BASED_MOV_DR_EXITING |
2415               CPU_BASED_USE_TSC_OFFSETING |
2416               CPU_BASED_MWAIT_EXITING |
2417               CPU_BASED_MONITOR_EXITING |
2418               CPU_BASED_INVLPG_EXITING |
2419               CPU_BASED_RDPMC_EXITING;
2420
2421         opt = CPU_BASED_TPR_SHADOW |
2422               CPU_BASED_USE_MSR_BITMAPS |
2423               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2424         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2425                                 &_cpu_based_exec_control) < 0)
2426                 return -EIO;
2427 #ifdef CONFIG_X86_64
2428         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2429                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2430                                            ~CPU_BASED_CR8_STORE_EXITING;
2431 #endif
2432         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2433                 min2 = 0;
2434                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2435                         SECONDARY_EXEC_WBINVD_EXITING |
2436                         SECONDARY_EXEC_ENABLE_VPID |
2437                         SECONDARY_EXEC_ENABLE_EPT |
2438                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2439                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2440                         SECONDARY_EXEC_RDTSCP;
2441                 if (adjust_vmx_controls(min2, opt2,
2442                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2443                                         &_cpu_based_2nd_exec_control) < 0)
2444                         return -EIO;
2445         }
2446 #ifndef CONFIG_X86_64
2447         if (!(_cpu_based_2nd_exec_control &
2448                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2449                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2450 #endif
2451         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2452                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2453                    enabled */
2454                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2455                                              CPU_BASED_CR3_STORE_EXITING |
2456                                              CPU_BASED_INVLPG_EXITING);
2457                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2458                       vmx_capability.ept, vmx_capability.vpid);
2459         }
2460
2461         min = 0;
2462 #ifdef CONFIG_X86_64
2463         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2464 #endif
2465         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2466         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2467                                 &_vmexit_control) < 0)
2468                 return -EIO;
2469
2470         min = 0;
2471         opt = VM_ENTRY_LOAD_IA32_PAT;
2472         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2473                                 &_vmentry_control) < 0)
2474                 return -EIO;
2475
2476         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2477
2478         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2479         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2480                 return -EIO;
2481
2482 #ifdef CONFIG_X86_64
2483         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2484         if (vmx_msr_high & (1u<<16))
2485                 return -EIO;
2486 #endif
2487
2488         /* Require Write-Back (WB) memory type for VMCS accesses. */
2489         if (((vmx_msr_high >> 18) & 15) != 6)
2490                 return -EIO;
2491
2492         vmcs_conf->size = vmx_msr_high & 0x1fff;
2493         vmcs_conf->order = get_order(vmcs_config.size);
2494         vmcs_conf->revision_id = vmx_msr_low;
2495
2496         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2497         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2498         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2499         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2500         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2501
2502         cpu_has_load_ia32_efer =
2503                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2504                                 VM_ENTRY_LOAD_IA32_EFER)
2505                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2506                                    VM_EXIT_LOAD_IA32_EFER);
2507
2508         cpu_has_load_perf_global_ctrl =
2509                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2510                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2511                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2512                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2513
2514         /*
2515          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2516          * but due to arrata below it can't be used. Workaround is to use
2517          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2518          *
2519          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2520          *
2521          * AAK155             (model 26)
2522          * AAP115             (model 30)
2523          * AAT100             (model 37)
2524          * BC86,AAY89,BD102   (model 44)
2525          * BA97               (model 46)
2526          *
2527          */
2528         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2529                 switch (boot_cpu_data.x86_model) {
2530                 case 26:
2531                 case 30:
2532                 case 37:
2533                 case 44:
2534                 case 46:
2535                         cpu_has_load_perf_global_ctrl = false;
2536                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2537                                         "does not work properly. Using workaround\n");
2538                         break;
2539                 default:
2540                         break;
2541                 }
2542         }
2543
2544         return 0;
2545 }
2546
2547 static struct vmcs *alloc_vmcs_cpu(int cpu)
2548 {
2549         int node = cpu_to_node(cpu);
2550         struct page *pages;
2551         struct vmcs *vmcs;
2552
2553         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2554         if (!pages)
2555                 return NULL;
2556         vmcs = page_address(pages);
2557         memset(vmcs, 0, vmcs_config.size);
2558         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2559         return vmcs;
2560 }
2561
2562 static struct vmcs *alloc_vmcs(void)
2563 {
2564         return alloc_vmcs_cpu(raw_smp_processor_id());
2565 }
2566
2567 static void free_vmcs(struct vmcs *vmcs)
2568 {
2569         free_pages((unsigned long)vmcs, vmcs_config.order);
2570 }
2571
2572 /*
2573  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2574  */
2575 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2576 {
2577         if (!loaded_vmcs->vmcs)
2578                 return;
2579         loaded_vmcs_clear(loaded_vmcs);
2580         free_vmcs(loaded_vmcs->vmcs);
2581         loaded_vmcs->vmcs = NULL;
2582 }
2583
2584 static void free_kvm_area(void)
2585 {
2586         int cpu;
2587
2588         for_each_possible_cpu(cpu) {
2589                 free_vmcs(per_cpu(vmxarea, cpu));
2590                 per_cpu(vmxarea, cpu) = NULL;
2591         }
2592 }
2593
2594 static __init int alloc_kvm_area(void)
2595 {
2596         int cpu;
2597
2598         for_each_possible_cpu(cpu) {
2599                 struct vmcs *vmcs;
2600
2601                 vmcs = alloc_vmcs_cpu(cpu);
2602                 if (!vmcs) {
2603                         free_kvm_area();
2604                         return -ENOMEM;
2605                 }
2606
2607                 per_cpu(vmxarea, cpu) = vmcs;
2608         }
2609         return 0;
2610 }
2611
2612 static __init int hardware_setup(void)
2613 {
2614         if (setup_vmcs_config(&vmcs_config) < 0)
2615                 return -EIO;
2616
2617         if (boot_cpu_has(X86_FEATURE_NX))
2618                 kvm_enable_efer_bits(EFER_NX);
2619
2620         if (!cpu_has_vmx_vpid())
2621                 enable_vpid = 0;
2622
2623         if (!cpu_has_vmx_ept() ||
2624             !cpu_has_vmx_ept_4levels()) {
2625                 enable_ept = 0;
2626                 enable_unrestricted_guest = 0;
2627         }
2628
2629         if (!cpu_has_vmx_unrestricted_guest())
2630                 enable_unrestricted_guest = 0;
2631
2632         if (!cpu_has_vmx_flexpriority())
2633                 flexpriority_enabled = 0;
2634
2635         if (!cpu_has_vmx_tpr_shadow())
2636                 kvm_x86_ops->update_cr8_intercept = NULL;
2637
2638         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2639                 kvm_disable_largepages();
2640
2641         if (!cpu_has_vmx_ple())
2642                 ple_gap = 0;
2643
2644         if (nested)
2645                 nested_vmx_setup_ctls_msrs();
2646
2647         return alloc_kvm_area();
2648 }
2649
2650 static __exit void hardware_unsetup(void)
2651 {
2652         free_kvm_area();
2653 }
2654
2655 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2656 {
2657         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2658
2659         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2660                 vmcs_write16(sf->selector, save->selector);
2661                 vmcs_writel(sf->base, save->base);
2662                 vmcs_write32(sf->limit, save->limit);
2663                 vmcs_write32(sf->ar_bytes, save->ar);
2664         } else {
2665                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2666                         << AR_DPL_SHIFT;
2667                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2668         }
2669 }
2670
2671 static void enter_pmode(struct kvm_vcpu *vcpu)
2672 {
2673         unsigned long flags;
2674         struct vcpu_vmx *vmx = to_vmx(vcpu);
2675
2676         vmx->emulation_required = 1;
2677         vmx->rmode.vm86_active = 0;
2678
2679         vmx_segment_cache_clear(vmx);
2680
2681         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2682         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2683         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2684         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2685
2686         flags = vmcs_readl(GUEST_RFLAGS);
2687         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2688         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2689         vmcs_writel(GUEST_RFLAGS, flags);
2690
2691         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2692                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2693
2694         update_exception_bitmap(vcpu);
2695
2696         if (emulate_invalid_guest_state)
2697                 return;
2698
2699         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2700         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2701         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2702         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2703
2704         vmx_segment_cache_clear(vmx);
2705
2706         vmcs_write16(GUEST_SS_SELECTOR, 0);
2707         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2708
2709         vmcs_write16(GUEST_CS_SELECTOR,
2710                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2711         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2712 }
2713
2714 static gva_t rmode_tss_base(struct kvm *kvm)
2715 {
2716         if (!kvm->arch.tss_addr) {
2717                 struct kvm_memslots *slots;
2718                 struct kvm_memory_slot *slot;
2719                 gfn_t base_gfn;
2720
2721                 slots = kvm_memslots(kvm);
2722                 slot = id_to_memslot(slots, 0);
2723                 base_gfn = slot->base_gfn + slot->npages - 3;
2724
2725                 return base_gfn << PAGE_SHIFT;
2726         }
2727         return kvm->arch.tss_addr;
2728 }
2729
2730 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2731 {
2732         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2733
2734         save->selector = vmcs_read16(sf->selector);
2735         save->base = vmcs_readl(sf->base);
2736         save->limit = vmcs_read32(sf->limit);
2737         save->ar = vmcs_read32(sf->ar_bytes);
2738         vmcs_write16(sf->selector, save->base >> 4);
2739         vmcs_write32(sf->base, save->base & 0xffff0);
2740         vmcs_write32(sf->limit, 0xffff);
2741         vmcs_write32(sf->ar_bytes, 0xf3);
2742         if (save->base & 0xf)
2743                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2744                             " aligned when entering protected mode (seg=%d)",
2745                             seg);
2746 }
2747
2748 static void enter_rmode(struct kvm_vcpu *vcpu)
2749 {
2750         unsigned long flags;
2751         struct vcpu_vmx *vmx = to_vmx(vcpu);
2752
2753         if (enable_unrestricted_guest)
2754                 return;
2755
2756         vmx->emulation_required = 1;
2757         vmx->rmode.vm86_active = 1;
2758
2759         /*
2760          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2761          * vcpu. Call it here with phys address pointing 16M below 4G.
2762          */
2763         if (!vcpu->kvm->arch.tss_addr) {
2764                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2765                              "called before entering vcpu\n");
2766                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2767                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2768                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2769         }
2770
2771         vmx_segment_cache_clear(vmx);
2772
2773         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2774         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2775         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2776
2777         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2778         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2779
2780         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2781         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2782
2783         flags = vmcs_readl(GUEST_RFLAGS);
2784         vmx->rmode.save_rflags = flags;
2785
2786         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2787
2788         vmcs_writel(GUEST_RFLAGS, flags);
2789         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2790         update_exception_bitmap(vcpu);
2791
2792         if (emulate_invalid_guest_state)
2793                 goto continue_rmode;
2794
2795         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2796         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2797         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2798
2799         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2800         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2801         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2802                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2803         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2804
2805         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2806         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2807         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2808         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2809
2810 continue_rmode:
2811         kvm_mmu_reset_context(vcpu);
2812 }
2813
2814 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2815 {
2816         struct vcpu_vmx *vmx = to_vmx(vcpu);
2817         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2818
2819         if (!msr)
2820                 return;
2821
2822         /*
2823          * Force kernel_gs_base reloading before EFER changes, as control
2824          * of this msr depends on is_long_mode().
2825          */
2826         vmx_load_host_state(to_vmx(vcpu));
2827         vcpu->arch.efer = efer;
2828         if (efer & EFER_LMA) {
2829                 vmcs_write32(VM_ENTRY_CONTROLS,
2830                              vmcs_read32(VM_ENTRY_CONTROLS) |
2831                              VM_ENTRY_IA32E_MODE);
2832                 msr->data = efer;
2833         } else {
2834                 vmcs_write32(VM_ENTRY_CONTROLS,
2835                              vmcs_read32(VM_ENTRY_CONTROLS) &
2836                              ~VM_ENTRY_IA32E_MODE);
2837
2838                 msr->data = efer & ~EFER_LME;
2839         }
2840         setup_msrs(vmx);
2841 }
2842
2843 #ifdef CONFIG_X86_64
2844
2845 static void enter_lmode(struct kvm_vcpu *vcpu)
2846 {
2847         u32 guest_tr_ar;
2848
2849         vmx_segment_cache_clear(to_vmx(vcpu));
2850
2851         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2852         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2853                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2854                                      __func__);
2855                 vmcs_write32(GUEST_TR_AR_BYTES,
2856                              (guest_tr_ar & ~AR_TYPE_MASK)
2857                              | AR_TYPE_BUSY_64_TSS);
2858         }
2859         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2860 }
2861
2862 static void exit_lmode(struct kvm_vcpu *vcpu)
2863 {
2864         vmcs_write32(VM_ENTRY_CONTROLS,
2865                      vmcs_read32(VM_ENTRY_CONTROLS)
2866                      & ~VM_ENTRY_IA32E_MODE);
2867         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2868 }
2869
2870 #endif
2871
2872 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2873 {
2874         vpid_sync_context(to_vmx(vcpu));
2875         if (enable_ept) {
2876                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2877                         return;
2878                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2879         }
2880 }
2881
2882 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2883 {
2884         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2885
2886         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2887         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2888 }
2889
2890 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2891 {
2892         if (enable_ept && is_paging(vcpu))
2893                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2894         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2895 }
2896
2897 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2898 {
2899         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2900
2901         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2902         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2903 }
2904
2905 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2906 {
2907         if (!test_bit(VCPU_EXREG_PDPTR,
2908                       (unsigned long *)&vcpu->arch.regs_dirty))
2909                 return;
2910
2911         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2912                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2913                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2914                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2915                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2916         }
2917 }
2918
2919 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2920 {
2921         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2922                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2923                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2924                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2925                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2926         }
2927
2928         __set_bit(VCPU_EXREG_PDPTR,
2929                   (unsigned long *)&vcpu->arch.regs_avail);
2930         __set_bit(VCPU_EXREG_PDPTR,
2931                   (unsigned long *)&vcpu->arch.regs_dirty);
2932 }
2933
2934 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2935
2936 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2937                                         unsigned long cr0,
2938                                         struct kvm_vcpu *vcpu)
2939 {
2940         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2941                 vmx_decache_cr3(vcpu);
2942         if (!(cr0 & X86_CR0_PG)) {
2943                 /* From paging/starting to nonpaging */
2944                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2945                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2946                              (CPU_BASED_CR3_LOAD_EXITING |
2947                               CPU_BASED_CR3_STORE_EXITING));
2948                 vcpu->arch.cr0 = cr0;
2949                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2950         } else if (!is_paging(vcpu)) {
2951                 /* From nonpaging to paging */
2952                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2953                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2954                              ~(CPU_BASED_CR3_LOAD_EXITING |
2955                                CPU_BASED_CR3_STORE_EXITING));
2956                 vcpu->arch.cr0 = cr0;
2957                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2958         }
2959
2960         if (!(cr0 & X86_CR0_WP))
2961                 *hw_cr0 &= ~X86_CR0_WP;
2962 }
2963
2964 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2965 {
2966         struct vcpu_vmx *vmx = to_vmx(vcpu);
2967         unsigned long hw_cr0;
2968
2969         if (enable_unrestricted_guest)
2970                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2971                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2972         else
2973                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2974
2975         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2976                 enter_pmode(vcpu);
2977
2978         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2979                 enter_rmode(vcpu);
2980
2981 #ifdef CONFIG_X86_64
2982         if (vcpu->arch.efer & EFER_LME) {
2983                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2984                         enter_lmode(vcpu);
2985                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2986                         exit_lmode(vcpu);
2987         }
2988 #endif
2989
2990         if (enable_ept)
2991                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2992
2993         if (!vcpu->fpu_active)
2994                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2995
2996         vmcs_writel(CR0_READ_SHADOW, cr0);
2997         vmcs_writel(GUEST_CR0, hw_cr0);
2998         vcpu->arch.cr0 = cr0;
2999         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3000 }
3001
3002 static u64 construct_eptp(unsigned long root_hpa)
3003 {
3004         u64 eptp;
3005
3006         /* TODO write the value reading from MSR */
3007         eptp = VMX_EPT_DEFAULT_MT |
3008                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3009         eptp |= (root_hpa & PAGE_MASK);
3010
3011         return eptp;
3012 }
3013
3014 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3015 {
3016         unsigned long guest_cr3;
3017         u64 eptp;
3018
3019         guest_cr3 = cr3;
3020         if (enable_ept) {
3021                 eptp = construct_eptp(cr3);
3022                 vmcs_write64(EPT_POINTER, eptp);
3023                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3024                         vcpu->kvm->arch.ept_identity_map_addr;
3025                 ept_load_pdptrs(vcpu);
3026         }
3027
3028         vmx_flush_tlb(vcpu);
3029         vmcs_writel(GUEST_CR3, guest_cr3);
3030 }
3031
3032 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3033 {
3034         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3035                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3036
3037         if (cr4 & X86_CR4_VMXE) {
3038                 /*
3039                  * To use VMXON (and later other VMX instructions), a guest
3040                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3041                  * So basically the check on whether to allow nested VMX
3042                  * is here.
3043                  */
3044                 if (!nested_vmx_allowed(vcpu))
3045                         return 1;
3046         } else if (to_vmx(vcpu)->nested.vmxon)
3047                 return 1;
3048
3049         vcpu->arch.cr4 = cr4;
3050         if (enable_ept) {
3051                 if (!is_paging(vcpu)) {
3052                         hw_cr4 &= ~X86_CR4_PAE;
3053                         hw_cr4 |= X86_CR4_PSE;
3054                 } else if (!(cr4 & X86_CR4_PAE)) {
3055                         hw_cr4 &= ~X86_CR4_PAE;
3056                 }
3057         }
3058
3059         vmcs_writel(CR4_READ_SHADOW, cr4);
3060         vmcs_writel(GUEST_CR4, hw_cr4);
3061         return 0;
3062 }
3063
3064 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3065                             struct kvm_segment *var, int seg)
3066 {
3067         struct vcpu_vmx *vmx = to_vmx(vcpu);
3068         struct kvm_save_segment *save;
3069         u32 ar;
3070
3071         if (vmx->rmode.vm86_active
3072             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3073                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3074                 || seg == VCPU_SREG_GS)
3075             && !emulate_invalid_guest_state) {
3076                 switch (seg) {
3077                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3078                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3079                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3080                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3081                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3082                 default: BUG();
3083                 }
3084                 var->selector = save->selector;
3085                 var->base = save->base;
3086                 var->limit = save->limit;
3087                 ar = save->ar;
3088                 if (seg == VCPU_SREG_TR
3089                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3090                         goto use_saved_rmode_seg;
3091         }
3092         var->base = vmx_read_guest_seg_base(vmx, seg);
3093         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3094         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3095         ar = vmx_read_guest_seg_ar(vmx, seg);
3096 use_saved_rmode_seg:
3097         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3098                 ar = 0;
3099         var->type = ar & 15;
3100         var->s = (ar >> 4) & 1;
3101         var->dpl = (ar >> 5) & 3;
3102         var->present = (ar >> 7) & 1;
3103         var->avl = (ar >> 12) & 1;
3104         var->l = (ar >> 13) & 1;
3105         var->db = (ar >> 14) & 1;
3106         var->g = (ar >> 15) & 1;
3107         var->unusable = (ar >> 16) & 1;
3108 }
3109
3110 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3111 {
3112         struct kvm_segment s;
3113
3114         if (to_vmx(vcpu)->rmode.vm86_active) {
3115                 vmx_get_segment(vcpu, &s, seg);
3116                 return s.base;
3117         }
3118         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3119 }
3120
3121 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3122 {
3123         if (!is_protmode(vcpu))
3124                 return 0;
3125
3126         if (!is_long_mode(vcpu)
3127             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3128                 return 3;
3129
3130         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3131 }
3132
3133 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3134 {
3135         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3136                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3137                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3138         }
3139         return to_vmx(vcpu)->cpl;
3140 }
3141
3142
3143 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3144 {
3145         u32 ar;
3146
3147         if (var->unusable)
3148                 ar = 1 << 16;
3149         else {
3150                 ar = var->type & 15;
3151                 ar |= (var->s & 1) << 4;
3152                 ar |= (var->dpl & 3) << 5;
3153                 ar |= (var->present & 1) << 7;
3154                 ar |= (var->avl & 1) << 12;
3155                 ar |= (var->l & 1) << 13;
3156                 ar |= (var->db & 1) << 14;
3157                 ar |= (var->g & 1) << 15;
3158         }
3159         if (ar == 0) /* a 0 value means unusable */
3160                 ar = AR_UNUSABLE_MASK;
3161
3162         return ar;
3163 }
3164
3165 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3166                             struct kvm_segment *var, int seg)
3167 {
3168         struct vcpu_vmx *vmx = to_vmx(vcpu);
3169         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3170         u32 ar;
3171
3172         vmx_segment_cache_clear(vmx);
3173
3174         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3175                 vmcs_write16(sf->selector, var->selector);
3176                 vmx->rmode.tr.selector = var->selector;
3177                 vmx->rmode.tr.base = var->base;
3178                 vmx->rmode.tr.limit = var->limit;
3179                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3180                 return;
3181         }
3182         vmcs_writel(sf->base, var->base);
3183         vmcs_write32(sf->limit, var->limit);
3184         vmcs_write16(sf->selector, var->selector);
3185         if (vmx->rmode.vm86_active && var->s) {
3186                 /*
3187                  * Hack real-mode segments into vm86 compatibility.
3188                  */
3189                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3190                         vmcs_writel(sf->base, 0xf0000);
3191                 ar = 0xf3;
3192         } else
3193                 ar = vmx_segment_access_rights(var);
3194
3195         /*
3196          *   Fix the "Accessed" bit in AR field of segment registers for older
3197          * qemu binaries.
3198          *   IA32 arch specifies that at the time of processor reset the
3199          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3200          * is setting it to 0 in the usedland code. This causes invalid guest
3201          * state vmexit when "unrestricted guest" mode is turned on.
3202          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3203          * tree. Newer qemu binaries with that qemu fix would not need this
3204          * kvm hack.
3205          */
3206         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3207                 ar |= 0x1; /* Accessed */
3208
3209         vmcs_write32(sf->ar_bytes, ar);
3210         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3211 }
3212
3213 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3214 {
3215         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3216
3217         *db = (ar >> 14) & 1;
3218         *l = (ar >> 13) & 1;
3219 }
3220
3221 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3222 {
3223         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3224         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3225 }
3226
3227 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3228 {
3229         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3230         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3231 }
3232
3233 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3234 {
3235         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3236         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3237 }
3238
3239 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3240 {
3241         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3242         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3243 }
3244
3245 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3246 {
3247         struct kvm_segment var;
3248         u32 ar;
3249
3250         vmx_get_segment(vcpu, &var, seg);
3251         ar = vmx_segment_access_rights(&var);
3252
3253         if (var.base != (var.selector << 4))
3254                 return false;
3255         if (var.limit != 0xffff)
3256                 return false;
3257         if (ar != 0xf3)
3258                 return false;
3259
3260         return true;
3261 }
3262
3263 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3264 {
3265         struct kvm_segment cs;
3266         unsigned int cs_rpl;
3267
3268         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3269         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3270
3271         if (cs.unusable)
3272                 return false;
3273         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3274                 return false;
3275         if (!cs.s)
3276                 return false;
3277         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3278                 if (cs.dpl > cs_rpl)
3279                         return false;
3280         } else {
3281                 if (cs.dpl != cs_rpl)
3282                         return false;
3283         }
3284         if (!cs.present)
3285                 return false;
3286
3287         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3288         return true;
3289 }
3290
3291 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3292 {
3293         struct kvm_segment ss;
3294         unsigned int ss_rpl;
3295
3296         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3297         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3298
3299         if (ss.unusable)
3300                 return true;
3301         if (ss.type != 3 && ss.type != 7)
3302                 return false;
3303         if (!ss.s)
3304                 return false;
3305         if (ss.dpl != ss_rpl) /* DPL != RPL */
3306                 return false;
3307         if (!ss.present)
3308                 return false;
3309
3310         return true;
3311 }
3312
3313 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3314 {
3315         struct kvm_segment var;
3316         unsigned int rpl;
3317
3318         vmx_get_segment(vcpu, &var, seg);
3319         rpl = var.selector & SELECTOR_RPL_MASK;
3320
3321         if (var.unusable)
3322                 return true;
3323         if (!var.s)
3324                 return false;
3325         if (!var.present)
3326                 return false;
3327         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3328                 if (var.dpl < rpl) /* DPL < RPL */
3329                         return false;
3330         }
3331
3332         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3333          * rights flags
3334          */
3335         return true;
3336 }
3337
3338 static bool tr_valid(struct kvm_vcpu *vcpu)
3339 {
3340         struct kvm_segment tr;
3341
3342         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3343
3344         if (tr.unusable)
3345                 return false;
3346         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3347                 return false;
3348         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3349                 return false;
3350         if (!tr.present)
3351                 return false;
3352
3353         return true;
3354 }
3355
3356 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3357 {
3358         struct kvm_segment ldtr;
3359
3360         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3361
3362         if (ldtr.unusable)
3363                 return true;
3364         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3365                 return false;
3366         if (ldtr.type != 2)
3367                 return false;
3368         if (!ldtr.present)
3369                 return false;
3370
3371         return true;
3372 }
3373
3374 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3375 {
3376         struct kvm_segment cs, ss;
3377
3378         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3379         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3380
3381         return ((cs.selector & SELECTOR_RPL_MASK) ==
3382                  (ss.selector & SELECTOR_RPL_MASK));
3383 }
3384
3385 /*
3386  * Check if guest state is valid. Returns true if valid, false if
3387  * not.
3388  * We assume that registers are always usable
3389  */
3390 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3391 {
3392         /* real mode guest state checks */
3393         if (!is_protmode(vcpu)) {
3394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3395                         return false;
3396                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3397                         return false;
3398                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3399                         return false;
3400                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3401                         return false;
3402                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3403                         return false;
3404                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3405                         return false;
3406         } else {
3407         /* protected mode guest state checks */
3408                 if (!cs_ss_rpl_check(vcpu))
3409                         return false;
3410                 if (!code_segment_valid(vcpu))
3411                         return false;
3412                 if (!stack_segment_valid(vcpu))
3413                         return false;
3414                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3415                         return false;
3416                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3417                         return false;
3418                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3419                         return false;
3420                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3421                         return false;
3422                 if (!tr_valid(vcpu))
3423                         return false;
3424                 if (!ldtr_valid(vcpu))
3425                         return false;
3426         }
3427         /* TODO:
3428          * - Add checks on RIP
3429          * - Add checks on RFLAGS
3430          */
3431
3432         return true;
3433 }
3434
3435 static int init_rmode_tss(struct kvm *kvm)
3436 {
3437         gfn_t fn;
3438         u16 data = 0;
3439         int r, idx, ret = 0;
3440
3441         idx = srcu_read_lock(&kvm->srcu);
3442         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3443         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3444         if (r < 0)
3445                 goto out;
3446         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3447         r = kvm_write_guest_page(kvm, fn++, &data,
3448                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3449         if (r < 0)
3450                 goto out;
3451         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3452         if (r < 0)
3453                 goto out;
3454         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3455         if (r < 0)
3456                 goto out;
3457         data = ~0;
3458         r = kvm_write_guest_page(kvm, fn, &data,
3459                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3460                                  sizeof(u8));
3461         if (r < 0)
3462                 goto out;
3463
3464         ret = 1;
3465 out:
3466         srcu_read_unlock(&kvm->srcu, idx);
3467         return ret;
3468 }
3469
3470 static int init_rmode_identity_map(struct kvm *kvm)
3471 {
3472         int i, idx, r, ret;
3473         pfn_t identity_map_pfn;
3474         u32 tmp;
3475
3476         if (!enable_ept)
3477                 return 1;
3478         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3479                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3480                         "haven't been allocated!\n");
3481                 return 0;
3482         }
3483         if (likely(kvm->arch.ept_identity_pagetable_done))
3484                 return 1;
3485         ret = 0;
3486         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3487         idx = srcu_read_lock(&kvm->srcu);
3488         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3489         if (r < 0)
3490                 goto out;
3491         /* Set up identity-mapping pagetable for EPT in real mode */
3492         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3493                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3494                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3495                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3496                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3497                 if (r < 0)
3498                         goto out;
3499         }
3500         kvm->arch.ept_identity_pagetable_done = true;
3501         ret = 1;
3502 out:
3503         srcu_read_unlock(&kvm->srcu, idx);
3504         return ret;
3505 }
3506
3507 static void seg_setup(int seg)
3508 {
3509         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3510         unsigned int ar;
3511
3512         vmcs_write16(sf->selector, 0);
3513         vmcs_writel(sf->base, 0);
3514         vmcs_write32(sf->limit, 0xffff);
3515         if (enable_unrestricted_guest) {
3516                 ar = 0x93;
3517                 if (seg == VCPU_SREG_CS)
3518                         ar |= 0x08; /* code segment */
3519         } else
3520                 ar = 0xf3;
3521
3522         vmcs_write32(sf->ar_bytes, ar);
3523 }
3524
3525 static int alloc_apic_access_page(struct kvm *kvm)
3526 {
3527         struct kvm_userspace_memory_region kvm_userspace_mem;
3528         int r = 0;
3529
3530         mutex_lock(&kvm->slots_lock);
3531         if (kvm->arch.apic_access_page)
3532                 goto out;
3533         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3534         kvm_userspace_mem.flags = 0;
3535         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3536         kvm_userspace_mem.memory_size = PAGE_SIZE;
3537         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3538         if (r)
3539                 goto out;
3540
3541         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3542 out:
3543         mutex_unlock(&kvm->slots_lock);
3544         return r;
3545 }
3546
3547 static int alloc_identity_pagetable(struct kvm *kvm)
3548 {
3549         struct kvm_userspace_memory_region kvm_userspace_mem;
3550         int r = 0;
3551
3552         mutex_lock(&kvm->slots_lock);
3553         if (kvm->arch.ept_identity_pagetable)
3554                 goto out;
3555         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3556         kvm_userspace_mem.flags = 0;
3557         kvm_userspace_mem.guest_phys_addr =
3558                 kvm->arch.ept_identity_map_addr;
3559         kvm_userspace_mem.memory_size = PAGE_SIZE;
3560         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3561         if (r)
3562                 goto out;
3563
3564         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3565                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3566 out:
3567         mutex_unlock(&kvm->slots_lock);
3568         return r;
3569 }
3570
3571 static void allocate_vpid(struct vcpu_vmx *vmx)
3572 {
3573         int vpid;
3574
3575         vmx->vpid = 0;
3576         if (!enable_vpid)
3577                 return;
3578         spin_lock(&vmx_vpid_lock);
3579         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3580         if (vpid < VMX_NR_VPIDS) {
3581                 vmx->vpid = vpid;
3582                 __set_bit(vpid, vmx_vpid_bitmap);
3583         }
3584         spin_unlock(&vmx_vpid_lock);
3585 }
3586
3587 static void free_vpid(struct vcpu_vmx *vmx)
3588 {
3589         if (!enable_vpid)
3590                 return;
3591         spin_lock(&vmx_vpid_lock);
3592         if (vmx->vpid != 0)
3593                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3594         spin_unlock(&vmx_vpid_lock);
3595 }
3596
3597 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3598 {
3599         int f = sizeof(unsigned long);
3600
3601         if (!cpu_has_vmx_msr_bitmap())
3602                 return;
3603
3604         /*
3605          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3606          * have the write-low and read-high bitmap offsets the wrong way round.
3607          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3608          */
3609         if (msr <= 0x1fff) {
3610                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3611                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3612         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3613                 msr &= 0x1fff;
3614                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3615                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3616         }
3617 }
3618
3619 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3620 {
3621         if (!longmode_only)
3622                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3623         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3624 }
3625
3626 /*
3627  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3628  * will not change in the lifetime of the guest.
3629  * Note that host-state that does change is set elsewhere. E.g., host-state
3630  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3631  */
3632 static void vmx_set_constant_host_state(void)
3633 {
3634         u32 low32, high32;
3635         unsigned long tmpl;
3636         struct desc_ptr dt;
3637
3638         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3639         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3640         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3641
3642         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3643         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3644         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3645         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3646         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3647
3648         native_store_idt(&dt);
3649         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3650
3651         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3652         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3653
3654         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3655         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3656         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3657         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3658
3659         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3660                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3661                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3662         }
3663 }
3664
3665 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3666 {
3667         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3668         if (enable_ept)
3669                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3670         if (is_guest_mode(&vmx->vcpu))
3671                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3672                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3673         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3674 }
3675
3676 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3677 {
3678         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3679         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3680                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3681 #ifdef CONFIG_X86_64
3682                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3683                                 CPU_BASED_CR8_LOAD_EXITING;
3684 #endif
3685         }
3686         if (!enable_ept)
3687                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3688                                 CPU_BASED_CR3_LOAD_EXITING  |
3689                                 CPU_BASED_INVLPG_EXITING;
3690         return exec_control;
3691 }
3692
3693 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3694 {
3695         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3696         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3697                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3698         if (vmx->vpid == 0)
3699                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3700         if (!enable_ept) {
3701                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3702                 enable_unrestricted_guest = 0;
3703         }
3704         if (!enable_unrestricted_guest)
3705                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3706         if (!ple_gap)
3707                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3708         return exec_control;
3709 }
3710
3711 static void ept_set_mmio_spte_mask(void)
3712 {
3713         /*
3714          * EPT Misconfigurations can be generated if the value of bits 2:0
3715          * of an EPT paging-structure entry is 110b (write/execute).
3716          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3717          * spte.
3718          */
3719         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3720 }
3721
3722 /*
3723  * Sets up the vmcs for emulated real mode.
3724  */
3725 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3726 {
3727 #ifdef CONFIG_X86_64
3728         unsigned long a;
3729 #endif
3730         int i;
3731
3732         /* I/O */
3733         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3734         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3735
3736         if (cpu_has_vmx_msr_bitmap())
3737                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3738
3739         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3740
3741         /* Control */
3742         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3743                 vmcs_config.pin_based_exec_ctrl);
3744
3745         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3746
3747         if (cpu_has_secondary_exec_ctrls()) {
3748                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3749                                 vmx_secondary_exec_control(vmx));
3750         }
3751
3752         if (ple_gap) {
3753                 vmcs_write32(PLE_GAP, ple_gap);
3754                 vmcs_write32(PLE_WINDOW, ple_window);
3755         }
3756
3757         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3758         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3759         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3760
3761         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3762         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3763         vmx_set_constant_host_state();
3764 #ifdef CONFIG_X86_64
3765         rdmsrl(MSR_FS_BASE, a);
3766         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3767         rdmsrl(MSR_GS_BASE, a);
3768         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3769 #else
3770         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3771         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3772 #endif
3773
3774         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3775         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3776         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3777         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3778         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3779
3780         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3781                 u32 msr_low, msr_high;
3782                 u64 host_pat;
3783                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3784                 host_pat = msr_low | ((u64) msr_high << 32);
3785                 /* Write the default value follow host pat */
3786                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3787                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3788                 vmx->vcpu.arch.pat = host_pat;
3789         }
3790
3791         for (i = 0; i < NR_VMX_MSR; ++i) {
3792                 u32 index = vmx_msr_index[i];
3793                 u32 data_low, data_high;
3794                 int j = vmx->nmsrs;
3795
3796                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3797                         continue;
3798                 if (wrmsr_safe(index, data_low, data_high) < 0)
3799                         continue;
3800                 vmx->guest_msrs[j].index = i;
3801                 vmx->guest_msrs[j].data = 0;
3802                 vmx->guest_msrs[j].mask = -1ull;
3803                 ++vmx->nmsrs;
3804         }
3805
3806         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3807
3808         /* 22.2.1, 20.8.1 */
3809         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3810
3811         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3812         set_cr4_guest_host_mask(vmx);
3813
3814         kvm_write_tsc(&vmx->vcpu, 0);
3815
3816         return 0;
3817 }
3818
3819 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3820 {
3821         struct vcpu_vmx *vmx = to_vmx(vcpu);
3822         u64 msr;
3823         int ret;
3824
3825         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3826
3827         vmx->rmode.vm86_active = 0;
3828
3829         vmx->soft_vnmi_blocked = 0;
3830
3831         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3832         kvm_set_cr8(&vmx->vcpu, 0);
3833         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3834         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3835                 msr |= MSR_IA32_APICBASE_BSP;
3836         kvm_set_apic_base(&vmx->vcpu, msr);
3837
3838         ret = fx_init(&vmx->vcpu);
3839         if (ret != 0)
3840                 goto out;
3841
3842         vmx_segment_cache_clear(vmx);
3843
3844         seg_setup(VCPU_SREG_CS);
3845         /*
3846          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3847          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3848          */
3849         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3850                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3851                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3852         } else {
3853                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3854                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3855         }
3856
3857         seg_setup(VCPU_SREG_DS);
3858         seg_setup(VCPU_SREG_ES);
3859         seg_setup(VCPU_SREG_FS);
3860         seg_setup(VCPU_SREG_GS);
3861         seg_setup(VCPU_SREG_SS);
3862
3863         vmcs_write16(GUEST_TR_SELECTOR, 0);
3864         vmcs_writel(GUEST_TR_BASE, 0);
3865         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3866         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3867
3868         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3869         vmcs_writel(GUEST_LDTR_BASE, 0);
3870         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3871         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3872
3873         vmcs_write32(GUEST_SYSENTER_CS, 0);
3874         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3875         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3876
3877         vmcs_writel(GUEST_RFLAGS, 0x02);
3878         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3879                 kvm_rip_write(vcpu, 0xfff0);
3880         else
3881                 kvm_rip_write(vcpu, 0);
3882         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3883
3884         vmcs_writel(GUEST_DR7, 0x400);
3885
3886         vmcs_writel(GUEST_GDTR_BASE, 0);
3887         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3888
3889         vmcs_writel(GUEST_IDTR_BASE, 0);
3890         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3891
3892         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3893         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3894         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3895
3896         /* Special registers */
3897         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3898
3899         setup_msrs(vmx);
3900
3901         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3902
3903         if (cpu_has_vmx_tpr_shadow()) {
3904                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3905                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3906                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3907                                      __pa(vmx->vcpu.arch.apic->regs));
3908                 vmcs_write32(TPR_THRESHOLD, 0);
3909         }
3910
3911         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3912                 vmcs_write64(APIC_ACCESS_ADDR,
3913                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3914
3915         if (vmx->vpid != 0)
3916                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3917
3918         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3919         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3920         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3921         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3922         vmx_set_cr4(&vmx->vcpu, 0);
3923         vmx_set_efer(&vmx->vcpu, 0);
3924         vmx_fpu_activate(&vmx->vcpu);
3925         update_exception_bitmap(&vmx->vcpu);
3926
3927         vpid_sync_context(vmx);
3928
3929         ret = 0;
3930
3931         /* HACK: Don't enable emulation on guest boot/reset */
3932         vmx->emulation_required = 0;
3933
3934 out:
3935         return ret;
3936 }
3937
3938 /*
3939  * In nested virtualization, check if L1 asked to exit on external interrupts.
3940  * For most existing hypervisors, this will always return true.
3941  */
3942 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3943 {
3944         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3945                 PIN_BASED_EXT_INTR_MASK;
3946 }
3947
3948 static void enable_irq_window(struct kvm_vcpu *vcpu)
3949 {
3950         u32 cpu_based_vm_exec_control;
3951         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3952                 /*
3953                  * We get here if vmx_interrupt_allowed() said we can't
3954                  * inject to L1 now because L2 must run. Ask L2 to exit
3955                  * right after entry, so we can inject to L1 more promptly.
3956                  */
3957                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3958                 return;
3959         }
3960
3961         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3962         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3963         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3964 }
3965
3966 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3967 {
3968         u32 cpu_based_vm_exec_control;
3969
3970         if (!cpu_has_virtual_nmis()) {
3971                 enable_irq_window(vcpu);
3972                 return;
3973         }
3974
3975         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3976                 enable_irq_window(vcpu);
3977                 return;
3978         }
3979         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3980         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3981         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3982 }
3983
3984 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3985 {
3986         struct vcpu_vmx *vmx = to_vmx(vcpu);
3987         uint32_t intr;
3988         int irq = vcpu->arch.interrupt.nr;
3989
3990         trace_kvm_inj_virq(irq);
3991
3992         ++vcpu->stat.irq_injections;
3993         if (vmx->rmode.vm86_active) {
3994                 int inc_eip = 0;
3995                 if (vcpu->arch.interrupt.soft)
3996                         inc_eip = vcpu->arch.event_exit_inst_len;
3997                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3998                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3999                 return;
4000         }
4001         intr = irq | INTR_INFO_VALID_MASK;
4002         if (vcpu->arch.interrupt.soft) {
4003                 intr |= INTR_TYPE_SOFT_INTR;
4004                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4005                              vmx->vcpu.arch.event_exit_inst_len);
4006         } else
4007                 intr |= INTR_TYPE_EXT_INTR;
4008         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4009 }
4010
4011 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4012 {
4013         struct vcpu_vmx *vmx = to_vmx(vcpu);
4014
4015         if (is_guest_mode(vcpu))
4016                 return;
4017
4018         if (!cpu_has_virtual_nmis()) {
4019                 /*
4020                  * Tracking the NMI-blocked state in software is built upon
4021                  * finding the next open IRQ window. This, in turn, depends on
4022                  * well-behaving guests: They have to keep IRQs disabled at
4023                  * least as long as the NMI handler runs. Otherwise we may
4024                  * cause NMI nesting, maybe breaking the guest. But as this is
4025                  * highly unlikely, we can live with the residual risk.
4026                  */
4027                 vmx->soft_vnmi_blocked = 1;
4028                 vmx->vnmi_blocked_time = 0;
4029         }
4030
4031         ++vcpu->stat.nmi_injections;
4032         vmx->nmi_known_unmasked = false;
4033         if (vmx->rmode.vm86_active) {
4034                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4035                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4036                 return;
4037         }
4038         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4039                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4040 }
4041
4042 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4043 {
4044         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4045                 return 0;
4046
4047         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4048                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4049                    | GUEST_INTR_STATE_NMI));
4050 }
4051
4052 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4053 {
4054         if (!cpu_has_virtual_nmis())
4055                 return to_vmx(vcpu)->soft_vnmi_blocked;
4056         if (to_vmx(vcpu)->nmi_known_unmasked)
4057                 return false;
4058         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4059 }
4060
4061 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4062 {
4063         struct vcpu_vmx *vmx = to_vmx(vcpu);
4064
4065         if (!cpu_has_virtual_nmis()) {
4066                 if (vmx->soft_vnmi_blocked != masked) {
4067                         vmx->soft_vnmi_blocked = masked;
4068                         vmx->vnmi_blocked_time = 0;
4069                 }
4070         } else {
4071                 vmx->nmi_known_unmasked = !masked;
4072                 if (masked)
4073                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4074                                       GUEST_INTR_STATE_NMI);
4075                 else
4076                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4077                                         GUEST_INTR_STATE_NMI);
4078         }
4079 }
4080
4081 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4082 {
4083         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4084                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4085                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4086                     (vmcs12->idt_vectoring_info_field &
4087                      VECTORING_INFO_VALID_MASK))
4088                         return 0;
4089                 nested_vmx_vmexit(vcpu);
4090                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4091                 vmcs12->vm_exit_intr_info = 0;
4092                 /* fall through to normal code, but now in L1, not L2 */
4093         }
4094
4095         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4096                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4097                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4098 }
4099
4100 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4101 {
4102         int ret;
4103         struct kvm_userspace_memory_region tss_mem = {
4104                 .slot = TSS_PRIVATE_MEMSLOT,
4105                 .guest_phys_addr = addr,
4106                 .memory_size = PAGE_SIZE * 3,
4107                 .flags = 0,
4108         };
4109
4110         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4111         if (ret)
4112                 return ret;
4113         kvm->arch.tss_addr = addr;
4114         if (!init_rmode_tss(kvm))
4115                 return  -ENOMEM;
4116
4117         return 0;
4118 }
4119
4120 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4121                                   int vec, u32 err_code)
4122 {
4123         /*
4124          * Instruction with address size override prefix opcode 0x67
4125          * Cause the #SS fault with 0 error code in VM86 mode.
4126          */
4127         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4128                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4129                         return 1;
4130         /*
4131          * Forward all other exceptions that are valid in real mode.
4132          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4133          *        the required debugging infrastructure rework.
4134          */
4135         switch (vec) {
4136         case DB_VECTOR:
4137                 if (vcpu->guest_debug &
4138                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4139                         return 0;
4140                 kvm_queue_exception(vcpu, vec);
4141                 return 1;
4142         case BP_VECTOR:
4143                 /*
4144                  * Update instruction length as we may reinject the exception
4145                  * from user space while in guest debugging mode.
4146                  */
4147                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4148                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4149                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4150                         return 0;
4151                 /* fall through */
4152         case DE_VECTOR:
4153         case OF_VECTOR:
4154         case BR_VECTOR:
4155         case UD_VECTOR:
4156         case DF_VECTOR:
4157         case SS_VECTOR:
4158         case GP_VECTOR:
4159         case MF_VECTOR:
4160                 kvm_queue_exception(vcpu, vec);
4161                 return 1;
4162         }
4163         return 0;
4164 }
4165
4166 /*
4167  * Trigger machine check on the host. We assume all the MSRs are already set up
4168  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4169  * We pass a fake environment to the machine check handler because we want
4170  * the guest to be always treated like user space, no matter what context
4171  * it used internally.
4172  */
4173 static void kvm_machine_check(void)
4174 {
4175 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4176         struct pt_regs regs = {
4177                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4178                 .flags = X86_EFLAGS_IF,
4179         };
4180
4181         do_machine_check(&regs, 0);
4182 #endif
4183 }
4184
4185 static int handle_machine_check(struct kvm_vcpu *vcpu)
4186 {
4187         /* already handled by vcpu_run */
4188         return 1;
4189 }
4190
4191 static int handle_exception(struct kvm_vcpu *vcpu)
4192 {
4193         struct vcpu_vmx *vmx = to_vmx(vcpu);
4194         struct kvm_run *kvm_run = vcpu->run;
4195         u32 intr_info, ex_no, error_code;
4196         unsigned long cr2, rip, dr6;
4197         u32 vect_info;
4198         enum emulation_result er;
4199
4200         vect_info = vmx->idt_vectoring_info;
4201         intr_info = vmx->exit_intr_info;
4202
4203         if (is_machine_check(intr_info))
4204                 return handle_machine_check(vcpu);
4205
4206         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4207             !is_page_fault(intr_info)) {
4208                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4209                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4210                 vcpu->run->internal.ndata = 2;
4211                 vcpu->run->internal.data[0] = vect_info;
4212                 vcpu->run->internal.data[1] = intr_info;
4213                 return 0;
4214         }
4215
4216         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4217                 return 1;  /* already handled by vmx_vcpu_run() */
4218
4219         if (is_no_device(intr_info)) {
4220                 vmx_fpu_activate(vcpu);
4221                 return 1;
4222         }
4223
4224         if (is_invalid_opcode(intr_info)) {
4225                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4226                 if (er != EMULATE_DONE)
4227                         kvm_queue_exception(vcpu, UD_VECTOR);
4228                 return 1;
4229         }
4230
4231         error_code = 0;
4232         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4233                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4234         if (is_page_fault(intr_info)) {
4235                 /* EPT won't cause page fault directly */
4236                 BUG_ON(enable_ept);
4237                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4238                 trace_kvm_page_fault(cr2, error_code);
4239
4240                 if (kvm_event_needs_reinjection(vcpu))
4241                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4242                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4243         }
4244
4245         if (vmx->rmode.vm86_active &&
4246             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4247                                                                 error_code)) {
4248                 if (vcpu->arch.halt_request) {
4249                         vcpu->arch.halt_request = 0;
4250                         return kvm_emulate_halt(vcpu);
4251                 }
4252                 return 1;
4253         }
4254
4255         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4256         switch (ex_no) {
4257         case DB_VECTOR:
4258                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4259                 if (!(vcpu->guest_debug &
4260                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4261                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4262                         kvm_queue_exception(vcpu, DB_VECTOR);
4263                         return 1;
4264                 }
4265                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4266                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4267                 /* fall through */
4268         case BP_VECTOR:
4269                 /*
4270                  * Update instruction length as we may reinject #BP from
4271                  * user space while in guest debugging mode. Reading it for
4272                  * #DB as well causes no harm, it is not used in that case.
4273                  */
4274                 vmx->vcpu.arch.event_exit_inst_len =
4275                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4276                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4277                 rip = kvm_rip_read(vcpu);
4278                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4279                 kvm_run->debug.arch.exception = ex_no;
4280                 break;
4281         default:
4282                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4283                 kvm_run->ex.exception = ex_no;
4284                 kvm_run->ex.error_code = error_code;
4285                 break;
4286         }
4287         return 0;
4288 }
4289
4290 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4291 {
4292         ++vcpu->stat.irq_exits;
4293         return 1;
4294 }
4295
4296 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4297 {
4298         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4299         return 0;
4300 }
4301
4302 static int handle_io(struct kvm_vcpu *vcpu)
4303 {
4304         unsigned long exit_qualification;
4305         int size, in, string;
4306         unsigned port;
4307
4308         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4309         string = (exit_qualification & 16) != 0;
4310         in = (exit_qualification & 8) != 0;
4311
4312         ++vcpu->stat.io_exits;
4313
4314         if (string || in)
4315                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4316
4317         port = exit_qualification >> 16;
4318         size = (exit_qualification & 7) + 1;
4319         skip_emulated_instruction(vcpu);
4320
4321         return kvm_fast_pio_out(vcpu, size, port);
4322 }
4323
4324 static void
4325 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4326 {
4327         /*
4328          * Patch in the VMCALL instruction:
4329          */
4330         hypercall[0] = 0x0f;
4331         hypercall[1] = 0x01;
4332         hypercall[2] = 0xc1;
4333 }
4334
4335 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4336 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4337 {
4338         if (to_vmx(vcpu)->nested.vmxon &&
4339             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4340                 return 1;
4341
4342         if (is_guest_mode(vcpu)) {
4343                 /*
4344                  * We get here when L2 changed cr0 in a way that did not change
4345                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4346                  * but did change L0 shadowed bits. This can currently happen
4347                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4348                  * loading) while pretending to allow the guest to change it.
4349                  */
4350                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4351                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4352                         return 1;
4353                 vmcs_writel(CR0_READ_SHADOW, val);
4354                 return 0;
4355         } else
4356                 return kvm_set_cr0(vcpu, val);
4357 }
4358
4359 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4360 {
4361         if (is_guest_mode(vcpu)) {
4362                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4363                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4364                         return 1;
4365                 vmcs_writel(CR4_READ_SHADOW, val);
4366                 return 0;
4367         } else
4368                 return kvm_set_cr4(vcpu, val);
4369 }
4370
4371 /* called to set cr0 as approriate for clts instruction exit. */
4372 static void handle_clts(struct kvm_vcpu *vcpu)
4373 {
4374         if (is_guest_mode(vcpu)) {
4375                 /*
4376                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4377                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4378                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4379                  */
4380                 vmcs_writel(CR0_READ_SHADOW,
4381                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4382                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4383         } else
4384                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4385 }
4386
4387 static int handle_cr(struct kvm_vcpu *vcpu)
4388 {
4389         unsigned long exit_qualification, val;
4390         int cr;
4391         int reg;
4392         int err;
4393
4394         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4395         cr = exit_qualification & 15;
4396         reg = (exit_qualification >> 8) & 15;
4397         switch ((exit_qualification >> 4) & 3) {
4398         case 0: /* mov to cr */
4399                 val = kvm_register_read(vcpu, reg);
4400                 trace_kvm_cr_write(cr, val);
4401                 switch (cr) {
4402                 case 0:
4403                         err = handle_set_cr0(vcpu, val);
4404                         kvm_complete_insn_gp(vcpu, err);
4405                         return 1;
4406                 case 3:
4407                         err = kvm_set_cr3(vcpu, val);
4408                         kvm_complete_insn_gp(vcpu, err);
4409                         return 1;
4410                 case 4:
4411                         err = handle_set_cr4(vcpu, val);
4412                         kvm_complete_insn_gp(vcpu, err);
4413                         return 1;
4414                 case 8: {
4415                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4416                                 u8 cr8 = kvm_register_read(vcpu, reg);
4417                                 err = kvm_set_cr8(vcpu, cr8);
4418                                 kvm_complete_insn_gp(vcpu, err);
4419                                 if (irqchip_in_kernel(vcpu->kvm))
4420                                         return 1;
4421                                 if (cr8_prev <= cr8)
4422                                         return 1;
4423                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4424                                 return 0;
4425                         }
4426                 };
4427                 break;
4428         case 2: /* clts */
4429                 handle_clts(vcpu);
4430                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4431                 skip_emulated_instruction(vcpu);
4432                 vmx_fpu_activate(vcpu);
4433                 return 1;
4434         case 1: /*mov from cr*/
4435                 switch (cr) {
4436                 case 3:
4437                         val = kvm_read_cr3(vcpu);
4438                         kvm_register_write(vcpu, reg, val);
4439                         trace_kvm_cr_read(cr, val);
4440                         skip_emulated_instruction(vcpu);
4441                         return 1;
4442                 case 8:
4443                         val = kvm_get_cr8(vcpu);
4444                         kvm_register_write(vcpu, reg, val);
4445                         trace_kvm_cr_read(cr, val);
4446                         skip_emulated_instruction(vcpu);
4447                         return 1;
4448                 }
4449                 break;
4450         case 3: /* lmsw */
4451                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4452                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4453                 kvm_lmsw(vcpu, val);
4454
4455                 skip_emulated_instruction(vcpu);
4456                 return 1;
4457         default:
4458                 break;
4459         }
4460         vcpu->run->exit_reason = 0;
4461         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4462                (int)(exit_qualification >> 4) & 3, cr);
4463         return 0;
4464 }
4465
4466 static int handle_dr(struct kvm_vcpu *vcpu)
4467 {
4468         unsigned long exit_qualification;
4469         int dr, reg;
4470
4471         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4472         if (!kvm_require_cpl(vcpu, 0))
4473                 return 1;
4474         dr = vmcs_readl(GUEST_DR7);
4475         if (dr & DR7_GD) {
4476                 /*
4477                  * As the vm-exit takes precedence over the debug trap, we
4478                  * need to emulate the latter, either for the host or the
4479                  * guest debugging itself.
4480                  */
4481                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4482                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4483                         vcpu->run->debug.arch.dr7 = dr;
4484                         vcpu->run->debug.arch.pc =
4485                                 vmcs_readl(GUEST_CS_BASE) +
4486                                 vmcs_readl(GUEST_RIP);
4487                         vcpu->run->debug.arch.exception = DB_VECTOR;
4488                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4489                         return 0;
4490                 } else {
4491                         vcpu->arch.dr7 &= ~DR7_GD;
4492                         vcpu->arch.dr6 |= DR6_BD;
4493                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4494                         kvm_queue_exception(vcpu, DB_VECTOR);
4495                         return 1;
4496                 }
4497         }
4498
4499         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4500         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4501         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4502         if (exit_qualification & TYPE_MOV_FROM_DR) {
4503                 unsigned long val;
4504                 if (!kvm_get_dr(vcpu, dr, &val))
4505                         kvm_register_write(vcpu, reg, val);
4506         } else
4507                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4508         skip_emulated_instruction(vcpu);
4509         return 1;
4510 }
4511
4512 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4513 {
4514         vmcs_writel(GUEST_DR7, val);
4515 }
4516
4517 static int handle_cpuid(struct kvm_vcpu *vcpu)
4518 {
4519         kvm_emulate_cpuid(vcpu);
4520         return 1;
4521 }
4522
4523 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4524 {
4525         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4526         u64 data;
4527
4528         if (vmx_get_msr(vcpu, ecx, &data)) {
4529                 trace_kvm_msr_read_ex(ecx);
4530                 kvm_inject_gp(vcpu, 0);
4531                 return 1;
4532         }
4533
4534         trace_kvm_msr_read(ecx, data);
4535
4536         /* FIXME: handling of bits 32:63 of rax, rdx */
4537         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4538         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4539         skip_emulated_instruction(vcpu);
4540         return 1;
4541 }
4542
4543 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4544 {
4545         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4546         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4547                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4548
4549         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4550                 trace_kvm_msr_write_ex(ecx, data);
4551                 kvm_inject_gp(vcpu, 0);
4552                 return 1;
4553         }
4554
4555         trace_kvm_msr_write(ecx, data);
4556         skip_emulated_instruction(vcpu);
4557         return 1;
4558 }
4559
4560 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4561 {
4562         kvm_make_request(KVM_REQ_EVENT, vcpu);
4563         return 1;
4564 }
4565
4566 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4567 {
4568         u32 cpu_based_vm_exec_control;
4569
4570         /* clear pending irq */
4571         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4572         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4573         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4574
4575         kvm_make_request(KVM_REQ_EVENT, vcpu);
4576
4577         ++vcpu->stat.irq_window_exits;
4578
4579         /*
4580          * If the user space waits to inject interrupts, exit as soon as
4581          * possible
4582          */
4583         if (!irqchip_in_kernel(vcpu->kvm) &&
4584             vcpu->run->request_interrupt_window &&
4585             !kvm_cpu_has_interrupt(vcpu)) {
4586                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4587                 return 0;
4588         }
4589         return 1;
4590 }
4591
4592 static int handle_halt(struct kvm_vcpu *vcpu)
4593 {
4594         skip_emulated_instruction(vcpu);
4595         return kvm_emulate_halt(vcpu);
4596 }
4597
4598 static int handle_vmcall(struct kvm_vcpu *vcpu)
4599 {
4600         skip_emulated_instruction(vcpu);
4601         kvm_emulate_hypercall(vcpu);
4602         return 1;
4603 }
4604
4605 static int handle_invd(struct kvm_vcpu *vcpu)
4606 {
4607         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4608 }
4609
4610 static int handle_invlpg(struct kvm_vcpu *vcpu)
4611 {
4612         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4613
4614         kvm_mmu_invlpg(vcpu, exit_qualification);
4615         skip_emulated_instruction(vcpu);
4616         return 1;
4617 }
4618
4619 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4620 {
4621         int err;
4622
4623         err = kvm_rdpmc(vcpu);
4624         kvm_complete_insn_gp(vcpu, err);
4625
4626         return 1;
4627 }
4628
4629 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4630 {
4631         skip_emulated_instruction(vcpu);
4632         kvm_emulate_wbinvd(vcpu);
4633         return 1;
4634 }
4635
4636 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4637 {
4638         u64 new_bv = kvm_read_edx_eax(vcpu);
4639         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4640
4641         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4642                 skip_emulated_instruction(vcpu);
4643         return 1;
4644 }
4645
4646 static int handle_apic_access(struct kvm_vcpu *vcpu)
4647 {
4648         if (likely(fasteoi)) {
4649                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4650                 int access_type, offset;
4651
4652                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4653                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4654                 /*
4655                  * Sane guest uses MOV to write EOI, with written value
4656                  * not cared. So make a short-circuit here by avoiding
4657                  * heavy instruction emulation.
4658                  */
4659                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4660                     (offset == APIC_EOI)) {
4661                         kvm_lapic_set_eoi(vcpu);
4662                         skip_emulated_instruction(vcpu);
4663                         return 1;
4664                 }
4665         }
4666         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4667 }
4668
4669 static int handle_task_switch(struct kvm_vcpu *vcpu)
4670 {
4671         struct vcpu_vmx *vmx = to_vmx(vcpu);
4672         unsigned long exit_qualification;
4673         bool has_error_code = false;
4674         u32 error_code = 0;
4675         u16 tss_selector;
4676         int reason, type, idt_v, idt_index;
4677
4678         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4679         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4680         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4681
4682         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4683
4684         reason = (u32)exit_qualification >> 30;
4685         if (reason == TASK_SWITCH_GATE && idt_v) {
4686                 switch (type) {
4687                 case INTR_TYPE_NMI_INTR:
4688                         vcpu->arch.nmi_injected = false;
4689                         vmx_set_nmi_mask(vcpu, true);
4690                         break;
4691                 case INTR_TYPE_EXT_INTR:
4692                 case INTR_TYPE_SOFT_INTR:
4693                         kvm_clear_interrupt_queue(vcpu);
4694                         break;
4695                 case INTR_TYPE_HARD_EXCEPTION:
4696                         if (vmx->idt_vectoring_info &
4697                             VECTORING_INFO_DELIVER_CODE_MASK) {
4698                                 has_error_code = true;
4699                                 error_code =
4700                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4701                         }
4702                         /* fall through */
4703                 case INTR_TYPE_SOFT_EXCEPTION:
4704                         kvm_clear_exception_queue(vcpu);
4705                         break;
4706                 default:
4707                         break;
4708                 }
4709         }
4710         tss_selector = exit_qualification;
4711
4712         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4713                        type != INTR_TYPE_EXT_INTR &&
4714                        type != INTR_TYPE_NMI_INTR))
4715                 skip_emulated_instruction(vcpu);
4716
4717         if (kvm_task_switch(vcpu, tss_selector,
4718                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4719                             has_error_code, error_code) == EMULATE_FAIL) {
4720                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4721                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4722                 vcpu->run->internal.ndata = 0;
4723                 return 0;
4724         }
4725
4726         /* clear all local breakpoint enable flags */
4727         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4728
4729         /*
4730          * TODO: What about debug traps on tss switch?
4731          *       Are we supposed to inject them and update dr6?
4732          */
4733
4734         return 1;
4735 }
4736
4737 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4738 {
4739         unsigned long exit_qualification;
4740         gpa_t gpa;
4741         int gla_validity;
4742
4743         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4744
4745         if (exit_qualification & (1 << 6)) {
4746                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4747                 return -EINVAL;
4748         }
4749
4750         gla_validity = (exit_qualification >> 7) & 0x3;
4751         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4752                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4753                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4754                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4755                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4756                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4757                         (long unsigned int)exit_qualification);
4758                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4759                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4760                 return 0;
4761         }
4762
4763         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4764         trace_kvm_page_fault(gpa, exit_qualification);
4765         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4766 }
4767
4768 static u64 ept_rsvd_mask(u64 spte, int level)
4769 {
4770         int i;
4771         u64 mask = 0;
4772
4773         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4774                 mask |= (1ULL << i);
4775
4776         if (level > 2)
4777                 /* bits 7:3 reserved */
4778                 mask |= 0xf8;
4779         else if (level == 2) {
4780                 if (spte & (1ULL << 7))
4781                         /* 2MB ref, bits 20:12 reserved */
4782                         mask |= 0x1ff000;
4783                 else
4784                         /* bits 6:3 reserved */
4785                         mask |= 0x78;
4786         }
4787
4788         return mask;
4789 }
4790
4791 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4792                                        int level)
4793 {
4794         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4795
4796         /* 010b (write-only) */
4797         WARN_ON((spte & 0x7) == 0x2);
4798
4799         /* 110b (write/execute) */
4800         WARN_ON((spte & 0x7) == 0x6);
4801
4802         /* 100b (execute-only) and value not supported by logical processor */
4803         if (!cpu_has_vmx_ept_execute_only())
4804                 WARN_ON((spte & 0x7) == 0x4);
4805
4806         /* not 000b */
4807         if ((spte & 0x7)) {
4808                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4809
4810                 if (rsvd_bits != 0) {
4811                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4812                                          __func__, rsvd_bits);
4813                         WARN_ON(1);
4814                 }
4815
4816                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4817                         u64 ept_mem_type = (spte & 0x38) >> 3;
4818
4819                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4820                             ept_mem_type == 7) {
4821                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4822                                                 __func__, ept_mem_type);
4823                                 WARN_ON(1);
4824                         }
4825                 }
4826         }
4827 }
4828
4829 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4830 {
4831         u64 sptes[4];
4832         int nr_sptes, i, ret;
4833         gpa_t gpa;
4834
4835         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4836
4837         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4838         if (likely(ret == 1))
4839                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4840                                               EMULATE_DONE;
4841         if (unlikely(!ret))
4842                 return 1;
4843
4844         /* It is the real ept misconfig */
4845         printk(KERN_ERR "EPT: Misconfiguration.\n");
4846         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4847
4848         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4849
4850         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4851                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4852
4853         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4854         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4855
4856         return 0;
4857 }
4858
4859 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4860 {
4861         u32 cpu_based_vm_exec_control;
4862
4863         /* clear pending NMI */
4864         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4865         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4866         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4867         ++vcpu->stat.nmi_window_exits;
4868         kvm_make_request(KVM_REQ_EVENT, vcpu);
4869
4870         return 1;
4871 }
4872
4873 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4874 {
4875         struct vcpu_vmx *vmx = to_vmx(vcpu);
4876         enum emulation_result err = EMULATE_DONE;
4877         int ret = 1;
4878         u32 cpu_exec_ctrl;
4879         bool intr_window_requested;
4880
4881         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4882         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4883
4884         while (!guest_state_valid(vcpu)) {
4885                 if (intr_window_requested
4886                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4887                         return handle_interrupt_window(&vmx->vcpu);
4888
4889                 err = emulate_instruction(vcpu, 0);
4890
4891                 if (err == EMULATE_DO_MMIO) {
4892                         ret = 0;
4893                         goto out;
4894                 }
4895
4896                 if (err != EMULATE_DONE)
4897                         return 0;
4898
4899                 if (signal_pending(current))
4900                         goto out;
4901                 if (need_resched())
4902                         schedule();
4903         }
4904
4905         vmx->emulation_required = 0;
4906 out:
4907         return ret;
4908 }
4909
4910 /*
4911  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4912  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4913  */
4914 static int handle_pause(struct kvm_vcpu *vcpu)
4915 {
4916         skip_emulated_instruction(vcpu);
4917         kvm_vcpu_on_spin(vcpu);
4918
4919         return 1;
4920 }
4921
4922 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4923 {
4924         kvm_queue_exception(vcpu, UD_VECTOR);
4925         return 1;
4926 }
4927
4928 /*
4929  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4930  * We could reuse a single VMCS for all the L2 guests, but we also want the
4931  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4932  * allows keeping them loaded on the processor, and in the future will allow
4933  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4934  * every entry if they never change.
4935  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4936  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4937  *
4938  * The following functions allocate and free a vmcs02 in this pool.
4939  */
4940
4941 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4942 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4943 {
4944         struct vmcs02_list *item;
4945         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4946                 if (item->vmptr == vmx->nested.current_vmptr) {
4947                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4948                         return &item->vmcs02;
4949                 }
4950
4951         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4952                 /* Recycle the least recently used VMCS. */
4953                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4954                         struct vmcs02_list, list);
4955                 item->vmptr = vmx->nested.current_vmptr;
4956                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4957                 return &item->vmcs02;
4958         }
4959
4960         /* Create a new VMCS */
4961         item = (struct vmcs02_list *)
4962                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4963         if (!item)
4964                 return NULL;
4965         item->vmcs02.vmcs = alloc_vmcs();
4966         if (!item->vmcs02.vmcs) {
4967                 kfree(item);
4968                 return NULL;
4969         }
4970         loaded_vmcs_init(&item->vmcs02);
4971         item->vmptr = vmx->nested.current_vmptr;
4972         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4973         vmx->nested.vmcs02_num++;
4974         return &item->vmcs02;
4975 }
4976
4977 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4978 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4979 {
4980         struct vmcs02_list *item;
4981         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4982                 if (item->vmptr == vmptr) {
4983                         free_loaded_vmcs(&item->vmcs02);
4984                         list_del(&item->list);
4985                         kfree(item);
4986                         vmx->nested.vmcs02_num--;
4987                         return;
4988                 }
4989 }
4990
4991 /*
4992  * Free all VMCSs saved for this vcpu, except the one pointed by
4993  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4994  * currently used, if running L2), and vmcs01 when running L2.
4995  */
4996 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4997 {
4998         struct vmcs02_list *item, *n;
4999         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5000                 if (vmx->loaded_vmcs != &item->vmcs02)
5001                         free_loaded_vmcs(&item->vmcs02);
5002                 list_del(&item->list);
5003                 kfree(item);
5004         }
5005         vmx->nested.vmcs02_num = 0;
5006
5007         if (vmx->loaded_vmcs != &vmx->vmcs01)
5008                 free_loaded_vmcs(&vmx->vmcs01);
5009 }
5010
5011 /*
5012  * Emulate the VMXON instruction.
5013  * Currently, we just remember that VMX is active, and do not save or even
5014  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5015  * do not currently need to store anything in that guest-allocated memory
5016  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5017  * argument is different from the VMXON pointer (which the spec says they do).
5018  */
5019 static int handle_vmon(struct kvm_vcpu *vcpu)
5020 {
5021         struct kvm_segment cs;
5022         struct vcpu_vmx *vmx = to_vmx(vcpu);
5023
5024         /* The Intel VMX Instruction Reference lists a bunch of bits that
5025          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5026          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5027          * Otherwise, we should fail with #UD. We test these now:
5028          */
5029         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5030             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5031             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5032                 kvm_queue_exception(vcpu, UD_VECTOR);
5033                 return 1;
5034         }
5035
5036         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5037         if (is_long_mode(vcpu) && !cs.l) {
5038                 kvm_queue_exception(vcpu, UD_VECTOR);
5039                 return 1;
5040         }
5041
5042         if (vmx_get_cpl(vcpu)) {
5043                 kvm_inject_gp(vcpu, 0);
5044                 return 1;
5045         }
5046
5047         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5048         vmx->nested.vmcs02_num = 0;
5049
5050         vmx->nested.vmxon = true;
5051
5052         skip_emulated_instruction(vcpu);
5053         return 1;
5054 }
5055
5056 /*
5057  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5058  * for running VMX instructions (except VMXON, whose prerequisites are
5059  * slightly different). It also specifies what exception to inject otherwise.
5060  */
5061 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5062 {
5063         struct kvm_segment cs;
5064         struct vcpu_vmx *vmx = to_vmx(vcpu);
5065
5066         if (!vmx->nested.vmxon) {
5067                 kvm_queue_exception(vcpu, UD_VECTOR);
5068                 return 0;
5069         }
5070
5071         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5072         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5073             (is_long_mode(vcpu) && !cs.l)) {
5074                 kvm_queue_exception(vcpu, UD_VECTOR);
5075                 return 0;
5076         }
5077
5078         if (vmx_get_cpl(vcpu)) {
5079                 kvm_inject_gp(vcpu, 0);
5080                 return 0;
5081         }
5082
5083         return 1;
5084 }
5085
5086 /*
5087  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5088  * just stops using VMX.
5089  */
5090 static void free_nested(struct vcpu_vmx *vmx)
5091 {
5092         if (!vmx->nested.vmxon)
5093                 return;
5094         vmx->nested.vmxon = false;
5095         if (vmx->nested.current_vmptr != -1ull) {
5096                 kunmap(vmx->nested.current_vmcs12_page);
5097                 nested_release_page(vmx->nested.current_vmcs12_page);
5098                 vmx->nested.current_vmptr = -1ull;
5099                 vmx->nested.current_vmcs12 = NULL;
5100         }
5101         /* Unpin physical memory we referred to in current vmcs02 */
5102         if (vmx->nested.apic_access_page) {
5103                 nested_release_page(vmx->nested.apic_access_page);
5104                 vmx->nested.apic_access_page = 0;
5105         }
5106
5107         nested_free_all_saved_vmcss(vmx);
5108 }
5109
5110 /* Emulate the VMXOFF instruction */
5111 static int handle_vmoff(struct kvm_vcpu *vcpu)
5112 {
5113         if (!nested_vmx_check_permission(vcpu))
5114                 return 1;
5115         free_nested(to_vmx(vcpu));
5116         skip_emulated_instruction(vcpu);
5117         return 1;
5118 }
5119
5120 /*
5121  * Decode the memory-address operand of a vmx instruction, as recorded on an
5122  * exit caused by such an instruction (run by a guest hypervisor).
5123  * On success, returns 0. When the operand is invalid, returns 1 and throws
5124  * #UD or #GP.
5125  */
5126 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5127                                  unsigned long exit_qualification,
5128                                  u32 vmx_instruction_info, gva_t *ret)
5129 {
5130         /*
5131          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5132          * Execution", on an exit, vmx_instruction_info holds most of the
5133          * addressing components of the operand. Only the displacement part
5134          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5135          * For how an actual address is calculated from all these components,
5136          * refer to Vol. 1, "Operand Addressing".
5137          */
5138         int  scaling = vmx_instruction_info & 3;
5139         int  addr_size = (vmx_instruction_info >> 7) & 7;
5140         bool is_reg = vmx_instruction_info & (1u << 10);
5141         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5142         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5143         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5144         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5145         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5146
5147         if (is_reg) {
5148                 kvm_queue_exception(vcpu, UD_VECTOR);
5149                 return 1;
5150         }
5151
5152         /* Addr = segment_base + offset */
5153         /* offset = base + [index * scale] + displacement */
5154         *ret = vmx_get_segment_base(vcpu, seg_reg);
5155         if (base_is_valid)
5156                 *ret += kvm_register_read(vcpu, base_reg);
5157         if (index_is_valid)
5158                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5159         *ret += exit_qualification; /* holds the displacement */
5160
5161         if (addr_size == 1) /* 32 bit */
5162                 *ret &= 0xffffffff;
5163
5164         /*
5165          * TODO: throw #GP (and return 1) in various cases that the VM*
5166          * instructions require it - e.g., offset beyond segment limit,
5167          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5168          * address, and so on. Currently these are not checked.
5169          */
5170         return 0;
5171 }
5172
5173 /*
5174  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5175  * set the success or error code of an emulated VMX instruction, as specified
5176  * by Vol 2B, VMX Instruction Reference, "Conventions".
5177  */
5178 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5179 {
5180         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5181                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5182                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5183 }
5184
5185 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5186 {
5187         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5188                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5189                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5190                         | X86_EFLAGS_CF);
5191 }
5192
5193 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5194                                         u32 vm_instruction_error)
5195 {
5196         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5197                 /*
5198                  * failValid writes the error number to the current VMCS, which
5199                  * can't be done there isn't a current VMCS.
5200                  */
5201                 nested_vmx_failInvalid(vcpu);
5202                 return;
5203         }
5204         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5205                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5206                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5207                         | X86_EFLAGS_ZF);
5208         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5209 }
5210
5211 /* Emulate the VMCLEAR instruction */
5212 static int handle_vmclear(struct kvm_vcpu *vcpu)
5213 {
5214         struct vcpu_vmx *vmx = to_vmx(vcpu);
5215         gva_t gva;
5216         gpa_t vmptr;
5217         struct vmcs12 *vmcs12;
5218         struct page *page;
5219         struct x86_exception e;
5220
5221         if (!nested_vmx_check_permission(vcpu))
5222                 return 1;
5223
5224         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5225                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5226                 return 1;
5227
5228         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5229                                 sizeof(vmptr), &e)) {
5230                 kvm_inject_page_fault(vcpu, &e);
5231                 return 1;
5232         }
5233
5234         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5235                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5236                 skip_emulated_instruction(vcpu);
5237                 return 1;
5238         }
5239
5240         if (vmptr == vmx->nested.current_vmptr) {
5241                 kunmap(vmx->nested.current_vmcs12_page);
5242                 nested_release_page(vmx->nested.current_vmcs12_page);
5243                 vmx->nested.current_vmptr = -1ull;
5244                 vmx->nested.current_vmcs12 = NULL;
5245         }
5246
5247         page = nested_get_page(vcpu, vmptr);
5248         if (page == NULL) {
5249                 /*
5250                  * For accurate processor emulation, VMCLEAR beyond available
5251                  * physical memory should do nothing at all. However, it is
5252                  * possible that a nested vmx bug, not a guest hypervisor bug,
5253                  * resulted in this case, so let's shut down before doing any
5254                  * more damage:
5255                  */
5256                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5257                 return 1;
5258         }
5259         vmcs12 = kmap(page);
5260         vmcs12->launch_state = 0;
5261         kunmap(page);
5262         nested_release_page(page);
5263
5264         nested_free_vmcs02(vmx, vmptr);
5265
5266         skip_emulated_instruction(vcpu);
5267         nested_vmx_succeed(vcpu);
5268         return 1;
5269 }
5270
5271 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5272
5273 /* Emulate the VMLAUNCH instruction */
5274 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5275 {
5276         return nested_vmx_run(vcpu, true);
5277 }
5278
5279 /* Emulate the VMRESUME instruction */
5280 static int handle_vmresume(struct kvm_vcpu *vcpu)
5281 {
5282
5283         return nested_vmx_run(vcpu, false);
5284 }
5285
5286 enum vmcs_field_type {
5287         VMCS_FIELD_TYPE_U16 = 0,
5288         VMCS_FIELD_TYPE_U64 = 1,
5289         VMCS_FIELD_TYPE_U32 = 2,
5290         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5291 };
5292
5293 static inline int vmcs_field_type(unsigned long field)
5294 {
5295         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5296                 return VMCS_FIELD_TYPE_U32;
5297         return (field >> 13) & 0x3 ;
5298 }
5299
5300 static inline int vmcs_field_readonly(unsigned long field)
5301 {
5302         return (((field >> 10) & 0x3) == 1);
5303 }
5304
5305 /*
5306  * Read a vmcs12 field. Since these can have varying lengths and we return
5307  * one type, we chose the biggest type (u64) and zero-extend the return value
5308  * to that size. Note that the caller, handle_vmread, might need to use only
5309  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5310  * 64-bit fields are to be returned).
5311  */
5312 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5313                                         unsigned long field, u64 *ret)
5314 {
5315         short offset = vmcs_field_to_offset(field);
5316         char *p;
5317
5318         if (offset < 0)
5319                 return 0;
5320
5321         p = ((char *)(get_vmcs12(vcpu))) + offset;
5322
5323         switch (vmcs_field_type(field)) {
5324         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5325                 *ret = *((natural_width *)p);
5326                 return 1;
5327         case VMCS_FIELD_TYPE_U16:
5328                 *ret = *((u16 *)p);
5329                 return 1;
5330         case VMCS_FIELD_TYPE_U32:
5331                 *ret = *((u32 *)p);
5332                 return 1;
5333         case VMCS_FIELD_TYPE_U64:
5334                 *ret = *((u64 *)p);
5335                 return 1;
5336         default:
5337                 return 0; /* can never happen. */
5338         }
5339 }
5340
5341 /*
5342  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5343  * used before) all generate the same failure when it is missing.
5344  */
5345 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5346 {
5347         struct vcpu_vmx *vmx = to_vmx(vcpu);
5348         if (vmx->nested.current_vmptr == -1ull) {
5349                 nested_vmx_failInvalid(vcpu);
5350                 skip_emulated_instruction(vcpu);
5351                 return 0;
5352         }
5353         return 1;
5354 }
5355
5356 static int handle_vmread(struct kvm_vcpu *vcpu)
5357 {
5358         unsigned long field;
5359         u64 field_value;
5360         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5361         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5362         gva_t gva = 0;
5363
5364         if (!nested_vmx_check_permission(vcpu) ||
5365             !nested_vmx_check_vmcs12(vcpu))
5366                 return 1;
5367
5368         /* Decode instruction info and find the field to read */
5369         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5370         /* Read the field, zero-extended to a u64 field_value */
5371         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5372                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5373                 skip_emulated_instruction(vcpu);
5374                 return 1;
5375         }
5376         /*
5377          * Now copy part of this value to register or memory, as requested.
5378          * Note that the number of bits actually copied is 32 or 64 depending
5379          * on the guest's mode (32 or 64 bit), not on the given field's length.
5380          */
5381         if (vmx_instruction_info & (1u << 10)) {
5382                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5383                         field_value);
5384         } else {
5385                 if (get_vmx_mem_address(vcpu, exit_qualification,
5386                                 vmx_instruction_info, &gva))
5387                         return 1;
5388                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5389                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5390                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5391         }
5392
5393         nested_vmx_succeed(vcpu);
5394         skip_emulated_instruction(vcpu);
5395         return 1;
5396 }
5397
5398
5399 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5400 {
5401         unsigned long field;
5402         gva_t gva;
5403         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5404         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5405         char *p;
5406         short offset;
5407         /* The value to write might be 32 or 64 bits, depending on L1's long
5408          * mode, and eventually we need to write that into a field of several
5409          * possible lengths. The code below first zero-extends the value to 64
5410          * bit (field_value), and then copies only the approriate number of
5411          * bits into the vmcs12 field.
5412          */
5413         u64 field_value = 0;
5414         struct x86_exception e;
5415
5416         if (!nested_vmx_check_permission(vcpu) ||
5417             !nested_vmx_check_vmcs12(vcpu))
5418                 return 1;
5419
5420         if (vmx_instruction_info & (1u << 10))
5421                 field_value = kvm_register_read(vcpu,
5422                         (((vmx_instruction_info) >> 3) & 0xf));
5423         else {
5424                 if (get_vmx_mem_address(vcpu, exit_qualification,
5425                                 vmx_instruction_info, &gva))
5426                         return 1;
5427                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5428                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5429                         kvm_inject_page_fault(vcpu, &e);
5430                         return 1;
5431                 }
5432         }
5433
5434
5435         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5436         if (vmcs_field_readonly(field)) {
5437                 nested_vmx_failValid(vcpu,
5438                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5439                 skip_emulated_instruction(vcpu);
5440                 return 1;
5441         }
5442
5443         offset = vmcs_field_to_offset(field);
5444         if (offset < 0) {
5445                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5446                 skip_emulated_instruction(vcpu);
5447                 return 1;
5448         }
5449         p = ((char *) get_vmcs12(vcpu)) + offset;
5450
5451         switch (vmcs_field_type(field)) {
5452         case VMCS_FIELD_TYPE_U16:
5453                 *(u16 *)p = field_value;
5454                 break;
5455         case VMCS_FIELD_TYPE_U32:
5456                 *(u32 *)p = field_value;
5457                 break;
5458         case VMCS_FIELD_TYPE_U64:
5459                 *(u64 *)p = field_value;
5460                 break;
5461         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5462                 *(natural_width *)p = field_value;
5463                 break;
5464         default:
5465                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5466                 skip_emulated_instruction(vcpu);
5467                 return 1;
5468         }
5469
5470         nested_vmx_succeed(vcpu);
5471         skip_emulated_instruction(vcpu);
5472         return 1;
5473 }
5474
5475 /* Emulate the VMPTRLD instruction */
5476 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5477 {
5478         struct vcpu_vmx *vmx = to_vmx(vcpu);
5479         gva_t gva;
5480         gpa_t vmptr;
5481         struct x86_exception e;
5482
5483         if (!nested_vmx_check_permission(vcpu))
5484                 return 1;
5485
5486         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5487                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5488                 return 1;
5489
5490         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5491                                 sizeof(vmptr), &e)) {
5492                 kvm_inject_page_fault(vcpu, &e);
5493                 return 1;
5494         }
5495
5496         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5497                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5498                 skip_emulated_instruction(vcpu);
5499                 return 1;
5500         }
5501
5502         if (vmx->nested.current_vmptr != vmptr) {
5503                 struct vmcs12 *new_vmcs12;
5504                 struct page *page;
5505                 page = nested_get_page(vcpu, vmptr);
5506                 if (page == NULL) {
5507                         nested_vmx_failInvalid(vcpu);
5508                         skip_emulated_instruction(vcpu);
5509                         return 1;
5510                 }
5511                 new_vmcs12 = kmap(page);
5512                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5513                         kunmap(page);
5514                         nested_release_page_clean(page);
5515                         nested_vmx_failValid(vcpu,
5516                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5517                         skip_emulated_instruction(vcpu);
5518                         return 1;
5519                 }
5520                 if (vmx->nested.current_vmptr != -1ull) {
5521                         kunmap(vmx->nested.current_vmcs12_page);
5522                         nested_release_page(vmx->nested.current_vmcs12_page);
5523                 }
5524
5525                 vmx->nested.current_vmptr = vmptr;
5526                 vmx->nested.current_vmcs12 = new_vmcs12;
5527                 vmx->nested.current_vmcs12_page = page;
5528         }
5529
5530         nested_vmx_succeed(vcpu);
5531         skip_emulated_instruction(vcpu);
5532         return 1;
5533 }
5534
5535 /* Emulate the VMPTRST instruction */
5536 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5537 {
5538         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5539         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5540         gva_t vmcs_gva;
5541         struct x86_exception e;
5542
5543         if (!nested_vmx_check_permission(vcpu))
5544                 return 1;
5545
5546         if (get_vmx_mem_address(vcpu, exit_qualification,
5547                         vmx_instruction_info, &vmcs_gva))
5548                 return 1;
5549         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5550         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5551                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5552                                  sizeof(u64), &e)) {
5553                 kvm_inject_page_fault(vcpu, &e);
5554                 return 1;
5555         }
5556         nested_vmx_succeed(vcpu);
5557         skip_emulated_instruction(vcpu);
5558         return 1;
5559 }
5560
5561 /*
5562  * The exit handlers return 1 if the exit was handled fully and guest execution
5563  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5564  * to be done to userspace and return 0.
5565  */
5566 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5567         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5568         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5569         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5570         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5571         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5572         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5573         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5574         [EXIT_REASON_CPUID]                   = handle_cpuid,
5575         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5576         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5577         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5578         [EXIT_REASON_HLT]                     = handle_halt,
5579         [EXIT_REASON_INVD]                    = handle_invd,
5580         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5581         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5582         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5583         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5584         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5585         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5586         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5587         [EXIT_REASON_VMREAD]                  = handle_vmread,
5588         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5589         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5590         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5591         [EXIT_REASON_VMON]                    = handle_vmon,
5592         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5593         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5594         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5595         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5596         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5597         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5598         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5599         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5600         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5601         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5602         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5603 };
5604
5605 static const int kvm_vmx_max_exit_handlers =
5606         ARRAY_SIZE(kvm_vmx_exit_handlers);
5607
5608 /*
5609  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5610  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5611  * disinterest in the current event (read or write a specific MSR) by using an
5612  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5613  */
5614 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5615         struct vmcs12 *vmcs12, u32 exit_reason)
5616 {
5617         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5618         gpa_t bitmap;
5619
5620         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5621                 return 1;
5622
5623         /*
5624          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5625          * for the four combinations of read/write and low/high MSR numbers.
5626          * First we need to figure out which of the four to use:
5627          */
5628         bitmap = vmcs12->msr_bitmap;
5629         if (exit_reason == EXIT_REASON_MSR_WRITE)
5630                 bitmap += 2048;
5631         if (msr_index >= 0xc0000000) {
5632                 msr_index -= 0xc0000000;
5633                 bitmap += 1024;
5634         }
5635
5636         /* Then read the msr_index'th bit from this bitmap: */
5637         if (msr_index < 1024*8) {
5638                 unsigned char b;
5639                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5640                 return 1 & (b >> (msr_index & 7));
5641         } else
5642                 return 1; /* let L1 handle the wrong parameter */
5643 }
5644
5645 /*
5646  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5647  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5648  * intercept (via guest_host_mask etc.) the current event.
5649  */
5650 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5651         struct vmcs12 *vmcs12)
5652 {
5653         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5654         int cr = exit_qualification & 15;
5655         int reg = (exit_qualification >> 8) & 15;
5656         unsigned long val = kvm_register_read(vcpu, reg);
5657
5658         switch ((exit_qualification >> 4) & 3) {
5659         case 0: /* mov to cr */
5660                 switch (cr) {
5661                 case 0:
5662                         if (vmcs12->cr0_guest_host_mask &
5663                             (val ^ vmcs12->cr0_read_shadow))
5664                                 return 1;
5665                         break;
5666                 case 3:
5667                         if ((vmcs12->cr3_target_count >= 1 &&
5668                                         vmcs12->cr3_target_value0 == val) ||
5669                                 (vmcs12->cr3_target_count >= 2 &&
5670                                         vmcs12->cr3_target_value1 == val) ||
5671                                 (vmcs12->cr3_target_count >= 3 &&
5672                                         vmcs12->cr3_target_value2 == val) ||
5673                                 (vmcs12->cr3_target_count >= 4 &&
5674                                         vmcs12->cr3_target_value3 == val))
5675                                 return 0;
5676                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5677                                 return 1;
5678                         break;
5679                 case 4:
5680                         if (vmcs12->cr4_guest_host_mask &
5681                             (vmcs12->cr4_read_shadow ^ val))
5682                                 return 1;
5683                         break;
5684                 case 8:
5685                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5686                                 return 1;
5687                         break;
5688                 }
5689                 break;
5690         case 2: /* clts */
5691                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5692                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5693                         return 1;
5694                 break;
5695         case 1: /* mov from cr */
5696                 switch (cr) {
5697                 case 3:
5698                         if (vmcs12->cpu_based_vm_exec_control &
5699                             CPU_BASED_CR3_STORE_EXITING)
5700                                 return 1;
5701                         break;
5702                 case 8:
5703                         if (vmcs12->cpu_based_vm_exec_control &
5704                             CPU_BASED_CR8_STORE_EXITING)
5705                                 return 1;
5706                         break;
5707                 }
5708                 break;
5709         case 3: /* lmsw */
5710                 /*
5711                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5712                  * cr0. Other attempted changes are ignored, with no exit.
5713                  */
5714                 if (vmcs12->cr0_guest_host_mask & 0xe &
5715                     (val ^ vmcs12->cr0_read_shadow))
5716                         return 1;
5717                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5718                     !(vmcs12->cr0_read_shadow & 0x1) &&
5719                     (val & 0x1))
5720                         return 1;
5721                 break;
5722         }
5723         return 0;
5724 }
5725
5726 /*
5727  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5728  * should handle it ourselves in L0 (and then continue L2). Only call this
5729  * when in is_guest_mode (L2).
5730  */
5731 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5732 {
5733         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5734         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5735         struct vcpu_vmx *vmx = to_vmx(vcpu);
5736         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5737
5738         if (vmx->nested.nested_run_pending)
5739                 return 0;
5740
5741         if (unlikely(vmx->fail)) {
5742                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5743                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5744                 return 1;
5745         }
5746
5747         switch (exit_reason) {
5748         case EXIT_REASON_EXCEPTION_NMI:
5749                 if (!is_exception(intr_info))
5750                         return 0;
5751                 else if (is_page_fault(intr_info))
5752                         return enable_ept;
5753                 return vmcs12->exception_bitmap &
5754                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5755         case EXIT_REASON_EXTERNAL_INTERRUPT:
5756                 return 0;
5757         case EXIT_REASON_TRIPLE_FAULT:
5758                 return 1;
5759         case EXIT_REASON_PENDING_INTERRUPT:
5760         case EXIT_REASON_NMI_WINDOW:
5761                 /*
5762                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5763                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5764                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5765                  * Same for NMI Window Exiting.
5766                  */
5767                 return 1;
5768         case EXIT_REASON_TASK_SWITCH:
5769                 return 1;
5770         case EXIT_REASON_CPUID:
5771                 return 1;
5772         case EXIT_REASON_HLT:
5773                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5774         case EXIT_REASON_INVD:
5775                 return 1;
5776         case EXIT_REASON_INVLPG:
5777                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5778         case EXIT_REASON_RDPMC:
5779                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5780         case EXIT_REASON_RDTSC:
5781                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5782         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5783         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5784         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5785         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5786         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5787                 /*
5788                  * VMX instructions trap unconditionally. This allows L1 to
5789                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5790                  */
5791                 return 1;
5792         case EXIT_REASON_CR_ACCESS:
5793                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5794         case EXIT_REASON_DR_ACCESS:
5795                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5796         case EXIT_REASON_IO_INSTRUCTION:
5797                 /* TODO: support IO bitmaps */
5798                 return 1;
5799         case EXIT_REASON_MSR_READ:
5800         case EXIT_REASON_MSR_WRITE:
5801                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5802         case EXIT_REASON_INVALID_STATE:
5803                 return 1;
5804         case EXIT_REASON_MWAIT_INSTRUCTION:
5805                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5806         case EXIT_REASON_MONITOR_INSTRUCTION:
5807                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5808         case EXIT_REASON_PAUSE_INSTRUCTION:
5809                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5810                         nested_cpu_has2(vmcs12,
5811                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5812         case EXIT_REASON_MCE_DURING_VMENTRY:
5813                 return 0;
5814         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5815                 return 1;
5816         case EXIT_REASON_APIC_ACCESS:
5817                 return nested_cpu_has2(vmcs12,
5818                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5819         case EXIT_REASON_EPT_VIOLATION:
5820         case EXIT_REASON_EPT_MISCONFIG:
5821                 return 0;
5822         case EXIT_REASON_WBINVD:
5823                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5824         case EXIT_REASON_XSETBV:
5825                 return 1;
5826         default:
5827                 return 1;
5828         }
5829 }
5830
5831 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5832 {
5833         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5834         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5835 }
5836
5837 /*
5838  * The guest has exited.  See if we can fix it or if we need userspace
5839  * assistance.
5840  */
5841 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5842 {
5843         struct vcpu_vmx *vmx = to_vmx(vcpu);
5844         u32 exit_reason = vmx->exit_reason;
5845         u32 vectoring_info = vmx->idt_vectoring_info;
5846
5847         /* If guest state is invalid, start emulating */
5848         if (vmx->emulation_required && emulate_invalid_guest_state)
5849                 return handle_invalid_guest_state(vcpu);
5850
5851         /*
5852          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5853          * we did not inject a still-pending event to L1 now because of
5854          * nested_run_pending, we need to re-enable this bit.
5855          */
5856         if (vmx->nested.nested_run_pending)
5857                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5858
5859         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5860             exit_reason == EXIT_REASON_VMRESUME))
5861                 vmx->nested.nested_run_pending = 1;
5862         else
5863                 vmx->nested.nested_run_pending = 0;
5864
5865         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5866                 nested_vmx_vmexit(vcpu);
5867                 return 1;
5868         }
5869
5870         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5871                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5872                 vcpu->run->fail_entry.hardware_entry_failure_reason
5873                         = exit_reason;
5874                 return 0;
5875         }
5876
5877         if (unlikely(vmx->fail)) {
5878                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5879                 vcpu->run->fail_entry.hardware_entry_failure_reason
5880                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5881                 return 0;
5882         }
5883
5884         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5885                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5886                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5887                         exit_reason != EXIT_REASON_TASK_SWITCH))
5888                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5889                        "(0x%x) and exit reason is 0x%x\n",
5890                        __func__, vectoring_info, exit_reason);
5891
5892         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5893             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5894                                         get_vmcs12(vcpu), vcpu)))) {
5895                 if (vmx_interrupt_allowed(vcpu)) {
5896                         vmx->soft_vnmi_blocked = 0;
5897                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5898                            vcpu->arch.nmi_pending) {
5899                         /*
5900                          * This CPU don't support us in finding the end of an
5901                          * NMI-blocked window if the guest runs with IRQs
5902                          * disabled. So we pull the trigger after 1 s of
5903                          * futile waiting, but inform the user about this.
5904                          */
5905                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5906                                "state on VCPU %d after 1 s timeout\n",
5907                                __func__, vcpu->vcpu_id);
5908                         vmx->soft_vnmi_blocked = 0;
5909                 }
5910         }
5911
5912         if (exit_reason < kvm_vmx_max_exit_handlers
5913             && kvm_vmx_exit_handlers[exit_reason])
5914                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5915         else {
5916                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5917                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5918         }
5919         return 0;
5920 }
5921
5922 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5923 {
5924         if (irr == -1 || tpr < irr) {
5925                 vmcs_write32(TPR_THRESHOLD, 0);
5926                 return;
5927         }
5928
5929         vmcs_write32(TPR_THRESHOLD, irr);
5930 }
5931
5932 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5933 {
5934         u32 exit_intr_info;
5935
5936         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5937               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5938                 return;
5939
5940         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5941         exit_intr_info = vmx->exit_intr_info;
5942
5943         /* Handle machine checks before interrupts are enabled */
5944         if (is_machine_check(exit_intr_info))
5945                 kvm_machine_check();
5946
5947         /* We need to handle NMIs before interrupts are enabled */
5948         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5949             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5950                 kvm_before_handle_nmi(&vmx->vcpu);
5951                 asm("int $2");
5952                 kvm_after_handle_nmi(&vmx->vcpu);
5953         }
5954 }
5955
5956 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5957 {
5958         u32 exit_intr_info;
5959         bool unblock_nmi;
5960         u8 vector;
5961         bool idtv_info_valid;
5962
5963         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5964
5965         if (cpu_has_virtual_nmis()) {
5966                 if (vmx->nmi_known_unmasked)
5967                         return;
5968                 /*
5969                  * Can't use vmx->exit_intr_info since we're not sure what
5970                  * the exit reason is.
5971                  */
5972                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5973                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5974                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5975                 /*
5976                  * SDM 3: 27.7.1.2 (September 2008)
5977                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5978                  * a guest IRET fault.
5979                  * SDM 3: 23.2.2 (September 2008)
5980                  * Bit 12 is undefined in any of the following cases:
5981                  *  If the VM exit sets the valid bit in the IDT-vectoring
5982                  *   information field.
5983                  *  If the VM exit is due to a double fault.
5984                  */
5985                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5986                     vector != DF_VECTOR && !idtv_info_valid)
5987                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5988                                       GUEST_INTR_STATE_NMI);
5989                 else
5990                         vmx->nmi_known_unmasked =
5991                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5992                                   & GUEST_INTR_STATE_NMI);
5993         } else if (unlikely(vmx->soft_vnmi_blocked))
5994                 vmx->vnmi_blocked_time +=
5995                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5996 }
5997
5998 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5999                                       u32 idt_vectoring_info,
6000                                       int instr_len_field,
6001                                       int error_code_field)
6002 {
6003         u8 vector;
6004         int type;
6005         bool idtv_info_valid;
6006
6007         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6008
6009         vmx->vcpu.arch.nmi_injected = false;
6010         kvm_clear_exception_queue(&vmx->vcpu);
6011         kvm_clear_interrupt_queue(&vmx->vcpu);
6012
6013         if (!idtv_info_valid)
6014                 return;
6015
6016         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6017
6018         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6019         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6020
6021         switch (type) {
6022         case INTR_TYPE_NMI_INTR:
6023                 vmx->vcpu.arch.nmi_injected = true;
6024                 /*
6025                  * SDM 3: 27.7.1.2 (September 2008)
6026                  * Clear bit "block by NMI" before VM entry if a NMI
6027                  * delivery faulted.
6028                  */
6029                 vmx_set_nmi_mask(&vmx->vcpu, false);
6030                 break;
6031         case INTR_TYPE_SOFT_EXCEPTION:
6032                 vmx->vcpu.arch.event_exit_inst_len =
6033                         vmcs_read32(instr_len_field);
6034                 /* fall through */
6035         case INTR_TYPE_HARD_EXCEPTION:
6036                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6037                         u32 err = vmcs_read32(error_code_field);
6038                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6039                 } else
6040                         kvm_queue_exception(&vmx->vcpu, vector);
6041                 break;
6042         case INTR_TYPE_SOFT_INTR:
6043                 vmx->vcpu.arch.event_exit_inst_len =
6044                         vmcs_read32(instr_len_field);
6045                 /* fall through */
6046         case INTR_TYPE_EXT_INTR:
6047                 kvm_queue_interrupt(&vmx->vcpu, vector,
6048                         type == INTR_TYPE_SOFT_INTR);
6049                 break;
6050         default:
6051                 break;
6052         }
6053 }
6054
6055 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6056 {
6057         if (is_guest_mode(&vmx->vcpu))
6058                 return;
6059         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6060                                   VM_EXIT_INSTRUCTION_LEN,
6061                                   IDT_VECTORING_ERROR_CODE);
6062 }
6063
6064 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6065 {
6066         if (is_guest_mode(vcpu))
6067                 return;
6068         __vmx_complete_interrupts(to_vmx(vcpu),
6069                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6070                                   VM_ENTRY_INSTRUCTION_LEN,
6071                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6072
6073         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6074 }
6075
6076 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6077 {
6078         int i, nr_msrs;
6079         struct perf_guest_switch_msr *msrs;
6080
6081         msrs = perf_guest_get_msrs(&nr_msrs);
6082
6083         if (!msrs)
6084                 return;
6085
6086         for (i = 0; i < nr_msrs; i++)
6087                 if (msrs[i].host == msrs[i].guest)
6088                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6089                 else
6090                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6091                                         msrs[i].host);
6092 }
6093
6094 #ifdef CONFIG_X86_64
6095 #define R "r"
6096 #define Q "q"
6097 #else
6098 #define R "e"
6099 #define Q "l"
6100 #endif
6101
6102 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6103 {
6104         struct vcpu_vmx *vmx = to_vmx(vcpu);
6105
6106         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6107                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6108                 if (vmcs12->idt_vectoring_info_field &
6109                                 VECTORING_INFO_VALID_MASK) {
6110                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6111                                 vmcs12->idt_vectoring_info_field);
6112                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6113                                 vmcs12->vm_exit_instruction_len);
6114                         if (vmcs12->idt_vectoring_info_field &
6115                                         VECTORING_INFO_DELIVER_CODE_MASK)
6116                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6117                                         vmcs12->idt_vectoring_error_code);
6118                 }
6119         }
6120
6121         /* Record the guest's net vcpu time for enforced NMI injections. */
6122         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6123                 vmx->entry_time = ktime_get();
6124
6125         /* Don't enter VMX if guest state is invalid, let the exit handler
6126            start emulation until we arrive back to a valid state */
6127         if (vmx->emulation_required && emulate_invalid_guest_state)
6128                 return;
6129
6130         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6131                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6132         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6133                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6134
6135         /* When single-stepping over STI and MOV SS, we must clear the
6136          * corresponding interruptibility bits in the guest state. Otherwise
6137          * vmentry fails as it then expects bit 14 (BS) in pending debug
6138          * exceptions being set, but that's not correct for the guest debugging
6139          * case. */
6140         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6141                 vmx_set_interrupt_shadow(vcpu, 0);
6142
6143         atomic_switch_perf_msrs(vmx);
6144
6145         vmx->__launched = vmx->loaded_vmcs->launched;
6146         asm(
6147                 /* Store host registers */
6148                 "push %%"R"dx; push %%"R"bp;"
6149                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6150                 "push %%"R"cx \n\t"
6151                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6152                 "je 1f \n\t"
6153                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6154                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6155                 "1: \n\t"
6156                 /* Reload cr2 if changed */
6157                 "mov %c[cr2](%0), %%"R"ax \n\t"
6158                 "mov %%cr2, %%"R"dx \n\t"
6159                 "cmp %%"R"ax, %%"R"dx \n\t"
6160                 "je 2f \n\t"
6161                 "mov %%"R"ax, %%cr2 \n\t"
6162                 "2: \n\t"
6163                 /* Check if vmlaunch of vmresume is needed */
6164                 "cmpl $0, %c[launched](%0) \n\t"
6165                 /* Load guest registers.  Don't clobber flags. */
6166                 "mov %c[rax](%0), %%"R"ax \n\t"
6167                 "mov %c[rbx](%0), %%"R"bx \n\t"
6168                 "mov %c[rdx](%0), %%"R"dx \n\t"
6169                 "mov %c[rsi](%0), %%"R"si \n\t"
6170                 "mov %c[rdi](%0), %%"R"di \n\t"
6171                 "mov %c[rbp](%0), %%"R"bp \n\t"
6172 #ifdef CONFIG_X86_64
6173                 "mov %c[r8](%0),  %%r8  \n\t"
6174                 "mov %c[r9](%0),  %%r9  \n\t"
6175                 "mov %c[r10](%0), %%r10 \n\t"
6176                 "mov %c[r11](%0), %%r11 \n\t"
6177                 "mov %c[r12](%0), %%r12 \n\t"
6178                 "mov %c[r13](%0), %%r13 \n\t"
6179                 "mov %c[r14](%0), %%r14 \n\t"
6180                 "mov %c[r15](%0), %%r15 \n\t"
6181 #endif
6182                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6183
6184                 /* Enter guest mode */
6185                 "jne .Llaunched \n\t"
6186                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6187                 "jmp .Lkvm_vmx_return \n\t"
6188                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6189                 ".Lkvm_vmx_return: "
6190                 /* Save guest registers, load host registers, keep flags */
6191                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6192                 "pop %0 \n\t"
6193                 "mov %%"R"ax, %c[rax](%0) \n\t"
6194                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6195                 "pop"Q" %c[rcx](%0) \n\t"
6196                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6197                 "mov %%"R"si, %c[rsi](%0) \n\t"
6198                 "mov %%"R"di, %c[rdi](%0) \n\t"
6199                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6200 #ifdef CONFIG_X86_64
6201                 "mov %%r8,  %c[r8](%0) \n\t"
6202                 "mov %%r9,  %c[r9](%0) \n\t"
6203                 "mov %%r10, %c[r10](%0) \n\t"
6204                 "mov %%r11, %c[r11](%0) \n\t"
6205                 "mov %%r12, %c[r12](%0) \n\t"
6206                 "mov %%r13, %c[r13](%0) \n\t"
6207                 "mov %%r14, %c[r14](%0) \n\t"
6208                 "mov %%r15, %c[r15](%0) \n\t"
6209 #endif
6210                 "mov %%cr2, %%"R"ax   \n\t"
6211                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6212
6213                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6214                 "setbe %c[fail](%0) \n\t"
6215               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6216                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6217                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6218                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6219                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6220                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6221                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6222                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6223                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6224                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6225                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6226 #ifdef CONFIG_X86_64
6227                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6228                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6229                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6230                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6231                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6232                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6233                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6234                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6235 #endif
6236                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6237                 [wordsize]"i"(sizeof(ulong))
6238               : "cc", "memory"
6239                 , R"ax", R"bx", R"di", R"si"
6240 #ifdef CONFIG_X86_64
6241                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6242 #endif
6243               );
6244
6245         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6246                                   | (1 << VCPU_EXREG_RFLAGS)
6247                                   | (1 << VCPU_EXREG_CPL)
6248                                   | (1 << VCPU_EXREG_PDPTR)
6249                                   | (1 << VCPU_EXREG_SEGMENTS)
6250                                   | (1 << VCPU_EXREG_CR3));
6251         vcpu->arch.regs_dirty = 0;
6252
6253         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6254
6255         if (is_guest_mode(vcpu)) {
6256                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6257                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6258                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6259                         vmcs12->idt_vectoring_error_code =
6260                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6261                         vmcs12->vm_exit_instruction_len =
6262                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6263                 }
6264         }
6265
6266         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6267         vmx->loaded_vmcs->launched = 1;
6268
6269         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6270         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6271
6272         vmx_complete_atomic_exit(vmx);
6273         vmx_recover_nmi_blocking(vmx);
6274         vmx_complete_interrupts(vmx);
6275 }
6276
6277 #undef R
6278 #undef Q
6279
6280 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6281 {
6282         struct vcpu_vmx *vmx = to_vmx(vcpu);
6283
6284         free_vpid(vmx);
6285         free_nested(vmx);
6286         free_loaded_vmcs(vmx->loaded_vmcs);
6287         kfree(vmx->guest_msrs);
6288         kvm_vcpu_uninit(vcpu);
6289         kmem_cache_free(kvm_vcpu_cache, vmx);
6290 }
6291
6292 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6293 {
6294         int err;
6295         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6296         int cpu;
6297
6298         if (!vmx)
6299                 return ERR_PTR(-ENOMEM);
6300
6301         allocate_vpid(vmx);
6302
6303         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6304         if (err)
6305                 goto free_vcpu;
6306
6307         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6308         err = -ENOMEM;
6309         if (!vmx->guest_msrs) {
6310                 goto uninit_vcpu;
6311         }
6312
6313         vmx->loaded_vmcs = &vmx->vmcs01;
6314         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6315         if (!vmx->loaded_vmcs->vmcs)
6316                 goto free_msrs;
6317         if (!vmm_exclusive)
6318                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6319         loaded_vmcs_init(vmx->loaded_vmcs);
6320         if (!vmm_exclusive)
6321                 kvm_cpu_vmxoff();
6322
6323         cpu = get_cpu();
6324         vmx_vcpu_load(&vmx->vcpu, cpu);
6325         vmx->vcpu.cpu = cpu;
6326         err = vmx_vcpu_setup(vmx);
6327         vmx_vcpu_put(&vmx->vcpu);
6328         put_cpu();
6329         if (err)
6330                 goto free_vmcs;
6331         if (vm_need_virtualize_apic_accesses(kvm))
6332                 err = alloc_apic_access_page(kvm);
6333                 if (err)
6334                         goto free_vmcs;
6335
6336         if (enable_ept) {
6337                 if (!kvm->arch.ept_identity_map_addr)
6338                         kvm->arch.ept_identity_map_addr =
6339                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6340                 err = -ENOMEM;
6341                 if (alloc_identity_pagetable(kvm) != 0)
6342                         goto free_vmcs;
6343                 if (!init_rmode_identity_map(kvm))
6344                         goto free_vmcs;
6345         }
6346
6347         vmx->nested.current_vmptr = -1ull;
6348         vmx->nested.current_vmcs12 = NULL;
6349
6350         return &vmx->vcpu;
6351
6352 free_vmcs:
6353         free_loaded_vmcs(vmx->loaded_vmcs);
6354 free_msrs:
6355         kfree(vmx->guest_msrs);
6356 uninit_vcpu:
6357         kvm_vcpu_uninit(&vmx->vcpu);
6358 free_vcpu:
6359         free_vpid(vmx);
6360         kmem_cache_free(kvm_vcpu_cache, vmx);
6361         return ERR_PTR(err);
6362 }
6363
6364 static void __init vmx_check_processor_compat(void *rtn)
6365 {
6366         struct vmcs_config vmcs_conf;
6367
6368         *(int *)rtn = 0;
6369         if (setup_vmcs_config(&vmcs_conf) < 0)
6370                 *(int *)rtn = -EIO;
6371         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6372                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6373                                 smp_processor_id());
6374                 *(int *)rtn = -EIO;
6375         }
6376 }
6377
6378 static int get_ept_level(void)
6379 {
6380         return VMX_EPT_DEFAULT_GAW + 1;
6381 }
6382
6383 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6384 {
6385         u64 ret;
6386
6387         /* For VT-d and EPT combination
6388          * 1. MMIO: always map as UC
6389          * 2. EPT with VT-d:
6390          *   a. VT-d without snooping control feature: can't guarantee the
6391          *      result, try to trust guest.
6392          *   b. VT-d with snooping control feature: snooping control feature of
6393          *      VT-d engine can guarantee the cache correctness. Just set it
6394          *      to WB to keep consistent with host. So the same as item 3.
6395          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6396          *    consistent with host MTRR
6397          */
6398         if (is_mmio)
6399                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6400         else if (vcpu->kvm->arch.iommu_domain &&
6401                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6402                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6403                       VMX_EPT_MT_EPTE_SHIFT;
6404         else
6405                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6406                         | VMX_EPT_IPAT_BIT;
6407
6408         return ret;
6409 }
6410
6411 static int vmx_get_lpage_level(void)
6412 {
6413         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6414                 return PT_DIRECTORY_LEVEL;
6415         else
6416                 /* For shadow and EPT supported 1GB page */
6417                 return PT_PDPE_LEVEL;
6418 }
6419
6420 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6421 {
6422         struct kvm_cpuid_entry2 *best;
6423         struct vcpu_vmx *vmx = to_vmx(vcpu);
6424         u32 exec_control;
6425
6426         vmx->rdtscp_enabled = false;
6427         if (vmx_rdtscp_supported()) {
6428                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6429                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6430                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6431                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6432                                 vmx->rdtscp_enabled = true;
6433                         else {
6434                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6435                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6436                                                 exec_control);
6437                         }
6438                 }
6439         }
6440 }
6441
6442 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6443 {
6444         if (func == 1 && nested)
6445                 entry->ecx |= bit(X86_FEATURE_VMX);
6446 }
6447
6448 /*
6449  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6450  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6451  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6452  * guest in a way that will both be appropriate to L1's requests, and our
6453  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6454  * function also has additional necessary side-effects, like setting various
6455  * vcpu->arch fields.
6456  */
6457 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6458 {
6459         struct vcpu_vmx *vmx = to_vmx(vcpu);
6460         u32 exec_control;
6461
6462         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6463         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6464         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6465         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6466         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6467         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6468         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6469         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6470         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6471         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6472         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6473         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6474         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6475         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6476         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6477         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6478         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6479         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6480         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6481         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6482         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6483         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6484         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6485         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6486         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6487         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6488         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6489         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6490         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6491         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6492         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6493         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6494         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6495         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6496         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6497         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6498
6499         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6500         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6501                 vmcs12->vm_entry_intr_info_field);
6502         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6503                 vmcs12->vm_entry_exception_error_code);
6504         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6505                 vmcs12->vm_entry_instruction_len);
6506         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6507                 vmcs12->guest_interruptibility_info);
6508         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6509         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6510         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6511         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6512         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6513                 vmcs12->guest_pending_dbg_exceptions);
6514         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6515         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6516
6517         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6518
6519         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6520                 (vmcs_config.pin_based_exec_ctrl |
6521                  vmcs12->pin_based_vm_exec_control));
6522
6523         /*
6524          * Whether page-faults are trapped is determined by a combination of
6525          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6526          * If enable_ept, L0 doesn't care about page faults and we should
6527          * set all of these to L1's desires. However, if !enable_ept, L0 does
6528          * care about (at least some) page faults, and because it is not easy
6529          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6530          * to exit on each and every L2 page fault. This is done by setting
6531          * MASK=MATCH=0 and (see below) EB.PF=1.
6532          * Note that below we don't need special code to set EB.PF beyond the
6533          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6534          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6535          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6536          *
6537          * A problem with this approach (when !enable_ept) is that L1 may be
6538          * injected with more page faults than it asked for. This could have
6539          * caused problems, but in practice existing hypervisors don't care.
6540          * To fix this, we will need to emulate the PFEC checking (on the L1
6541          * page tables), using walk_addr(), when injecting PFs to L1.
6542          */
6543         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6544                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6545         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6546                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6547
6548         if (cpu_has_secondary_exec_ctrls()) {
6549                 u32 exec_control = vmx_secondary_exec_control(vmx);
6550                 if (!vmx->rdtscp_enabled)
6551                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6552                 /* Take the following fields only from vmcs12 */
6553                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6554                 if (nested_cpu_has(vmcs12,
6555                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6556                         exec_control |= vmcs12->secondary_vm_exec_control;
6557
6558                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6559                         /*
6560                          * Translate L1 physical address to host physical
6561                          * address for vmcs02. Keep the page pinned, so this
6562                          * physical address remains valid. We keep a reference
6563                          * to it so we can release it later.
6564                          */
6565                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6566                                 nested_release_page(vmx->nested.apic_access_page);
6567                         vmx->nested.apic_access_page =
6568                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6569                         /*
6570                          * If translation failed, no matter: This feature asks
6571                          * to exit when accessing the given address, and if it
6572                          * can never be accessed, this feature won't do
6573                          * anything anyway.
6574                          */
6575                         if (!vmx->nested.apic_access_page)
6576                                 exec_control &=
6577                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6578                         else
6579                                 vmcs_write64(APIC_ACCESS_ADDR,
6580                                   page_to_phys(vmx->nested.apic_access_page));
6581                 }
6582
6583                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6584         }
6585
6586
6587         /*
6588          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6589          * Some constant fields are set here by vmx_set_constant_host_state().
6590          * Other fields are different per CPU, and will be set later when
6591          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6592          */
6593         vmx_set_constant_host_state();
6594
6595         /*
6596          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6597          * entry, but only if the current (host) sp changed from the value
6598          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6599          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6600          * here we just force the write to happen on entry.
6601          */
6602         vmx->host_rsp = 0;
6603
6604         exec_control = vmx_exec_control(vmx); /* L0's desires */
6605         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6606         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6607         exec_control &= ~CPU_BASED_TPR_SHADOW;
6608         exec_control |= vmcs12->cpu_based_vm_exec_control;
6609         /*
6610          * Merging of IO and MSR bitmaps not currently supported.
6611          * Rather, exit every time.
6612          */
6613         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6614         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6615         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6616
6617         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6618
6619         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6620          * bitwise-or of what L1 wants to trap for L2, and what we want to
6621          * trap. Note that CR0.TS also needs updating - we do this later.
6622          */
6623         update_exception_bitmap(vcpu);
6624         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6625         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6626
6627         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6628         vmcs_write32(VM_EXIT_CONTROLS,
6629                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6630         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6631                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6632
6633         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6634                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6635         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6636                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6637
6638
6639         set_cr4_guest_host_mask(vmx);
6640
6641         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6642                 vmcs_write64(TSC_OFFSET,
6643                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6644         else
6645                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6646
6647         if (enable_vpid) {
6648                 /*
6649                  * Trivially support vpid by letting L2s share their parent
6650                  * L1's vpid. TODO: move to a more elaborate solution, giving
6651                  * each L2 its own vpid and exposing the vpid feature to L1.
6652                  */
6653                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6654                 vmx_flush_tlb(vcpu);
6655         }
6656
6657         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6658                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6659         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6660                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6661         else
6662                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6663         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6664         vmx_set_efer(vcpu, vcpu->arch.efer);
6665
6666         /*
6667          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6668          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6669          * The CR0_READ_SHADOW is what L2 should have expected to read given
6670          * the specifications by L1; It's not enough to take
6671          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6672          * have more bits than L1 expected.
6673          */
6674         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6675         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6676
6677         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6678         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6679
6680         /* shadow page tables on either EPT or shadow page tables */
6681         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6682         kvm_mmu_reset_context(vcpu);
6683
6684         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6685         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6686 }
6687
6688 /*
6689  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6690  * for running an L2 nested guest.
6691  */
6692 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6693 {
6694         struct vmcs12 *vmcs12;
6695         struct vcpu_vmx *vmx = to_vmx(vcpu);
6696         int cpu;
6697         struct loaded_vmcs *vmcs02;
6698
6699         if (!nested_vmx_check_permission(vcpu) ||
6700             !nested_vmx_check_vmcs12(vcpu))
6701                 return 1;
6702
6703         skip_emulated_instruction(vcpu);
6704         vmcs12 = get_vmcs12(vcpu);
6705
6706         /*
6707          * The nested entry process starts with enforcing various prerequisites
6708          * on vmcs12 as required by the Intel SDM, and act appropriately when
6709          * they fail: As the SDM explains, some conditions should cause the
6710          * instruction to fail, while others will cause the instruction to seem
6711          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6712          * To speed up the normal (success) code path, we should avoid checking
6713          * for misconfigurations which will anyway be caught by the processor
6714          * when using the merged vmcs02.
6715          */
6716         if (vmcs12->launch_state == launch) {
6717                 nested_vmx_failValid(vcpu,
6718                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6719                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6720                 return 1;
6721         }
6722
6723         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6724                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6725                 /*TODO: Also verify bits beyond physical address width are 0*/
6726                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6727                 return 1;
6728         }
6729
6730         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6731                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6732                 /*TODO: Also verify bits beyond physical address width are 0*/
6733                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6734                 return 1;
6735         }
6736
6737         if (vmcs12->vm_entry_msr_load_count > 0 ||
6738             vmcs12->vm_exit_msr_load_count > 0 ||
6739             vmcs12->vm_exit_msr_store_count > 0) {
6740                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6741                                     __func__);
6742                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6743                 return 1;
6744         }
6745
6746         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6747               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6748             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6749               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6750             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6751               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6752             !vmx_control_verify(vmcs12->vm_exit_controls,
6753               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6754             !vmx_control_verify(vmcs12->vm_entry_controls,
6755               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6756         {
6757                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6758                 return 1;
6759         }
6760
6761         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6762             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6763                 nested_vmx_failValid(vcpu,
6764                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6765                 return 1;
6766         }
6767
6768         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6769             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6770                 nested_vmx_entry_failure(vcpu, vmcs12,
6771                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6772                 return 1;
6773         }
6774         if (vmcs12->vmcs_link_pointer != -1ull) {
6775                 nested_vmx_entry_failure(vcpu, vmcs12,
6776                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6777                 return 1;
6778         }
6779
6780         /*
6781          * We're finally done with prerequisite checking, and can start with
6782          * the nested entry.
6783          */
6784
6785         vmcs02 = nested_get_current_vmcs02(vmx);
6786         if (!vmcs02)
6787                 return -ENOMEM;
6788
6789         enter_guest_mode(vcpu);
6790
6791         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6792
6793         cpu = get_cpu();
6794         vmx->loaded_vmcs = vmcs02;
6795         vmx_vcpu_put(vcpu);
6796         vmx_vcpu_load(vcpu, cpu);
6797         vcpu->cpu = cpu;
6798         put_cpu();
6799
6800         vmcs12->launch_state = 1;
6801
6802         prepare_vmcs02(vcpu, vmcs12);
6803
6804         /*
6805          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6806          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6807          * returned as far as L1 is concerned. It will only return (and set
6808          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6809          */
6810         return 1;
6811 }
6812
6813 /*
6814  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6815  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6816  * This function returns the new value we should put in vmcs12.guest_cr0.
6817  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6818  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6819  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6820  *     didn't trap the bit, because if L1 did, so would L0).
6821  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6822  *     been modified by L2, and L1 knows it. So just leave the old value of
6823  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6824  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6825  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6826  *     changed these bits, and therefore they need to be updated, but L0
6827  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6828  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6829  */
6830 static inline unsigned long
6831 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6832 {
6833         return
6834         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6835         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6836         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6837                         vcpu->arch.cr0_guest_owned_bits));
6838 }
6839
6840 static inline unsigned long
6841 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6842 {
6843         return
6844         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6845         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6846         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6847                         vcpu->arch.cr4_guest_owned_bits));
6848 }
6849
6850 /*
6851  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6852  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6853  * and this function updates it to reflect the changes to the guest state while
6854  * L2 was running (and perhaps made some exits which were handled directly by L0
6855  * without going back to L1), and to reflect the exit reason.
6856  * Note that we do not have to copy here all VMCS fields, just those that
6857  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6858  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6859  * which already writes to vmcs12 directly.
6860  */
6861 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6862 {
6863         /* update guest state fields: */
6864         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6865         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6866
6867         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6868         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6869         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6870         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6871
6872         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6873         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6874         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6875         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6876         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6877         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6878         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6879         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6880         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6881         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6882         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6883         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6884         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6885         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6886         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6887         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6888         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6889         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6890         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6891         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6892         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6893         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6894         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6895         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6896         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6897         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6898         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6899         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6900         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6901         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6902         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6903         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6904         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6905         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6906         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6907         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6908
6909         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6910         vmcs12->guest_interruptibility_info =
6911                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6912         vmcs12->guest_pending_dbg_exceptions =
6913                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6914
6915         /* TODO: These cannot have changed unless we have MSR bitmaps and
6916          * the relevant bit asks not to trap the change */
6917         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6918         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6919                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6920         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6921         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6922         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6923
6924         /* update exit information fields: */
6925
6926         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6927         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6928
6929         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6930         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6931         vmcs12->idt_vectoring_info_field =
6932                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6933         vmcs12->idt_vectoring_error_code =
6934                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6935         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6936         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6937
6938         /* clear vm-entry fields which are to be cleared on exit */
6939         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6940                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6941 }
6942
6943 /*
6944  * A part of what we need to when the nested L2 guest exits and we want to
6945  * run its L1 parent, is to reset L1's guest state to the host state specified
6946  * in vmcs12.
6947  * This function is to be called not only on normal nested exit, but also on
6948  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6949  * Failures During or After Loading Guest State").
6950  * This function should be called when the active VMCS is L1's (vmcs01).
6951  */
6952 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6953 {
6954         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6955                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6956         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6957                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6958         else
6959                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6960         vmx_set_efer(vcpu, vcpu->arch.efer);
6961
6962         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6963         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6964         /*
6965          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6966          * actually changed, because it depends on the current state of
6967          * fpu_active (which may have changed).
6968          * Note that vmx_set_cr0 refers to efer set above.
6969          */
6970         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6971         /*
6972          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6973          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6974          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6975          */
6976         update_exception_bitmap(vcpu);
6977         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6978         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6979
6980         /*
6981          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6982          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6983          */
6984         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6985         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6986
6987         /* shadow page tables on either EPT or shadow page tables */
6988         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6989         kvm_mmu_reset_context(vcpu);
6990
6991         if (enable_vpid) {
6992                 /*
6993                  * Trivially support vpid by letting L2s share their parent
6994                  * L1's vpid. TODO: move to a more elaborate solution, giving
6995                  * each L2 its own vpid and exposing the vpid feature to L1.
6996                  */
6997                 vmx_flush_tlb(vcpu);
6998         }
6999
7000
7001         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7002         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7003         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7004         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7005         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7006         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7007         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7008         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7009         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7010         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7011         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7012         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7013         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7014         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7015         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7016
7017         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7018                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7019         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7020                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7021                         vmcs12->host_ia32_perf_global_ctrl);
7022 }
7023
7024 /*
7025  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7026  * and modify vmcs12 to make it see what it would expect to see there if
7027  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7028  */
7029 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7030 {
7031         struct vcpu_vmx *vmx = to_vmx(vcpu);
7032         int cpu;
7033         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7034
7035         leave_guest_mode(vcpu);
7036         prepare_vmcs12(vcpu, vmcs12);
7037
7038         cpu = get_cpu();
7039         vmx->loaded_vmcs = &vmx->vmcs01;
7040         vmx_vcpu_put(vcpu);
7041         vmx_vcpu_load(vcpu, cpu);
7042         vcpu->cpu = cpu;
7043         put_cpu();
7044
7045         /* if no vmcs02 cache requested, remove the one we used */
7046         if (VMCS02_POOL_SIZE == 0)
7047                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7048
7049         load_vmcs12_host_state(vcpu, vmcs12);
7050
7051         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7052         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7053
7054         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7055         vmx->host_rsp = 0;
7056
7057         /* Unpin physical memory we referred to in vmcs02 */
7058         if (vmx->nested.apic_access_page) {
7059                 nested_release_page(vmx->nested.apic_access_page);
7060                 vmx->nested.apic_access_page = 0;
7061         }
7062
7063         /*
7064          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7065          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7066          * success or failure flag accordingly.
7067          */
7068         if (unlikely(vmx->fail)) {
7069                 vmx->fail = 0;
7070                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7071         } else
7072                 nested_vmx_succeed(vcpu);
7073 }
7074
7075 /*
7076  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7077  * 23.7 "VM-entry failures during or after loading guest state" (this also
7078  * lists the acceptable exit-reason and exit-qualification parameters).
7079  * It should only be called before L2 actually succeeded to run, and when
7080  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7081  */
7082 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7083                         struct vmcs12 *vmcs12,
7084                         u32 reason, unsigned long qualification)
7085 {
7086         load_vmcs12_host_state(vcpu, vmcs12);
7087         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7088         vmcs12->exit_qualification = qualification;
7089         nested_vmx_succeed(vcpu);
7090 }
7091
7092 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7093                                struct x86_instruction_info *info,
7094                                enum x86_intercept_stage stage)
7095 {
7096         return X86EMUL_CONTINUE;
7097 }
7098
7099 static struct kvm_x86_ops vmx_x86_ops = {
7100         .cpu_has_kvm_support = cpu_has_kvm_support,
7101         .disabled_by_bios = vmx_disabled_by_bios,
7102         .hardware_setup = hardware_setup,
7103         .hardware_unsetup = hardware_unsetup,
7104         .check_processor_compatibility = vmx_check_processor_compat,
7105         .hardware_enable = hardware_enable,
7106         .hardware_disable = hardware_disable,
7107         .cpu_has_accelerated_tpr = report_flexpriority,
7108
7109         .vcpu_create = vmx_create_vcpu,
7110         .vcpu_free = vmx_free_vcpu,
7111         .vcpu_reset = vmx_vcpu_reset,
7112
7113         .prepare_guest_switch = vmx_save_host_state,
7114         .vcpu_load = vmx_vcpu_load,
7115         .vcpu_put = vmx_vcpu_put,
7116
7117         .set_guest_debug = set_guest_debug,
7118         .get_msr = vmx_get_msr,
7119         .set_msr = vmx_set_msr,
7120         .get_segment_base = vmx_get_segment_base,
7121         .get_segment = vmx_get_segment,
7122         .set_segment = vmx_set_segment,
7123         .get_cpl = vmx_get_cpl,
7124         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7125         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7126         .decache_cr3 = vmx_decache_cr3,
7127         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7128         .set_cr0 = vmx_set_cr0,
7129         .set_cr3 = vmx_set_cr3,
7130         .set_cr4 = vmx_set_cr4,
7131         .set_efer = vmx_set_efer,
7132         .get_idt = vmx_get_idt,
7133         .set_idt = vmx_set_idt,
7134         .get_gdt = vmx_get_gdt,
7135         .set_gdt = vmx_set_gdt,
7136         .set_dr7 = vmx_set_dr7,
7137         .cache_reg = vmx_cache_reg,
7138         .get_rflags = vmx_get_rflags,
7139         .set_rflags = vmx_set_rflags,
7140         .fpu_activate = vmx_fpu_activate,
7141         .fpu_deactivate = vmx_fpu_deactivate,
7142
7143         .tlb_flush = vmx_flush_tlb,
7144
7145         .run = vmx_vcpu_run,
7146         .handle_exit = vmx_handle_exit,
7147         .skip_emulated_instruction = skip_emulated_instruction,
7148         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7149         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7150         .patch_hypercall = vmx_patch_hypercall,
7151         .set_irq = vmx_inject_irq,
7152         .set_nmi = vmx_inject_nmi,
7153         .queue_exception = vmx_queue_exception,
7154         .cancel_injection = vmx_cancel_injection,
7155         .interrupt_allowed = vmx_interrupt_allowed,
7156         .nmi_allowed = vmx_nmi_allowed,
7157         .get_nmi_mask = vmx_get_nmi_mask,
7158         .set_nmi_mask = vmx_set_nmi_mask,
7159         .enable_nmi_window = enable_nmi_window,
7160         .enable_irq_window = enable_irq_window,
7161         .update_cr8_intercept = update_cr8_intercept,
7162
7163         .set_tss_addr = vmx_set_tss_addr,
7164         .get_tdp_level = get_ept_level,
7165         .get_mt_mask = vmx_get_mt_mask,
7166
7167         .get_exit_info = vmx_get_exit_info,
7168
7169         .get_lpage_level = vmx_get_lpage_level,
7170
7171         .cpuid_update = vmx_cpuid_update,
7172
7173         .rdtscp_supported = vmx_rdtscp_supported,
7174
7175         .set_supported_cpuid = vmx_set_supported_cpuid,
7176
7177         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7178
7179         .set_tsc_khz = vmx_set_tsc_khz,
7180         .write_tsc_offset = vmx_write_tsc_offset,
7181         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7182         .compute_tsc_offset = vmx_compute_tsc_offset,
7183         .read_l1_tsc = vmx_read_l1_tsc,
7184
7185         .set_tdp_cr3 = vmx_set_cr3,
7186
7187         .check_intercept = vmx_check_intercept,
7188 };
7189
7190 static int __init vmx_init(void)
7191 {
7192         int r, i;
7193
7194         rdmsrl_safe(MSR_EFER, &host_efer);
7195
7196         for (i = 0; i < NR_VMX_MSR; ++i)
7197                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7198
7199         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7200         if (!vmx_io_bitmap_a)
7201                 return -ENOMEM;
7202
7203         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7204         if (!vmx_io_bitmap_b) {
7205                 r = -ENOMEM;
7206                 goto out;
7207         }
7208
7209         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7210         if (!vmx_msr_bitmap_legacy) {
7211                 r = -ENOMEM;
7212                 goto out1;
7213         }
7214
7215         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7216         if (!vmx_msr_bitmap_longmode) {
7217                 r = -ENOMEM;
7218                 goto out2;
7219         }
7220
7221         /*
7222          * Allow direct access to the PC debug port (it is often used for I/O
7223          * delays, but the vmexits simply slow things down).
7224          */
7225         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7226         clear_bit(0x80, vmx_io_bitmap_a);
7227
7228         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7229
7230         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7231         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7232
7233         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7234
7235         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7236                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7237         if (r)
7238                 goto out3;
7239
7240         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7241         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7242         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7243         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7244         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7245         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7246
7247         if (enable_ept) {
7248                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7249                                 VMX_EPT_EXECUTABLE_MASK);
7250                 ept_set_mmio_spte_mask();
7251                 kvm_enable_tdp();
7252         } else
7253                 kvm_disable_tdp();
7254
7255         return 0;
7256
7257 out3:
7258         free_page((unsigned long)vmx_msr_bitmap_longmode);
7259 out2:
7260         free_page((unsigned long)vmx_msr_bitmap_legacy);
7261 out1:
7262         free_page((unsigned long)vmx_io_bitmap_b);
7263 out:
7264         free_page((unsigned long)vmx_io_bitmap_a);
7265         return r;
7266 }
7267
7268 static void __exit vmx_exit(void)
7269 {
7270         free_page((unsigned long)vmx_msr_bitmap_legacy);
7271         free_page((unsigned long)vmx_msr_bitmap_longmode);
7272         free_page((unsigned long)vmx_io_bitmap_b);
7273         free_page((unsigned long)vmx_io_bitmap_a);
7274
7275         kvm_exit();
7276 }
7277
7278 module_init(vmx_init)
7279 module_exit(vmx_exit)