arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define DR7_GD_MASK (1 << 13)
  42 #define DR6_BD_MASK (1 << 13)
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50
  51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  52
  53 /* enable NPT for AMD64 and X86 with PAE */
  54 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  55 static bool npt_enabled = true;
  56 #else
  57 static bool npt_enabled = false;
  58 #endif
  59 static int npt = 1;
  60
  61 module_param(npt, int, S_IRUGO);
  62
  63 static void kvm_reput_irq(struct vcpu_svm *svm);
  64 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  65
  66 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  67 {
  68         return container_of(vcpu, struct vcpu_svm, vcpu);
  69 }
  70
  71 static unsigned long iopm_base;
  72
  73 struct kvm_ldttss_desc {
  74         u16 limit0;
  75         u16 base0;
  76         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  77         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  78         u32 base3;
  79         u32 zero1;
  80 } __attribute__((packed));
  81
  82 struct svm_cpu_data {
  83         int cpu;
  84
  85         u64 asid_generation;
  86         u32 max_asid;
  87         u32 next_asid;
  88         struct kvm_ldttss_desc *tss_desc;
  89
  90         struct page *save_area;
  91 };
  92
  93 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  94 static uint32_t svm_features;
  95
  96 struct svm_init_data {
  97         int cpu;
  98         int r;
  99 };
 100
 101 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 102
 103 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 104 #define MSRS_RANGE_SIZE 2048
 105 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 106
 107 #define MAX_INST_SIZE 15
 108
 109 static inline u32 svm_has(u32 feat)
 110 {
 111         return svm_features & feat;
 112 }
 113
 114 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 115 {
 116         int word_index = __ffs(vcpu->arch.irq_summary);
 117         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 118         int irq = word_index * BITS_PER_LONG + bit_index;
 119
 120         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 121         if (!vcpu->arch.irq_pending[word_index])
 122                 clear_bit(word_index, &vcpu->arch.irq_summary);
 123         return irq;
 124 }
 125
 126 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 127 {
 128         set_bit(irq, vcpu->arch.irq_pending);
 129         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 130 }
 131
 132 static inline void clgi(void)
 133 {
 134         asm volatile (__ex(SVM_CLGI));
 135 }
 136
 137 static inline void stgi(void)
 138 {
 139         asm volatile (__ex(SVM_STGI));
 140 }
 141
 142 static inline void invlpga(unsigned long addr, u32 asid)
 143 {
 144         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 145 }
 146
 147 static inline unsigned long kvm_read_cr2(void)
 148 {
 149         unsigned long cr2;
 150
 151         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 152         return cr2;
 153 }
 154
 155 static inline void kvm_write_cr2(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%cr2" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr6(void)
 161 {
 162         unsigned long dr6;
 163
 164         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 165         return dr6;
 166 }
 167
 168 static inline void write_dr6(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr6" :: "r" (val));
 171 }
 172
 173 static inline unsigned long read_dr7(void)
 174 {
 175         unsigned long dr7;
 176
 177         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 178         return dr7;
 179 }
 180
 181 static inline void write_dr7(unsigned long val)
 182 {
 183         asm volatile ("mov %0, %%dr7" :: "r" (val));
 184 }
 185
 186 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 187 {
 188         to_svm(vcpu)->asid_generation--;
 189 }
 190
 191 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 192 {
 193         force_new_asid(vcpu);
 194 }
 195
 196 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 197 {
 198         if (!npt_enabled && !(efer & EFER_LMA))
 199                 efer &= ~EFER_LME;
 200
 201         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 202         vcpu->arch.shadow_efer = efer;
 203 }
 204
 205 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 206                                 bool has_error_code, u32 error_code)
 207 {
 208         struct vcpu_svm *svm = to_svm(vcpu);
 209
 210         svm->vmcb->control.event_inj = nr
 211                 | SVM_EVTINJ_VALID
 212                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 213                 | SVM_EVTINJ_TYPE_EXEPT;
 214         svm->vmcb->control.event_inj_err = error_code;
 215 }
 216
 217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 222 }
 223
 224 static int is_external_interrupt(u32 info)
 225 {
 226         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 227         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 228 }
 229
 230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 231 {
 232         struct vcpu_svm *svm = to_svm(vcpu);
 233
 234         if (!svm->next_rip) {
 235                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 236                 return;
 237         }
 238         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 239                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 240                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 241
 242         kvm_rip_write(vcpu, svm->next_rip);
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = 1;
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         const char *msg;
 251
 252         if (!cpu_has_svm(&msg)) {
 253                 printk(KERN_INFO "has_svn: %s\n", msg);
 254                 return 0;
 255         }
 256
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         uint64_t efer;
 263
 264         wrmsrl(MSR_VM_HSAVE_PA, 0);
 265         rdmsrl(MSR_EFER, efer);
 266         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 267 }
 268
 269 static void svm_hardware_enable(void *garbage)
 270 {
 271
 272         struct svm_cpu_data *svm_data;
 273         uint64_t efer;
 274         struct desc_ptr gdt_descr;
 275         struct desc_struct *gdt;
 276         int me = raw_smp_processor_id();
 277
 278         if (!has_svm()) {
 279                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 280                 return;
 281         }
 282         svm_data = per_cpu(svm_data, me);
 283
 284         if (!svm_data) {
 285                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 286                        me);
 287                 return;
 288         }
 289
 290         svm_data->asid_generation = 1;
 291         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 292         svm_data->next_asid = svm_data->max_asid + 1;
 293
 294         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 295         gdt = (struct desc_struct *)gdt_descr.address;
 296         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 297
 298         rdmsrl(MSR_EFER, efer);
 299         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 300
 301         wrmsrl(MSR_VM_HSAVE_PA,
 302                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 303 }
 304
 305 static void svm_cpu_uninit(int cpu)
 306 {
 307         struct svm_cpu_data *svm_data
 308                 = per_cpu(svm_data, raw_smp_processor_id());
 309
 310         if (!svm_data)
 311                 return;
 312
 313         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 314         __free_page(svm_data->save_area);
 315         kfree(svm_data);
 316 }
 317
 318 static int svm_cpu_init(int cpu)
 319 {
 320         struct svm_cpu_data *svm_data;
 321         int r;
 322
 323         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 324         if (!svm_data)
 325                 return -ENOMEM;
 326         svm_data->cpu = cpu;
 327         svm_data->save_area = alloc_page(GFP_KERNEL);
 328         r = -ENOMEM;
 329         if (!svm_data->save_area)
 330                 goto err_1;
 331
 332         per_cpu(svm_data, cpu) = svm_data;
 333
 334         return 0;
 335
 336 err_1:
 337         kfree(svm_data);
 338         return r;
 339
 340 }
 341
 342 static void set_msr_interception(u32 *msrpm, unsigned msr,
 343                                  int read, int write)
 344 {
 345         int i;
 346
 347         for (i = 0; i < NUM_MSR_MAPS; i++) {
 348                 if (msr >= msrpm_ranges[i] &&
 349                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 350                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 351                                           msrpm_ranges[i]) * 2;
 352
 353                         u32 *base = msrpm + (msr_offset / 32);
 354                         u32 msr_shift = msr_offset % 32;
 355                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 356                         *base = (*base & ~(0x3 << msr_shift)) |
 357                                 (mask << msr_shift);
 358                         return;
 359                 }
 360         }
 361         BUG();
 362 }
 363
 364 static void svm_vcpu_init_msrpm(u32 *msrpm)
 365 {
 366         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 367
 368 #ifdef CONFIG_X86_64
 369         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 370         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 371         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 372         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 373         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 374         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 375 #endif
 376         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 377         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 378         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 379         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 380 }
 381
 382 static void svm_enable_lbrv(struct vcpu_svm *svm)
 383 {
 384         u32 *msrpm = svm->msrpm;
 385
 386         svm->vmcb->control.lbr_ctl = 1;
 387         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 388         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 389         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 390         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 391 }
 392
 393 static void svm_disable_lbrv(struct vcpu_svm *svm)
 394 {
 395         u32 *msrpm = svm->msrpm;
 396
 397         svm->vmcb->control.lbr_ctl = 0;
 398         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 399         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 400         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 401         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 402 }
 403
 404 static __init int svm_hardware_setup(void)
 405 {
 406         int cpu;
 407         struct page *iopm_pages;
 408         void *iopm_va;
 409         int r;
 410
 411         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 412
 413         if (!iopm_pages)
 414                 return -ENOMEM;
 415
 416         iopm_va = page_address(iopm_pages);
 417         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 418         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 419         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 420
 421         if (boot_cpu_has(X86_FEATURE_NX))
 422                 kvm_enable_efer_bits(EFER_NX);
 423
 424         for_each_online_cpu(cpu) {
 425                 r = svm_cpu_init(cpu);
 426                 if (r)
 427                         goto err;
 428         }
 429
 430         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 431
 432         if (!svm_has(SVM_FEATURE_NPT))
 433                 npt_enabled = false;
 434
 435         if (npt_enabled && !npt) {
 436                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 437                 npt_enabled = false;
 438         }
 439
 440         if (npt_enabled) {
 441                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 442                 kvm_enable_tdp();
 443         } else
 444                 kvm_disable_tdp();
 445
 446         return 0;
 447
 448 err:
 449         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 450         iopm_base = 0;
 451         return r;
 452 }
 453
 454 static __exit void svm_hardware_unsetup(void)
 455 {
 456         int cpu;
 457
 458         for_each_online_cpu(cpu)
 459                 svm_cpu_uninit(cpu);
 460
 461         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 462         iopm_base = 0;
 463 }
 464
 465 static void init_seg(struct vmcb_seg *seg)
 466 {
 467         seg->selector = 0;
 468         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 469                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 470         seg->limit = 0xffff;
 471         seg->base = 0;
 472 }
 473
 474 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 475 {
 476         seg->selector = 0;
 477         seg->attrib = SVM_SELECTOR_P_MASK | type;
 478         seg->limit = 0xffff;
 479         seg->base = 0;
 480 }
 481
 482 static void init_vmcb(struct vcpu_svm *svm)
 483 {
 484         struct vmcb_control_area *control = &svm->vmcb->control;
 485         struct vmcb_save_area *save = &svm->vmcb->save;
 486
 487         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 488                                         INTERCEPT_CR3_MASK |
 489                                         INTERCEPT_CR4_MASK;
 490
 491         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 492                                         INTERCEPT_CR3_MASK |
 493                                         INTERCEPT_CR4_MASK |
 494                                         INTERCEPT_CR8_MASK;
 495
 496         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 497                                         INTERCEPT_DR1_MASK |
 498                                         INTERCEPT_DR2_MASK |
 499                                         INTERCEPT_DR3_MASK;
 500
 501         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 502                                         INTERCEPT_DR1_MASK |
 503                                         INTERCEPT_DR2_MASK |
 504                                         INTERCEPT_DR3_MASK |
 505                                         INTERCEPT_DR5_MASK |
 506                                         INTERCEPT_DR7_MASK;
 507
 508         control->intercept_exceptions = (1 << PF_VECTOR) |
 509                                         (1 << UD_VECTOR) |
 510                                         (1 << MC_VECTOR);
 511
 512
 513         control->intercept =    (1ULL << INTERCEPT_INTR) |
 514                                 (1ULL << INTERCEPT_NMI) |
 515                                 (1ULL << INTERCEPT_SMI) |
 516                                 (1ULL << INTERCEPT_CPUID) |
 517                                 (1ULL << INTERCEPT_INVD) |
 518                                 (1ULL << INTERCEPT_HLT) |
 519                                 (1ULL << INTERCEPT_INVLPG) |
 520                                 (1ULL << INTERCEPT_INVLPGA) |
 521                                 (1ULL << INTERCEPT_IOIO_PROT) |
 522                                 (1ULL << INTERCEPT_MSR_PROT) |
 523                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 524                                 (1ULL << INTERCEPT_SHUTDOWN) |
 525                                 (1ULL << INTERCEPT_VMRUN) |
 526                                 (1ULL << INTERCEPT_VMMCALL) |
 527                                 (1ULL << INTERCEPT_VMLOAD) |
 528                                 (1ULL << INTERCEPT_VMSAVE) |
 529                                 (1ULL << INTERCEPT_STGI) |
 530                                 (1ULL << INTERCEPT_CLGI) |
 531                                 (1ULL << INTERCEPT_SKINIT) |
 532                                 (1ULL << INTERCEPT_WBINVD) |
 533                                 (1ULL << INTERCEPT_MONITOR) |
 534                                 (1ULL << INTERCEPT_MWAIT);
 535
 536         control->iopm_base_pa = iopm_base;
 537         control->msrpm_base_pa = __pa(svm->msrpm);
 538         control->tsc_offset = 0;
 539         control->int_ctl = V_INTR_MASKING_MASK;
 540
 541         init_seg(&save->es);
 542         init_seg(&save->ss);
 543         init_seg(&save->ds);
 544         init_seg(&save->fs);
 545         init_seg(&save->gs);
 546
 547         save->cs.selector = 0xf000;
 548         /* Executable/Readable Code Segment */
 549         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 550                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 551         save->cs.limit = 0xffff;
 552         /*
 553          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 554          * be consistent with it.
 555          *
 556          * Replace when we have real mode working for vmx.
 557          */
 558         save->cs.base = 0xf0000;
 559
 560         save->gdtr.limit = 0xffff;
 561         save->idtr.limit = 0xffff;
 562
 563         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 564         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 565
 566         save->efer = MSR_EFER_SVME_MASK;
 567         save->dr6 = 0xffff0ff0;
 568         save->dr7 = 0x400;
 569         save->rflags = 2;
 570         save->rip = 0x0000fff0;
 571         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 572
 573         /*
 574          * cr0 val on cpu init should be 0x60000010, we enable cpu
 575          * cache by default. the orderly way is to enable cache in bios.
 576          */
 577         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 578         save->cr4 = X86_CR4_PAE;
 579         /* rdx = ?? */
 580
 581         if (npt_enabled) {
 582                 /* Setup VMCB for Nested Paging */
 583                 control->nested_ctl = 1;
 584                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 585                                         (1ULL << INTERCEPT_INVLPG));
 586                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 587                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 588                                                 INTERCEPT_CR3_MASK);
 589                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 590                                                  INTERCEPT_CR3_MASK);
 591                 save->g_pat = 0x0007040600070406ULL;
 592                 /* enable caching because the QEMU Bios doesn't enable it */
 593                 save->cr0 = X86_CR0_ET;
 594                 save->cr3 = 0;
 595                 save->cr4 = 0;
 596         }
 597         force_new_asid(&svm->vcpu);
 598 }
 599
 600 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         init_vmcb(svm);
 605
 606         if (vcpu->vcpu_id != 0) {
 607                 kvm_rip_write(vcpu, 0);
 608                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 609                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 610         }
 611         vcpu->arch.regs_avail = ~0;
 612         vcpu->arch.regs_dirty = ~0;
 613
 614         return 0;
 615 }
 616
 617 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 618 {
 619         struct vcpu_svm *svm;
 620         struct page *page;
 621         struct page *msrpm_pages;
 622         int err;
 623
 624         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 625         if (!svm) {
 626                 err = -ENOMEM;
 627                 goto out;
 628         }
 629
 630         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 631         if (err)
 632                 goto free_svm;
 633
 634         page = alloc_page(GFP_KERNEL);
 635         if (!page) {
 636                 err = -ENOMEM;
 637                 goto uninit;
 638         }
 639
 640         err = -ENOMEM;
 641         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 642         if (!msrpm_pages)
 643                 goto uninit;
 644         svm->msrpm = page_address(msrpm_pages);
 645         svm_vcpu_init_msrpm(svm->msrpm);
 646
 647         svm->vmcb = page_address(page);
 648         clear_page(svm->vmcb);
 649         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 650         svm->asid_generation = 0;
 651         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 652         init_vmcb(svm);
 653
 654         fx_init(&svm->vcpu);
 655         svm->vcpu.fpu_active = 1;
 656         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 657         if (svm->vcpu.vcpu_id == 0)
 658                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 659
 660         return &svm->vcpu;
 661
 662 uninit:
 663         kvm_vcpu_uninit(&svm->vcpu);
 664 free_svm:
 665         kmem_cache_free(kvm_vcpu_cache, svm);
 666 out:
 667         return ERR_PTR(err);
 668 }
 669
 670 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 671 {
 672         struct vcpu_svm *svm = to_svm(vcpu);
 673
 674         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 675         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 676         kvm_vcpu_uninit(vcpu);
 677         kmem_cache_free(kvm_vcpu_cache, svm);
 678 }
 679
 680 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 681 {
 682         struct vcpu_svm *svm = to_svm(vcpu);
 683         int i;
 684
 685         if (unlikely(cpu != vcpu->cpu)) {
 686                 u64 tsc_this, delta;
 687
 688                 /*
 689                  * Make sure that the guest sees a monotonically
 690                  * increasing TSC.
 691                  */
 692                 rdtscll(tsc_this);
 693                 delta = vcpu->arch.host_tsc - tsc_this;
 694                 svm->vmcb->control.tsc_offset += delta;
 695                 vcpu->cpu = cpu;
 696                 kvm_migrate_timers(vcpu);
 697         }
 698
 699         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 700                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 701 }
 702
 703 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 704 {
 705         struct vcpu_svm *svm = to_svm(vcpu);
 706         int i;
 707
 708         ++vcpu->stat.host_state_reload;
 709         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 710                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 711
 712         rdtscll(vcpu->arch.host_tsc);
 713 }
 714
 715 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 716 {
 717         return to_svm(vcpu)->vmcb->save.rflags;
 718 }
 719
 720 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 721 {
 722         to_svm(vcpu)->vmcb->save.rflags = rflags;
 723 }
 724
 725 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 726 {
 727         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 728
 729         switch (seg) {
 730         case VCPU_SREG_CS: return &save->cs;
 731         case VCPU_SREG_DS: return &save->ds;
 732         case VCPU_SREG_ES: return &save->es;
 733         case VCPU_SREG_FS: return &save->fs;
 734         case VCPU_SREG_GS: return &save->gs;
 735         case VCPU_SREG_SS: return &save->ss;
 736         case VCPU_SREG_TR: return &save->tr;
 737         case VCPU_SREG_LDTR: return &save->ldtr;
 738         }
 739         BUG();
 740         return NULL;
 741 }
 742
 743 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 744 {
 745         struct vmcb_seg *s = svm_seg(vcpu, seg);
 746
 747         return s->base;
 748 }
 749
 750 static void svm_get_segment(struct kvm_vcpu *vcpu,
 751                             struct kvm_segment *var, int seg)
 752 {
 753         struct vmcb_seg *s = svm_seg(vcpu, seg);
 754
 755         var->base = s->base;
 756         var->limit = s->limit;
 757         var->selector = s->selector;
 758         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 759         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 760         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 761         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 762         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 763         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 764         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 765         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 766
 767         /*
 768          * SVM always stores 0 for the 'G' bit in the CS selector in
 769          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 770          * Intel's VMENTRY has a check on the 'G' bit.
 771          */
 772         if (seg == VCPU_SREG_CS)
 773                 var->g = s->limit > 0xfffff;
 774
 775         /*
 776          * Work around a bug where the busy flag in the tr selector
 777          * isn't exposed
 778          */
 779         if (seg == VCPU_SREG_TR)
 780                 var->type |= 0x2;
 781
 782         var->unusable = !var->present;
 783 }
 784
 785 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 786 {
 787         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 788
 789         return save->cpl;
 790 }
 791
 792 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 793 {
 794         struct vcpu_svm *svm = to_svm(vcpu);
 795
 796         dt->limit = svm->vmcb->save.idtr.limit;
 797         dt->base = svm->vmcb->save.idtr.base;
 798 }
 799
 800 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 801 {
 802         struct vcpu_svm *svm = to_svm(vcpu);
 803
 804         svm->vmcb->save.idtr.limit = dt->limit;
 805         svm->vmcb->save.idtr.base = dt->base ;
 806 }
 807
 808 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 809 {
 810         struct vcpu_svm *svm = to_svm(vcpu);
 811
 812         dt->limit = svm->vmcb->save.gdtr.limit;
 813         dt->base = svm->vmcb->save.gdtr.base;
 814 }
 815
 816 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 817 {
 818         struct vcpu_svm *svm = to_svm(vcpu);
 819
 820         svm->vmcb->save.gdtr.limit = dt->limit;
 821         svm->vmcb->save.gdtr.base = dt->base ;
 822 }
 823
 824 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 825 {
 826 }
 827
 828 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 829 {
 830         struct vcpu_svm *svm = to_svm(vcpu);
 831
 832 #ifdef CONFIG_X86_64
 833         if (vcpu->arch.shadow_efer & EFER_LME) {
 834                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 835                         vcpu->arch.shadow_efer |= EFER_LMA;
 836                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 837                 }
 838
 839                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 840                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 841                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 842                 }
 843         }
 844 #endif
 845         if (npt_enabled)
 846                 goto set;
 847
 848         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 849                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 850                 vcpu->fpu_active = 1;
 851         }
 852
 853         vcpu->arch.cr0 = cr0;
 854         cr0 |= X86_CR0_PG | X86_CR0_WP;
 855         if (!vcpu->fpu_active) {
 856                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 857                 cr0 |= X86_CR0_TS;
 858         }
 859 set:
 860         /*
 861          * re-enable caching here because the QEMU bios
 862          * does not do it - this results in some delay at
 863          * reboot
 864          */
 865         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 866         svm->vmcb->save.cr0 = cr0;
 867 }
 868
 869 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 870 {
 871         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 872         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 873
 874         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 875                 force_new_asid(vcpu);
 876
 877         vcpu->arch.cr4 = cr4;
 878         if (!npt_enabled)
 879                 cr4 |= X86_CR4_PAE;
 880         cr4 |= host_cr4_mce;
 881         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 882 }
 883
 884 static void svm_set_segment(struct kvm_vcpu *vcpu,
 885                             struct kvm_segment *var, int seg)
 886 {
 887         struct vcpu_svm *svm = to_svm(vcpu);
 888         struct vmcb_seg *s = svm_seg(vcpu, seg);
 889
 890         s->base = var->base;
 891         s->limit = var->limit;
 892         s->selector = var->selector;
 893         if (var->unusable)
 894                 s->attrib = 0;
 895         else {
 896                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 897                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 898                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 899                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 900                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 901                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 902                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 903                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 904         }
 905         if (seg == VCPU_SREG_CS)
 906                 svm->vmcb->save.cpl
 907                         = (svm->vmcb->save.cs.attrib
 908                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 909
 910 }
 911
 912 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 913 {
 914         return -EOPNOTSUPP;
 915 }
 916
 917 static int svm_get_irq(struct kvm_vcpu *vcpu)
 918 {
 919         struct vcpu_svm *svm = to_svm(vcpu);
 920         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 921
 922         if (is_external_interrupt(exit_int_info))
 923                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 924         return -1;
 925 }
 926
 927 static void load_host_msrs(struct kvm_vcpu *vcpu)
 928 {
 929 #ifdef CONFIG_X86_64
 930         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 931 #endif
 932 }
 933
 934 static void save_host_msrs(struct kvm_vcpu *vcpu)
 935 {
 936 #ifdef CONFIG_X86_64
 937         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 938 #endif
 939 }
 940
 941 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 942 {
 943         if (svm_data->next_asid > svm_data->max_asid) {
 944                 ++svm_data->asid_generation;
 945                 svm_data->next_asid = 1;
 946                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 947         }
 948
 949         svm->vcpu.cpu = svm_data->cpu;
 950         svm->asid_generation = svm_data->asid_generation;
 951         svm->vmcb->control.asid = svm_data->next_asid++;
 952 }
 953
 954 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 955 {
 956         unsigned long val = to_svm(vcpu)->db_regs[dr];
 957         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 958         return val;
 959 }
 960
 961 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 962                        int *exception)
 963 {
 964         struct vcpu_svm *svm = to_svm(vcpu);
 965
 966         *exception = 0;
 967
 968         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 969                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 970                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 971                 *exception = DB_VECTOR;
 972                 return;
 973         }
 974
 975         switch (dr) {
 976         case 0 ... 3:
 977                 svm->db_regs[dr] = value;
 978                 return;
 979         case 4 ... 5:
 980                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 981                         *exception = UD_VECTOR;
 982                         return;
 983                 }
 984         case 7: {
 985                 if (value & ~((1ULL << 32) - 1)) {
 986                         *exception = GP_VECTOR;
 987                         return;
 988                 }
 989                 svm->vmcb->save.dr7 = value;
 990                 return;
 991         }
 992         default:
 993                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 994                        __func__, dr);
 995                 *exception = UD_VECTOR;
 996                 return;
 997         }
 998 }
 999
1000 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1001 {
1002         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1003         struct kvm *kvm = svm->vcpu.kvm;
1004         u64 fault_address;
1005         u32 error_code;
1006         bool event_injection = false;
1007
1008         if (!irqchip_in_kernel(kvm) &&
1009             is_external_interrupt(exit_int_info)) {
1010                 event_injection = true;
1011                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1012         }
1013
1014         fault_address  = svm->vmcb->control.exit_info_2;
1015         error_code = svm->vmcb->control.exit_info_1;
1016
1017         if (!npt_enabled)
1018                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1019                             (u32)fault_address, (u32)(fault_address >> 32),
1020                             handler);
1021         else
1022                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1023                             (u32)fault_address, (u32)(fault_address >> 32),
1024                             handler);
1025         /*
1026          * FIXME: Tis shouldn't be necessary here, but there is a flush
1027          * missing in the MMU code. Until we find this bug, flush the
1028          * complete TLB here on an NPF
1029          */
1030         if (npt_enabled)
1031                 svm_flush_tlb(&svm->vcpu);
1032
1033         if (!npt_enabled && event_injection)
1034                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1035         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1036 }
1037
1038 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1039 {
1040         int er;
1041
1042         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1043         if (er != EMULATE_DONE)
1044                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1045         return 1;
1046 }
1047
1048 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1049 {
1050         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1051         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1052                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1053         svm->vcpu.fpu_active = 1;
1054
1055         return 1;
1056 }
1057
1058 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1059 {
1060         /*
1061          * On an #MC intercept the MCE handler is not called automatically in
1062          * the host. So do it by hand here.
1063          */
1064         asm volatile (
1065                 "int $0x12\n");
1066         /* not sure if we ever come back to this point */
1067
1068         return 1;
1069 }
1070
1071 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1072 {
1073         /*
1074          * VMCB is undefined after a SHUTDOWN intercept
1075          * so reinitialize it.
1076          */
1077         clear_page(svm->vmcb);
1078         init_vmcb(svm);
1079
1080         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1081         return 0;
1082 }
1083
1084 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1085 {
1086         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1087         int size, down, in, string, rep;
1088         unsigned port;
1089
1090         ++svm->vcpu.stat.io_exits;
1091
1092         svm->next_rip = svm->vmcb->control.exit_info_2;
1093
1094         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1095
1096         if (string) {
1097                 if (emulate_instruction(&svm->vcpu,
1098                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1099                         return 0;
1100                 return 1;
1101         }
1102
1103         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1104         port = io_info >> 16;
1105         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1106         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1107         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1108
1109         skip_emulated_instruction(&svm->vcpu);
1110         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1111 }
1112
1113 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1114 {
1115         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1116         return 1;
1117 }
1118
1119 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1120 {
1121         ++svm->vcpu.stat.irq_exits;
1122         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1123         return 1;
1124 }
1125
1126 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1127 {
1128         return 1;
1129 }
1130
1131 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1132 {
1133         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1134         skip_emulated_instruction(&svm->vcpu);
1135         return kvm_emulate_halt(&svm->vcpu);
1136 }
1137
1138 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1139 {
1140         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1141         skip_emulated_instruction(&svm->vcpu);
1142         kvm_emulate_hypercall(&svm->vcpu);
1143         return 1;
1144 }
1145
1146 static int invalid_op_interception(struct vcpu_svm *svm,
1147                                    struct kvm_run *kvm_run)
1148 {
1149         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1150         return 1;
1151 }
1152
1153 static int task_switch_interception(struct vcpu_svm *svm,
1154                                     struct kvm_run *kvm_run)
1155 {
1156         u16 tss_selector;
1157
1158         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1159         if (svm->vmcb->control.exit_info_2 &
1160             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1161                 return kvm_task_switch(&svm->vcpu, tss_selector,
1162                                        TASK_SWITCH_IRET);
1163         if (svm->vmcb->control.exit_info_2 &
1164             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1165                 return kvm_task_switch(&svm->vcpu, tss_selector,
1166                                        TASK_SWITCH_JMP);
1167         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1168 }
1169
1170 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171 {
1172         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1173         kvm_emulate_cpuid(&svm->vcpu);
1174         return 1;
1175 }
1176
1177 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1178 {
1179         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1180                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1181         return 1;
1182 }
1183
1184 static int emulate_on_interception(struct vcpu_svm *svm,
1185                                    struct kvm_run *kvm_run)
1186 {
1187         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1188                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1189         return 1;
1190 }
1191
1192 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1193 {
1194         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1195         if (irqchip_in_kernel(svm->vcpu.kvm))
1196                 return 1;
1197         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1198         return 0;
1199 }
1200
1201 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1202 {
1203         struct vcpu_svm *svm = to_svm(vcpu);
1204
1205         switch (ecx) {
1206         case MSR_IA32_TIME_STAMP_COUNTER: {
1207                 u64 tsc;
1208
1209                 rdtscll(tsc);
1210                 *data = svm->vmcb->control.tsc_offset + tsc;
1211                 break;
1212         }
1213         case MSR_K6_STAR:
1214                 *data = svm->vmcb->save.star;
1215                 break;
1216 #ifdef CONFIG_X86_64
1217         case MSR_LSTAR:
1218                 *data = svm->vmcb->save.lstar;
1219                 break;
1220         case MSR_CSTAR:
1221                 *data = svm->vmcb->save.cstar;
1222                 break;
1223         case MSR_KERNEL_GS_BASE:
1224                 *data = svm->vmcb->save.kernel_gs_base;
1225                 break;
1226         case MSR_SYSCALL_MASK:
1227                 *data = svm->vmcb->save.sfmask;
1228                 break;
1229 #endif
1230         case MSR_IA32_SYSENTER_CS:
1231                 *data = svm->vmcb->save.sysenter_cs;
1232                 break;
1233         case MSR_IA32_SYSENTER_EIP:
1234                 *data = svm->vmcb->save.sysenter_eip;
1235                 break;
1236         case MSR_IA32_SYSENTER_ESP:
1237                 *data = svm->vmcb->save.sysenter_esp;
1238                 break;
1239         /* Nobody will change the following 5 values in the VMCB so
1240            we can safely return them on rdmsr. They will always be 0
1241            until LBRV is implemented. */
1242         case MSR_IA32_DEBUGCTLMSR:
1243                 *data = svm->vmcb->save.dbgctl;
1244                 break;
1245         case MSR_IA32_LASTBRANCHFROMIP:
1246                 *data = svm->vmcb->save.br_from;
1247                 break;
1248         case MSR_IA32_LASTBRANCHTOIP:
1249                 *data = svm->vmcb->save.br_to;
1250                 break;
1251         case MSR_IA32_LASTINTFROMIP:
1252                 *data = svm->vmcb->save.last_excp_from;
1253                 break;
1254         case MSR_IA32_LASTINTTOIP:
1255                 *data = svm->vmcb->save.last_excp_to;
1256                 break;
1257         default:
1258                 return kvm_get_msr_common(vcpu, ecx, data);
1259         }
1260         return 0;
1261 }
1262
1263 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1264 {
1265         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1266         u64 data;
1267
1268         if (svm_get_msr(&svm->vcpu, ecx, &data))
1269                 kvm_inject_gp(&svm->vcpu, 0);
1270         else {
1271                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1272                             (u32)(data >> 32), handler);
1273
1274                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1275                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1276                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1277                 skip_emulated_instruction(&svm->vcpu);
1278         }
1279         return 1;
1280 }
1281
1282 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1283 {
1284         struct vcpu_svm *svm = to_svm(vcpu);
1285
1286         switch (ecx) {
1287         case MSR_IA32_TIME_STAMP_COUNTER: {
1288                 u64 tsc;
1289
1290                 rdtscll(tsc);
1291                 svm->vmcb->control.tsc_offset = data - tsc;
1292                 break;
1293         }
1294         case MSR_K6_STAR:
1295                 svm->vmcb->save.star = data;
1296                 break;
1297 #ifdef CONFIG_X86_64
1298         case MSR_LSTAR:
1299                 svm->vmcb->save.lstar = data;
1300                 break;
1301         case MSR_CSTAR:
1302                 svm->vmcb->save.cstar = data;
1303                 break;
1304         case MSR_KERNEL_GS_BASE:
1305                 svm->vmcb->save.kernel_gs_base = data;
1306                 break;
1307         case MSR_SYSCALL_MASK:
1308                 svm->vmcb->save.sfmask = data;
1309                 break;
1310 #endif
1311         case MSR_IA32_SYSENTER_CS:
1312                 svm->vmcb->save.sysenter_cs = data;
1313                 break;
1314         case MSR_IA32_SYSENTER_EIP:
1315                 svm->vmcb->save.sysenter_eip = data;
1316                 break;
1317         case MSR_IA32_SYSENTER_ESP:
1318                 svm->vmcb->save.sysenter_esp = data;
1319                 break;
1320         case MSR_IA32_DEBUGCTLMSR:
1321                 if (!svm_has(SVM_FEATURE_LBRV)) {
1322                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1323                                         __func__, data);
1324                         break;
1325                 }
1326                 if (data & DEBUGCTL_RESERVED_BITS)
1327                         return 1;
1328
1329                 svm->vmcb->save.dbgctl = data;
1330                 if (data & (1ULL<<0))
1331                         svm_enable_lbrv(svm);
1332                 else
1333                         svm_disable_lbrv(svm);
1334                 break;
1335         case MSR_K7_EVNTSEL0:
1336         case MSR_K7_EVNTSEL1:
1337         case MSR_K7_EVNTSEL2:
1338         case MSR_K7_EVNTSEL3:
1339         case MSR_K7_PERFCTR0:
1340         case MSR_K7_PERFCTR1:
1341         case MSR_K7_PERFCTR2:
1342         case MSR_K7_PERFCTR3:
1343                 /*
1344                  * Just discard all writes to the performance counters; this
1345                  * should keep both older linux and windows 64-bit guests
1346                  * happy
1347                  */
1348                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1349
1350                 break;
1351         default:
1352                 return kvm_set_msr_common(vcpu, ecx, data);
1353         }
1354         return 0;
1355 }
1356
1357 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1358 {
1359         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1360         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1361                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1362
1363         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1364                     handler);
1365
1366         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1367         if (svm_set_msr(&svm->vcpu, ecx, data))
1368                 kvm_inject_gp(&svm->vcpu, 0);
1369         else
1370                 skip_emulated_instruction(&svm->vcpu);
1371         return 1;
1372 }
1373
1374 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1375 {
1376         if (svm->vmcb->control.exit_info_1)
1377                 return wrmsr_interception(svm, kvm_run);
1378         else
1379                 return rdmsr_interception(svm, kvm_run);
1380 }
1381
1382 static int interrupt_window_interception(struct vcpu_svm *svm,
1383                                    struct kvm_run *kvm_run)
1384 {
1385         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1386
1387         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1388         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1389         /*
1390          * If the user space waits to inject interrupts, exit as soon as
1391          * possible
1392          */
1393         if (kvm_run->request_interrupt_window &&
1394             !svm->vcpu.arch.irq_summary) {
1395                 ++svm->vcpu.stat.irq_window_exits;
1396                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1397                 return 0;
1398         }
1399
1400         return 1;
1401 }
1402
1403 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1404                                       struct kvm_run *kvm_run) = {
1405         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1406         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1407         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1408         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1409         /* for now: */
1410         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1411         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1412         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1413         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1414         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1415         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1416         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1417         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1418         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1419         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1420         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1421         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1422         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1423         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1424         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1425         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1426         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1427         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1428         [SVM_EXIT_INTR]                         = intr_interception,
1429         [SVM_EXIT_NMI]                          = nmi_interception,
1430         [SVM_EXIT_SMI]                          = nop_on_interception,
1431         [SVM_EXIT_INIT]                         = nop_on_interception,
1432         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1433         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1434         [SVM_EXIT_CPUID]                        = cpuid_interception,
1435         [SVM_EXIT_INVD]                         = emulate_on_interception,
1436         [SVM_EXIT_HLT]                          = halt_interception,
1437         [SVM_EXIT_INVLPG]                       = invlpg_interception,
1438         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1439         [SVM_EXIT_IOIO]                         = io_interception,
1440         [SVM_EXIT_MSR]                          = msr_interception,
1441         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1442         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1443         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1444         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1445         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1446         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1447         [SVM_EXIT_STGI]                         = invalid_op_interception,
1448         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1449         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1450         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1451         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1452         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1453         [SVM_EXIT_NPF]                          = pf_interception,
1454 };
1455
1456 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1457 {
1458         struct vcpu_svm *svm = to_svm(vcpu);
1459         u32 exit_code = svm->vmcb->control.exit_code;
1460
1461         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1462                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1463
1464         if (npt_enabled) {
1465                 int mmu_reload = 0;
1466                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1467                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1468                         mmu_reload = 1;
1469                 }
1470                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1471                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1472                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1473                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1474                                 kvm_inject_gp(vcpu, 0);
1475                                 return 1;
1476                         }
1477                 }
1478                 if (mmu_reload) {
1479                         kvm_mmu_reset_context(vcpu);
1480                         kvm_mmu_load(vcpu);
1481                 }
1482         }
1483
1484         kvm_reput_irq(svm);
1485
1486         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1487                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1488                 kvm_run->fail_entry.hardware_entry_failure_reason
1489                         = svm->vmcb->control.exit_code;
1490                 return 0;
1491         }
1492
1493         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1494             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1495             exit_code != SVM_EXIT_NPF)
1496                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1497                        "exit_code 0x%x\n",
1498                        __func__, svm->vmcb->control.exit_int_info,
1499                        exit_code);
1500
1501         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1502             || !svm_exit_handlers[exit_code]) {
1503                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1504                 kvm_run->hw.hardware_exit_reason = exit_code;
1505                 return 0;
1506         }
1507
1508         return svm_exit_handlers[exit_code](svm, kvm_run);
1509 }
1510
1511 static void reload_tss(struct kvm_vcpu *vcpu)
1512 {
1513         int cpu = raw_smp_processor_id();
1514
1515         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1516         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1517         load_TR_desc();
1518 }
1519
1520 static void pre_svm_run(struct vcpu_svm *svm)
1521 {
1522         int cpu = raw_smp_processor_id();
1523
1524         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1525
1526         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1527         if (svm->vcpu.cpu != cpu ||
1528             svm->asid_generation != svm_data->asid_generation)
1529                 new_asid(svm, svm_data);
1530 }
1531
1532
1533 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1534 {
1535         struct vmcb_control_area *control;
1536
1537         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1538
1539         ++svm->vcpu.stat.irq_injections;
1540         control = &svm->vmcb->control;
1541         control->int_vector = irq;
1542         control->int_ctl &= ~V_INTR_PRIO_MASK;
1543         control->int_ctl |= V_IRQ_MASK |
1544                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1545 }
1546
1547 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1548 {
1549         struct vcpu_svm *svm = to_svm(vcpu);
1550
1551         svm_inject_irq(svm, irq);
1552 }
1553
1554 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1555 {
1556         struct vcpu_svm *svm = to_svm(vcpu);
1557         struct vmcb *vmcb = svm->vmcb;
1558         int max_irr, tpr;
1559
1560         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1561                 return;
1562
1563         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1564
1565         max_irr = kvm_lapic_find_highest_irr(vcpu);
1566         if (max_irr == -1)
1567                 return;
1568
1569         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1570
1571         if (tpr >= (max_irr & 0xf0))
1572                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1573 }
1574
1575 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1576 {
1577         struct vcpu_svm *svm = to_svm(vcpu);
1578         struct vmcb *vmcb = svm->vmcb;
1579         int intr_vector = -1;
1580
1581         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1582             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1583                 intr_vector = vmcb->control.exit_int_info &
1584                               SVM_EVTINJ_VEC_MASK;
1585                 vmcb->control.exit_int_info = 0;
1586                 svm_inject_irq(svm, intr_vector);
1587                 goto out;
1588         }
1589
1590         if (vmcb->control.int_ctl & V_IRQ_MASK)
1591                 goto out;
1592
1593         if (!kvm_cpu_has_interrupt(vcpu))
1594                 goto out;
1595
1596         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1597             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1598             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1599                 /* unable to deliver irq, set pending irq */
1600                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1601                 svm_inject_irq(svm, 0x0);
1602                 goto out;
1603         }
1604         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1605         intr_vector = kvm_cpu_get_interrupt(vcpu);
1606         svm_inject_irq(svm, intr_vector);
1607         kvm_timer_intr_post(vcpu, intr_vector);
1608 out:
1609         update_cr8_intercept(vcpu);
1610 }
1611
1612 static void kvm_reput_irq(struct vcpu_svm *svm)
1613 {
1614         struct vmcb_control_area *control = &svm->vmcb->control;
1615
1616         if ((control->int_ctl & V_IRQ_MASK)
1617             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1618                 control->int_ctl &= ~V_IRQ_MASK;
1619                 push_irq(&svm->vcpu, control->int_vector);
1620         }
1621
1622         svm->vcpu.arch.interrupt_window_open =
1623                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1624 }
1625
1626 static void svm_do_inject_vector(struct vcpu_svm *svm)
1627 {
1628         struct kvm_vcpu *vcpu = &svm->vcpu;
1629         int word_index = __ffs(vcpu->arch.irq_summary);
1630         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1631         int irq = word_index * BITS_PER_LONG + bit_index;
1632
1633         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1634         if (!vcpu->arch.irq_pending[word_index])
1635                 clear_bit(word_index, &vcpu->arch.irq_summary);
1636         svm_inject_irq(svm, irq);
1637 }
1638
1639 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1640                                        struct kvm_run *kvm_run)
1641 {
1642         struct vcpu_svm *svm = to_svm(vcpu);
1643         struct vmcb_control_area *control = &svm->vmcb->control;
1644
1645         svm->vcpu.arch.interrupt_window_open =
1646                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1647                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1648
1649         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1650                 /*
1651                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1652                  */
1653                 svm_do_inject_vector(svm);
1654
1655         /*
1656          * Interrupts blocked.  Wait for unblock.
1657          */
1658         if (!svm->vcpu.arch.interrupt_window_open &&
1659             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1660                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1661          else
1662                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1663 }
1664
1665 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1666 {
1667         return 0;
1668 }
1669
1670 static void save_db_regs(unsigned long *db_regs)
1671 {
1672         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1673         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1674         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1675         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1676 }
1677
1678 static void load_db_regs(unsigned long *db_regs)
1679 {
1680         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1681         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1682         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1683         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1684 }
1685
1686 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1687 {
1688         force_new_asid(vcpu);
1689 }
1690
1691 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1692 {
1693 }
1694
1695 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1696 {
1697         struct vcpu_svm *svm = to_svm(vcpu);
1698
1699         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1700                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1701                 kvm_lapic_set_tpr(vcpu, cr8);
1702         }
1703 }
1704
1705 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1706 {
1707         struct vcpu_svm *svm = to_svm(vcpu);
1708         u64 cr8;
1709
1710         if (!irqchip_in_kernel(vcpu->kvm))
1711                 return;
1712
1713         cr8 = kvm_get_cr8(vcpu);
1714         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1715         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1716 }
1717
1718 #ifdef CONFIG_X86_64
1719 #define R "r"
1720 #else
1721 #define R "e"
1722 #endif
1723
1724 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1725 {
1726         struct vcpu_svm *svm = to_svm(vcpu);
1727         u16 fs_selector;
1728         u16 gs_selector;
1729         u16 ldt_selector;
1730
1731         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1732         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1733         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1734
1735         pre_svm_run(svm);
1736
1737         sync_lapic_to_cr8(vcpu);
1738
1739         save_host_msrs(vcpu);
1740         fs_selector = kvm_read_fs();
1741         gs_selector = kvm_read_gs();
1742         ldt_selector = kvm_read_ldt();
1743         svm->host_cr2 = kvm_read_cr2();
1744         svm->host_dr6 = read_dr6();
1745         svm->host_dr7 = read_dr7();
1746         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1747         /* required for live migration with NPT */
1748         if (npt_enabled)
1749                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1750
1751         if (svm->vmcb->save.dr7 & 0xff) {
1752                 write_dr7(0);
1753                 save_db_regs(svm->host_db_regs);
1754                 load_db_regs(svm->db_regs);
1755         }
1756
1757         clgi();
1758
1759         local_irq_enable();
1760
1761         asm volatile (
1762                 "push %%"R"bp; \n\t"
1763                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1764                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1765                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1766                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1767                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1768                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1769 #ifdef CONFIG_X86_64
1770                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1771                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1772                 "mov %c[r10](%[svm]), %%r10 \n\t"
1773                 "mov %c[r11](%[svm]), %%r11 \n\t"
1774                 "mov %c[r12](%[svm]), %%r12 \n\t"
1775                 "mov %c[r13](%[svm]), %%r13 \n\t"
1776                 "mov %c[r14](%[svm]), %%r14 \n\t"
1777                 "mov %c[r15](%[svm]), %%r15 \n\t"
1778 #endif
1779
1780                 /* Enter guest mode */
1781                 "push %%"R"ax \n\t"
1782                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1783                 __ex(SVM_VMLOAD) "\n\t"
1784                 __ex(SVM_VMRUN) "\n\t"
1785                 __ex(SVM_VMSAVE) "\n\t"
1786                 "pop %%"R"ax \n\t"
1787
1788                 /* Save guest registers, load host registers */
1789                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1790                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1791                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1792                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1793                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1794                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1795 #ifdef CONFIG_X86_64
1796                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1797                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1798                 "mov %%r10, %c[r10](%[svm]) \n\t"
1799                 "mov %%r11, %c[r11](%[svm]) \n\t"
1800                 "mov %%r12, %c[r12](%[svm]) \n\t"
1801                 "mov %%r13, %c[r13](%[svm]) \n\t"
1802                 "mov %%r14, %c[r14](%[svm]) \n\t"
1803                 "mov %%r15, %c[r15](%[svm]) \n\t"
1804 #endif
1805                 "pop %%"R"bp"
1806                 :
1807                 : [svm]"a"(svm),
1808                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1809                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1810                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1811                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1812                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1813                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1814                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1815 #ifdef CONFIG_X86_64
1816                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1817                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1818                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1819                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1820                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1821                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1822                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1823                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1824 #endif
1825                 : "cc", "memory"
1826                 , R"bx", R"cx", R"dx", R"si", R"di"
1827 #ifdef CONFIG_X86_64
1828                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1829 #endif
1830                 );
1831
1832         if ((svm->vmcb->save.dr7 & 0xff))
1833                 load_db_regs(svm->host_db_regs);
1834
1835         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1836         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1837         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1838         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1839
1840         write_dr6(svm->host_dr6);
1841         write_dr7(svm->host_dr7);
1842         kvm_write_cr2(svm->host_cr2);
1843
1844         kvm_load_fs(fs_selector);
1845         kvm_load_gs(gs_selector);
1846         kvm_load_ldt(ldt_selector);
1847         load_host_msrs(vcpu);
1848
1849         reload_tss(vcpu);
1850
1851         local_irq_disable();
1852
1853         stgi();
1854
1855         sync_cr8_to_lapic(vcpu);
1856
1857         svm->next_rip = 0;
1858 }
1859
1860 #undef R
1861
1862 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1863 {
1864         struct vcpu_svm *svm = to_svm(vcpu);
1865
1866         if (npt_enabled) {
1867                 svm->vmcb->control.nested_cr3 = root;
1868                 force_new_asid(vcpu);
1869                 return;
1870         }
1871
1872         svm->vmcb->save.cr3 = root;
1873         force_new_asid(vcpu);
1874
1875         if (vcpu->fpu_active) {
1876                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1877                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1878                 vcpu->fpu_active = 0;
1879         }
1880 }
1881
1882 static int is_disabled(void)
1883 {
1884         u64 vm_cr;
1885
1886         rdmsrl(MSR_VM_CR, vm_cr);
1887         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1888                 return 1;
1889
1890         return 0;
1891 }
1892
1893 static void
1894 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1895 {
1896         /*
1897          * Patch in the VMMCALL instruction:
1898          */
1899         hypercall[0] = 0x0f;
1900         hypercall[1] = 0x01;
1901         hypercall[2] = 0xd9;
1902 }
1903
1904 static void svm_check_processor_compat(void *rtn)
1905 {
1906         *(int *)rtn = 0;
1907 }
1908
1909 static bool svm_cpu_has_accelerated_tpr(void)
1910 {
1911         return false;
1912 }
1913
1914 static int get_npt_level(void)
1915 {
1916 #ifdef CONFIG_X86_64
1917         return PT64_ROOT_LEVEL;
1918 #else
1919         return PT32E_ROOT_LEVEL;
1920 #endif
1921 }
1922
1923 static int svm_get_mt_mask_shift(void)
1924 {
1925         return 0;
1926 }
1927
1928 static struct kvm_x86_ops svm_x86_ops = {
1929         .cpu_has_kvm_support = has_svm,
1930         .disabled_by_bios = is_disabled,
1931         .hardware_setup = svm_hardware_setup,
1932         .hardware_unsetup = svm_hardware_unsetup,
1933         .check_processor_compatibility = svm_check_processor_compat,
1934         .hardware_enable = svm_hardware_enable,
1935         .hardware_disable = svm_hardware_disable,
1936         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1937
1938         .vcpu_create = svm_create_vcpu,
1939         .vcpu_free = svm_free_vcpu,
1940         .vcpu_reset = svm_vcpu_reset,
1941
1942         .prepare_guest_switch = svm_prepare_guest_switch,
1943         .vcpu_load = svm_vcpu_load,
1944         .vcpu_put = svm_vcpu_put,
1945
1946         .set_guest_debug = svm_guest_debug,
1947         .get_msr = svm_get_msr,
1948         .set_msr = svm_set_msr,
1949         .get_segment_base = svm_get_segment_base,
1950         .get_segment = svm_get_segment,
1951         .set_segment = svm_set_segment,
1952         .get_cpl = svm_get_cpl,
1953         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1954         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1955         .set_cr0 = svm_set_cr0,
1956         .set_cr3 = svm_set_cr3,
1957         .set_cr4 = svm_set_cr4,
1958         .set_efer = svm_set_efer,
1959         .get_idt = svm_get_idt,
1960         .set_idt = svm_set_idt,
1961         .get_gdt = svm_get_gdt,
1962         .set_gdt = svm_set_gdt,
1963         .get_dr = svm_get_dr,
1964         .set_dr = svm_set_dr,
1965         .get_rflags = svm_get_rflags,
1966         .set_rflags = svm_set_rflags,
1967
1968         .tlb_flush = svm_flush_tlb,
1969
1970         .run = svm_vcpu_run,
1971         .handle_exit = handle_exit,
1972         .skip_emulated_instruction = skip_emulated_instruction,
1973         .patch_hypercall = svm_patch_hypercall,
1974         .get_irq = svm_get_irq,
1975         .set_irq = svm_set_irq,
1976         .queue_exception = svm_queue_exception,
1977         .exception_injected = svm_exception_injected,
1978         .inject_pending_irq = svm_intr_assist,
1979         .inject_pending_vectors = do_interrupt_requests,
1980
1981         .set_tss_addr = svm_set_tss_addr,
1982         .get_tdp_level = get_npt_level,
1983         .get_mt_mask_shift = svm_get_mt_mask_shift,
1984 };
1985
1986 static int __init svm_init(void)
1987 {
1988         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1989                               THIS_MODULE);
1990 }
1991
1992 static void __exit svm_exit(void)
1993 {
1994         kvm_exit();
1995 }
1996
1997 module_init(svm_init)
1998 module_exit(svm_exit)