2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
54 #error Invalid PTTYPE value
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
70 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
71 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
72 bool pte_writable[PT_MAX_FULL_LEVELS];
76 struct x86_exception fault;
79 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
81 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
84 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
85 pt_element_t __user *ptep_user, unsigned index,
86 pt_element_t orig_pte, pt_element_t new_pte)
93 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
94 /* Check if the user is doing something meaningless. */
95 if (unlikely(npages != 1))
98 table = kmap_atomic(page);
99 ret = CMPXCHG(&table[index], orig_pte, new_pte);
100 kunmap_atomic(table);
102 kvm_release_page_dirty(page);
104 return (ret != orig_pte);
107 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
109 struct guest_walker *walker,
112 unsigned level, index;
113 pt_element_t pte, orig_pte;
114 pt_element_t __user *ptep_user;
118 for (level = walker->max_level; level >= walker->level; --level) {
119 pte = orig_pte = walker->ptes[level - 1];
120 table_gfn = walker->table_gfn[level - 1];
121 ptep_user = walker->ptep_user[level - 1];
122 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
123 if (!(pte & PT_ACCESSED_MASK)) {
124 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
125 pte |= PT_ACCESSED_MASK;
127 if (level == walker->level && write_fault && !is_dirty_gpte(pte)) {
128 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
129 pte |= PT_DIRTY_MASK;
135 * If the slot is read-only, simply do not process the accessed
136 * and dirty bits. This is the correct thing to do if the slot
137 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
138 * are only supported if the accessed and dirty bits are already
139 * set in the ROM (so that MMIO writes are never needed).
141 * Note that NPT does not allow this at all and faults, since
142 * it always wants nested page table entries for the guest
143 * page tables to be writable. And EPT works but will simply
144 * overwrite the read-only memory to set the accessed and dirty
147 if (unlikely(!walker->pte_writable[level - 1]))
150 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
154 mark_page_dirty(vcpu->kvm, table_gfn);
155 walker->ptes[level] = pte;
161 * Fetch a guest pte for a guest virtual address
163 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
164 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
165 gva_t addr, u32 access)
169 pt_element_t __user *uninitialized_var(ptep_user);
171 unsigned index, pt_access, pte_access, accessed_dirty;
174 const int write_fault = access & PFERR_WRITE_MASK;
175 const int user_fault = access & PFERR_USER_MASK;
176 const int fetch_fault = access & PFERR_FETCH_MASK;
181 trace_kvm_mmu_pagetable_walk(addr, access);
183 walker->level = mmu->root_level;
184 pte = mmu->get_cr3(vcpu);
187 if (walker->level == PT32E_ROOT_LEVEL) {
188 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
189 trace_kvm_mmu_paging_element(pte, walker->level);
190 if (!is_present_gpte(pte))
195 walker->max_level = walker->level;
196 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
197 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
199 accessed_dirty = PT_ACCESSED_MASK;
200 pt_access = pte_access = ACC_ALL;
205 unsigned long host_addr;
207 pt_access &= pte_access;
210 index = PT_INDEX(addr, walker->level);
212 table_gfn = gpte_to_gfn(pte);
213 offset = index * sizeof(pt_element_t);
214 pte_gpa = gfn_to_gpa(table_gfn) + offset;
215 walker->table_gfn[walker->level - 1] = table_gfn;
216 walker->pte_gpa[walker->level - 1] = pte_gpa;
218 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
219 PFERR_USER_MASK|PFERR_WRITE_MASK);
220 if (unlikely(real_gfn == UNMAPPED_GVA))
222 real_gfn = gpa_to_gfn(real_gfn);
224 host_addr = gfn_to_hva_prot(vcpu->kvm, real_gfn,
225 &walker->pte_writable[walker->level - 1]);
226 if (unlikely(kvm_is_error_hva(host_addr)))
229 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
230 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
232 walker->ptep_user[walker->level - 1] = ptep_user;
234 trace_kvm_mmu_paging_element(pte, walker->level);
236 if (unlikely(!is_present_gpte(pte)))
239 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
241 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
245 accessed_dirty &= pte;
246 pte_access = pt_access & gpte_access(vcpu, pte);
248 walker->ptes[walker->level - 1] = pte;
249 } while (!is_last_gpte(mmu, walker->level, pte));
251 if (unlikely(permission_fault(mmu, pte_access, access))) {
252 errcode |= PFERR_PRESENT_MASK;
256 gfn = gpte_to_gfn_lvl(pte, walker->level);
257 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
259 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
260 gfn += pse36_gfn_delta(pte);
262 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access);
263 if (real_gpa == UNMAPPED_GVA)
266 walker->gfn = real_gpa >> PAGE_SHIFT;
269 protect_clean_gpte(&pte_access, pte);
272 * On a write fault, fold the dirty bit into accessed_dirty by
273 * shifting it one place right.
275 accessed_dirty &= pte >> (PT_DIRTY_SHIFT - PT_ACCESSED_SHIFT);
277 if (unlikely(!accessed_dirty)) {
278 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
279 if (unlikely(ret < 0))
285 walker->pt_access = pt_access;
286 walker->pte_access = pte_access;
287 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
288 __func__, (u64)pte, pte_access, pt_access);
292 errcode |= write_fault | user_fault;
293 if (fetch_fault && (mmu->nx ||
294 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
295 errcode |= PFERR_FETCH_MASK;
297 walker->fault.vector = PF_VECTOR;
298 walker->fault.error_code_valid = true;
299 walker->fault.error_code = errcode;
300 walker->fault.address = addr;
301 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
303 trace_kvm_mmu_walker_error(walker->fault.error_code);
307 static int FNAME(walk_addr)(struct guest_walker *walker,
308 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
310 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
314 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
315 struct kvm_vcpu *vcpu, gva_t addr,
318 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
323 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
324 u64 *spte, pt_element_t gpte, bool no_dirty_log)
330 if (prefetch_invalid_gpte(vcpu, sp, spte, gpte))
333 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
335 gfn = gpte_to_gfn(gpte);
336 pte_access = sp->role.access & gpte_access(vcpu, gpte);
337 protect_clean_gpte(&pte_access, gpte);
338 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
339 no_dirty_log && (pte_access & ACC_WRITE_MASK));
340 if (is_error_pfn(pfn))
344 * we call mmu_set_spte() with host_writable = true because
345 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
347 mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL,
348 gfn, pfn, true, true);
353 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
354 u64 *spte, const void *pte)
356 pt_element_t gpte = *(const pt_element_t *)pte;
358 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
361 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
362 struct guest_walker *gw, int level)
364 pt_element_t curr_pte;
365 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
369 if (level == PT_PAGE_TABLE_LEVEL) {
370 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
371 base_gpa = pte_gpa & ~mask;
372 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
374 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
375 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
376 curr_pte = gw->prefetch_ptes[index];
378 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
379 &curr_pte, sizeof(curr_pte));
381 return r || curr_pte != gw->ptes[level - 1];
384 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
387 struct kvm_mmu_page *sp;
388 pt_element_t *gptep = gw->prefetch_ptes;
392 sp = page_header(__pa(sptep));
394 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
398 return __direct_pte_prefetch(vcpu, sp, sptep);
400 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
403 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
407 if (is_shadow_present_pte(*spte))
410 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
416 * Fetch a shadow pte for a specific level in the paging hierarchy.
417 * If the guest tries to write a write-protected page, we need to
418 * emulate this operation, return 1 to indicate this case.
420 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
421 struct guest_walker *gw,
422 int write_fault, int hlevel,
423 pfn_t pfn, bool map_writable, bool prefault)
425 struct kvm_mmu_page *sp = NULL;
426 struct kvm_shadow_walk_iterator it;
427 unsigned direct_access, access = gw->pt_access;
428 int top_level, emulate = 0;
430 direct_access = gw->pte_access;
432 top_level = vcpu->arch.mmu.root_level;
433 if (top_level == PT32E_ROOT_LEVEL)
434 top_level = PT32_ROOT_LEVEL;
436 * Verify that the top-level gpte is still there. Since the page
437 * is a root page, it is either write protected (and cannot be
438 * changed from now on) or it is invalid (in which case, we don't
439 * really care if it changes underneath us after this point).
441 if (FNAME(gpte_changed)(vcpu, gw, top_level))
442 goto out_gpte_changed;
444 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
445 goto out_gpte_changed;
447 for (shadow_walk_init(&it, vcpu, addr);
448 shadow_walk_okay(&it) && it.level > gw->level;
449 shadow_walk_next(&it)) {
452 clear_sp_write_flooding_count(it.sptep);
453 drop_large_spte(vcpu, it.sptep);
456 if (!is_shadow_present_pte(*it.sptep)) {
457 table_gfn = gw->table_gfn[it.level - 2];
458 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
459 false, access, it.sptep);
463 * Verify that the gpte in the page we've just write
464 * protected is still there.
466 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
467 goto out_gpte_changed;
470 link_shadow_page(it.sptep, sp);
474 shadow_walk_okay(&it) && it.level > hlevel;
475 shadow_walk_next(&it)) {
478 clear_sp_write_flooding_count(it.sptep);
479 validate_direct_spte(vcpu, it.sptep, direct_access);
481 drop_large_spte(vcpu, it.sptep);
483 if (is_shadow_present_pte(*it.sptep))
486 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
488 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
489 true, direct_access, it.sptep);
490 link_shadow_page(it.sptep, sp);
493 clear_sp_write_flooding_count(it.sptep);
494 mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate,
495 it.level, gw->gfn, pfn, prefault, map_writable);
496 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
502 kvm_mmu_put_page(sp, it.sptep);
503 kvm_release_pfn_clean(pfn);
508 * To see whether the mapped gfn can write its page table in the current
511 * It is the helper function of FNAME(page_fault). When guest uses large page
512 * size to map the writable gfn which is used as current page table, we should
513 * force kvm to use small page size to map it because new shadow page will be
514 * created when kvm establishes shadow page table that stop kvm using large
515 * page size. Do it early can avoid unnecessary #PF and emulation.
517 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
518 * currently used as its page table.
520 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
521 * since the PDPT is always shadowed, that means, we can not use large page
522 * size to map the gfn which is used as PDPT.
525 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
526 struct guest_walker *walker, int user_fault,
527 bool *write_fault_to_shadow_pgtable)
530 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
531 bool self_changed = false;
533 if (!(walker->pte_access & ACC_WRITE_MASK ||
534 (!is_write_protection(vcpu) && !user_fault)))
537 for (level = walker->level; level <= walker->max_level; level++) {
538 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
540 self_changed |= !(gfn & mask);
541 *write_fault_to_shadow_pgtable |= !gfn;
548 * Page fault handler. There are several causes for a page fault:
549 * - there is no shadow pte for the guest pte
550 * - write access through a shadow pte marked read only so that we can set
552 * - write access to a shadow pte marked read only so we can update the page
553 * dirty bitmap, when userspace requests it
554 * - mmio access; in this case we will never install a present shadow pte
555 * - normal guest page fault due to the guest pte marked not present, not
556 * writable, or not executable
558 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
559 * a negative value on error.
561 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
564 int write_fault = error_code & PFERR_WRITE_MASK;
565 int user_fault = error_code & PFERR_USER_MASK;
566 struct guest_walker walker;
569 int level = PT_PAGE_TABLE_LEVEL;
571 unsigned long mmu_seq;
572 bool map_writable, is_self_change_mapping;
574 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
576 if (unlikely(error_code & PFERR_RSVD_MASK))
577 return handle_mmio_page_fault(vcpu, addr, error_code,
578 mmu_is_nested(vcpu));
580 r = mmu_topup_memory_caches(vcpu);
585 * Look up the guest pte for the faulting address.
587 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
590 * The page is not mapped by the guest. Let the guest handle it.
593 pgprintk("%s: guest page fault\n", __func__);
595 inject_page_fault(vcpu, &walker.fault);
600 vcpu->arch.write_fault_to_shadow_pgtable = false;
602 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
603 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
605 if (walker.level >= PT_DIRECTORY_LEVEL)
606 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn)
607 || is_self_change_mapping;
610 if (!force_pt_level) {
611 level = min(walker.level, mapping_level(vcpu, walker.gfn));
612 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
615 mmu_seq = vcpu->kvm->mmu_notifier_seq;
618 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
622 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
623 walker.gfn, pfn, walker.pte_access, &r))
627 * Do not change pte_access if the pfn is a mmio page, otherwise
628 * we will cache the incorrect access into mmio spte.
630 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
631 !is_write_protection(vcpu) && !user_fault &&
632 !is_noslot_pfn(pfn)) {
633 walker.pte_access |= ACC_WRITE_MASK;
634 walker.pte_access &= ~ACC_USER_MASK;
637 * If we converted a user page to a kernel page,
638 * so that the kernel can write to it when cr0.wp=0,
639 * then we should prevent the kernel from executing it
640 * if SMEP is enabled.
642 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
643 walker.pte_access &= ~ACC_EXEC_MASK;
646 spin_lock(&vcpu->kvm->mmu_lock);
647 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
650 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
651 make_mmu_pages_available(vcpu);
653 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
654 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
655 level, pfn, map_writable, prefault);
656 ++vcpu->stat.pf_fixed;
657 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
658 spin_unlock(&vcpu->kvm->mmu_lock);
663 spin_unlock(&vcpu->kvm->mmu_lock);
664 kvm_release_pfn_clean(pfn);
668 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
672 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
675 offset = sp->role.quadrant << PT64_LEVEL_BITS;
677 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
680 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
682 struct kvm_shadow_walk_iterator iterator;
683 struct kvm_mmu_page *sp;
687 vcpu_clear_mmio_info(vcpu, gva);
690 * No need to check return value here, rmap_can_add() can
691 * help us to skip pte prefetch later.
693 mmu_topup_memory_caches(vcpu);
695 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
700 spin_lock(&vcpu->kvm->mmu_lock);
701 for_each_shadow_entry(vcpu, gva, iterator) {
702 level = iterator.level;
703 sptep = iterator.sptep;
705 sp = page_header(__pa(sptep));
706 if (is_last_spte(*sptep, level)) {
713 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
714 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
716 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
717 kvm_flush_remote_tlbs(vcpu->kvm);
719 if (!rmap_can_add(vcpu))
722 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
723 sizeof(pt_element_t)))
726 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
729 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
732 spin_unlock(&vcpu->kvm->mmu_lock);
735 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
736 struct x86_exception *exception)
738 struct guest_walker walker;
739 gpa_t gpa = UNMAPPED_GVA;
742 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
745 gpa = gfn_to_gpa(walker.gfn);
746 gpa |= vaddr & ~PAGE_MASK;
747 } else if (exception)
748 *exception = walker.fault;
753 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
755 struct x86_exception *exception)
757 struct guest_walker walker;
758 gpa_t gpa = UNMAPPED_GVA;
761 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
764 gpa = gfn_to_gpa(walker.gfn);
765 gpa |= vaddr & ~PAGE_MASK;
766 } else if (exception)
767 *exception = walker.fault;
773 * Using the cached information from sp->gfns is safe because:
774 * - The spte has a reference to the struct page, so the pfn for a given gfn
775 * can't change unless all sptes pointing to it are nuked first.
778 * We should flush all tlbs if spte is dropped even though guest is
779 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
780 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
781 * used by guest then tlbs are not flushed, so guest is allowed to access the
783 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
785 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
787 int i, nr_present = 0;
791 /* direct kvm_mmu_page can not be unsync. */
792 BUG_ON(sp->role.direct);
794 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
796 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
805 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
807 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
808 sizeof(pt_element_t)))
811 if (prefetch_invalid_gpte(vcpu, sp, &sp->spt[i], gpte)) {
812 vcpu->kvm->tlbs_dirty++;
816 gfn = gpte_to_gfn(gpte);
817 pte_access = sp->role.access;
818 pte_access &= gpte_access(vcpu, gpte);
819 protect_clean_gpte(&pte_access, gpte);
821 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
824 if (gfn != sp->gfns[i]) {
825 drop_spte(vcpu->kvm, &sp->spt[i]);
826 vcpu->kvm->tlbs_dirty++;
832 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
834 set_spte(vcpu, &sp->spt[i], pte_access,
835 PT_PAGE_TABLE_LEVEL, gfn,
836 spte_to_pfn(sp->spt[i]), true, false,
846 #undef PT_BASE_ADDR_MASK
848 #undef PT_LVL_ADDR_MASK
849 #undef PT_LVL_OFFSET_MASK
851 #undef PT_MAX_FULL_LEVELS
853 #undef gpte_to_gfn_lvl