2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
52 bool tdp_enabled = false;
56 AUDIT_POST_PAGE_FAULT,
67 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
68 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72 #define pgprintk(x...) do { } while (0)
73 #define rmap_printk(x...) do { } while (0)
79 module_param(dbg, bool, 0644);
83 #define ASSERT(x) do { } while (0)
87 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
88 __FILE__, __LINE__, #x); \
92 #define PTE_PREFETCH_NUM 8
94 #define PT_FIRST_AVAIL_BITS_SHIFT 10
95 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
97 #define PT64_LEVEL_BITS 9
99 #define PT64_LEVEL_SHIFT(level) \
100 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
102 #define PT64_INDEX(address, level)\
103 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
106 #define PT32_LEVEL_BITS 10
108 #define PT32_LEVEL_SHIFT(level) \
109 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
111 #define PT32_LVL_OFFSET_MASK(level) \
112 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT32_LEVEL_BITS))) - 1))
115 #define PT32_INDEX(address, level)\
116 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
119 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
120 #define PT64_DIR_BASE_ADDR_MASK \
121 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
122 #define PT64_LVL_ADDR_MASK(level) \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT64_LEVEL_BITS))) - 1))
125 #define PT64_LVL_OFFSET_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
137 | shadow_x_mask | shadow_nx_mask)
139 #define ACC_EXEC_MASK 1
140 #define ACC_WRITE_MASK PT_WRITABLE_MASK
141 #define ACC_USER_MASK PT_USER_MASK
142 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
144 #include <trace/events/kvm.h>
146 #define CREATE_TRACE_POINTS
147 #include "mmutrace.h"
149 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
150 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
152 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
154 /* make pte_list_desc fit well in cache line */
155 #define PTE_LIST_EXT 3
157 struct pte_list_desc {
158 u64 *sptes[PTE_LIST_EXT];
159 struct pte_list_desc *more;
162 struct kvm_shadow_walk_iterator {
170 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
171 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
172 shadow_walk_okay(&(_walker)); \
173 shadow_walk_next(&(_walker)))
175 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
176 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
177 shadow_walk_okay(&(_walker)) && \
178 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
179 __shadow_walk_next(&(_walker), spte))
181 static struct kmem_cache *pte_list_desc_cache;
182 static struct kmem_cache *mmu_page_header_cache;
183 static struct percpu_counter kvm_total_used_mmu_pages;
185 static u64 __read_mostly shadow_nx_mask;
186 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
187 static u64 __read_mostly shadow_user_mask;
188 static u64 __read_mostly shadow_accessed_mask;
189 static u64 __read_mostly shadow_dirty_mask;
190 static u64 __read_mostly shadow_mmio_mask;
192 static void mmu_spte_set(u64 *sptep, u64 spte);
193 static void mmu_free_roots(struct kvm_vcpu *vcpu);
195 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
197 shadow_mmio_mask = mmio_mask;
199 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
202 * the low bit of the generation number is always presumed to be zero.
203 * This disables mmio caching during memslot updates. The concept is
204 * similar to a seqcount but instead of retrying the access we just punt
205 * and ignore the cache.
207 * spte bits 3-11 are used as bits 1-9 of the generation number,
208 * the bits 52-61 are used as bits 10-19 of the generation number.
210 #define MMIO_SPTE_GEN_LOW_SHIFT 2
211 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
213 #define MMIO_GEN_SHIFT 20
214 #define MMIO_GEN_LOW_SHIFT 10
215 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
216 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
217 #define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1)
219 static u64 generation_mmio_spte_mask(unsigned int gen)
223 WARN_ON(gen > MMIO_MAX_GEN);
225 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
226 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
230 static unsigned int get_mmio_spte_generation(u64 spte)
234 spte &= ~shadow_mmio_mask;
236 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
237 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
241 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
243 return kvm_memslots(kvm)->generation & MMIO_GEN_MASK;
246 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
249 unsigned int gen = kvm_current_mmio_generation(kvm);
250 u64 mask = generation_mmio_spte_mask(gen);
252 access &= ACC_WRITE_MASK | ACC_USER_MASK;
253 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
255 trace_mark_mmio_spte(sptep, gfn, access, gen);
256 mmu_spte_set(sptep, mask);
259 static bool is_mmio_spte(u64 spte)
261 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
264 static gfn_t get_mmio_spte_gfn(u64 spte)
266 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
267 return (spte & ~mask) >> PAGE_SHIFT;
270 static unsigned get_mmio_spte_access(u64 spte)
272 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
273 return (spte & ~mask) & ~PAGE_MASK;
276 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
277 pfn_t pfn, unsigned access)
279 if (unlikely(is_noslot_pfn(pfn))) {
280 mark_mmio_spte(kvm, sptep, gfn, access);
287 static bool check_mmio_spte(struct kvm *kvm, u64 spte)
289 unsigned int kvm_gen, spte_gen;
291 kvm_gen = kvm_current_mmio_generation(kvm);
292 spte_gen = get_mmio_spte_generation(spte);
294 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
295 return likely(kvm_gen == spte_gen);
298 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
299 u64 dirty_mask, u64 nx_mask, u64 x_mask)
301 shadow_user_mask = user_mask;
302 shadow_accessed_mask = accessed_mask;
303 shadow_dirty_mask = dirty_mask;
304 shadow_nx_mask = nx_mask;
305 shadow_x_mask = x_mask;
307 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
309 static int is_cpuid_PSE36(void)
314 static int is_nx(struct kvm_vcpu *vcpu)
316 return vcpu->arch.efer & EFER_NX;
319 static int is_shadow_present_pte(u64 pte)
321 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
324 static int is_large_pte(u64 pte)
326 return pte & PT_PAGE_SIZE_MASK;
329 static int is_rmap_spte(u64 pte)
331 return is_shadow_present_pte(pte);
334 static int is_last_spte(u64 pte, int level)
336 if (level == PT_PAGE_TABLE_LEVEL)
338 if (is_large_pte(pte))
343 static pfn_t spte_to_pfn(u64 pte)
345 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
348 static gfn_t pse36_gfn_delta(u32 gpte)
350 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
352 return (gpte & PT32_DIR_PSE36_MASK) << shift;
356 static void __set_spte(u64 *sptep, u64 spte)
361 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
366 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
368 return xchg(sptep, spte);
371 static u64 __get_spte_lockless(u64 *sptep)
373 return ACCESS_ONCE(*sptep);
376 static bool __check_direct_spte_mmio_pf(u64 spte)
378 /* It is valid if the spte is zapped. */
390 static void count_spte_clear(u64 *sptep, u64 spte)
392 struct kvm_mmu_page *sp = page_header(__pa(sptep));
394 if (is_shadow_present_pte(spte))
397 /* Ensure the spte is completely set before we increase the count */
399 sp->clear_spte_count++;
402 static void __set_spte(u64 *sptep, u64 spte)
404 union split_spte *ssptep, sspte;
406 ssptep = (union split_spte *)sptep;
407 sspte = (union split_spte)spte;
409 ssptep->spte_high = sspte.spte_high;
412 * If we map the spte from nonpresent to present, We should store
413 * the high bits firstly, then set present bit, so cpu can not
414 * fetch this spte while we are setting the spte.
418 ssptep->spte_low = sspte.spte_low;
421 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
423 union split_spte *ssptep, sspte;
425 ssptep = (union split_spte *)sptep;
426 sspte = (union split_spte)spte;
428 ssptep->spte_low = sspte.spte_low;
431 * If we map the spte from present to nonpresent, we should clear
432 * present bit firstly to avoid vcpu fetch the old high bits.
436 ssptep->spte_high = sspte.spte_high;
437 count_spte_clear(sptep, spte);
440 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
442 union split_spte *ssptep, sspte, orig;
444 ssptep = (union split_spte *)sptep;
445 sspte = (union split_spte)spte;
447 /* xchg acts as a barrier before the setting of the high bits */
448 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
449 orig.spte_high = ssptep->spte_high;
450 ssptep->spte_high = sspte.spte_high;
451 count_spte_clear(sptep, spte);
457 * The idea using the light way get the spte on x86_32 guest is from
458 * gup_get_pte(arch/x86/mm/gup.c).
460 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
461 * coalesces them and we are running out of the MMU lock. Therefore
462 * we need to protect against in-progress updates of the spte.
464 * Reading the spte while an update is in progress may get the old value
465 * for the high part of the spte. The race is fine for a present->non-present
466 * change (because the high part of the spte is ignored for non-present spte),
467 * but for a present->present change we must reread the spte.
469 * All such changes are done in two steps (present->non-present and
470 * non-present->present), hence it is enough to count the number of
471 * present->non-present updates: if it changed while reading the spte,
472 * we might have hit the race. This is done using clear_spte_count.
474 static u64 __get_spte_lockless(u64 *sptep)
476 struct kvm_mmu_page *sp = page_header(__pa(sptep));
477 union split_spte spte, *orig = (union split_spte *)sptep;
481 count = sp->clear_spte_count;
484 spte.spte_low = orig->spte_low;
487 spte.spte_high = orig->spte_high;
490 if (unlikely(spte.spte_low != orig->spte_low ||
491 count != sp->clear_spte_count))
497 static bool __check_direct_spte_mmio_pf(u64 spte)
499 union split_spte sspte = (union split_spte)spte;
500 u32 high_mmio_mask = shadow_mmio_mask >> 32;
502 /* It is valid if the spte is zapped. */
506 /* It is valid if the spte is being zapped. */
507 if (sspte.spte_low == 0ull &&
508 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
515 static bool spte_is_locklessly_modifiable(u64 spte)
517 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
518 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
521 static bool spte_has_volatile_bits(u64 spte)
524 * Always atomicly update spte if it can be updated
525 * out of mmu-lock, it can ensure dirty bit is not lost,
526 * also, it can help us to get a stable is_writable_pte()
527 * to ensure tlb flush is not missed.
529 if (spte_is_locklessly_modifiable(spte))
532 if (!shadow_accessed_mask)
535 if (!is_shadow_present_pte(spte))
538 if ((spte & shadow_accessed_mask) &&
539 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
545 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
547 return (old_spte & bit_mask) && !(new_spte & bit_mask);
550 /* Rules for using mmu_spte_set:
551 * Set the sptep from nonpresent to present.
552 * Note: the sptep being assigned *must* be either not present
553 * or in a state where the hardware will not attempt to update
556 static void mmu_spte_set(u64 *sptep, u64 new_spte)
558 WARN_ON(is_shadow_present_pte(*sptep));
559 __set_spte(sptep, new_spte);
562 /* Rules for using mmu_spte_update:
563 * Update the state bits, it means the mapped pfn is not changged.
565 * Whenever we overwrite a writable spte with a read-only one we
566 * should flush remote TLBs. Otherwise rmap_write_protect
567 * will find a read-only spte, even though the writable spte
568 * might be cached on a CPU's TLB, the return value indicates this
571 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
573 u64 old_spte = *sptep;
576 WARN_ON(!is_rmap_spte(new_spte));
578 if (!is_shadow_present_pte(old_spte)) {
579 mmu_spte_set(sptep, new_spte);
583 if (!spte_has_volatile_bits(old_spte))
584 __update_clear_spte_fast(sptep, new_spte);
586 old_spte = __update_clear_spte_slow(sptep, new_spte);
589 * For the spte updated out of mmu-lock is safe, since
590 * we always atomicly update it, see the comments in
591 * spte_has_volatile_bits().
593 if (spte_is_locklessly_modifiable(old_spte) &&
594 !is_writable_pte(new_spte))
597 if (!shadow_accessed_mask)
600 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
601 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
602 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
603 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
609 * Rules for using mmu_spte_clear_track_bits:
610 * It sets the sptep from present to nonpresent, and track the
611 * state bits, it is used to clear the last level sptep.
613 static int mmu_spte_clear_track_bits(u64 *sptep)
616 u64 old_spte = *sptep;
618 if (!spte_has_volatile_bits(old_spte))
619 __update_clear_spte_fast(sptep, 0ull);
621 old_spte = __update_clear_spte_slow(sptep, 0ull);
623 if (!is_rmap_spte(old_spte))
626 pfn = spte_to_pfn(old_spte);
629 * KVM does not hold the refcount of the page used by
630 * kvm mmu, before reclaiming the page, we should
631 * unmap it from mmu first.
633 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
635 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
636 kvm_set_pfn_accessed(pfn);
637 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
638 kvm_set_pfn_dirty(pfn);
643 * Rules for using mmu_spte_clear_no_track:
644 * Directly clear spte without caring the state bits of sptep,
645 * it is used to set the upper level spte.
647 static void mmu_spte_clear_no_track(u64 *sptep)
649 __update_clear_spte_fast(sptep, 0ull);
652 static u64 mmu_spte_get_lockless(u64 *sptep)
654 return __get_spte_lockless(sptep);
657 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
660 * Prevent page table teardown by making any free-er wait during
661 * kvm_flush_remote_tlbs() IPI to all active vcpus.
664 vcpu->mode = READING_SHADOW_PAGE_TABLES;
666 * Make sure a following spte read is not reordered ahead of the write
672 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
675 * Make sure the write to vcpu->mode is not reordered in front of
676 * reads to sptes. If it does, kvm_commit_zap_page() can see us
677 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
680 vcpu->mode = OUTSIDE_GUEST_MODE;
684 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
685 struct kmem_cache *base_cache, int min)
689 if (cache->nobjs >= min)
691 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
692 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
695 cache->objects[cache->nobjs++] = obj;
700 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
705 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
706 struct kmem_cache *cache)
709 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
712 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
717 if (cache->nobjs >= min)
719 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
720 page = (void *)__get_free_page(GFP_KERNEL);
723 cache->objects[cache->nobjs++] = page;
728 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
731 free_page((unsigned long)mc->objects[--mc->nobjs]);
734 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
738 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
739 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
742 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
745 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
746 mmu_page_header_cache, 4);
751 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
753 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
754 pte_list_desc_cache);
755 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
756 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
757 mmu_page_header_cache);
760 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
765 p = mc->objects[--mc->nobjs];
769 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
771 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
774 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
776 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
779 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
781 if (!sp->role.direct)
782 return sp->gfns[index];
784 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
787 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
790 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
792 sp->gfns[index] = gfn;
796 * Return the pointer to the large page information for a given gfn,
797 * handling slots that are not large page aligned.
799 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
800 struct kvm_memory_slot *slot,
805 idx = gfn_to_index(gfn, slot->base_gfn, level);
806 return &slot->arch.lpage_info[level - 2][idx];
809 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
811 struct kvm_memory_slot *slot;
812 struct kvm_lpage_info *linfo;
815 slot = gfn_to_memslot(kvm, gfn);
816 for (i = PT_DIRECTORY_LEVEL;
817 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
818 linfo = lpage_info_slot(gfn, slot, i);
819 linfo->write_count += 1;
821 kvm->arch.indirect_shadow_pages++;
824 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
826 struct kvm_memory_slot *slot;
827 struct kvm_lpage_info *linfo;
830 slot = gfn_to_memslot(kvm, gfn);
831 for (i = PT_DIRECTORY_LEVEL;
832 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
833 linfo = lpage_info_slot(gfn, slot, i);
834 linfo->write_count -= 1;
835 WARN_ON(linfo->write_count < 0);
837 kvm->arch.indirect_shadow_pages--;
840 static int has_wrprotected_page(struct kvm *kvm,
844 struct kvm_memory_slot *slot;
845 struct kvm_lpage_info *linfo;
847 slot = gfn_to_memslot(kvm, gfn);
849 linfo = lpage_info_slot(gfn, slot, level);
850 return linfo->write_count;
856 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
858 unsigned long page_size;
861 page_size = kvm_host_page_size(kvm, gfn);
863 for (i = PT_PAGE_TABLE_LEVEL;
864 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
865 if (page_size >= KVM_HPAGE_SIZE(i))
874 static struct kvm_memory_slot *
875 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
878 struct kvm_memory_slot *slot;
880 slot = gfn_to_memslot(vcpu->kvm, gfn);
881 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
882 (no_dirty_log && slot->dirty_bitmap))
888 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
890 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
893 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
895 int host_level, level, max_level;
897 host_level = host_mapping_level(vcpu->kvm, large_gfn);
899 if (host_level == PT_PAGE_TABLE_LEVEL)
902 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
904 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
905 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
912 * Pte mapping structures:
914 * If pte_list bit zero is zero, then pte_list point to the spte.
916 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
917 * pte_list_desc containing more mappings.
919 * Returns the number of pte entries before the spte was added or zero if
920 * the spte was not added.
923 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
924 unsigned long *pte_list)
926 struct pte_list_desc *desc;
930 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
931 *pte_list = (unsigned long)spte;
932 } else if (!(*pte_list & 1)) {
933 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
934 desc = mmu_alloc_pte_list_desc(vcpu);
935 desc->sptes[0] = (u64 *)*pte_list;
936 desc->sptes[1] = spte;
937 *pte_list = (unsigned long)desc | 1;
940 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
941 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
942 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
944 count += PTE_LIST_EXT;
946 if (desc->sptes[PTE_LIST_EXT-1]) {
947 desc->more = mmu_alloc_pte_list_desc(vcpu);
950 for (i = 0; desc->sptes[i]; ++i)
952 desc->sptes[i] = spte;
958 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
959 int i, struct pte_list_desc *prev_desc)
963 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
965 desc->sptes[i] = desc->sptes[j];
966 desc->sptes[j] = NULL;
969 if (!prev_desc && !desc->more)
970 *pte_list = (unsigned long)desc->sptes[0];
973 prev_desc->more = desc->more;
975 *pte_list = (unsigned long)desc->more | 1;
976 mmu_free_pte_list_desc(desc);
979 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
981 struct pte_list_desc *desc;
982 struct pte_list_desc *prev_desc;
986 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
988 } else if (!(*pte_list & 1)) {
989 rmap_printk("pte_list_remove: %p 1->0\n", spte);
990 if ((u64 *)*pte_list != spte) {
991 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
996 rmap_printk("pte_list_remove: %p many->many\n", spte);
997 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1000 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1001 if (desc->sptes[i] == spte) {
1002 pte_list_desc_remove_entry(pte_list,
1010 pr_err("pte_list_remove: %p many->many\n", spte);
1015 typedef void (*pte_list_walk_fn) (u64 *spte);
1016 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1018 struct pte_list_desc *desc;
1024 if (!(*pte_list & 1))
1025 return fn((u64 *)*pte_list);
1027 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1029 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1035 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1036 struct kvm_memory_slot *slot)
1040 idx = gfn_to_index(gfn, slot->base_gfn, level);
1041 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1045 * Take gfn and return the reverse mapping to it.
1047 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1049 struct kvm_memory_slot *slot;
1051 slot = gfn_to_memslot(kvm, gfn);
1052 return __gfn_to_rmap(gfn, level, slot);
1055 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1057 struct kvm_mmu_memory_cache *cache;
1059 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1060 return mmu_memory_cache_free_objects(cache);
1063 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1065 struct kvm_mmu_page *sp;
1066 unsigned long *rmapp;
1068 sp = page_header(__pa(spte));
1069 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1070 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1071 return pte_list_add(vcpu, spte, rmapp);
1074 static void rmap_remove(struct kvm *kvm, u64 *spte)
1076 struct kvm_mmu_page *sp;
1078 unsigned long *rmapp;
1080 sp = page_header(__pa(spte));
1081 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1082 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1083 pte_list_remove(spte, rmapp);
1087 * Used by the following functions to iterate through the sptes linked by a
1088 * rmap. All fields are private and not assumed to be used outside.
1090 struct rmap_iterator {
1091 /* private fields */
1092 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1093 int pos; /* index of the sptep */
1097 * Iteration must be started by this function. This should also be used after
1098 * removing/dropping sptes from the rmap link because in such cases the
1099 * information in the itererator may not be valid.
1101 * Returns sptep if found, NULL otherwise.
1103 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1113 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1115 return iter->desc->sptes[iter->pos];
1119 * Must be used with a valid iterator: e.g. after rmap_get_first().
1121 * Returns sptep if found, NULL otherwise.
1123 static u64 *rmap_get_next(struct rmap_iterator *iter)
1126 if (iter->pos < PTE_LIST_EXT - 1) {
1130 sptep = iter->desc->sptes[iter->pos];
1135 iter->desc = iter->desc->more;
1139 /* desc->sptes[0] cannot be NULL */
1140 return iter->desc->sptes[iter->pos];
1147 static void drop_spte(struct kvm *kvm, u64 *sptep)
1149 if (mmu_spte_clear_track_bits(sptep))
1150 rmap_remove(kvm, sptep);
1154 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1156 if (is_large_pte(*sptep)) {
1157 WARN_ON(page_header(__pa(sptep))->role.level ==
1158 PT_PAGE_TABLE_LEVEL);
1159 drop_spte(kvm, sptep);
1167 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1169 if (__drop_large_spte(vcpu->kvm, sptep))
1170 kvm_flush_remote_tlbs(vcpu->kvm);
1174 * Write-protect on the specified @sptep, @pt_protect indicates whether
1175 * spte write-protection is caused by protecting shadow page table.
1177 * Note: write protection is difference between dirty logging and spte
1179 * - for dirty logging, the spte can be set to writable at anytime if
1180 * its dirty bitmap is properly set.
1181 * - for spte protection, the spte can be writable only after unsync-ing
1184 * Return true if tlb need be flushed.
1186 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1190 if (!is_writable_pte(spte) &&
1191 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1194 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1197 spte &= ~SPTE_MMU_WRITEABLE;
1198 spte = spte & ~PT_WRITABLE_MASK;
1200 return mmu_spte_update(sptep, spte);
1203 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1207 struct rmap_iterator iter;
1210 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1211 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1213 flush |= spte_write_protect(kvm, sptep, pt_protect);
1214 sptep = rmap_get_next(&iter);
1221 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1222 * @kvm: kvm instance
1223 * @slot: slot to protect
1224 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1225 * @mask: indicates which pages we should protect
1227 * Used when we do not need to care about huge page mappings: e.g. during dirty
1228 * logging we do not have any such mappings.
1230 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1231 struct kvm_memory_slot *slot,
1232 gfn_t gfn_offset, unsigned long mask)
1234 unsigned long *rmapp;
1237 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1238 PT_PAGE_TABLE_LEVEL, slot);
1239 __rmap_write_protect(kvm, rmapp, false);
1241 /* clear the first set bit */
1246 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1248 struct kvm_memory_slot *slot;
1249 unsigned long *rmapp;
1251 bool write_protected = false;
1253 slot = gfn_to_memslot(kvm, gfn);
1255 for (i = PT_PAGE_TABLE_LEVEL;
1256 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1257 rmapp = __gfn_to_rmap(gfn, i, slot);
1258 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1261 return write_protected;
1264 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1265 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1269 struct rmap_iterator iter;
1270 int need_tlb_flush = 0;
1272 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1273 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1274 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx gfn %llx (%d)\n",
1275 sptep, *sptep, gfn, level);
1277 drop_spte(kvm, sptep);
1281 return need_tlb_flush;
1284 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1285 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1289 struct rmap_iterator iter;
1292 pte_t *ptep = (pte_t *)data;
1295 WARN_ON(pte_huge(*ptep));
1296 new_pfn = pte_pfn(*ptep);
1298 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1299 BUG_ON(!is_shadow_present_pte(*sptep));
1300 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1301 sptep, *sptep, gfn, level);
1305 if (pte_write(*ptep)) {
1306 drop_spte(kvm, sptep);
1307 sptep = rmap_get_first(*rmapp, &iter);
1309 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1310 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1312 new_spte &= ~PT_WRITABLE_MASK;
1313 new_spte &= ~SPTE_HOST_WRITEABLE;
1314 new_spte &= ~shadow_accessed_mask;
1316 mmu_spte_clear_track_bits(sptep);
1317 mmu_spte_set(sptep, new_spte);
1318 sptep = rmap_get_next(&iter);
1323 kvm_flush_remote_tlbs(kvm);
1328 static int kvm_handle_hva_range(struct kvm *kvm,
1329 unsigned long start,
1332 int (*handler)(struct kvm *kvm,
1333 unsigned long *rmapp,
1334 struct kvm_memory_slot *slot,
1337 unsigned long data))
1341 struct kvm_memslots *slots;
1342 struct kvm_memory_slot *memslot;
1344 slots = kvm_memslots(kvm);
1346 kvm_for_each_memslot(memslot, slots) {
1347 unsigned long hva_start, hva_end;
1348 gfn_t gfn_start, gfn_end;
1350 hva_start = max(start, memslot->userspace_addr);
1351 hva_end = min(end, memslot->userspace_addr +
1352 (memslot->npages << PAGE_SHIFT));
1353 if (hva_start >= hva_end)
1356 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1357 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1359 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1360 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1362 for (j = PT_PAGE_TABLE_LEVEL;
1363 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1364 unsigned long idx, idx_end;
1365 unsigned long *rmapp;
1366 gfn_t gfn = gfn_start;
1369 * {idx(page_j) | page_j intersects with
1370 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1372 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1373 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1375 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1377 for (; idx <= idx_end;
1378 ++idx, gfn += (1UL << KVM_HPAGE_GFN_SHIFT(j)))
1379 ret |= handler(kvm, rmapp++, memslot,
1387 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1389 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1390 struct kvm_memory_slot *slot,
1391 gfn_t gfn, int level,
1392 unsigned long data))
1394 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1397 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1399 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1402 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1404 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1407 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1409 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1412 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1413 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1417 struct rmap_iterator uninitialized_var(iter);
1420 BUG_ON(!shadow_accessed_mask);
1422 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1423 sptep = rmap_get_next(&iter)) {
1424 BUG_ON(!is_shadow_present_pte(*sptep));
1426 if (*sptep & shadow_accessed_mask) {
1428 clear_bit((ffs(shadow_accessed_mask) - 1),
1429 (unsigned long *)sptep);
1432 trace_kvm_age_page(gfn, level, slot, young);
1436 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1437 struct kvm_memory_slot *slot, gfn_t gfn,
1438 int level, unsigned long data)
1441 struct rmap_iterator iter;
1445 * If there's no access bit in the secondary pte set by the
1446 * hardware it's up to gup-fast/gup to set the access bit in
1447 * the primary pte or in the page structure.
1449 if (!shadow_accessed_mask)
1452 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1453 sptep = rmap_get_next(&iter)) {
1454 BUG_ON(!is_shadow_present_pte(*sptep));
1456 if (*sptep & shadow_accessed_mask) {
1465 #define RMAP_RECYCLE_THRESHOLD 1000
1467 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1469 unsigned long *rmapp;
1470 struct kvm_mmu_page *sp;
1472 sp = page_header(__pa(spte));
1474 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1476 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, gfn, sp->role.level, 0);
1477 kvm_flush_remote_tlbs(vcpu->kvm);
1480 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1483 * In case of absence of EPT Access and Dirty Bits supports,
1484 * emulate the accessed bit for EPT, by checking if this page has
1485 * an EPT mapping, and clearing it if it does. On the next access,
1486 * a new EPT mapping will be established.
1487 * This has some overhead, but not as much as the cost of swapping
1488 * out actively used pages or breaking up actively used hugepages.
1490 if (!shadow_accessed_mask) {
1492 * We are holding the kvm->mmu_lock, and we are blowing up
1493 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1494 * This is correct as long as we don't decouple the mmu_lock
1495 * protected regions (like invalidate_range_start|end does).
1497 kvm->mmu_notifier_seq++;
1498 return kvm_handle_hva_range(kvm, start, end, 0,
1502 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1505 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1507 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1511 static int is_empty_shadow_page(u64 *spt)
1516 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1517 if (is_shadow_present_pte(*pos)) {
1518 printk(KERN_ERR "%s: %p %llx\n", __func__,
1527 * This value is the sum of all of the kvm instances's
1528 * kvm->arch.n_used_mmu_pages values. We need a global,
1529 * aggregate version in order to make the slab shrinker
1532 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1534 kvm->arch.n_used_mmu_pages += nr;
1535 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1538 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1540 ASSERT(is_empty_shadow_page(sp->spt));
1541 hlist_del(&sp->hash_link);
1542 list_del(&sp->link);
1543 free_page((unsigned long)sp->spt);
1544 if (!sp->role.direct)
1545 free_page((unsigned long)sp->gfns);
1546 kmem_cache_free(mmu_page_header_cache, sp);
1549 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1551 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1554 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1555 struct kvm_mmu_page *sp, u64 *parent_pte)
1560 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1563 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1566 pte_list_remove(parent_pte, &sp->parent_ptes);
1569 static void drop_parent_pte(struct kvm_mmu_page *sp,
1572 mmu_page_remove_parent_pte(sp, parent_pte);
1573 mmu_spte_clear_no_track(parent_pte);
1576 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1577 u64 *parent_pte, int direct)
1579 struct kvm_mmu_page *sp;
1581 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1582 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1584 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1585 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1588 * The active_mmu_pages list is the FIFO list, do not move the
1589 * page until it is zapped. kvm_zap_obsolete_pages depends on
1590 * this feature. See the comments in kvm_zap_obsolete_pages().
1592 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1593 sp->parent_ptes = 0;
1594 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1595 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1599 static void mark_unsync(u64 *spte);
1600 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1602 pte_list_walk(&sp->parent_ptes, mark_unsync);
1605 static void mark_unsync(u64 *spte)
1607 struct kvm_mmu_page *sp;
1610 sp = page_header(__pa(spte));
1611 index = spte - sp->spt;
1612 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1614 if (sp->unsync_children++)
1616 kvm_mmu_mark_parents_unsync(sp);
1619 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1620 struct kvm_mmu_page *sp)
1625 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1629 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1630 struct kvm_mmu_page *sp, u64 *spte,
1636 #define KVM_PAGE_ARRAY_NR 16
1638 struct kvm_mmu_pages {
1639 struct mmu_page_and_offset {
1640 struct kvm_mmu_page *sp;
1642 } page[KVM_PAGE_ARRAY_NR];
1646 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1652 for (i=0; i < pvec->nr; i++)
1653 if (pvec->page[i].sp == sp)
1656 pvec->page[pvec->nr].sp = sp;
1657 pvec->page[pvec->nr].idx = idx;
1659 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1662 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1663 struct kvm_mmu_pages *pvec)
1665 int i, ret, nr_unsync_leaf = 0;
1667 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1668 struct kvm_mmu_page *child;
1669 u64 ent = sp->spt[i];
1671 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1672 goto clear_child_bitmap;
1674 child = page_header(ent & PT64_BASE_ADDR_MASK);
1676 if (child->unsync_children) {
1677 if (mmu_pages_add(pvec, child, i))
1680 ret = __mmu_unsync_walk(child, pvec);
1682 goto clear_child_bitmap;
1684 nr_unsync_leaf += ret;
1687 } else if (child->unsync) {
1689 if (mmu_pages_add(pvec, child, i))
1692 goto clear_child_bitmap;
1697 __clear_bit(i, sp->unsync_child_bitmap);
1698 sp->unsync_children--;
1699 WARN_ON((int)sp->unsync_children < 0);
1703 return nr_unsync_leaf;
1706 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1707 struct kvm_mmu_pages *pvec)
1709 if (!sp->unsync_children)
1712 mmu_pages_add(pvec, sp, 0);
1713 return __mmu_unsync_walk(sp, pvec);
1716 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1718 WARN_ON(!sp->unsync);
1719 trace_kvm_mmu_sync_page(sp);
1721 --kvm->stat.mmu_unsync;
1724 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1725 struct list_head *invalid_list);
1726 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1727 struct list_head *invalid_list);
1730 * NOTE: we should pay more attention on the zapped-obsolete page
1731 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1732 * since it has been deleted from active_mmu_pages but still can be found
1735 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1736 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1737 * all the obsolete pages.
1739 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1740 hlist_for_each_entry(_sp, \
1741 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1742 if ((_sp)->gfn != (_gfn)) {} else
1744 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1745 for_each_gfn_sp(_kvm, _sp, _gfn) \
1746 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1748 /* @sp->gfn should be write-protected at the call site */
1749 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1750 struct list_head *invalid_list, bool clear_unsync)
1752 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1753 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1758 kvm_unlink_unsync_page(vcpu->kvm, sp);
1760 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1761 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1769 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1770 struct kvm_mmu_page *sp)
1772 LIST_HEAD(invalid_list);
1775 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1777 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1782 #ifdef CONFIG_KVM_MMU_AUDIT
1783 #include "mmu_audit.c"
1785 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1786 static void mmu_audit_disable(void) { }
1789 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1790 struct list_head *invalid_list)
1792 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1795 /* @gfn should be write-protected at the call site */
1796 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1798 struct kvm_mmu_page *s;
1799 LIST_HEAD(invalid_list);
1802 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1806 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1807 kvm_unlink_unsync_page(vcpu->kvm, s);
1808 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1809 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1810 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1816 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1818 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1821 struct mmu_page_path {
1822 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1823 unsigned int idx[PT64_ROOT_LEVEL-1];
1826 #define for_each_sp(pvec, sp, parents, i) \
1827 for (i = mmu_pages_next(&pvec, &parents, -1), \
1828 sp = pvec.page[i].sp; \
1829 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1830 i = mmu_pages_next(&pvec, &parents, i))
1832 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1833 struct mmu_page_path *parents,
1838 for (n = i+1; n < pvec->nr; n++) {
1839 struct kvm_mmu_page *sp = pvec->page[n].sp;
1841 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1842 parents->idx[0] = pvec->page[n].idx;
1846 parents->parent[sp->role.level-2] = sp;
1847 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1853 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1855 struct kvm_mmu_page *sp;
1856 unsigned int level = 0;
1859 unsigned int idx = parents->idx[level];
1861 sp = parents->parent[level];
1865 --sp->unsync_children;
1866 WARN_ON((int)sp->unsync_children < 0);
1867 __clear_bit(idx, sp->unsync_child_bitmap);
1869 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1872 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1873 struct mmu_page_path *parents,
1874 struct kvm_mmu_pages *pvec)
1876 parents->parent[parent->role.level-1] = NULL;
1880 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1881 struct kvm_mmu_page *parent)
1884 struct kvm_mmu_page *sp;
1885 struct mmu_page_path parents;
1886 struct kvm_mmu_pages pages;
1887 LIST_HEAD(invalid_list);
1889 kvm_mmu_pages_init(parent, &parents, &pages);
1890 while (mmu_unsync_walk(parent, &pages)) {
1891 bool protected = false;
1893 for_each_sp(pages, sp, parents, i)
1894 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1897 kvm_flush_remote_tlbs(vcpu->kvm);
1899 for_each_sp(pages, sp, parents, i) {
1900 kvm_sync_page(vcpu, sp, &invalid_list);
1901 mmu_pages_clear_parents(&parents);
1903 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1904 cond_resched_lock(&vcpu->kvm->mmu_lock);
1905 kvm_mmu_pages_init(parent, &parents, &pages);
1909 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1913 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1917 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1919 sp->write_flooding_count = 0;
1922 static void clear_sp_write_flooding_count(u64 *spte)
1924 struct kvm_mmu_page *sp = page_header(__pa(spte));
1926 __clear_sp_write_flooding_count(sp);
1929 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1931 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1934 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1942 union kvm_mmu_page_role role;
1944 struct kvm_mmu_page *sp;
1945 bool need_sync = false;
1947 role = vcpu->arch.mmu.base_role;
1949 role.direct = direct;
1952 role.access = access;
1953 if (!vcpu->arch.mmu.direct_map
1954 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1955 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1956 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1957 role.quadrant = quadrant;
1959 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1960 if (is_obsolete_sp(vcpu->kvm, sp))
1963 if (!need_sync && sp->unsync)
1966 if (sp->role.word != role.word)
1969 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1972 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1973 if (sp->unsync_children) {
1974 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1975 kvm_mmu_mark_parents_unsync(sp);
1976 } else if (sp->unsync)
1977 kvm_mmu_mark_parents_unsync(sp);
1979 __clear_sp_write_flooding_count(sp);
1980 trace_kvm_mmu_get_page(sp, false);
1983 ++vcpu->kvm->stat.mmu_cache_miss;
1984 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1989 hlist_add_head(&sp->hash_link,
1990 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1992 if (rmap_write_protect(vcpu->kvm, gfn))
1993 kvm_flush_remote_tlbs(vcpu->kvm);
1994 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1995 kvm_sync_pages(vcpu, gfn);
1997 account_shadowed(vcpu->kvm, gfn);
1999 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2000 init_shadow_page_table(sp);
2001 trace_kvm_mmu_get_page(sp, true);
2005 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2006 struct kvm_vcpu *vcpu, u64 addr)
2008 iterator->addr = addr;
2009 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2010 iterator->level = vcpu->arch.mmu.shadow_root_level;
2012 if (iterator->level == PT64_ROOT_LEVEL &&
2013 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2014 !vcpu->arch.mmu.direct_map)
2017 if (iterator->level == PT32E_ROOT_LEVEL) {
2018 iterator->shadow_addr
2019 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2020 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2022 if (!iterator->shadow_addr)
2023 iterator->level = 0;
2027 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2029 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2032 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2033 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2037 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2040 if (is_last_spte(spte, iterator->level)) {
2041 iterator->level = 0;
2045 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2049 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2051 return __shadow_walk_next(iterator, *iterator->sptep);
2054 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
2058 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2059 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2061 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2062 shadow_user_mask | shadow_x_mask;
2065 spte |= shadow_accessed_mask;
2067 mmu_spte_set(sptep, spte);
2070 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2071 unsigned direct_access)
2073 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2074 struct kvm_mmu_page *child;
2077 * For the direct sp, if the guest pte's dirty bit
2078 * changed form clean to dirty, it will corrupt the
2079 * sp's access: allow writable in the read-only sp,
2080 * so we should update the spte at this point to get
2081 * a new sp with the correct access.
2083 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2084 if (child->role.access == direct_access)
2087 drop_parent_pte(child, sptep);
2088 kvm_flush_remote_tlbs(vcpu->kvm);
2092 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2096 struct kvm_mmu_page *child;
2099 if (is_shadow_present_pte(pte)) {
2100 if (is_last_spte(pte, sp->role.level)) {
2101 drop_spte(kvm, spte);
2102 if (is_large_pte(pte))
2105 child = page_header(pte & PT64_BASE_ADDR_MASK);
2106 drop_parent_pte(child, spte);
2111 if (is_mmio_spte(pte))
2112 mmu_spte_clear_no_track(spte);
2117 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2118 struct kvm_mmu_page *sp)
2122 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2123 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2126 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2128 mmu_page_remove_parent_pte(sp, parent_pte);
2131 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2134 struct rmap_iterator iter;
2136 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2137 drop_parent_pte(sp, sptep);
2140 static int mmu_zap_unsync_children(struct kvm *kvm,
2141 struct kvm_mmu_page *parent,
2142 struct list_head *invalid_list)
2145 struct mmu_page_path parents;
2146 struct kvm_mmu_pages pages;
2148 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2151 kvm_mmu_pages_init(parent, &parents, &pages);
2152 while (mmu_unsync_walk(parent, &pages)) {
2153 struct kvm_mmu_page *sp;
2155 for_each_sp(pages, sp, parents, i) {
2156 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2157 mmu_pages_clear_parents(&parents);
2160 kvm_mmu_pages_init(parent, &parents, &pages);
2166 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2167 struct list_head *invalid_list)
2171 trace_kvm_mmu_prepare_zap_page(sp);
2172 ++kvm->stat.mmu_shadow_zapped;
2173 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2174 kvm_mmu_page_unlink_children(kvm, sp);
2175 kvm_mmu_unlink_parents(kvm, sp);
2177 if (!sp->role.invalid && !sp->role.direct)
2178 unaccount_shadowed(kvm, sp->gfn);
2181 kvm_unlink_unsync_page(kvm, sp);
2182 if (!sp->root_count) {
2185 list_move(&sp->link, invalid_list);
2186 kvm_mod_used_mmu_pages(kvm, -1);
2188 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2191 * The obsolete pages can not be used on any vcpus.
2192 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2194 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2195 kvm_reload_remote_mmus(kvm);
2198 sp->role.invalid = 1;
2202 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2203 struct list_head *invalid_list)
2205 struct kvm_mmu_page *sp, *nsp;
2207 if (list_empty(invalid_list))
2211 * wmb: make sure everyone sees our modifications to the page tables
2212 * rmb: make sure we see changes to vcpu->mode
2217 * Wait for all vcpus to exit guest mode and/or lockless shadow
2220 kvm_flush_remote_tlbs(kvm);
2222 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2223 WARN_ON(!sp->role.invalid || sp->root_count);
2224 kvm_mmu_free_page(sp);
2228 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2229 struct list_head *invalid_list)
2231 struct kvm_mmu_page *sp;
2233 if (list_empty(&kvm->arch.active_mmu_pages))
2236 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2237 struct kvm_mmu_page, link);
2238 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2244 * Changing the number of mmu pages allocated to the vm
2245 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2247 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2249 LIST_HEAD(invalid_list);
2251 spin_lock(&kvm->mmu_lock);
2253 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2254 /* Need to free some mmu pages to achieve the goal. */
2255 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2256 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2259 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2260 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2263 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2265 spin_unlock(&kvm->mmu_lock);
2268 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2270 struct kvm_mmu_page *sp;
2271 LIST_HEAD(invalid_list);
2274 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2276 spin_lock(&kvm->mmu_lock);
2277 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2278 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2281 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2283 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2284 spin_unlock(&kvm->mmu_lock);
2288 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2291 * The function is based on mtrr_type_lookup() in
2292 * arch/x86/kernel/cpu/mtrr/generic.c
2294 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2299 u8 prev_match, curr_match;
2300 int num_var_ranges = KVM_NR_VAR_MTRR;
2302 if (!mtrr_state->enabled)
2305 /* Make end inclusive end, instead of exclusive */
2308 /* Look in fixed ranges. Just return the type as per start */
2309 if (mtrr_state->have_fixed && (start < 0x100000)) {
2312 if (start < 0x80000) {
2314 idx += (start >> 16);
2315 return mtrr_state->fixed_ranges[idx];
2316 } else if (start < 0xC0000) {
2318 idx += ((start - 0x80000) >> 14);
2319 return mtrr_state->fixed_ranges[idx];
2320 } else if (start < 0x1000000) {
2322 idx += ((start - 0xC0000) >> 12);
2323 return mtrr_state->fixed_ranges[idx];
2328 * Look in variable ranges
2329 * Look of multiple ranges matching this address and pick type
2330 * as per MTRR precedence
2332 if (!(mtrr_state->enabled & 2))
2333 return mtrr_state->def_type;
2336 for (i = 0; i < num_var_ranges; ++i) {
2337 unsigned short start_state, end_state;
2339 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2342 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2343 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2344 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2345 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2347 start_state = ((start & mask) == (base & mask));
2348 end_state = ((end & mask) == (base & mask));
2349 if (start_state != end_state)
2352 if ((start & mask) != (base & mask))
2355 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2356 if (prev_match == 0xFF) {
2357 prev_match = curr_match;
2361 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2362 curr_match == MTRR_TYPE_UNCACHABLE)
2363 return MTRR_TYPE_UNCACHABLE;
2365 if ((prev_match == MTRR_TYPE_WRBACK &&
2366 curr_match == MTRR_TYPE_WRTHROUGH) ||
2367 (prev_match == MTRR_TYPE_WRTHROUGH &&
2368 curr_match == MTRR_TYPE_WRBACK)) {
2369 prev_match = MTRR_TYPE_WRTHROUGH;
2370 curr_match = MTRR_TYPE_WRTHROUGH;
2373 if (prev_match != curr_match)
2374 return MTRR_TYPE_UNCACHABLE;
2377 if (prev_match != 0xFF)
2380 return mtrr_state->def_type;
2383 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2387 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2388 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2389 if (mtrr == 0xfe || mtrr == 0xff)
2390 mtrr = MTRR_TYPE_WRBACK;
2393 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2395 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2397 trace_kvm_mmu_unsync_page(sp);
2398 ++vcpu->kvm->stat.mmu_unsync;
2401 kvm_mmu_mark_parents_unsync(sp);
2404 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2406 struct kvm_mmu_page *s;
2408 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2411 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2412 __kvm_unsync_page(vcpu, s);
2416 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2419 struct kvm_mmu_page *s;
2420 bool need_unsync = false;
2422 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2426 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2433 kvm_unsync_pages(vcpu, gfn);
2437 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2438 unsigned pte_access, int level,
2439 gfn_t gfn, pfn_t pfn, bool speculative,
2440 bool can_unsync, bool host_writable)
2445 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2448 spte = PT_PRESENT_MASK;
2450 spte |= shadow_accessed_mask;
2452 if (pte_access & ACC_EXEC_MASK)
2453 spte |= shadow_x_mask;
2455 spte |= shadow_nx_mask;
2457 if (pte_access & ACC_USER_MASK)
2458 spte |= shadow_user_mask;
2460 if (level > PT_PAGE_TABLE_LEVEL)
2461 spte |= PT_PAGE_SIZE_MASK;
2463 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2464 kvm_is_reserved_pfn(pfn));
2467 spte |= SPTE_HOST_WRITEABLE;
2469 pte_access &= ~ACC_WRITE_MASK;
2471 spte |= (u64)pfn << PAGE_SHIFT;
2473 if (pte_access & ACC_WRITE_MASK) {
2476 * Other vcpu creates new sp in the window between
2477 * mapping_level() and acquiring mmu-lock. We can
2478 * allow guest to retry the access, the mapping can
2479 * be fixed if guest refault.
2481 if (level > PT_PAGE_TABLE_LEVEL &&
2482 has_wrprotected_page(vcpu->kvm, gfn, level))
2485 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2488 * Optimization: for pte sync, if spte was writable the hash
2489 * lookup is unnecessary (and expensive). Write protection
2490 * is responsibility of mmu_get_page / kvm_sync_page.
2491 * Same reasoning can be applied to dirty page accounting.
2493 if (!can_unsync && is_writable_pte(*sptep))
2496 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2497 pgprintk("%s: found shadow page for %llx, marking ro\n",
2500 pte_access &= ~ACC_WRITE_MASK;
2501 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2505 if (pte_access & ACC_WRITE_MASK)
2506 mark_page_dirty(vcpu->kvm, gfn);
2509 if (mmu_spte_update(sptep, spte))
2510 kvm_flush_remote_tlbs(vcpu->kvm);
2515 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2516 unsigned pte_access, int write_fault, int *emulate,
2517 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2520 int was_rmapped = 0;
2523 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2524 *sptep, write_fault, gfn);
2526 if (is_rmap_spte(*sptep)) {
2528 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2529 * the parent of the now unreachable PTE.
2531 if (level > PT_PAGE_TABLE_LEVEL &&
2532 !is_large_pte(*sptep)) {
2533 struct kvm_mmu_page *child;
2536 child = page_header(pte & PT64_BASE_ADDR_MASK);
2537 drop_parent_pte(child, sptep);
2538 kvm_flush_remote_tlbs(vcpu->kvm);
2539 } else if (pfn != spte_to_pfn(*sptep)) {
2540 pgprintk("hfn old %llx new %llx\n",
2541 spte_to_pfn(*sptep), pfn);
2542 drop_spte(vcpu->kvm, sptep);
2543 kvm_flush_remote_tlbs(vcpu->kvm);
2548 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2549 true, host_writable)) {
2552 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2555 if (unlikely(is_mmio_spte(*sptep) && emulate))
2558 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2559 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2560 is_large_pte(*sptep)? "2MB" : "4kB",
2561 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2563 if (!was_rmapped && is_large_pte(*sptep))
2564 ++vcpu->kvm->stat.lpages;
2566 if (is_shadow_present_pte(*sptep)) {
2568 rmap_count = rmap_add(vcpu, sptep, gfn);
2569 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2570 rmap_recycle(vcpu, sptep, gfn);
2574 kvm_release_pfn_clean(pfn);
2577 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2580 struct kvm_memory_slot *slot;
2582 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2584 return KVM_PFN_ERR_FAULT;
2586 return gfn_to_pfn_memslot_atomic(slot, gfn);
2589 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2590 struct kvm_mmu_page *sp,
2591 u64 *start, u64 *end)
2593 struct page *pages[PTE_PREFETCH_NUM];
2594 unsigned access = sp->role.access;
2598 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2599 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2602 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2606 for (i = 0; i < ret; i++, gfn++, start++)
2607 mmu_set_spte(vcpu, start, access, 0, NULL,
2608 sp->role.level, gfn, page_to_pfn(pages[i]),
2614 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2615 struct kvm_mmu_page *sp, u64 *sptep)
2617 u64 *spte, *start = NULL;
2620 WARN_ON(!sp->role.direct);
2622 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2625 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2626 if (is_shadow_present_pte(*spte) || spte == sptep) {
2629 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2637 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2639 struct kvm_mmu_page *sp;
2642 * Since it's no accessed bit on EPT, it's no way to
2643 * distinguish between actually accessed translations
2644 * and prefetched, so disable pte prefetch if EPT is
2647 if (!shadow_accessed_mask)
2650 sp = page_header(__pa(sptep));
2651 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2654 __direct_pte_prefetch(vcpu, sp, sptep);
2657 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2658 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2661 struct kvm_shadow_walk_iterator iterator;
2662 struct kvm_mmu_page *sp;
2666 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2669 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2670 if (iterator.level == level) {
2671 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2672 write, &emulate, level, gfn, pfn,
2673 prefault, map_writable);
2674 direct_pte_prefetch(vcpu, iterator.sptep);
2675 ++vcpu->stat.pf_fixed;
2679 drop_large_spte(vcpu, iterator.sptep);
2680 if (!is_shadow_present_pte(*iterator.sptep)) {
2681 u64 base_addr = iterator.addr;
2683 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2684 pseudo_gfn = base_addr >> PAGE_SHIFT;
2685 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2687 1, ACC_ALL, iterator.sptep);
2689 link_shadow_page(iterator.sptep, sp, true);
2695 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2699 info.si_signo = SIGBUS;
2701 info.si_code = BUS_MCEERR_AR;
2702 info.si_addr = (void __user *)address;
2703 info.si_addr_lsb = PAGE_SHIFT;
2705 send_sig_info(SIGBUS, &info, tsk);
2708 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2711 * Do not cache the mmio info caused by writing the readonly gfn
2712 * into the spte otherwise read access on readonly gfn also can
2713 * caused mmio page fault and treat it as mmio access.
2714 * Return 1 to tell kvm to emulate it.
2716 if (pfn == KVM_PFN_ERR_RO_FAULT)
2719 if (pfn == KVM_PFN_ERR_HWPOISON) {
2720 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2727 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2728 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2732 int level = *levelp;
2735 * Check if it's a transparent hugepage. If this would be an
2736 * hugetlbfs page, level wouldn't be set to
2737 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2740 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2741 level == PT_PAGE_TABLE_LEVEL &&
2742 PageTransCompound(pfn_to_page(pfn)) &&
2743 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2746 * mmu_notifier_retry was successful and we hold the
2747 * mmu_lock here, so the pmd can't become splitting
2748 * from under us, and in turn
2749 * __split_huge_page_refcount() can't run from under
2750 * us and we can safely transfer the refcount from
2751 * PG_tail to PG_head as we switch the pfn to tail to
2754 *levelp = level = PT_DIRECTORY_LEVEL;
2755 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2756 VM_BUG_ON((gfn & mask) != (pfn & mask));
2760 kvm_release_pfn_clean(pfn);
2768 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2769 pfn_t pfn, unsigned access, int *ret_val)
2773 /* The pfn is invalid, report the error! */
2774 if (unlikely(is_error_pfn(pfn))) {
2775 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2779 if (unlikely(is_noslot_pfn(pfn)))
2780 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2787 static bool page_fault_can_be_fast(u32 error_code)
2790 * Do not fix the mmio spte with invalid generation number which
2791 * need to be updated by slow page fault path.
2793 if (unlikely(error_code & PFERR_RSVD_MASK))
2797 * #PF can be fast only if the shadow page table is present and it
2798 * is caused by write-protect, that means we just need change the
2799 * W bit of the spte which can be done out of mmu-lock.
2801 if (!(error_code & PFERR_PRESENT_MASK) ||
2802 !(error_code & PFERR_WRITE_MASK))
2809 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2810 u64 *sptep, u64 spte)
2814 WARN_ON(!sp->role.direct);
2817 * The gfn of direct spte is stable since it is calculated
2820 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2822 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2823 mark_page_dirty(vcpu->kvm, gfn);
2830 * - true: let the vcpu to access on the same address again.
2831 * - false: let the real page fault path to fix it.
2833 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2836 struct kvm_shadow_walk_iterator iterator;
2837 struct kvm_mmu_page *sp;
2841 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2844 if (!page_fault_can_be_fast(error_code))
2847 walk_shadow_page_lockless_begin(vcpu);
2848 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2849 if (!is_shadow_present_pte(spte) || iterator.level < level)
2853 * If the mapping has been changed, let the vcpu fault on the
2854 * same address again.
2856 if (!is_rmap_spte(spte)) {
2861 sp = page_header(__pa(iterator.sptep));
2862 if (!is_last_spte(spte, sp->role.level))
2866 * Check if it is a spurious fault caused by TLB lazily flushed.
2868 * Need not check the access of upper level table entries since
2869 * they are always ACC_ALL.
2871 if (is_writable_pte(spte)) {
2877 * Currently, to simplify the code, only the spte write-protected
2878 * by dirty-log can be fast fixed.
2880 if (!spte_is_locklessly_modifiable(spte))
2884 * Do not fix write-permission on the large spte since we only dirty
2885 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2886 * that means other pages are missed if its slot is dirty-logged.
2888 * Instead, we let the slow page fault path create a normal spte to
2891 * See the comments in kvm_arch_commit_memory_region().
2893 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2897 * Currently, fast page fault only works for direct mapping since
2898 * the gfn is not stable for indirect shadow page.
2899 * See Documentation/virtual/kvm/locking.txt to get more detail.
2901 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2903 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2905 walk_shadow_page_lockless_end(vcpu);
2910 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2911 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2912 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2914 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2915 gfn_t gfn, bool prefault)
2921 unsigned long mmu_seq;
2922 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2924 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2925 if (likely(!force_pt_level)) {
2926 level = mapping_level(vcpu, gfn);
2928 * This path builds a PAE pagetable - so we can map
2929 * 2mb pages at maximum. Therefore check if the level
2930 * is larger than that.
2932 if (level > PT_DIRECTORY_LEVEL)
2933 level = PT_DIRECTORY_LEVEL;
2935 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2937 level = PT_PAGE_TABLE_LEVEL;
2939 if (fast_page_fault(vcpu, v, level, error_code))
2942 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2945 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2948 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2951 spin_lock(&vcpu->kvm->mmu_lock);
2952 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2954 make_mmu_pages_available(vcpu);
2955 if (likely(!force_pt_level))
2956 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2957 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2959 spin_unlock(&vcpu->kvm->mmu_lock);
2965 spin_unlock(&vcpu->kvm->mmu_lock);
2966 kvm_release_pfn_clean(pfn);
2971 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2974 struct kvm_mmu_page *sp;
2975 LIST_HEAD(invalid_list);
2977 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2980 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2981 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2982 vcpu->arch.mmu.direct_map)) {
2983 hpa_t root = vcpu->arch.mmu.root_hpa;
2985 spin_lock(&vcpu->kvm->mmu_lock);
2986 sp = page_header(root);
2988 if (!sp->root_count && sp->role.invalid) {
2989 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2990 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2992 spin_unlock(&vcpu->kvm->mmu_lock);
2993 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2997 spin_lock(&vcpu->kvm->mmu_lock);
2998 for (i = 0; i < 4; ++i) {
2999 hpa_t root = vcpu->arch.mmu.pae_root[i];
3002 root &= PT64_BASE_ADDR_MASK;
3003 sp = page_header(root);
3005 if (!sp->root_count && sp->role.invalid)
3006 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3009 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3011 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3012 spin_unlock(&vcpu->kvm->mmu_lock);
3013 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3016 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3020 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3021 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3028 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3030 struct kvm_mmu_page *sp;
3033 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3034 spin_lock(&vcpu->kvm->mmu_lock);
3035 make_mmu_pages_available(vcpu);
3036 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3039 spin_unlock(&vcpu->kvm->mmu_lock);
3040 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3041 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3042 for (i = 0; i < 4; ++i) {
3043 hpa_t root = vcpu->arch.mmu.pae_root[i];
3045 ASSERT(!VALID_PAGE(root));
3046 spin_lock(&vcpu->kvm->mmu_lock);
3047 make_mmu_pages_available(vcpu);
3048 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3050 PT32_ROOT_LEVEL, 1, ACC_ALL,
3052 root = __pa(sp->spt);
3054 spin_unlock(&vcpu->kvm->mmu_lock);
3055 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3057 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3064 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3066 struct kvm_mmu_page *sp;
3071 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3073 if (mmu_check_root(vcpu, root_gfn))
3077 * Do we shadow a long mode page table? If so we need to
3078 * write-protect the guests page table root.
3080 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3081 hpa_t root = vcpu->arch.mmu.root_hpa;
3083 ASSERT(!VALID_PAGE(root));
3085 spin_lock(&vcpu->kvm->mmu_lock);
3086 make_mmu_pages_available(vcpu);
3087 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3089 root = __pa(sp->spt);
3091 spin_unlock(&vcpu->kvm->mmu_lock);
3092 vcpu->arch.mmu.root_hpa = root;
3097 * We shadow a 32 bit page table. This may be a legacy 2-level
3098 * or a PAE 3-level page table. In either case we need to be aware that
3099 * the shadow page table may be a PAE or a long mode page table.
3101 pm_mask = PT_PRESENT_MASK;
3102 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3103 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3105 for (i = 0; i < 4; ++i) {
3106 hpa_t root = vcpu->arch.mmu.pae_root[i];
3108 ASSERT(!VALID_PAGE(root));
3109 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3110 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3111 if (!is_present_gpte(pdptr)) {
3112 vcpu->arch.mmu.pae_root[i] = 0;
3115 root_gfn = pdptr >> PAGE_SHIFT;
3116 if (mmu_check_root(vcpu, root_gfn))
3119 spin_lock(&vcpu->kvm->mmu_lock);
3120 make_mmu_pages_available(vcpu);
3121 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3124 root = __pa(sp->spt);
3126 spin_unlock(&vcpu->kvm->mmu_lock);
3128 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3130 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3133 * If we shadow a 32 bit page table with a long mode page
3134 * table we enter this path.
3136 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3137 if (vcpu->arch.mmu.lm_root == NULL) {
3139 * The additional page necessary for this is only
3140 * allocated on demand.
3145 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3146 if (lm_root == NULL)
3149 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3151 vcpu->arch.mmu.lm_root = lm_root;
3154 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3160 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3162 if (vcpu->arch.mmu.direct_map)
3163 return mmu_alloc_direct_roots(vcpu);
3165 return mmu_alloc_shadow_roots(vcpu);
3168 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3171 struct kvm_mmu_page *sp;
3173 if (vcpu->arch.mmu.direct_map)
3176 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3179 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3180 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3181 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3182 hpa_t root = vcpu->arch.mmu.root_hpa;
3183 sp = page_header(root);
3184 mmu_sync_children(vcpu, sp);
3185 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3188 for (i = 0; i < 4; ++i) {
3189 hpa_t root = vcpu->arch.mmu.pae_root[i];
3191 if (root && VALID_PAGE(root)) {
3192 root &= PT64_BASE_ADDR_MASK;
3193 sp = page_header(root);
3194 mmu_sync_children(vcpu, sp);
3197 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3200 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3202 spin_lock(&vcpu->kvm->mmu_lock);
3203 mmu_sync_roots(vcpu);
3204 spin_unlock(&vcpu->kvm->mmu_lock);
3206 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3208 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3209 u32 access, struct x86_exception *exception)
3212 exception->error_code = 0;
3216 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3218 struct x86_exception *exception)
3221 exception->error_code = 0;
3222 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3225 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3228 return vcpu_match_mmio_gpa(vcpu, addr);
3230 return vcpu_match_mmio_gva(vcpu, addr);
3235 * On direct hosts, the last spte is only allows two states
3236 * for mmio page fault:
3237 * - It is the mmio spte
3238 * - It is zapped or it is being zapped.
3240 * This function completely checks the spte when the last spte
3241 * is not the mmio spte.
3243 static bool check_direct_spte_mmio_pf(u64 spte)
3245 return __check_direct_spte_mmio_pf(spte);
3248 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3250 struct kvm_shadow_walk_iterator iterator;
3253 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3256 walk_shadow_page_lockless_begin(vcpu);
3257 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3258 if (!is_shadow_present_pte(spte))
3260 walk_shadow_page_lockless_end(vcpu);
3265 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3269 if (quickly_check_mmio_pf(vcpu, addr, direct))
3270 return RET_MMIO_PF_EMULATE;
3272 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3274 if (is_mmio_spte(spte)) {
3275 gfn_t gfn = get_mmio_spte_gfn(spte);
3276 unsigned access = get_mmio_spte_access(spte);
3278 if (!check_mmio_spte(vcpu->kvm, spte))
3279 return RET_MMIO_PF_INVALID;
3284 trace_handle_mmio_page_fault(addr, gfn, access);
3285 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3286 return RET_MMIO_PF_EMULATE;
3290 * It's ok if the gva is remapped by other cpus on shadow guest,
3291 * it's a BUG if the gfn is not a mmio page.
3293 if (direct && !check_direct_spte_mmio_pf(spte))
3294 return RET_MMIO_PF_BUG;
3297 * If the page table is zapped by other cpus, let CPU fault again on
3300 return RET_MMIO_PF_RETRY;
3302 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3304 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3305 u32 error_code, bool direct)
3309 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3310 WARN_ON(ret == RET_MMIO_PF_BUG);
3314 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3315 u32 error_code, bool prefault)
3320 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3322 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3323 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3325 if (likely(r != RET_MMIO_PF_INVALID))
3329 r = mmu_topup_memory_caches(vcpu);
3334 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3336 gfn = gva >> PAGE_SHIFT;
3338 return nonpaging_map(vcpu, gva & PAGE_MASK,
3339 error_code, gfn, prefault);
3342 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3344 struct kvm_arch_async_pf arch;
3346 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3348 arch.direct_map = vcpu->arch.mmu.direct_map;
3349 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3351 return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch);
3354 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3356 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3357 kvm_event_needs_reinjection(vcpu)))
3360 return kvm_x86_ops->interrupt_allowed(vcpu);
3363 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3364 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3368 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3371 return false; /* *pfn has correct page already */
3373 if (!prefault && can_do_async_pf(vcpu)) {
3374 trace_kvm_try_async_get_page(gva, gfn);
3375 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3376 trace_kvm_async_pf_doublefault(gva, gfn);
3377 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3379 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3383 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3388 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3395 gfn_t gfn = gpa >> PAGE_SHIFT;
3396 unsigned long mmu_seq;
3397 int write = error_code & PFERR_WRITE_MASK;
3401 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3403 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3404 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3406 if (likely(r != RET_MMIO_PF_INVALID))
3410 r = mmu_topup_memory_caches(vcpu);
3414 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3415 if (likely(!force_pt_level)) {
3416 level = mapping_level(vcpu, gfn);
3417 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3419 level = PT_PAGE_TABLE_LEVEL;
3421 if (fast_page_fault(vcpu, gpa, level, error_code))
3424 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3427 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3430 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3433 spin_lock(&vcpu->kvm->mmu_lock);
3434 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3436 make_mmu_pages_available(vcpu);
3437 if (likely(!force_pt_level))
3438 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3439 r = __direct_map(vcpu, gpa, write, map_writable,
3440 level, gfn, pfn, prefault);
3441 spin_unlock(&vcpu->kvm->mmu_lock);
3446 spin_unlock(&vcpu->kvm->mmu_lock);
3447 kvm_release_pfn_clean(pfn);
3451 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3452 struct kvm_mmu *context)
3454 context->page_fault = nonpaging_page_fault;
3455 context->gva_to_gpa = nonpaging_gva_to_gpa;
3456 context->sync_page = nonpaging_sync_page;
3457 context->invlpg = nonpaging_invlpg;
3458 context->update_pte = nonpaging_update_pte;
3459 context->root_level = 0;
3460 context->shadow_root_level = PT32E_ROOT_LEVEL;
3461 context->root_hpa = INVALID_PAGE;
3462 context->direct_map = true;
3463 context->nx = false;
3466 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3468 mmu_free_roots(vcpu);
3471 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3473 return kvm_read_cr3(vcpu);
3476 static void inject_page_fault(struct kvm_vcpu *vcpu,
3477 struct x86_exception *fault)
3479 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3482 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3483 unsigned access, int *nr_present)
3485 if (unlikely(is_mmio_spte(*sptep))) {
3486 if (gfn != get_mmio_spte_gfn(*sptep)) {
3487 mmu_spte_clear_no_track(sptep);
3492 mark_mmio_spte(kvm, sptep, gfn, access);
3499 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3504 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3505 return mmu->last_pte_bitmap & (1 << index);
3508 #define PTTYPE_EPT 18 /* arbitrary */
3509 #define PTTYPE PTTYPE_EPT
3510 #include "paging_tmpl.h"
3514 #include "paging_tmpl.h"
3518 #include "paging_tmpl.h"
3521 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3522 struct kvm_mmu *context)
3524 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3525 u64 exb_bit_rsvd = 0;
3526 u64 gbpages_bit_rsvd = 0;
3527 u64 nonleaf_bit8_rsvd = 0;
3529 context->bad_mt_xwr = 0;
3532 exb_bit_rsvd = rsvd_bits(63, 63);
3533 if (!guest_cpuid_has_gbpages(vcpu))
3534 gbpages_bit_rsvd = rsvd_bits(7, 7);
3537 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3538 * leaf entries) on AMD CPUs only.
3540 if (guest_cpuid_is_amd(vcpu))
3541 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3543 switch (context->root_level) {
3544 case PT32_ROOT_LEVEL:
3545 /* no rsvd bits for 2 level 4K page table entries */
3546 context->rsvd_bits_mask[0][1] = 0;
3547 context->rsvd_bits_mask[0][0] = 0;
3548 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3550 if (!is_pse(vcpu)) {
3551 context->rsvd_bits_mask[1][1] = 0;
3555 if (is_cpuid_PSE36())
3556 /* 36bits PSE 4MB page */
3557 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3559 /* 32 bits PSE 4MB page */
3560 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3562 case PT32E_ROOT_LEVEL:
3563 context->rsvd_bits_mask[0][2] =
3564 rsvd_bits(maxphyaddr, 63) |
3565 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3566 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3567 rsvd_bits(maxphyaddr, 62); /* PDE */
3568 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3569 rsvd_bits(maxphyaddr, 62); /* PTE */
3570 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3571 rsvd_bits(maxphyaddr, 62) |
3572 rsvd_bits(13, 20); /* large page */
3573 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3575 case PT64_ROOT_LEVEL:
3576 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3577 nonleaf_bit8_rsvd | rsvd_bits(7, 7) | rsvd_bits(maxphyaddr, 51);
3578 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3579 nonleaf_bit8_rsvd | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);
3580 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3581 rsvd_bits(maxphyaddr, 51);
3582 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3583 rsvd_bits(maxphyaddr, 51);
3584 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3585 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3586 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3588 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3589 rsvd_bits(maxphyaddr, 51) |
3590 rsvd_bits(13, 20); /* large page */
3591 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3596 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3597 struct kvm_mmu *context, bool execonly)
3599 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3602 context->rsvd_bits_mask[0][3] =
3603 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3604 context->rsvd_bits_mask[0][2] =
3605 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3606 context->rsvd_bits_mask[0][1] =
3607 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3608 context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3611 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3612 context->rsvd_bits_mask[1][2] =
3613 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3614 context->rsvd_bits_mask[1][1] =
3615 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3616 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3618 for (pte = 0; pte < 64; pte++) {
3619 int rwx_bits = pte & 7;
3621 if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||
3622 rwx_bits == 0x2 || rwx_bits == 0x6 ||
3623 (rwx_bits == 0x4 && !execonly))
3624 context->bad_mt_xwr |= (1ull << pte);
3628 void update_permission_bitmask(struct kvm_vcpu *vcpu,
3629 struct kvm_mmu *mmu, bool ept)
3631 unsigned bit, byte, pfec;
3633 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3635 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3636 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3637 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3640 wf = pfec & PFERR_WRITE_MASK;
3641 uf = pfec & PFERR_USER_MASK;
3642 ff = pfec & PFERR_FETCH_MASK;
3644 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3645 * subject to SMAP restrictions, and cleared otherwise. The
3646 * bit is only meaningful if the SMAP bit is set in CR4.
3648 smapf = !(pfec & PFERR_RSVD_MASK);
3649 for (bit = 0; bit < 8; ++bit) {
3650 x = bit & ACC_EXEC_MASK;
3651 w = bit & ACC_WRITE_MASK;
3652 u = bit & ACC_USER_MASK;
3655 /* Not really needed: !nx will cause pte.nx to fault */
3657 /* Allow supervisor writes if !cr0.wp */
3658 w |= !is_write_protection(vcpu) && !uf;
3659 /* Disallow supervisor fetches of user code if cr4.smep */
3660 x &= !(cr4_smep && u && !uf);
3663 * SMAP:kernel-mode data accesses from user-mode
3664 * mappings should fault. A fault is considered
3665 * as a SMAP violation if all of the following
3666 * conditions are ture:
3667 * - X86_CR4_SMAP is set in CR4
3668 * - An user page is accessed
3669 * - Page fault in kernel mode
3670 * - if CPL = 3 or X86_EFLAGS_AC is clear
3672 * Here, we cover the first three conditions.
3673 * The fourth is computed dynamically in
3674 * permission_fault() and is in smapf.
3676 * Also, SMAP does not affect instruction
3677 * fetches, add the !ff check here to make it
3680 smap = cr4_smap && u && !uf && !ff;
3682 /* Not really needed: no U/S accesses on ept */
3685 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3687 map |= fault << bit;
3689 mmu->permissions[byte] = map;
3693 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3696 unsigned level, root_level = mmu->root_level;
3697 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3699 if (root_level == PT32E_ROOT_LEVEL)
3701 /* PT_PAGE_TABLE_LEVEL always terminates */
3702 map = 1 | (1 << ps_set_index);
3703 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3704 if (level <= PT_PDPE_LEVEL
3705 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3706 map |= 1 << (ps_set_index | (level - 1));
3708 mmu->last_pte_bitmap = map;
3711 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3712 struct kvm_mmu *context,
3715 context->nx = is_nx(vcpu);
3716 context->root_level = level;
3718 reset_rsvds_bits_mask(vcpu, context);
3719 update_permission_bitmask(vcpu, context, false);
3720 update_last_pte_bitmap(vcpu, context);
3722 ASSERT(is_pae(vcpu));
3723 context->page_fault = paging64_page_fault;
3724 context->gva_to_gpa = paging64_gva_to_gpa;
3725 context->sync_page = paging64_sync_page;
3726 context->invlpg = paging64_invlpg;
3727 context->update_pte = paging64_update_pte;
3728 context->shadow_root_level = level;
3729 context->root_hpa = INVALID_PAGE;
3730 context->direct_map = false;
3733 static void paging64_init_context(struct kvm_vcpu *vcpu,
3734 struct kvm_mmu *context)
3736 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3739 static void paging32_init_context(struct kvm_vcpu *vcpu,
3740 struct kvm_mmu *context)
3742 context->nx = false;
3743 context->root_level = PT32_ROOT_LEVEL;
3745 reset_rsvds_bits_mask(vcpu, context);
3746 update_permission_bitmask(vcpu, context, false);
3747 update_last_pte_bitmap(vcpu, context);
3749 context->page_fault = paging32_page_fault;
3750 context->gva_to_gpa = paging32_gva_to_gpa;
3751 context->sync_page = paging32_sync_page;
3752 context->invlpg = paging32_invlpg;
3753 context->update_pte = paging32_update_pte;
3754 context->shadow_root_level = PT32E_ROOT_LEVEL;
3755 context->root_hpa = INVALID_PAGE;
3756 context->direct_map = false;
3759 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3760 struct kvm_mmu *context)
3762 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3765 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3767 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3769 context->base_role.word = 0;
3770 context->page_fault = tdp_page_fault;
3771 context->sync_page = nonpaging_sync_page;
3772 context->invlpg = nonpaging_invlpg;
3773 context->update_pte = nonpaging_update_pte;
3774 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3775 context->root_hpa = INVALID_PAGE;
3776 context->direct_map = true;
3777 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3778 context->get_cr3 = get_cr3;
3779 context->get_pdptr = kvm_pdptr_read;
3780 context->inject_page_fault = kvm_inject_page_fault;
3782 if (!is_paging(vcpu)) {
3783 context->nx = false;
3784 context->gva_to_gpa = nonpaging_gva_to_gpa;
3785 context->root_level = 0;
3786 } else if (is_long_mode(vcpu)) {
3787 context->nx = is_nx(vcpu);
3788 context->root_level = PT64_ROOT_LEVEL;
3789 reset_rsvds_bits_mask(vcpu, context);
3790 context->gva_to_gpa = paging64_gva_to_gpa;
3791 } else if (is_pae(vcpu)) {
3792 context->nx = is_nx(vcpu);
3793 context->root_level = PT32E_ROOT_LEVEL;
3794 reset_rsvds_bits_mask(vcpu, context);
3795 context->gva_to_gpa = paging64_gva_to_gpa;
3797 context->nx = false;
3798 context->root_level = PT32_ROOT_LEVEL;
3799 reset_rsvds_bits_mask(vcpu, context);
3800 context->gva_to_gpa = paging32_gva_to_gpa;
3803 update_permission_bitmask(vcpu, context, false);
3804 update_last_pte_bitmap(vcpu, context);
3807 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3809 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3811 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3813 if (!is_paging(vcpu))
3814 nonpaging_init_context(vcpu, context);
3815 else if (is_long_mode(vcpu))
3816 paging64_init_context(vcpu, context);
3817 else if (is_pae(vcpu))
3818 paging32E_init_context(vcpu, context);
3820 paging32_init_context(vcpu, context);
3822 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3823 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3824 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3825 vcpu->arch.mmu.base_role.smep_andnot_wp
3826 = smep && !is_write_protection(vcpu);
3828 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3830 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
3834 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3836 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3839 context->page_fault = ept_page_fault;
3840 context->gva_to_gpa = ept_gva_to_gpa;
3841 context->sync_page = ept_sync_page;
3842 context->invlpg = ept_invlpg;
3843 context->update_pte = ept_update_pte;
3844 context->root_level = context->shadow_root_level;
3845 context->root_hpa = INVALID_PAGE;
3846 context->direct_map = false;
3848 update_permission_bitmask(vcpu, context, true);
3849 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
3851 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
3853 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
3855 kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3856 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3857 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3858 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3859 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3862 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3864 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3866 g_context->get_cr3 = get_cr3;
3867 g_context->get_pdptr = kvm_pdptr_read;
3868 g_context->inject_page_fault = kvm_inject_page_fault;
3871 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3872 * translation of l2_gpa to l1_gpa addresses is done using the
3873 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3874 * functions between mmu and nested_mmu are swapped.
3876 if (!is_paging(vcpu)) {
3877 g_context->nx = false;
3878 g_context->root_level = 0;
3879 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3880 } else if (is_long_mode(vcpu)) {
3881 g_context->nx = is_nx(vcpu);
3882 g_context->root_level = PT64_ROOT_LEVEL;
3883 reset_rsvds_bits_mask(vcpu, g_context);
3884 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3885 } else if (is_pae(vcpu)) {
3886 g_context->nx = is_nx(vcpu);
3887 g_context->root_level = PT32E_ROOT_LEVEL;
3888 reset_rsvds_bits_mask(vcpu, g_context);
3889 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3891 g_context->nx = false;
3892 g_context->root_level = PT32_ROOT_LEVEL;
3893 reset_rsvds_bits_mask(vcpu, g_context);
3894 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3897 update_permission_bitmask(vcpu, g_context, false);
3898 update_last_pte_bitmap(vcpu, g_context);
3901 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
3903 if (mmu_is_nested(vcpu))
3904 return init_kvm_nested_mmu(vcpu);
3905 else if (tdp_enabled)
3906 return init_kvm_tdp_mmu(vcpu);
3908 return init_kvm_softmmu(vcpu);
3911 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3915 kvm_mmu_unload(vcpu);
3918 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3920 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3924 r = mmu_topup_memory_caches(vcpu);
3927 r = mmu_alloc_roots(vcpu);
3928 kvm_mmu_sync_roots(vcpu);
3931 /* set_cr3() should ensure TLB has been flushed */
3932 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3936 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3938 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3940 mmu_free_roots(vcpu);
3941 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3943 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3945 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3946 struct kvm_mmu_page *sp, u64 *spte,
3949 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3950 ++vcpu->kvm->stat.mmu_pde_zapped;
3954 ++vcpu->kvm->stat.mmu_pte_updated;
3955 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3958 static bool need_remote_flush(u64 old, u64 new)
3960 if (!is_shadow_present_pte(old))
3962 if (!is_shadow_present_pte(new))
3964 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3966 old ^= shadow_nx_mask;
3967 new ^= shadow_nx_mask;
3968 return (old & ~new & PT64_PERM_MASK) != 0;
3971 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3972 bool remote_flush, bool local_flush)
3978 kvm_flush_remote_tlbs(vcpu->kvm);
3979 else if (local_flush)
3980 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3983 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3984 const u8 *new, int *bytes)
3990 * Assume that the pte write on a page table of the same type
3991 * as the current vcpu paging mode since we update the sptes only
3992 * when they have the same mode.
3994 if (is_pae(vcpu) && *bytes == 4) {
3995 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3998 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
4001 new = (const u8 *)&gentry;
4006 gentry = *(const u32 *)new;
4009 gentry = *(const u64 *)new;
4020 * If we're seeing too many writes to a page, it may no longer be a page table,
4021 * or we may be forking, in which case it is better to unmap the page.
4023 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4026 * Skip write-flooding detected for the sp whose level is 1, because
4027 * it can become unsync, then the guest page is not write-protected.
4029 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4032 return ++sp->write_flooding_count >= 3;
4036 * Misaligned accesses are too much trouble to fix up; also, they usually
4037 * indicate a page is not used as a page table.
4039 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4042 unsigned offset, pte_size, misaligned;
4044 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4045 gpa, bytes, sp->role.word);
4047 offset = offset_in_page(gpa);
4048 pte_size = sp->role.cr4_pae ? 8 : 4;
4051 * Sometimes, the OS only writes the last one bytes to update status
4052 * bits, for example, in linux, andb instruction is used in clear_bit().
4054 if (!(offset & (pte_size - 1)) && bytes == 1)
4057 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4058 misaligned |= bytes < 4;
4063 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4065 unsigned page_offset, quadrant;
4069 page_offset = offset_in_page(gpa);
4070 level = sp->role.level;
4072 if (!sp->role.cr4_pae) {
4073 page_offset <<= 1; /* 32->64 */
4075 * A 32-bit pde maps 4MB while the shadow pdes map
4076 * only 2MB. So we need to double the offset again
4077 * and zap two pdes instead of one.
4079 if (level == PT32_ROOT_LEVEL) {
4080 page_offset &= ~7; /* kill rounding error */
4084 quadrant = page_offset >> PAGE_SHIFT;
4085 page_offset &= ~PAGE_MASK;
4086 if (quadrant != sp->role.quadrant)
4090 spte = &sp->spt[page_offset / sizeof(*spte)];
4094 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4095 const u8 *new, int bytes)
4097 gfn_t gfn = gpa >> PAGE_SHIFT;
4098 union kvm_mmu_page_role mask = { .word = 0 };
4099 struct kvm_mmu_page *sp;
4100 LIST_HEAD(invalid_list);
4101 u64 entry, gentry, *spte;
4103 bool remote_flush, local_flush, zap_page;
4106 * If we don't have indirect shadow pages, it means no page is
4107 * write-protected, so we can exit simply.
4109 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4112 zap_page = remote_flush = local_flush = false;
4114 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4116 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4119 * No need to care whether allocation memory is successful
4120 * or not since pte prefetch is skiped if it does not have
4121 * enough objects in the cache.
4123 mmu_topup_memory_caches(vcpu);
4125 spin_lock(&vcpu->kvm->mmu_lock);
4126 ++vcpu->kvm->stat.mmu_pte_write;
4127 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4129 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
4130 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4131 if (detect_write_misaligned(sp, gpa, bytes) ||
4132 detect_write_flooding(sp)) {
4133 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4135 ++vcpu->kvm->stat.mmu_flooded;
4139 spte = get_written_sptes(sp, gpa, &npte);
4146 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4148 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4149 & mask.word) && rmap_can_add(vcpu))
4150 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4151 if (need_remote_flush(entry, *spte))
4152 remote_flush = true;
4156 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4157 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4158 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4159 spin_unlock(&vcpu->kvm->mmu_lock);
4162 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4167 if (vcpu->arch.mmu.direct_map)
4170 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4172 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4176 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4178 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4180 LIST_HEAD(invalid_list);
4182 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4185 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4186 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4189 ++vcpu->kvm->stat.mmu_recycled;
4191 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4194 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4196 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4197 return vcpu_match_mmio_gpa(vcpu, addr);
4199 return vcpu_match_mmio_gva(vcpu, addr);
4202 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4203 void *insn, int insn_len)
4205 int r, emulation_type = EMULTYPE_RETRY;
4206 enum emulation_result er;
4208 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4217 if (is_mmio_page_fault(vcpu, cr2))
4220 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4225 case EMULATE_USER_EXIT:
4226 ++vcpu->stat.mmio_exits;
4236 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4238 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4240 vcpu->arch.mmu.invlpg(vcpu, gva);
4241 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4242 ++vcpu->stat.invlpg;
4244 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4246 void kvm_enable_tdp(void)
4250 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4252 void kvm_disable_tdp(void)
4254 tdp_enabled = false;
4256 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4258 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4260 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4261 if (vcpu->arch.mmu.lm_root != NULL)
4262 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4265 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4273 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4274 * Therefore we need to allocate shadow page tables in the first
4275 * 4GB of memory, which happens to fit the DMA32 zone.
4277 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4281 vcpu->arch.mmu.pae_root = page_address(page);
4282 for (i = 0; i < 4; ++i)
4283 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4288 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4292 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4293 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4294 vcpu->arch.mmu.translate_gpa = translate_gpa;
4295 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4297 return alloc_mmu_pages(vcpu);
4300 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4303 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4308 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4310 struct kvm_memory_slot *memslot;
4314 memslot = id_to_memslot(kvm->memslots, slot);
4315 last_gfn = memslot->base_gfn + memslot->npages - 1;
4317 spin_lock(&kvm->mmu_lock);
4319 for (i = PT_PAGE_TABLE_LEVEL;
4320 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4321 unsigned long *rmapp;
4322 unsigned long last_index, index;
4324 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4325 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4327 for (index = 0; index <= last_index; ++index, ++rmapp) {
4329 __rmap_write_protect(kvm, rmapp, false);
4331 if (need_resched() || spin_needbreak(&kvm->mmu_lock))
4332 cond_resched_lock(&kvm->mmu_lock);
4336 spin_unlock(&kvm->mmu_lock);
4339 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4340 * which do tlb flush out of mmu-lock should be serialized by
4341 * kvm->slots_lock otherwise tlb flush would be missed.
4343 lockdep_assert_held(&kvm->slots_lock);
4346 * We can flush all the TLBs out of the mmu lock without TLB
4347 * corruption since we just change the spte from writable to
4348 * readonly so that we only need to care the case of changing
4349 * spte from present to present (changing the spte from present
4350 * to nonpresent will flush all the TLBs immediately), in other
4351 * words, the only case we care is mmu_spte_update() where we
4352 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4353 * instead of PT_WRITABLE_MASK, that means it does not depend
4354 * on PT_WRITABLE_MASK anymore.
4356 kvm_flush_remote_tlbs(kvm);
4359 #define BATCH_ZAP_PAGES 10
4360 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4362 struct kvm_mmu_page *sp, *node;
4366 list_for_each_entry_safe_reverse(sp, node,
4367 &kvm->arch.active_mmu_pages, link) {
4371 * No obsolete page exists before new created page since
4372 * active_mmu_pages is the FIFO list.
4374 if (!is_obsolete_sp(kvm, sp))
4378 * Since we are reversely walking the list and the invalid
4379 * list will be moved to the head, skip the invalid page
4380 * can help us to avoid the infinity list walking.
4382 if (sp->role.invalid)
4386 * Need not flush tlb since we only zap the sp with invalid
4387 * generation number.
4389 if (batch >= BATCH_ZAP_PAGES &&
4390 cond_resched_lock(&kvm->mmu_lock)) {
4395 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4396 &kvm->arch.zapped_obsolete_pages);
4404 * Should flush tlb before free page tables since lockless-walking
4405 * may use the pages.
4407 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4411 * Fast invalidate all shadow pages and use lock-break technique
4412 * to zap obsolete pages.
4414 * It's required when memslot is being deleted or VM is being
4415 * destroyed, in these cases, we should ensure that KVM MMU does
4416 * not use any resource of the being-deleted slot or all slots
4417 * after calling the function.
4419 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4421 spin_lock(&kvm->mmu_lock);
4422 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4423 kvm->arch.mmu_valid_gen++;
4426 * Notify all vcpus to reload its shadow page table
4427 * and flush TLB. Then all vcpus will switch to new
4428 * shadow page table with the new mmu_valid_gen.
4430 * Note: we should do this under the protection of
4431 * mmu-lock, otherwise, vcpu would purge shadow page
4432 * but miss tlb flush.
4434 kvm_reload_remote_mmus(kvm);
4436 kvm_zap_obsolete_pages(kvm);
4437 spin_unlock(&kvm->mmu_lock);
4440 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4442 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4445 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
4448 * The very rare case: if the generation-number is round,
4449 * zap all shadow pages.
4451 if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
4452 printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
4453 kvm_mmu_invalidate_zap_all_pages(kvm);
4457 static unsigned long
4458 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4461 int nr_to_scan = sc->nr_to_scan;
4462 unsigned long freed = 0;
4464 spin_lock(&kvm_lock);
4466 list_for_each_entry(kvm, &vm_list, vm_list) {
4468 LIST_HEAD(invalid_list);
4471 * Never scan more than sc->nr_to_scan VM instances.
4472 * Will not hit this condition practically since we do not try
4473 * to shrink more than one VM and it is very unlikely to see
4474 * !n_used_mmu_pages so many times.
4479 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4480 * here. We may skip a VM instance errorneosly, but we do not
4481 * want to shrink a VM that only started to populate its MMU
4484 if (!kvm->arch.n_used_mmu_pages &&
4485 !kvm_has_zapped_obsolete_pages(kvm))
4488 idx = srcu_read_lock(&kvm->srcu);
4489 spin_lock(&kvm->mmu_lock);
4491 if (kvm_has_zapped_obsolete_pages(kvm)) {
4492 kvm_mmu_commit_zap_page(kvm,
4493 &kvm->arch.zapped_obsolete_pages);
4497 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4499 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4502 spin_unlock(&kvm->mmu_lock);
4503 srcu_read_unlock(&kvm->srcu, idx);
4506 * unfair on small ones
4507 * per-vm shrinkers cry out
4508 * sadness comes quickly
4510 list_move_tail(&kvm->vm_list, &vm_list);
4514 spin_unlock(&kvm_lock);
4518 static unsigned long
4519 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4521 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4524 static struct shrinker mmu_shrinker = {
4525 .count_objects = mmu_shrink_count,
4526 .scan_objects = mmu_shrink_scan,
4527 .seeks = DEFAULT_SEEKS * 10,
4530 static void mmu_destroy_caches(void)
4532 if (pte_list_desc_cache)
4533 kmem_cache_destroy(pte_list_desc_cache);
4534 if (mmu_page_header_cache)
4535 kmem_cache_destroy(mmu_page_header_cache);
4538 int kvm_mmu_module_init(void)
4540 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4541 sizeof(struct pte_list_desc),
4543 if (!pte_list_desc_cache)
4546 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4547 sizeof(struct kvm_mmu_page),
4549 if (!mmu_page_header_cache)
4552 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
4555 register_shrinker(&mmu_shrinker);
4560 mmu_destroy_caches();
4565 * Caculate mmu pages needed for kvm.
4567 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4569 unsigned int nr_mmu_pages;
4570 unsigned int nr_pages = 0;
4571 struct kvm_memslots *slots;
4572 struct kvm_memory_slot *memslot;
4574 slots = kvm_memslots(kvm);
4576 kvm_for_each_memslot(memslot, slots)
4577 nr_pages += memslot->npages;
4579 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4580 nr_mmu_pages = max(nr_mmu_pages,
4581 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4583 return nr_mmu_pages;
4586 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4588 struct kvm_shadow_walk_iterator iterator;
4592 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4595 walk_shadow_page_lockless_begin(vcpu);
4596 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4597 sptes[iterator.level-1] = spte;
4599 if (!is_shadow_present_pte(spte))
4602 walk_shadow_page_lockless_end(vcpu);
4606 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4608 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4612 kvm_mmu_unload(vcpu);
4613 free_mmu_pages(vcpu);
4614 mmu_free_memory_caches(vcpu);
4617 void kvm_mmu_module_exit(void)
4619 mmu_destroy_caches();
4620 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4621 unregister_shrinker(&mmu_shrinker);
4622 mmu_audit_disable();