2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
202 access &= ACC_WRITE_MASK | ACC_USER_MASK;
204 trace_mark_mmio_spte(sptep, gfn, access);
205 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
208 static bool is_mmio_spte(u64 spte)
210 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
213 static gfn_t get_mmio_spte_gfn(u64 spte)
215 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
218 static unsigned get_mmio_spte_access(u64 spte)
220 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
225 if (unlikely(is_noslot_pfn(pfn))) {
226 mark_mmio_spte(sptep, gfn, access);
233 static inline u64 rsvd_bits(int s, int e)
235 return ((1ULL << (e - s + 1)) - 1) << s;
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239 u64 dirty_mask, u64 nx_mask, u64 x_mask)
241 shadow_user_mask = user_mask;
242 shadow_accessed_mask = accessed_mask;
243 shadow_dirty_mask = dirty_mask;
244 shadow_nx_mask = nx_mask;
245 shadow_x_mask = x_mask;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu *vcpu)
256 return vcpu->arch.efer & EFER_NX;
259 static int is_shadow_present_pte(u64 pte)
261 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
264 static int is_large_pte(u64 pte)
266 return pte & PT_PAGE_SIZE_MASK;
269 static int is_dirty_gpte(unsigned long pte)
271 return pte & PT_DIRTY_MASK;
274 static int is_rmap_spte(u64 pte)
276 return is_shadow_present_pte(pte);
279 static int is_last_spte(u64 pte, int level)
281 if (level == PT_PAGE_TABLE_LEVEL)
283 if (is_large_pte(pte))
288 static pfn_t spte_to_pfn(u64 pte)
290 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
293 static gfn_t pse36_gfn_delta(u32 gpte)
295 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
297 return (gpte & PT32_DIR_PSE36_MASK) << shift;
301 static void __set_spte(u64 *sptep, u64 spte)
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
313 return xchg(sptep, spte);
316 static u64 __get_spte_lockless(u64 *sptep)
318 return ACCESS_ONCE(*sptep);
321 static bool __check_direct_spte_mmio_pf(u64 spte)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64 *sptep, u64 spte)
337 struct kvm_mmu_page *sp = page_header(__pa(sptep));
339 if (is_shadow_present_pte(spte))
342 /* Ensure the spte is completely set before we increase the count */
344 sp->clear_spte_count++;
347 static void __set_spte(u64 *sptep, u64 spte)
349 union split_spte *ssptep, sspte;
351 ssptep = (union split_spte *)sptep;
352 sspte = (union split_spte)spte;
354 ssptep->spte_high = sspte.spte_high;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep->spte_low = sspte.spte_low;
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
368 union split_spte *ssptep, sspte;
370 ssptep = (union split_spte *)sptep;
371 sspte = (union split_spte)spte;
373 ssptep->spte_low = sspte.spte_low;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep->spte_high = sspte.spte_high;
382 count_spte_clear(sptep, spte);
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
387 union split_spte *ssptep, sspte, orig;
389 ssptep = (union split_spte *)sptep;
390 sspte = (union split_spte)spte;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394 orig.spte_high = ssptep->spte_high;
395 ssptep->spte_high = sspte.spte_high;
396 count_spte_clear(sptep, spte);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64 __get_spte_lockless(u64 *sptep)
410 struct kvm_mmu_page *sp = page_header(__pa(sptep));
411 union split_spte spte, *orig = (union split_spte *)sptep;
415 count = sp->clear_spte_count;
418 spte.spte_low = orig->spte_low;
421 spte.spte_high = orig->spte_high;
424 if (unlikely(spte.spte_low != orig->spte_low ||
425 count != sp->clear_spte_count))
431 static bool __check_direct_spte_mmio_pf(u64 spte)
433 union split_spte sspte = (union split_spte)spte;
434 u32 high_mmio_mask = shadow_mmio_mask >> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte.spte_low == 0ull &&
442 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
449 static bool spte_is_locklessly_modifiable(u64 spte)
451 return !(~spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE));
454 static bool spte_has_volatile_bits(u64 spte)
457 * Always atomicly update spte if it can be updated
458 * out of mmu-lock, it can ensure dirty bit is not lost,
459 * also, it can help us to get a stable is_writable_pte()
460 * to ensure tlb flush is not missed.
462 if (spte_is_locklessly_modifiable(spte))
465 if (!shadow_accessed_mask)
468 if (!is_shadow_present_pte(spte))
471 if ((spte & shadow_accessed_mask) &&
472 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
478 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
480 return (old_spte & bit_mask) && !(new_spte & bit_mask);
483 /* Rules for using mmu_spte_set:
484 * Set the sptep from nonpresent to present.
485 * Note: the sptep being assigned *must* be either not present
486 * or in a state where the hardware will not attempt to update
489 static void mmu_spte_set(u64 *sptep, u64 new_spte)
491 WARN_ON(is_shadow_present_pte(*sptep));
492 __set_spte(sptep, new_spte);
495 /* Rules for using mmu_spte_update:
496 * Update the state bits, it means the mapped pfn is not changged.
498 * Whenever we overwrite a writable spte with a read-only one we
499 * should flush remote TLBs. Otherwise rmap_write_protect
500 * will find a read-only spte, even though the writable spte
501 * might be cached on a CPU's TLB, the return value indicates this
504 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 u64 old_spte = *sptep;
509 WARN_ON(!is_rmap_spte(new_spte));
511 if (!is_shadow_present_pte(old_spte)) {
512 mmu_spte_set(sptep, new_spte);
516 if (!spte_has_volatile_bits(old_spte))
517 __update_clear_spte_fast(sptep, new_spte);
519 old_spte = __update_clear_spte_slow(sptep, new_spte);
522 * For the spte updated out of mmu-lock is safe, since
523 * we always atomicly update it, see the comments in
524 * spte_has_volatile_bits().
526 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
529 if (!shadow_accessed_mask)
532 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
533 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
534 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
535 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
541 * Rules for using mmu_spte_clear_track_bits:
542 * It sets the sptep from present to nonpresent, and track the
543 * state bits, it is used to clear the last level sptep.
545 static int mmu_spte_clear_track_bits(u64 *sptep)
548 u64 old_spte = *sptep;
550 if (!spte_has_volatile_bits(old_spte))
551 __update_clear_spte_fast(sptep, 0ull);
553 old_spte = __update_clear_spte_slow(sptep, 0ull);
555 if (!is_rmap_spte(old_spte))
558 pfn = spte_to_pfn(old_spte);
561 * KVM does not hold the refcount of the page used by
562 * kvm mmu, before reclaiming the page, we should
563 * unmap it from mmu first.
565 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
567 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
568 kvm_set_pfn_accessed(pfn);
569 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
570 kvm_set_pfn_dirty(pfn);
575 * Rules for using mmu_spte_clear_no_track:
576 * Directly clear spte without caring the state bits of sptep,
577 * it is used to set the upper level spte.
579 static void mmu_spte_clear_no_track(u64 *sptep)
581 __update_clear_spte_fast(sptep, 0ull);
584 static u64 mmu_spte_get_lockless(u64 *sptep)
586 return __get_spte_lockless(sptep);
589 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
592 * Prevent page table teardown by making any free-er wait during
593 * kvm_flush_remote_tlbs() IPI to all active vcpus.
596 vcpu->mode = READING_SHADOW_PAGE_TABLES;
598 * Make sure a following spte read is not reordered ahead of the write
604 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
607 * Make sure the write to vcpu->mode is not reordered in front of
608 * reads to sptes. If it does, kvm_commit_zap_page() can see us
609 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
612 vcpu->mode = OUTSIDE_GUEST_MODE;
616 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
617 struct kmem_cache *base_cache, int min)
621 if (cache->nobjs >= min)
623 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
624 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
627 cache->objects[cache->nobjs++] = obj;
632 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
637 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
638 struct kmem_cache *cache)
641 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
644 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
649 if (cache->nobjs >= min)
651 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
652 page = (void *)__get_free_page(GFP_KERNEL);
655 cache->objects[cache->nobjs++] = page;
660 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
663 free_page((unsigned long)mc->objects[--mc->nobjs]);
666 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
670 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
671 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
674 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
677 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
678 mmu_page_header_cache, 4);
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
686 pte_list_desc_cache);
687 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
688 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
689 mmu_page_header_cache);
692 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
697 p = mc->objects[--mc->nobjs];
701 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
703 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
706 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
708 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
711 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
713 if (!sp->role.direct)
714 return sp->gfns[index];
716 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
719 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
722 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
724 sp->gfns[index] = gfn;
728 * Return the pointer to the large page information for a given gfn,
729 * handling slots that are not large page aligned.
731 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
732 struct kvm_memory_slot *slot,
737 idx = gfn_to_index(gfn, slot->base_gfn, level);
738 return &slot->arch.lpage_info[level - 2][idx];
741 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
743 struct kvm_memory_slot *slot;
744 struct kvm_lpage_info *linfo;
747 slot = gfn_to_memslot(kvm, gfn);
748 for (i = PT_DIRECTORY_LEVEL;
749 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
750 linfo = lpage_info_slot(gfn, slot, i);
751 linfo->write_count += 1;
753 kvm->arch.indirect_shadow_pages++;
756 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
758 struct kvm_memory_slot *slot;
759 struct kvm_lpage_info *linfo;
762 slot = gfn_to_memslot(kvm, gfn);
763 for (i = PT_DIRECTORY_LEVEL;
764 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
765 linfo = lpage_info_slot(gfn, slot, i);
766 linfo->write_count -= 1;
767 WARN_ON(linfo->write_count < 0);
769 kvm->arch.indirect_shadow_pages--;
772 static int has_wrprotected_page(struct kvm *kvm,
776 struct kvm_memory_slot *slot;
777 struct kvm_lpage_info *linfo;
779 slot = gfn_to_memslot(kvm, gfn);
781 linfo = lpage_info_slot(gfn, slot, level);
782 return linfo->write_count;
788 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
790 unsigned long page_size;
793 page_size = kvm_host_page_size(kvm, gfn);
795 for (i = PT_PAGE_TABLE_LEVEL;
796 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
797 if (page_size >= KVM_HPAGE_SIZE(i))
806 static struct kvm_memory_slot *
807 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
810 struct kvm_memory_slot *slot;
812 slot = gfn_to_memslot(vcpu->kvm, gfn);
813 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
814 (no_dirty_log && slot->dirty_bitmap))
820 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
822 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
825 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
827 int host_level, level, max_level;
829 host_level = host_mapping_level(vcpu->kvm, large_gfn);
831 if (host_level == PT_PAGE_TABLE_LEVEL)
834 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
835 kvm_x86_ops->get_lpage_level() : host_level;
837 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
838 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
845 * Pte mapping structures:
847 * If pte_list bit zero is zero, then pte_list point to the spte.
849 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850 * pte_list_desc containing more mappings.
852 * Returns the number of pte entries before the spte was added or zero if
853 * the spte was not added.
856 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
857 unsigned long *pte_list)
859 struct pte_list_desc *desc;
863 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
864 *pte_list = (unsigned long)spte;
865 } else if (!(*pte_list & 1)) {
866 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
867 desc = mmu_alloc_pte_list_desc(vcpu);
868 desc->sptes[0] = (u64 *)*pte_list;
869 desc->sptes[1] = spte;
870 *pte_list = (unsigned long)desc | 1;
873 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
874 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
875 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
877 count += PTE_LIST_EXT;
879 if (desc->sptes[PTE_LIST_EXT-1]) {
880 desc->more = mmu_alloc_pte_list_desc(vcpu);
883 for (i = 0; desc->sptes[i]; ++i)
885 desc->sptes[i] = spte;
891 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
892 int i, struct pte_list_desc *prev_desc)
896 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
898 desc->sptes[i] = desc->sptes[j];
899 desc->sptes[j] = NULL;
902 if (!prev_desc && !desc->more)
903 *pte_list = (unsigned long)desc->sptes[0];
906 prev_desc->more = desc->more;
908 *pte_list = (unsigned long)desc->more | 1;
909 mmu_free_pte_list_desc(desc);
912 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
914 struct pte_list_desc *desc;
915 struct pte_list_desc *prev_desc;
919 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
921 } else if (!(*pte_list & 1)) {
922 rmap_printk("pte_list_remove: %p 1->0\n", spte);
923 if ((u64 *)*pte_list != spte) {
924 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
929 rmap_printk("pte_list_remove: %p many->many\n", spte);
930 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
933 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
934 if (desc->sptes[i] == spte) {
935 pte_list_desc_remove_entry(pte_list,
943 pr_err("pte_list_remove: %p many->many\n", spte);
948 typedef void (*pte_list_walk_fn) (u64 *spte);
949 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
951 struct pte_list_desc *desc;
957 if (!(*pte_list & 1))
958 return fn((u64 *)*pte_list);
960 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
962 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
968 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
969 struct kvm_memory_slot *slot)
973 if (likely(level == PT_PAGE_TABLE_LEVEL))
974 return &slot->rmap[gfn - slot->base_gfn];
976 idx = gfn_to_index(gfn, slot->base_gfn, level);
977 return &slot->arch.rmap_pde[level - PT_DIRECTORY_LEVEL][idx];
981 * Take gfn and return the reverse mapping to it.
983 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
985 struct kvm_memory_slot *slot;
987 slot = gfn_to_memslot(kvm, gfn);
988 return __gfn_to_rmap(gfn, level, slot);
991 static bool rmap_can_add(struct kvm_vcpu *vcpu)
993 struct kvm_mmu_memory_cache *cache;
995 cache = &vcpu->arch.mmu_pte_list_desc_cache;
996 return mmu_memory_cache_free_objects(cache);
999 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1001 struct kvm_mmu_page *sp;
1002 unsigned long *rmapp;
1004 sp = page_header(__pa(spte));
1005 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1006 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1007 return pte_list_add(vcpu, spte, rmapp);
1010 static void rmap_remove(struct kvm *kvm, u64 *spte)
1012 struct kvm_mmu_page *sp;
1014 unsigned long *rmapp;
1016 sp = page_header(__pa(spte));
1017 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1018 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1019 pte_list_remove(spte, rmapp);
1023 * Used by the following functions to iterate through the sptes linked by a
1024 * rmap. All fields are private and not assumed to be used outside.
1026 struct rmap_iterator {
1027 /* private fields */
1028 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1029 int pos; /* index of the sptep */
1033 * Iteration must be started by this function. This should also be used after
1034 * removing/dropping sptes from the rmap link because in such cases the
1035 * information in the itererator may not be valid.
1037 * Returns sptep if found, NULL otherwise.
1039 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1049 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1051 return iter->desc->sptes[iter->pos];
1055 * Must be used with a valid iterator: e.g. after rmap_get_first().
1057 * Returns sptep if found, NULL otherwise.
1059 static u64 *rmap_get_next(struct rmap_iterator *iter)
1062 if (iter->pos < PTE_LIST_EXT - 1) {
1066 sptep = iter->desc->sptes[iter->pos];
1071 iter->desc = iter->desc->more;
1075 /* desc->sptes[0] cannot be NULL */
1076 return iter->desc->sptes[iter->pos];
1083 static void drop_spte(struct kvm *kvm, u64 *sptep)
1085 if (mmu_spte_clear_track_bits(sptep))
1086 rmap_remove(kvm, sptep);
1090 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1092 if (is_large_pte(*sptep)) {
1093 WARN_ON(page_header(__pa(sptep))->role.level ==
1094 PT_PAGE_TABLE_LEVEL);
1095 drop_spte(kvm, sptep);
1103 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1105 if (__drop_large_spte(vcpu->kvm, sptep))
1106 kvm_flush_remote_tlbs(vcpu->kvm);
1110 * Write-protect on the specified @sptep, @pt_protect indicates whether
1111 * spte writ-protection is caused by protecting shadow page table.
1112 * @flush indicates whether tlb need be flushed.
1114 * Note: write protection is difference between drity logging and spte
1116 * - for dirty logging, the spte can be set to writable at anytime if
1117 * its dirty bitmap is properly set.
1118 * - for spte protection, the spte can be writable only after unsync-ing
1121 * Return true if the spte is dropped.
1124 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1128 if (!is_writable_pte(spte) &&
1129 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1132 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1134 if (__drop_large_spte(kvm, sptep)) {
1140 spte &= ~SPTE_MMU_WRITEABLE;
1141 spte = spte & ~PT_WRITABLE_MASK;
1143 *flush |= mmu_spte_update(sptep, spte);
1147 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1148 int level, bool pt_protect)
1151 struct rmap_iterator iter;
1154 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1155 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1156 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1157 sptep = rmap_get_first(*rmapp, &iter);
1161 sptep = rmap_get_next(&iter);
1168 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1169 * @kvm: kvm instance
1170 * @slot: slot to protect
1171 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1172 * @mask: indicates which pages we should protect
1174 * Used when we do not need to care about huge page mappings: e.g. during dirty
1175 * logging we do not have any such mappings.
1177 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1178 struct kvm_memory_slot *slot,
1179 gfn_t gfn_offset, unsigned long mask)
1181 unsigned long *rmapp;
1184 rmapp = &slot->rmap[gfn_offset + __ffs(mask)];
1185 __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL, false);
1187 /* clear the first set bit */
1192 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1194 struct kvm_memory_slot *slot;
1195 unsigned long *rmapp;
1197 bool write_protected = false;
1199 slot = gfn_to_memslot(kvm, gfn);
1201 for (i = PT_PAGE_TABLE_LEVEL;
1202 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1203 rmapp = __gfn_to_rmap(gfn, i, slot);
1204 write_protected |= __rmap_write_protect(kvm, rmapp, i, true);
1207 return write_protected;
1210 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1211 struct kvm_memory_slot *slot, unsigned long data)
1214 struct rmap_iterator iter;
1215 int need_tlb_flush = 0;
1217 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1218 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1219 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1221 drop_spte(kvm, sptep);
1225 return need_tlb_flush;
1228 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1229 struct kvm_memory_slot *slot, unsigned long data)
1232 struct rmap_iterator iter;
1235 pte_t *ptep = (pte_t *)data;
1238 WARN_ON(pte_huge(*ptep));
1239 new_pfn = pte_pfn(*ptep);
1241 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1242 BUG_ON(!is_shadow_present_pte(*sptep));
1243 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1247 if (pte_write(*ptep)) {
1248 drop_spte(kvm, sptep);
1249 sptep = rmap_get_first(*rmapp, &iter);
1251 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1252 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1254 new_spte &= ~PT_WRITABLE_MASK;
1255 new_spte &= ~SPTE_HOST_WRITEABLE;
1256 new_spte &= ~shadow_accessed_mask;
1258 mmu_spte_clear_track_bits(sptep);
1259 mmu_spte_set(sptep, new_spte);
1260 sptep = rmap_get_next(&iter);
1265 kvm_flush_remote_tlbs(kvm);
1270 static int kvm_handle_hva_range(struct kvm *kvm,
1271 unsigned long start,
1274 int (*handler)(struct kvm *kvm,
1275 unsigned long *rmapp,
1276 struct kvm_memory_slot *slot,
1277 unsigned long data))
1281 struct kvm_memslots *slots;
1282 struct kvm_memory_slot *memslot;
1284 slots = kvm_memslots(kvm);
1286 kvm_for_each_memslot(memslot, slots) {
1287 unsigned long hva_start, hva_end;
1288 gfn_t gfn_start, gfn_end;
1290 hva_start = max(start, memslot->userspace_addr);
1291 hva_end = min(end, memslot->userspace_addr +
1292 (memslot->npages << PAGE_SHIFT));
1293 if (hva_start >= hva_end)
1296 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1297 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1299 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1300 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1302 for (j = PT_PAGE_TABLE_LEVEL;
1303 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1304 unsigned long idx, idx_end;
1305 unsigned long *rmapp;
1308 * {idx(page_j) | page_j intersects with
1309 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1311 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1312 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1314 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1316 for (; idx <= idx_end; ++idx)
1317 ret |= handler(kvm, rmapp++, memslot, data);
1324 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1326 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1327 struct kvm_memory_slot *slot,
1328 unsigned long data))
1330 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1333 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1335 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1338 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1340 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1343 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1345 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1348 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1349 struct kvm_memory_slot *slot, unsigned long data)
1352 struct rmap_iterator uninitialized_var(iter);
1356 * In case of absence of EPT Access and Dirty Bits supports,
1357 * emulate the accessed bit for EPT, by checking if this page has
1358 * an EPT mapping, and clearing it if it does. On the next access,
1359 * a new EPT mapping will be established.
1360 * This has some overhead, but not as much as the cost of swapping
1361 * out actively used pages or breaking up actively used hugepages.
1363 if (!shadow_accessed_mask) {
1364 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1368 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1369 sptep = rmap_get_next(&iter)) {
1370 BUG_ON(!is_shadow_present_pte(*sptep));
1372 if (*sptep & shadow_accessed_mask) {
1374 clear_bit((ffs(shadow_accessed_mask) - 1),
1375 (unsigned long *)sptep);
1379 /* @data has hva passed to kvm_age_hva(). */
1380 trace_kvm_age_page(data, slot, young);
1384 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1385 struct kvm_memory_slot *slot, unsigned long data)
1388 struct rmap_iterator iter;
1392 * If there's no access bit in the secondary pte set by the
1393 * hardware it's up to gup-fast/gup to set the access bit in
1394 * the primary pte or in the page structure.
1396 if (!shadow_accessed_mask)
1399 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1400 sptep = rmap_get_next(&iter)) {
1401 BUG_ON(!is_shadow_present_pte(*sptep));
1403 if (*sptep & shadow_accessed_mask) {
1412 #define RMAP_RECYCLE_THRESHOLD 1000
1414 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1416 unsigned long *rmapp;
1417 struct kvm_mmu_page *sp;
1419 sp = page_header(__pa(spte));
1421 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1423 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1424 kvm_flush_remote_tlbs(vcpu->kvm);
1427 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1429 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1432 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1434 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1438 static int is_empty_shadow_page(u64 *spt)
1443 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1444 if (is_shadow_present_pte(*pos)) {
1445 printk(KERN_ERR "%s: %p %llx\n", __func__,
1454 * This value is the sum of all of the kvm instances's
1455 * kvm->arch.n_used_mmu_pages values. We need a global,
1456 * aggregate version in order to make the slab shrinker
1459 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1461 kvm->arch.n_used_mmu_pages += nr;
1462 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1466 * Remove the sp from shadow page cache, after call it,
1467 * we can not find this sp from the cache, and the shadow
1468 * page table is still valid.
1469 * It should be under the protection of mmu lock.
1471 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1473 ASSERT(is_empty_shadow_page(sp->spt));
1474 hlist_del(&sp->hash_link);
1475 if (!sp->role.direct)
1476 free_page((unsigned long)sp->gfns);
1480 * Free the shadow page table and the sp, we can do it
1481 * out of the protection of mmu lock.
1483 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1485 list_del(&sp->link);
1486 free_page((unsigned long)sp->spt);
1487 kmem_cache_free(mmu_page_header_cache, sp);
1490 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1492 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1495 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1496 struct kvm_mmu_page *sp, u64 *parent_pte)
1501 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1504 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1507 pte_list_remove(parent_pte, &sp->parent_ptes);
1510 static void drop_parent_pte(struct kvm_mmu_page *sp,
1513 mmu_page_remove_parent_pte(sp, parent_pte);
1514 mmu_spte_clear_no_track(parent_pte);
1517 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1518 u64 *parent_pte, int direct)
1520 struct kvm_mmu_page *sp;
1521 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1522 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1524 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1525 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1526 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1527 bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1528 sp->parent_ptes = 0;
1529 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1530 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1534 static void mark_unsync(u64 *spte);
1535 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1537 pte_list_walk(&sp->parent_ptes, mark_unsync);
1540 static void mark_unsync(u64 *spte)
1542 struct kvm_mmu_page *sp;
1545 sp = page_header(__pa(spte));
1546 index = spte - sp->spt;
1547 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1549 if (sp->unsync_children++)
1551 kvm_mmu_mark_parents_unsync(sp);
1554 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1555 struct kvm_mmu_page *sp)
1560 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1564 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1565 struct kvm_mmu_page *sp, u64 *spte,
1571 #define KVM_PAGE_ARRAY_NR 16
1573 struct kvm_mmu_pages {
1574 struct mmu_page_and_offset {
1575 struct kvm_mmu_page *sp;
1577 } page[KVM_PAGE_ARRAY_NR];
1581 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1587 for (i=0; i < pvec->nr; i++)
1588 if (pvec->page[i].sp == sp)
1591 pvec->page[pvec->nr].sp = sp;
1592 pvec->page[pvec->nr].idx = idx;
1594 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1597 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1598 struct kvm_mmu_pages *pvec)
1600 int i, ret, nr_unsync_leaf = 0;
1602 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1603 struct kvm_mmu_page *child;
1604 u64 ent = sp->spt[i];
1606 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1607 goto clear_child_bitmap;
1609 child = page_header(ent & PT64_BASE_ADDR_MASK);
1611 if (child->unsync_children) {
1612 if (mmu_pages_add(pvec, child, i))
1615 ret = __mmu_unsync_walk(child, pvec);
1617 goto clear_child_bitmap;
1619 nr_unsync_leaf += ret;
1622 } else if (child->unsync) {
1624 if (mmu_pages_add(pvec, child, i))
1627 goto clear_child_bitmap;
1632 __clear_bit(i, sp->unsync_child_bitmap);
1633 sp->unsync_children--;
1634 WARN_ON((int)sp->unsync_children < 0);
1638 return nr_unsync_leaf;
1641 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1642 struct kvm_mmu_pages *pvec)
1644 if (!sp->unsync_children)
1647 mmu_pages_add(pvec, sp, 0);
1648 return __mmu_unsync_walk(sp, pvec);
1651 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1653 WARN_ON(!sp->unsync);
1654 trace_kvm_mmu_sync_page(sp);
1656 --kvm->stat.mmu_unsync;
1659 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1660 struct list_head *invalid_list);
1661 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1662 struct list_head *invalid_list);
1664 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1665 hlist_for_each_entry(sp, pos, \
1666 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1667 if ((sp)->gfn != (gfn)) {} else
1669 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1670 hlist_for_each_entry(sp, pos, \
1671 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1672 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1673 (sp)->role.invalid) {} else
1675 /* @sp->gfn should be write-protected at the call site */
1676 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1677 struct list_head *invalid_list, bool clear_unsync)
1679 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1680 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1685 kvm_unlink_unsync_page(vcpu->kvm, sp);
1687 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1688 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1692 kvm_mmu_flush_tlb(vcpu);
1696 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1697 struct kvm_mmu_page *sp)
1699 LIST_HEAD(invalid_list);
1702 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1704 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1709 #ifdef CONFIG_KVM_MMU_AUDIT
1710 #include "mmu_audit.c"
1712 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1713 static void mmu_audit_disable(void) { }
1716 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1717 struct list_head *invalid_list)
1719 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1722 /* @gfn should be write-protected at the call site */
1723 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1725 struct kvm_mmu_page *s;
1726 struct hlist_node *node;
1727 LIST_HEAD(invalid_list);
1730 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1734 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1735 kvm_unlink_unsync_page(vcpu->kvm, s);
1736 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1737 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1738 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1744 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1746 kvm_mmu_flush_tlb(vcpu);
1749 struct mmu_page_path {
1750 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1751 unsigned int idx[PT64_ROOT_LEVEL-1];
1754 #define for_each_sp(pvec, sp, parents, i) \
1755 for (i = mmu_pages_next(&pvec, &parents, -1), \
1756 sp = pvec.page[i].sp; \
1757 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1758 i = mmu_pages_next(&pvec, &parents, i))
1760 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1761 struct mmu_page_path *parents,
1766 for (n = i+1; n < pvec->nr; n++) {
1767 struct kvm_mmu_page *sp = pvec->page[n].sp;
1769 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1770 parents->idx[0] = pvec->page[n].idx;
1774 parents->parent[sp->role.level-2] = sp;
1775 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1781 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1783 struct kvm_mmu_page *sp;
1784 unsigned int level = 0;
1787 unsigned int idx = parents->idx[level];
1789 sp = parents->parent[level];
1793 --sp->unsync_children;
1794 WARN_ON((int)sp->unsync_children < 0);
1795 __clear_bit(idx, sp->unsync_child_bitmap);
1797 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1800 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1801 struct mmu_page_path *parents,
1802 struct kvm_mmu_pages *pvec)
1804 parents->parent[parent->role.level-1] = NULL;
1808 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1809 struct kvm_mmu_page *parent)
1812 struct kvm_mmu_page *sp;
1813 struct mmu_page_path parents;
1814 struct kvm_mmu_pages pages;
1815 LIST_HEAD(invalid_list);
1817 kvm_mmu_pages_init(parent, &parents, &pages);
1818 while (mmu_unsync_walk(parent, &pages)) {
1819 bool protected = false;
1821 for_each_sp(pages, sp, parents, i)
1822 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1825 kvm_flush_remote_tlbs(vcpu->kvm);
1827 for_each_sp(pages, sp, parents, i) {
1828 kvm_sync_page(vcpu, sp, &invalid_list);
1829 mmu_pages_clear_parents(&parents);
1831 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1832 cond_resched_lock(&vcpu->kvm->mmu_lock);
1833 kvm_mmu_pages_init(parent, &parents, &pages);
1837 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1841 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1845 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1847 sp->write_flooding_count = 0;
1850 static void clear_sp_write_flooding_count(u64 *spte)
1852 struct kvm_mmu_page *sp = page_header(__pa(spte));
1854 __clear_sp_write_flooding_count(sp);
1857 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1865 union kvm_mmu_page_role role;
1867 struct kvm_mmu_page *sp;
1868 struct hlist_node *node;
1869 bool need_sync = false;
1871 role = vcpu->arch.mmu.base_role;
1873 role.direct = direct;
1876 role.access = access;
1877 if (!vcpu->arch.mmu.direct_map
1878 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1879 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1880 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1881 role.quadrant = quadrant;
1883 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1884 if (!need_sync && sp->unsync)
1887 if (sp->role.word != role.word)
1890 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1893 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1894 if (sp->unsync_children) {
1895 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1896 kvm_mmu_mark_parents_unsync(sp);
1897 } else if (sp->unsync)
1898 kvm_mmu_mark_parents_unsync(sp);
1900 __clear_sp_write_flooding_count(sp);
1901 trace_kvm_mmu_get_page(sp, false);
1904 ++vcpu->kvm->stat.mmu_cache_miss;
1905 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1910 hlist_add_head(&sp->hash_link,
1911 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1913 if (rmap_write_protect(vcpu->kvm, gfn))
1914 kvm_flush_remote_tlbs(vcpu->kvm);
1915 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1916 kvm_sync_pages(vcpu, gfn);
1918 account_shadowed(vcpu->kvm, gfn);
1920 init_shadow_page_table(sp);
1921 trace_kvm_mmu_get_page(sp, true);
1925 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1926 struct kvm_vcpu *vcpu, u64 addr)
1928 iterator->addr = addr;
1929 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1930 iterator->level = vcpu->arch.mmu.shadow_root_level;
1932 if (iterator->level == PT64_ROOT_LEVEL &&
1933 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1934 !vcpu->arch.mmu.direct_map)
1937 if (iterator->level == PT32E_ROOT_LEVEL) {
1938 iterator->shadow_addr
1939 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1940 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1942 if (!iterator->shadow_addr)
1943 iterator->level = 0;
1947 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1949 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1952 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1953 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1957 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1960 if (is_last_spte(spte, iterator->level)) {
1961 iterator->level = 0;
1965 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1969 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1971 return __shadow_walk_next(iterator, *iterator->sptep);
1974 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1978 spte = __pa(sp->spt)
1979 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1980 | PT_WRITABLE_MASK | PT_USER_MASK;
1981 mmu_spte_set(sptep, spte);
1984 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1985 unsigned direct_access)
1987 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1988 struct kvm_mmu_page *child;
1991 * For the direct sp, if the guest pte's dirty bit
1992 * changed form clean to dirty, it will corrupt the
1993 * sp's access: allow writable in the read-only sp,
1994 * so we should update the spte at this point to get
1995 * a new sp with the correct access.
1997 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1998 if (child->role.access == direct_access)
2001 drop_parent_pte(child, sptep);
2002 kvm_flush_remote_tlbs(vcpu->kvm);
2006 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2010 struct kvm_mmu_page *child;
2013 if (is_shadow_present_pte(pte)) {
2014 if (is_last_spte(pte, sp->role.level)) {
2015 drop_spte(kvm, spte);
2016 if (is_large_pte(pte))
2019 child = page_header(pte & PT64_BASE_ADDR_MASK);
2020 drop_parent_pte(child, spte);
2025 if (is_mmio_spte(pte))
2026 mmu_spte_clear_no_track(spte);
2031 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2032 struct kvm_mmu_page *sp)
2036 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2037 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2040 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2042 mmu_page_remove_parent_pte(sp, parent_pte);
2045 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2048 struct rmap_iterator iter;
2050 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2051 drop_parent_pte(sp, sptep);
2054 static int mmu_zap_unsync_children(struct kvm *kvm,
2055 struct kvm_mmu_page *parent,
2056 struct list_head *invalid_list)
2059 struct mmu_page_path parents;
2060 struct kvm_mmu_pages pages;
2062 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2065 kvm_mmu_pages_init(parent, &parents, &pages);
2066 while (mmu_unsync_walk(parent, &pages)) {
2067 struct kvm_mmu_page *sp;
2069 for_each_sp(pages, sp, parents, i) {
2070 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2071 mmu_pages_clear_parents(&parents);
2074 kvm_mmu_pages_init(parent, &parents, &pages);
2080 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2081 struct list_head *invalid_list)
2085 trace_kvm_mmu_prepare_zap_page(sp);
2086 ++kvm->stat.mmu_shadow_zapped;
2087 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2088 kvm_mmu_page_unlink_children(kvm, sp);
2089 kvm_mmu_unlink_parents(kvm, sp);
2090 if (!sp->role.invalid && !sp->role.direct)
2091 unaccount_shadowed(kvm, sp->gfn);
2093 kvm_unlink_unsync_page(kvm, sp);
2094 if (!sp->root_count) {
2097 list_move(&sp->link, invalid_list);
2098 kvm_mod_used_mmu_pages(kvm, -1);
2100 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2101 kvm_reload_remote_mmus(kvm);
2104 sp->role.invalid = 1;
2108 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2109 struct list_head *invalid_list)
2111 struct kvm_mmu_page *sp;
2113 if (list_empty(invalid_list))
2117 * wmb: make sure everyone sees our modifications to the page tables
2118 * rmb: make sure we see changes to vcpu->mode
2123 * Wait for all vcpus to exit guest mode and/or lockless shadow
2126 kvm_flush_remote_tlbs(kvm);
2129 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2130 WARN_ON(!sp->role.invalid || sp->root_count);
2131 kvm_mmu_isolate_page(sp);
2132 kvm_mmu_free_page(sp);
2133 } while (!list_empty(invalid_list));
2137 * Changing the number of mmu pages allocated to the vm
2138 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2140 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2142 LIST_HEAD(invalid_list);
2144 * If we set the number of mmu pages to be smaller be than the
2145 * number of actived pages , we must to free some mmu pages before we
2149 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2150 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2151 !list_empty(&kvm->arch.active_mmu_pages)) {
2152 struct kvm_mmu_page *page;
2154 page = container_of(kvm->arch.active_mmu_pages.prev,
2155 struct kvm_mmu_page, link);
2156 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2158 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2159 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2162 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2165 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2167 struct kvm_mmu_page *sp;
2168 struct hlist_node *node;
2169 LIST_HEAD(invalid_list);
2172 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2174 spin_lock(&kvm->mmu_lock);
2175 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2176 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2179 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2181 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2182 spin_unlock(&kvm->mmu_lock);
2186 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2188 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2190 int slot = memslot_id(kvm, gfn);
2191 struct kvm_mmu_page *sp = page_header(__pa(pte));
2193 __set_bit(slot, sp->slot_bitmap);
2197 * The function is based on mtrr_type_lookup() in
2198 * arch/x86/kernel/cpu/mtrr/generic.c
2200 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2205 u8 prev_match, curr_match;
2206 int num_var_ranges = KVM_NR_VAR_MTRR;
2208 if (!mtrr_state->enabled)
2211 /* Make end inclusive end, instead of exclusive */
2214 /* Look in fixed ranges. Just return the type as per start */
2215 if (mtrr_state->have_fixed && (start < 0x100000)) {
2218 if (start < 0x80000) {
2220 idx += (start >> 16);
2221 return mtrr_state->fixed_ranges[idx];
2222 } else if (start < 0xC0000) {
2224 idx += ((start - 0x80000) >> 14);
2225 return mtrr_state->fixed_ranges[idx];
2226 } else if (start < 0x1000000) {
2228 idx += ((start - 0xC0000) >> 12);
2229 return mtrr_state->fixed_ranges[idx];
2234 * Look in variable ranges
2235 * Look of multiple ranges matching this address and pick type
2236 * as per MTRR precedence
2238 if (!(mtrr_state->enabled & 2))
2239 return mtrr_state->def_type;
2242 for (i = 0; i < num_var_ranges; ++i) {
2243 unsigned short start_state, end_state;
2245 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2248 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2249 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2250 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2251 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2253 start_state = ((start & mask) == (base & mask));
2254 end_state = ((end & mask) == (base & mask));
2255 if (start_state != end_state)
2258 if ((start & mask) != (base & mask))
2261 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2262 if (prev_match == 0xFF) {
2263 prev_match = curr_match;
2267 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2268 curr_match == MTRR_TYPE_UNCACHABLE)
2269 return MTRR_TYPE_UNCACHABLE;
2271 if ((prev_match == MTRR_TYPE_WRBACK &&
2272 curr_match == MTRR_TYPE_WRTHROUGH) ||
2273 (prev_match == MTRR_TYPE_WRTHROUGH &&
2274 curr_match == MTRR_TYPE_WRBACK)) {
2275 prev_match = MTRR_TYPE_WRTHROUGH;
2276 curr_match = MTRR_TYPE_WRTHROUGH;
2279 if (prev_match != curr_match)
2280 return MTRR_TYPE_UNCACHABLE;
2283 if (prev_match != 0xFF)
2286 return mtrr_state->def_type;
2289 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2293 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2294 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2295 if (mtrr == 0xfe || mtrr == 0xff)
2296 mtrr = MTRR_TYPE_WRBACK;
2299 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2301 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2303 trace_kvm_mmu_unsync_page(sp);
2304 ++vcpu->kvm->stat.mmu_unsync;
2307 kvm_mmu_mark_parents_unsync(sp);
2310 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2312 struct kvm_mmu_page *s;
2313 struct hlist_node *node;
2315 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2318 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2319 __kvm_unsync_page(vcpu, s);
2323 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2326 struct kvm_mmu_page *s;
2327 struct hlist_node *node;
2328 bool need_unsync = false;
2330 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2334 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2337 if (!need_unsync && !s->unsync) {
2342 kvm_unsync_pages(vcpu, gfn);
2346 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2347 unsigned pte_access, int user_fault,
2348 int write_fault, int level,
2349 gfn_t gfn, pfn_t pfn, bool speculative,
2350 bool can_unsync, bool host_writable)
2355 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2358 spte = PT_PRESENT_MASK;
2360 spte |= shadow_accessed_mask;
2362 if (pte_access & ACC_EXEC_MASK)
2363 spte |= shadow_x_mask;
2365 spte |= shadow_nx_mask;
2367 if (pte_access & ACC_USER_MASK)
2368 spte |= shadow_user_mask;
2370 if (level > PT_PAGE_TABLE_LEVEL)
2371 spte |= PT_PAGE_SIZE_MASK;
2373 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2374 kvm_is_mmio_pfn(pfn));
2377 spte |= SPTE_HOST_WRITEABLE;
2379 pte_access &= ~ACC_WRITE_MASK;
2381 spte |= (u64)pfn << PAGE_SHIFT;
2383 if ((pte_access & ACC_WRITE_MASK)
2384 || (!vcpu->arch.mmu.direct_map && write_fault
2385 && !is_write_protection(vcpu) && !user_fault)) {
2387 if (level > PT_PAGE_TABLE_LEVEL &&
2388 has_wrprotected_page(vcpu->kvm, gfn, level)) {
2390 drop_spte(vcpu->kvm, sptep);
2394 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2396 if (!vcpu->arch.mmu.direct_map
2397 && !(pte_access & ACC_WRITE_MASK)) {
2398 spte &= ~PT_USER_MASK;
2400 * If we converted a user page to a kernel page,
2401 * so that the kernel can write to it when cr0.wp=0,
2402 * then we should prevent the kernel from executing it
2403 * if SMEP is enabled.
2405 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2406 spte |= PT64_NX_MASK;
2410 * Optimization: for pte sync, if spte was writable the hash
2411 * lookup is unnecessary (and expensive). Write protection
2412 * is responsibility of mmu_get_page / kvm_sync_page.
2413 * Same reasoning can be applied to dirty page accounting.
2415 if (!can_unsync && is_writable_pte(*sptep))
2418 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2419 pgprintk("%s: found shadow page for %llx, marking ro\n",
2422 pte_access &= ~ACC_WRITE_MASK;
2423 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2427 if (pte_access & ACC_WRITE_MASK)
2428 mark_page_dirty(vcpu->kvm, gfn);
2431 if (mmu_spte_update(sptep, spte))
2432 kvm_flush_remote_tlbs(vcpu->kvm);
2437 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2438 unsigned pt_access, unsigned pte_access,
2439 int user_fault, int write_fault,
2440 int *emulate, int level, gfn_t gfn,
2441 pfn_t pfn, bool speculative,
2444 int was_rmapped = 0;
2447 pgprintk("%s: spte %llx access %x write_fault %d"
2448 " user_fault %d gfn %llx\n",
2449 __func__, *sptep, pt_access,
2450 write_fault, user_fault, gfn);
2452 if (is_rmap_spte(*sptep)) {
2454 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2455 * the parent of the now unreachable PTE.
2457 if (level > PT_PAGE_TABLE_LEVEL &&
2458 !is_large_pte(*sptep)) {
2459 struct kvm_mmu_page *child;
2462 child = page_header(pte & PT64_BASE_ADDR_MASK);
2463 drop_parent_pte(child, sptep);
2464 kvm_flush_remote_tlbs(vcpu->kvm);
2465 } else if (pfn != spte_to_pfn(*sptep)) {
2466 pgprintk("hfn old %llx new %llx\n",
2467 spte_to_pfn(*sptep), pfn);
2468 drop_spte(vcpu->kvm, sptep);
2469 kvm_flush_remote_tlbs(vcpu->kvm);
2474 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2475 level, gfn, pfn, speculative, true,
2479 kvm_mmu_flush_tlb(vcpu);
2482 if (unlikely(is_mmio_spte(*sptep) && emulate))
2485 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2486 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2487 is_large_pte(*sptep)? "2MB" : "4kB",
2488 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2490 if (!was_rmapped && is_large_pte(*sptep))
2491 ++vcpu->kvm->stat.lpages;
2493 if (is_shadow_present_pte(*sptep)) {
2494 page_header_update_slot(vcpu->kvm, sptep, gfn);
2496 rmap_count = rmap_add(vcpu, sptep, gfn);
2497 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2498 rmap_recycle(vcpu, sptep, gfn);
2501 kvm_release_pfn_clean(pfn);
2504 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2506 mmu_free_roots(vcpu);
2509 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2512 struct kvm_memory_slot *slot;
2515 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2517 return get_fault_pfn();
2519 hva = gfn_to_hva_memslot(slot, gfn);
2521 return hva_to_pfn_atomic(hva);
2524 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2525 struct kvm_mmu_page *sp,
2526 u64 *start, u64 *end)
2528 struct page *pages[PTE_PREFETCH_NUM];
2529 unsigned access = sp->role.access;
2533 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2534 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2537 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2541 for (i = 0; i < ret; i++, gfn++, start++)
2542 mmu_set_spte(vcpu, start, ACC_ALL,
2544 sp->role.level, gfn,
2545 page_to_pfn(pages[i]), true, true);
2550 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2551 struct kvm_mmu_page *sp, u64 *sptep)
2553 u64 *spte, *start = NULL;
2556 WARN_ON(!sp->role.direct);
2558 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2561 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2562 if (is_shadow_present_pte(*spte) || spte == sptep) {
2565 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2573 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2575 struct kvm_mmu_page *sp;
2578 * Since it's no accessed bit on EPT, it's no way to
2579 * distinguish between actually accessed translations
2580 * and prefetched, so disable pte prefetch if EPT is
2583 if (!shadow_accessed_mask)
2586 sp = page_header(__pa(sptep));
2587 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2590 __direct_pte_prefetch(vcpu, sp, sptep);
2593 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2594 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2597 struct kvm_shadow_walk_iterator iterator;
2598 struct kvm_mmu_page *sp;
2602 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2603 if (iterator.level == level) {
2604 unsigned pte_access = ACC_ALL;
2606 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2608 level, gfn, pfn, prefault, map_writable);
2609 direct_pte_prefetch(vcpu, iterator.sptep);
2610 ++vcpu->stat.pf_fixed;
2614 if (!is_shadow_present_pte(*iterator.sptep)) {
2615 u64 base_addr = iterator.addr;
2617 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2618 pseudo_gfn = base_addr >> PAGE_SHIFT;
2619 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2621 1, ACC_ALL, iterator.sptep);
2623 pgprintk("nonpaging_map: ENOMEM\n");
2624 kvm_release_pfn_clean(pfn);
2628 mmu_spte_set(iterator.sptep,
2630 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2631 | shadow_user_mask | shadow_x_mask
2632 | shadow_accessed_mask);
2638 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2642 info.si_signo = SIGBUS;
2644 info.si_code = BUS_MCEERR_AR;
2645 info.si_addr = (void __user *)address;
2646 info.si_addr_lsb = PAGE_SHIFT;
2648 send_sig_info(SIGBUS, &info, tsk);
2651 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2653 kvm_release_pfn_clean(pfn);
2654 if (is_hwpoison_pfn(pfn)) {
2655 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2662 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2663 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2667 int level = *levelp;
2670 * Check if it's a transparent hugepage. If this would be an
2671 * hugetlbfs page, level wouldn't be set to
2672 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2675 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2676 level == PT_PAGE_TABLE_LEVEL &&
2677 PageTransCompound(pfn_to_page(pfn)) &&
2678 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2681 * mmu_notifier_retry was successful and we hold the
2682 * mmu_lock here, so the pmd can't become splitting
2683 * from under us, and in turn
2684 * __split_huge_page_refcount() can't run from under
2685 * us and we can safely transfer the refcount from
2686 * PG_tail to PG_head as we switch the pfn to tail to
2689 *levelp = level = PT_DIRECTORY_LEVEL;
2690 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2691 VM_BUG_ON((gfn & mask) != (pfn & mask));
2695 kvm_release_pfn_clean(pfn);
2703 static bool mmu_invalid_pfn(pfn_t pfn)
2705 return unlikely(is_invalid_pfn(pfn));
2708 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2709 pfn_t pfn, unsigned access, int *ret_val)
2713 /* The pfn is invalid, report the error! */
2714 if (unlikely(is_invalid_pfn(pfn))) {
2715 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2719 if (unlikely(is_noslot_pfn(pfn)))
2720 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2727 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2730 * #PF can be fast only if the shadow page table is present and it
2731 * is caused by write-protect, that means we just need change the
2732 * W bit of the spte which can be done out of mmu-lock.
2734 if (!(error_code & PFERR_PRESENT_MASK) ||
2735 !(error_code & PFERR_WRITE_MASK))
2742 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2744 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2747 WARN_ON(!sp->role.direct);
2750 * The gfn of direct spte is stable since it is calculated
2753 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2755 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2756 mark_page_dirty(vcpu->kvm, gfn);
2763 * - true: let the vcpu to access on the same address again.
2764 * - false: let the real page fault path to fix it.
2766 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2769 struct kvm_shadow_walk_iterator iterator;
2773 if (!page_fault_can_be_fast(vcpu, error_code))
2776 walk_shadow_page_lockless_begin(vcpu);
2777 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2778 if (!is_shadow_present_pte(spte) || iterator.level < level)
2782 * If the mapping has been changed, let the vcpu fault on the
2783 * same address again.
2785 if (!is_rmap_spte(spte)) {
2790 if (!is_last_spte(spte, level))
2794 * Check if it is a spurious fault caused by TLB lazily flushed.
2796 * Need not check the access of upper level table entries since
2797 * they are always ACC_ALL.
2799 if (is_writable_pte(spte)) {
2805 * Currently, to simplify the code, only the spte write-protected
2806 * by dirty-log can be fast fixed.
2808 if (!spte_is_locklessly_modifiable(spte))
2812 * Currently, fast page fault only works for direct mapping since
2813 * the gfn is not stable for indirect shadow page.
2814 * See Documentation/virtual/kvm/locking.txt to get more detail.
2816 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2818 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2820 walk_shadow_page_lockless_end(vcpu);
2825 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2826 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2828 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2829 gfn_t gfn, bool prefault)
2835 unsigned long mmu_seq;
2836 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2838 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2839 if (likely(!force_pt_level)) {
2840 level = mapping_level(vcpu, gfn);
2842 * This path builds a PAE pagetable - so we can map
2843 * 2mb pages at maximum. Therefore check if the level
2844 * is larger than that.
2846 if (level > PT_DIRECTORY_LEVEL)
2847 level = PT_DIRECTORY_LEVEL;
2849 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2851 level = PT_PAGE_TABLE_LEVEL;
2853 if (fast_page_fault(vcpu, v, level, error_code))
2856 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2859 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2862 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2865 spin_lock(&vcpu->kvm->mmu_lock);
2866 if (mmu_notifier_retry(vcpu, mmu_seq))
2868 kvm_mmu_free_some_pages(vcpu);
2869 if (likely(!force_pt_level))
2870 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2871 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2873 spin_unlock(&vcpu->kvm->mmu_lock);
2879 spin_unlock(&vcpu->kvm->mmu_lock);
2880 kvm_release_pfn_clean(pfn);
2885 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2888 struct kvm_mmu_page *sp;
2889 LIST_HEAD(invalid_list);
2891 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2893 spin_lock(&vcpu->kvm->mmu_lock);
2894 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2895 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2896 vcpu->arch.mmu.direct_map)) {
2897 hpa_t root = vcpu->arch.mmu.root_hpa;
2899 sp = page_header(root);
2901 if (!sp->root_count && sp->role.invalid) {
2902 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2903 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2905 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2906 spin_unlock(&vcpu->kvm->mmu_lock);
2909 for (i = 0; i < 4; ++i) {
2910 hpa_t root = vcpu->arch.mmu.pae_root[i];
2913 root &= PT64_BASE_ADDR_MASK;
2914 sp = page_header(root);
2916 if (!sp->root_count && sp->role.invalid)
2917 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2920 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2922 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2923 spin_unlock(&vcpu->kvm->mmu_lock);
2924 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2927 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2931 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2932 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2939 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2941 struct kvm_mmu_page *sp;
2944 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2945 spin_lock(&vcpu->kvm->mmu_lock);
2946 kvm_mmu_free_some_pages(vcpu);
2947 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2950 spin_unlock(&vcpu->kvm->mmu_lock);
2951 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2952 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2953 for (i = 0; i < 4; ++i) {
2954 hpa_t root = vcpu->arch.mmu.pae_root[i];
2956 ASSERT(!VALID_PAGE(root));
2957 spin_lock(&vcpu->kvm->mmu_lock);
2958 kvm_mmu_free_some_pages(vcpu);
2959 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2961 PT32_ROOT_LEVEL, 1, ACC_ALL,
2963 root = __pa(sp->spt);
2965 spin_unlock(&vcpu->kvm->mmu_lock);
2966 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2968 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2975 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2977 struct kvm_mmu_page *sp;
2982 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2984 if (mmu_check_root(vcpu, root_gfn))
2988 * Do we shadow a long mode page table? If so we need to
2989 * write-protect the guests page table root.
2991 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2992 hpa_t root = vcpu->arch.mmu.root_hpa;
2994 ASSERT(!VALID_PAGE(root));
2996 spin_lock(&vcpu->kvm->mmu_lock);
2997 kvm_mmu_free_some_pages(vcpu);
2998 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3000 root = __pa(sp->spt);
3002 spin_unlock(&vcpu->kvm->mmu_lock);
3003 vcpu->arch.mmu.root_hpa = root;
3008 * We shadow a 32 bit page table. This may be a legacy 2-level
3009 * or a PAE 3-level page table. In either case we need to be aware that
3010 * the shadow page table may be a PAE or a long mode page table.
3012 pm_mask = PT_PRESENT_MASK;
3013 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3014 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3016 for (i = 0; i < 4; ++i) {
3017 hpa_t root = vcpu->arch.mmu.pae_root[i];
3019 ASSERT(!VALID_PAGE(root));
3020 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3021 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3022 if (!is_present_gpte(pdptr)) {
3023 vcpu->arch.mmu.pae_root[i] = 0;
3026 root_gfn = pdptr >> PAGE_SHIFT;
3027 if (mmu_check_root(vcpu, root_gfn))
3030 spin_lock(&vcpu->kvm->mmu_lock);
3031 kvm_mmu_free_some_pages(vcpu);
3032 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3035 root = __pa(sp->spt);
3037 spin_unlock(&vcpu->kvm->mmu_lock);
3039 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3041 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3044 * If we shadow a 32 bit page table with a long mode page
3045 * table we enter this path.
3047 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3048 if (vcpu->arch.mmu.lm_root == NULL) {
3050 * The additional page necessary for this is only
3051 * allocated on demand.
3056 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3057 if (lm_root == NULL)
3060 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3062 vcpu->arch.mmu.lm_root = lm_root;
3065 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3071 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3073 if (vcpu->arch.mmu.direct_map)
3074 return mmu_alloc_direct_roots(vcpu);
3076 return mmu_alloc_shadow_roots(vcpu);
3079 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3082 struct kvm_mmu_page *sp;
3084 if (vcpu->arch.mmu.direct_map)
3087 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3090 vcpu_clear_mmio_info(vcpu, ~0ul);
3091 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3092 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3093 hpa_t root = vcpu->arch.mmu.root_hpa;
3094 sp = page_header(root);
3095 mmu_sync_children(vcpu, sp);
3096 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3099 for (i = 0; i < 4; ++i) {
3100 hpa_t root = vcpu->arch.mmu.pae_root[i];
3102 if (root && VALID_PAGE(root)) {
3103 root &= PT64_BASE_ADDR_MASK;
3104 sp = page_header(root);
3105 mmu_sync_children(vcpu, sp);
3108 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3111 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3113 spin_lock(&vcpu->kvm->mmu_lock);
3114 mmu_sync_roots(vcpu);
3115 spin_unlock(&vcpu->kvm->mmu_lock);
3118 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3119 u32 access, struct x86_exception *exception)
3122 exception->error_code = 0;
3126 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3128 struct x86_exception *exception)
3131 exception->error_code = 0;
3132 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3135 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3138 return vcpu_match_mmio_gpa(vcpu, addr);
3140 return vcpu_match_mmio_gva(vcpu, addr);
3145 * On direct hosts, the last spte is only allows two states
3146 * for mmio page fault:
3147 * - It is the mmio spte
3148 * - It is zapped or it is being zapped.
3150 * This function completely checks the spte when the last spte
3151 * is not the mmio spte.
3153 static bool check_direct_spte_mmio_pf(u64 spte)
3155 return __check_direct_spte_mmio_pf(spte);
3158 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3160 struct kvm_shadow_walk_iterator iterator;
3163 walk_shadow_page_lockless_begin(vcpu);
3164 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3165 if (!is_shadow_present_pte(spte))
3167 walk_shadow_page_lockless_end(vcpu);
3173 * If it is a real mmio page fault, return 1 and emulat the instruction
3174 * directly, return 0 to let CPU fault again on the address, -1 is
3175 * returned if bug is detected.
3177 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3181 if (quickly_check_mmio_pf(vcpu, addr, direct))
3184 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3186 if (is_mmio_spte(spte)) {
3187 gfn_t gfn = get_mmio_spte_gfn(spte);
3188 unsigned access = get_mmio_spte_access(spte);
3193 trace_handle_mmio_page_fault(addr, gfn, access);
3194 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3199 * It's ok if the gva is remapped by other cpus on shadow guest,
3200 * it's a BUG if the gfn is not a mmio page.
3202 if (direct && !check_direct_spte_mmio_pf(spte))
3206 * If the page table is zapped by other cpus, let CPU fault again on
3211 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3213 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3214 u32 error_code, bool direct)
3218 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3223 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3224 u32 error_code, bool prefault)
3229 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3231 if (unlikely(error_code & PFERR_RSVD_MASK))
3232 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3234 r = mmu_topup_memory_caches(vcpu);
3239 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3241 gfn = gva >> PAGE_SHIFT;
3243 return nonpaging_map(vcpu, gva & PAGE_MASK,
3244 error_code, gfn, prefault);
3247 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3249 struct kvm_arch_async_pf arch;
3251 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3253 arch.direct_map = vcpu->arch.mmu.direct_map;
3254 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3256 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3259 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3261 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3262 kvm_event_needs_reinjection(vcpu)))
3265 return kvm_x86_ops->interrupt_allowed(vcpu);
3268 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3269 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3273 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3276 return false; /* *pfn has correct page already */
3278 put_page(pfn_to_page(*pfn));
3280 if (!prefault && can_do_async_pf(vcpu)) {
3281 trace_kvm_try_async_get_page(gva, gfn);
3282 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3283 trace_kvm_async_pf_doublefault(gva, gfn);
3284 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3286 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3290 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3295 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3302 gfn_t gfn = gpa >> PAGE_SHIFT;
3303 unsigned long mmu_seq;
3304 int write = error_code & PFERR_WRITE_MASK;
3308 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3310 if (unlikely(error_code & PFERR_RSVD_MASK))
3311 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3313 r = mmu_topup_memory_caches(vcpu);
3317 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3318 if (likely(!force_pt_level)) {
3319 level = mapping_level(vcpu, gfn);
3320 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3322 level = PT_PAGE_TABLE_LEVEL;
3324 if (fast_page_fault(vcpu, gpa, level, error_code))
3327 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3330 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3333 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3336 spin_lock(&vcpu->kvm->mmu_lock);
3337 if (mmu_notifier_retry(vcpu, mmu_seq))
3339 kvm_mmu_free_some_pages(vcpu);
3340 if (likely(!force_pt_level))
3341 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3342 r = __direct_map(vcpu, gpa, write, map_writable,
3343 level, gfn, pfn, prefault);
3344 spin_unlock(&vcpu->kvm->mmu_lock);
3349 spin_unlock(&vcpu->kvm->mmu_lock);
3350 kvm_release_pfn_clean(pfn);
3354 static void nonpaging_free(struct kvm_vcpu *vcpu)
3356 mmu_free_roots(vcpu);
3359 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3360 struct kvm_mmu *context)
3362 context->new_cr3 = nonpaging_new_cr3;
3363 context->page_fault = nonpaging_page_fault;
3364 context->gva_to_gpa = nonpaging_gva_to_gpa;
3365 context->free = nonpaging_free;
3366 context->sync_page = nonpaging_sync_page;
3367 context->invlpg = nonpaging_invlpg;
3368 context->update_pte = nonpaging_update_pte;
3369 context->root_level = 0;
3370 context->shadow_root_level = PT32E_ROOT_LEVEL;
3371 context->root_hpa = INVALID_PAGE;
3372 context->direct_map = true;
3373 context->nx = false;
3377 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3379 ++vcpu->stat.tlb_flush;
3380 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3383 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3385 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3386 mmu_free_roots(vcpu);
3389 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3391 return kvm_read_cr3(vcpu);
3394 static void inject_page_fault(struct kvm_vcpu *vcpu,
3395 struct x86_exception *fault)
3397 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3400 static void paging_free(struct kvm_vcpu *vcpu)
3402 nonpaging_free(vcpu);
3405 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3409 bit7 = (gpte >> 7) & 1;
3410 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3413 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3416 if (unlikely(is_mmio_spte(*sptep))) {
3417 if (gfn != get_mmio_spte_gfn(*sptep)) {
3418 mmu_spte_clear_no_track(sptep);
3423 mark_mmio_spte(sptep, gfn, access);
3431 #include "paging_tmpl.h"
3435 #include "paging_tmpl.h"
3438 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3439 struct kvm_mmu *context)
3441 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3442 u64 exb_bit_rsvd = 0;
3445 exb_bit_rsvd = rsvd_bits(63, 63);
3446 switch (context->root_level) {
3447 case PT32_ROOT_LEVEL:
3448 /* no rsvd bits for 2 level 4K page table entries */
3449 context->rsvd_bits_mask[0][1] = 0;
3450 context->rsvd_bits_mask[0][0] = 0;
3451 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3453 if (!is_pse(vcpu)) {
3454 context->rsvd_bits_mask[1][1] = 0;
3458 if (is_cpuid_PSE36())
3459 /* 36bits PSE 4MB page */
3460 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3462 /* 32 bits PSE 4MB page */
3463 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3465 case PT32E_ROOT_LEVEL:
3466 context->rsvd_bits_mask[0][2] =
3467 rsvd_bits(maxphyaddr, 63) |
3468 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3469 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3470 rsvd_bits(maxphyaddr, 62); /* PDE */
3471 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3472 rsvd_bits(maxphyaddr, 62); /* PTE */
3473 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3474 rsvd_bits(maxphyaddr, 62) |
3475 rsvd_bits(13, 20); /* large page */
3476 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3478 case PT64_ROOT_LEVEL:
3479 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3480 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3481 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3482 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3483 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3484 rsvd_bits(maxphyaddr, 51);
3485 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3486 rsvd_bits(maxphyaddr, 51);
3487 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3488 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3489 rsvd_bits(maxphyaddr, 51) |
3491 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3492 rsvd_bits(maxphyaddr, 51) |
3493 rsvd_bits(13, 20); /* large page */
3494 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3499 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3500 struct kvm_mmu *context,
3503 context->nx = is_nx(vcpu);
3504 context->root_level = level;
3506 reset_rsvds_bits_mask(vcpu, context);
3508 ASSERT(is_pae(vcpu));
3509 context->new_cr3 = paging_new_cr3;
3510 context->page_fault = paging64_page_fault;
3511 context->gva_to_gpa = paging64_gva_to_gpa;
3512 context->sync_page = paging64_sync_page;
3513 context->invlpg = paging64_invlpg;
3514 context->update_pte = paging64_update_pte;
3515 context->free = paging_free;
3516 context->shadow_root_level = level;
3517 context->root_hpa = INVALID_PAGE;
3518 context->direct_map = false;
3522 static int paging64_init_context(struct kvm_vcpu *vcpu,
3523 struct kvm_mmu *context)
3525 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3528 static int paging32_init_context(struct kvm_vcpu *vcpu,
3529 struct kvm_mmu *context)
3531 context->nx = false;
3532 context->root_level = PT32_ROOT_LEVEL;
3534 reset_rsvds_bits_mask(vcpu, context);
3536 context->new_cr3 = paging_new_cr3;
3537 context->page_fault = paging32_page_fault;
3538 context->gva_to_gpa = paging32_gva_to_gpa;
3539 context->free = paging_free;
3540 context->sync_page = paging32_sync_page;
3541 context->invlpg = paging32_invlpg;
3542 context->update_pte = paging32_update_pte;
3543 context->shadow_root_level = PT32E_ROOT_LEVEL;
3544 context->root_hpa = INVALID_PAGE;
3545 context->direct_map = false;
3549 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3550 struct kvm_mmu *context)
3552 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3555 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3557 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3559 context->base_role.word = 0;
3560 context->new_cr3 = nonpaging_new_cr3;
3561 context->page_fault = tdp_page_fault;
3562 context->free = nonpaging_free;
3563 context->sync_page = nonpaging_sync_page;
3564 context->invlpg = nonpaging_invlpg;
3565 context->update_pte = nonpaging_update_pte;
3566 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3567 context->root_hpa = INVALID_PAGE;
3568 context->direct_map = true;
3569 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3570 context->get_cr3 = get_cr3;
3571 context->get_pdptr = kvm_pdptr_read;
3572 context->inject_page_fault = kvm_inject_page_fault;
3574 if (!is_paging(vcpu)) {
3575 context->nx = false;
3576 context->gva_to_gpa = nonpaging_gva_to_gpa;
3577 context->root_level = 0;
3578 } else if (is_long_mode(vcpu)) {
3579 context->nx = is_nx(vcpu);
3580 context->root_level = PT64_ROOT_LEVEL;
3581 reset_rsvds_bits_mask(vcpu, context);
3582 context->gva_to_gpa = paging64_gva_to_gpa;
3583 } else if (is_pae(vcpu)) {
3584 context->nx = is_nx(vcpu);
3585 context->root_level = PT32E_ROOT_LEVEL;
3586 reset_rsvds_bits_mask(vcpu, context);
3587 context->gva_to_gpa = paging64_gva_to_gpa;
3589 context->nx = false;
3590 context->root_level = PT32_ROOT_LEVEL;
3591 reset_rsvds_bits_mask(vcpu, context);
3592 context->gva_to_gpa = paging32_gva_to_gpa;
3598 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3601 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3603 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3605 if (!is_paging(vcpu))
3606 r = nonpaging_init_context(vcpu, context);
3607 else if (is_long_mode(vcpu))
3608 r = paging64_init_context(vcpu, context);
3609 else if (is_pae(vcpu))
3610 r = paging32E_init_context(vcpu, context);
3612 r = paging32_init_context(vcpu, context);
3614 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3615 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3616 vcpu->arch.mmu.base_role.smep_andnot_wp
3617 = smep && !is_write_protection(vcpu);
3621 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3623 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3625 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3627 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3628 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3629 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3630 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3635 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3637 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3639 g_context->get_cr3 = get_cr3;
3640 g_context->get_pdptr = kvm_pdptr_read;
3641 g_context->inject_page_fault = kvm_inject_page_fault;
3644 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3645 * translation of l2_gpa to l1_gpa addresses is done using the
3646 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3647 * functions between mmu and nested_mmu are swapped.
3649 if (!is_paging(vcpu)) {
3650 g_context->nx = false;
3651 g_context->root_level = 0;
3652 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3653 } else if (is_long_mode(vcpu)) {
3654 g_context->nx = is_nx(vcpu);
3655 g_context->root_level = PT64_ROOT_LEVEL;
3656 reset_rsvds_bits_mask(vcpu, g_context);
3657 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3658 } else if (is_pae(vcpu)) {
3659 g_context->nx = is_nx(vcpu);
3660 g_context->root_level = PT32E_ROOT_LEVEL;
3661 reset_rsvds_bits_mask(vcpu, g_context);
3662 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3664 g_context->nx = false;
3665 g_context->root_level = PT32_ROOT_LEVEL;
3666 reset_rsvds_bits_mask(vcpu, g_context);
3667 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3673 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3675 if (mmu_is_nested(vcpu))
3676 return init_kvm_nested_mmu(vcpu);
3677 else if (tdp_enabled)
3678 return init_kvm_tdp_mmu(vcpu);
3680 return init_kvm_softmmu(vcpu);
3683 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3686 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3687 /* mmu.free() should set root_hpa = INVALID_PAGE */
3688 vcpu->arch.mmu.free(vcpu);
3691 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3693 destroy_kvm_mmu(vcpu);
3694 return init_kvm_mmu(vcpu);
3696 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3698 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3702 r = mmu_topup_memory_caches(vcpu);
3705 r = mmu_alloc_roots(vcpu);
3706 spin_lock(&vcpu->kvm->mmu_lock);
3707 mmu_sync_roots(vcpu);
3708 spin_unlock(&vcpu->kvm->mmu_lock);
3711 /* set_cr3() should ensure TLB has been flushed */
3712 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3716 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3718 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3720 mmu_free_roots(vcpu);
3722 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3724 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3725 struct kvm_mmu_page *sp, u64 *spte,
3728 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3729 ++vcpu->kvm->stat.mmu_pde_zapped;
3733 ++vcpu->kvm->stat.mmu_pte_updated;
3734 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3737 static bool need_remote_flush(u64 old, u64 new)
3739 if (!is_shadow_present_pte(old))
3741 if (!is_shadow_present_pte(new))
3743 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3745 old ^= PT64_NX_MASK;
3746 new ^= PT64_NX_MASK;
3747 return (old & ~new & PT64_PERM_MASK) != 0;
3750 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3751 bool remote_flush, bool local_flush)
3757 kvm_flush_remote_tlbs(vcpu->kvm);
3758 else if (local_flush)
3759 kvm_mmu_flush_tlb(vcpu);
3762 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3763 const u8 *new, int *bytes)
3769 * Assume that the pte write on a page table of the same type
3770 * as the current vcpu paging mode since we update the sptes only
3771 * when they have the same mode.
3773 if (is_pae(vcpu) && *bytes == 4) {
3774 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3777 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3780 new = (const u8 *)&gentry;
3785 gentry = *(const u32 *)new;
3788 gentry = *(const u64 *)new;
3799 * If we're seeing too many writes to a page, it may no longer be a page table,
3800 * or we may be forking, in which case it is better to unmap the page.
3802 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3805 * Skip write-flooding detected for the sp whose level is 1, because
3806 * it can become unsync, then the guest page is not write-protected.
3808 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3811 return ++sp->write_flooding_count >= 3;
3815 * Misaligned accesses are too much trouble to fix up; also, they usually
3816 * indicate a page is not used as a page table.
3818 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3821 unsigned offset, pte_size, misaligned;
3823 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3824 gpa, bytes, sp->role.word);
3826 offset = offset_in_page(gpa);
3827 pte_size = sp->role.cr4_pae ? 8 : 4;
3830 * Sometimes, the OS only writes the last one bytes to update status
3831 * bits, for example, in linux, andb instruction is used in clear_bit().
3833 if (!(offset & (pte_size - 1)) && bytes == 1)
3836 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3837 misaligned |= bytes < 4;
3842 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3844 unsigned page_offset, quadrant;
3848 page_offset = offset_in_page(gpa);
3849 level = sp->role.level;
3851 if (!sp->role.cr4_pae) {
3852 page_offset <<= 1; /* 32->64 */
3854 * A 32-bit pde maps 4MB while the shadow pdes map
3855 * only 2MB. So we need to double the offset again
3856 * and zap two pdes instead of one.
3858 if (level == PT32_ROOT_LEVEL) {
3859 page_offset &= ~7; /* kill rounding error */
3863 quadrant = page_offset >> PAGE_SHIFT;
3864 page_offset &= ~PAGE_MASK;
3865 if (quadrant != sp->role.quadrant)
3869 spte = &sp->spt[page_offset / sizeof(*spte)];
3873 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3874 const u8 *new, int bytes)
3876 gfn_t gfn = gpa >> PAGE_SHIFT;
3877 union kvm_mmu_page_role mask = { .word = 0 };
3878 struct kvm_mmu_page *sp;
3879 struct hlist_node *node;
3880 LIST_HEAD(invalid_list);
3881 u64 entry, gentry, *spte;
3883 bool remote_flush, local_flush, zap_page;
3886 * If we don't have indirect shadow pages, it means no page is
3887 * write-protected, so we can exit simply.
3889 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3892 zap_page = remote_flush = local_flush = false;
3894 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3896 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3899 * No need to care whether allocation memory is successful
3900 * or not since pte prefetch is skiped if it does not have
3901 * enough objects in the cache.
3903 mmu_topup_memory_caches(vcpu);
3905 spin_lock(&vcpu->kvm->mmu_lock);
3906 ++vcpu->kvm->stat.mmu_pte_write;
3907 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3909 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3910 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3911 if (detect_write_misaligned(sp, gpa, bytes) ||
3912 detect_write_flooding(sp)) {
3913 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3915 ++vcpu->kvm->stat.mmu_flooded;
3919 spte = get_written_sptes(sp, gpa, &npte);
3926 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3928 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3929 & mask.word) && rmap_can_add(vcpu))
3930 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3931 if (!remote_flush && need_remote_flush(entry, *spte))
3932 remote_flush = true;
3936 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3937 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3938 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3939 spin_unlock(&vcpu->kvm->mmu_lock);
3942 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3947 if (vcpu->arch.mmu.direct_map)
3950 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3952 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3956 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3958 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3960 LIST_HEAD(invalid_list);
3962 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3963 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3964 struct kvm_mmu_page *sp;
3966 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3967 struct kvm_mmu_page, link);
3968 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3969 ++vcpu->kvm->stat.mmu_recycled;
3971 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3974 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3976 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3977 return vcpu_match_mmio_gpa(vcpu, addr);
3979 return vcpu_match_mmio_gva(vcpu, addr);
3982 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3983 void *insn, int insn_len)
3985 int r, emulation_type = EMULTYPE_RETRY;
3986 enum emulation_result er;
3988 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3997 if (is_mmio_page_fault(vcpu, cr2))
4000 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4005 case EMULATE_DO_MMIO:
4006 ++vcpu->stat.mmio_exits;
4016 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4018 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4020 vcpu->arch.mmu.invlpg(vcpu, gva);
4021 kvm_mmu_flush_tlb(vcpu);
4022 ++vcpu->stat.invlpg;
4024 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4026 void kvm_enable_tdp(void)
4030 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4032 void kvm_disable_tdp(void)
4034 tdp_enabled = false;
4036 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4038 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4040 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4041 if (vcpu->arch.mmu.lm_root != NULL)
4042 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4045 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4053 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4054 * Therefore we need to allocate shadow page tables in the first
4055 * 4GB of memory, which happens to fit the DMA32 zone.
4057 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4061 vcpu->arch.mmu.pae_root = page_address(page);
4062 for (i = 0; i < 4; ++i)
4063 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4068 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4072 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4073 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4074 vcpu->arch.mmu.translate_gpa = translate_gpa;
4075 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4077 return alloc_mmu_pages(vcpu);
4080 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4083 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4085 return init_kvm_mmu(vcpu);
4088 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4090 struct kvm_mmu_page *sp;
4093 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
4097 if (!test_bit(slot, sp->slot_bitmap))
4101 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
4102 if (!is_shadow_present_pte(pt[i]) ||
4103 !is_last_spte(pt[i], sp->role.level))
4106 spte_write_protect(kvm, &pt[i], &flush, false);
4109 kvm_flush_remote_tlbs(kvm);
4112 void kvm_mmu_zap_all(struct kvm *kvm)
4114 struct kvm_mmu_page *sp, *node;
4115 LIST_HEAD(invalid_list);
4117 spin_lock(&kvm->mmu_lock);
4119 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4120 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4123 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4124 spin_unlock(&kvm->mmu_lock);
4127 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4128 struct list_head *invalid_list)
4130 struct kvm_mmu_page *page;
4132 if (list_empty(&kvm->arch.active_mmu_pages))
4135 page = container_of(kvm->arch.active_mmu_pages.prev,
4136 struct kvm_mmu_page, link);
4137 kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4140 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4143 int nr_to_scan = sc->nr_to_scan;
4145 if (nr_to_scan == 0)
4148 raw_spin_lock(&kvm_lock);
4150 list_for_each_entry(kvm, &vm_list, vm_list) {
4152 LIST_HEAD(invalid_list);
4155 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4156 * here. We may skip a VM instance errorneosly, but we do not
4157 * want to shrink a VM that only started to populate its MMU
4160 if (kvm->arch.n_used_mmu_pages > 0) {
4166 idx = srcu_read_lock(&kvm->srcu);
4167 spin_lock(&kvm->mmu_lock);
4169 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4170 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4172 spin_unlock(&kvm->mmu_lock);
4173 srcu_read_unlock(&kvm->srcu, idx);
4175 list_move_tail(&kvm->vm_list, &vm_list);
4179 raw_spin_unlock(&kvm_lock);
4182 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4185 static struct shrinker mmu_shrinker = {
4186 .shrink = mmu_shrink,
4187 .seeks = DEFAULT_SEEKS * 10,
4190 static void mmu_destroy_caches(void)
4192 if (pte_list_desc_cache)
4193 kmem_cache_destroy(pte_list_desc_cache);
4194 if (mmu_page_header_cache)
4195 kmem_cache_destroy(mmu_page_header_cache);
4198 int kvm_mmu_module_init(void)
4200 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4201 sizeof(struct pte_list_desc),
4203 if (!pte_list_desc_cache)
4206 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4207 sizeof(struct kvm_mmu_page),
4209 if (!mmu_page_header_cache)
4212 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4215 register_shrinker(&mmu_shrinker);
4220 mmu_destroy_caches();
4225 * Caculate mmu pages needed for kvm.
4227 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4229 unsigned int nr_mmu_pages;
4230 unsigned int nr_pages = 0;
4231 struct kvm_memslots *slots;
4232 struct kvm_memory_slot *memslot;
4234 slots = kvm_memslots(kvm);
4236 kvm_for_each_memslot(memslot, slots)
4237 nr_pages += memslot->npages;
4239 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4240 nr_mmu_pages = max(nr_mmu_pages,
4241 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4243 return nr_mmu_pages;
4246 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4248 struct kvm_shadow_walk_iterator iterator;
4252 walk_shadow_page_lockless_begin(vcpu);
4253 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4254 sptes[iterator.level-1] = spte;
4256 if (!is_shadow_present_pte(spte))
4259 walk_shadow_page_lockless_end(vcpu);
4263 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4265 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4269 destroy_kvm_mmu(vcpu);
4270 free_mmu_pages(vcpu);
4271 mmu_free_memory_caches(vcpu);
4274 void kvm_mmu_module_exit(void)
4276 mmu_destroy_caches();
4277 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4278 unregister_shrinker(&mmu_shrinker);
4279 mmu_audit_disable();