3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79 *((u32 *) (apic->regs + reg_off)) = val;
82 static inline int apic_test_vector(int vec, void *bitmap)
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89 struct kvm_lapic *apic = vcpu->arch.apic;
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
95 static inline void apic_set_vector(int vec, void *bitmap)
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
100 static inline void apic_clear_vector(int vec, void *bitmap)
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
115 struct static_key_deferred apic_hw_disabled __read_mostly;
116 struct static_key_deferred apic_sw_disabled __read_mostly;
118 static inline int apic_enabled(struct kvm_lapic *apic)
120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 static inline int kvm_apic_id(struct kvm_lapic *apic)
132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
135 static void recalculate_apic_map(struct kvm *kvm)
137 struct kvm_apic_map *new, *old = NULL;
138 struct kvm_vcpu *vcpu;
141 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
143 mutex_lock(&kvm->arch.apic_map_lock);
149 /* flat mode is default */
152 new->lid_mask = 0xff;
153 new->broadcast = APIC_BROADCAST;
155 kvm_for_each_vcpu(i, vcpu, kvm) {
156 struct kvm_lapic *apic = vcpu->arch.apic;
158 if (!kvm_apic_present(vcpu))
161 if (apic_x2apic_mode(apic)) {
164 new->cid_mask = new->lid_mask = 0xffff;
165 new->broadcast = X2APIC_BROADCAST;
166 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
167 if (kvm_apic_get_reg(apic, APIC_DFR) ==
175 new->lid_mask = 0xff;
180 * All APICs have to be configured in the same mode by an OS.
181 * We take advatage of this while building logical id loockup
182 * table. After reset APICs are in software disabled mode, so if
183 * we find apic with different setting we assume this is the mode
184 * OS wants all apics to be in; build lookup table accordingly.
186 if (kvm_apic_sw_enabled(apic))
190 kvm_for_each_vcpu(i, vcpu, kvm) {
191 struct kvm_lapic *apic = vcpu->arch.apic;
195 if (!kvm_apic_present(vcpu))
198 aid = kvm_apic_id(apic);
199 ldr = kvm_apic_get_reg(apic, APIC_LDR);
200 cid = apic_cluster_id(new, ldr);
201 lid = apic_logical_id(new, ldr);
203 if (aid < ARRAY_SIZE(new->phys_map))
204 new->phys_map[aid] = apic;
205 if (lid && cid < ARRAY_SIZE(new->logical_map))
206 new->logical_map[cid][ffs(lid) - 1] = apic;
209 old = rcu_dereference_protected(kvm->arch.apic_map,
210 lockdep_is_held(&kvm->arch.apic_map_lock));
211 rcu_assign_pointer(kvm->arch.apic_map, new);
212 mutex_unlock(&kvm->arch.apic_map_lock);
217 kvm_vcpu_request_scan_ioapic(kvm);
220 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
222 bool enabled = val & APIC_SPIV_APIC_ENABLED;
224 apic_set_reg(apic, APIC_SPIV, val);
226 if (enabled != apic->sw_enabled) {
227 apic->sw_enabled = enabled;
229 static_key_slow_dec_deferred(&apic_sw_disabled);
230 recalculate_apic_map(apic->vcpu->kvm);
232 static_key_slow_inc(&apic_sw_disabled.key);
236 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
238 apic_set_reg(apic, APIC_ID, id << 24);
239 recalculate_apic_map(apic->vcpu->kvm);
242 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
244 apic_set_reg(apic, APIC_LDR, id);
245 recalculate_apic_map(apic->vcpu->kvm);
248 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
250 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
253 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
255 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
258 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
263 static inline int apic_lvtt_period(struct kvm_lapic *apic)
265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
268 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
270 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
273 static inline int apic_lvt_nmi_mode(u32 lvt_val)
275 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
278 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
280 struct kvm_lapic *apic = vcpu->arch.apic;
281 struct kvm_cpuid_entry2 *feat;
282 u32 v = APIC_VERSION;
284 if (!kvm_vcpu_has_lapic(vcpu))
287 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
288 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
289 v |= APIC_LVR_DIRECTED_EOI;
290 apic_set_reg(apic, APIC_LVR, v);
293 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
294 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
295 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
296 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
297 LINT_MASK, LINT_MASK, /* LVT0-1 */
298 LVT_MASK /* LVTERR */
301 static int find_highest_vector(void *bitmap)
306 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
307 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
308 reg = bitmap + REG_POS(vec);
310 return fls(*reg) - 1 + vec;
316 static u8 count_vectors(void *bitmap)
322 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
323 reg = bitmap + REG_POS(vec);
324 count += hweight32(*reg);
330 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
333 struct kvm_lapic *apic = vcpu->arch.apic;
335 for (i = 0; i <= 7; i++) {
336 pir_val = xchg(&pir[i], 0);
338 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
341 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
343 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
345 apic_set_vector(vec, apic->regs + APIC_IRR);
347 * irr_pending must be true if any interrupt is pending; set it after
348 * APIC_IRR to avoid race with apic_clear_irr
350 apic->irr_pending = true;
353 static inline int apic_search_irr(struct kvm_lapic *apic)
355 return find_highest_vector(apic->regs + APIC_IRR);
358 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
363 * Note that irr_pending is just a hint. It will be always
364 * true with virtual interrupt delivery enabled.
366 if (!apic->irr_pending)
369 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
370 result = apic_search_irr(apic);
371 ASSERT(result == -1 || result >= 16);
376 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
378 struct kvm_vcpu *vcpu;
382 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
383 /* try to update RVI */
384 apic_clear_vector(vec, apic->regs + APIC_IRR);
385 kvm_make_request(KVM_REQ_EVENT, vcpu);
387 apic->irr_pending = false;
388 apic_clear_vector(vec, apic->regs + APIC_IRR);
389 if (apic_search_irr(apic) != -1)
390 apic->irr_pending = true;
394 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
396 struct kvm_vcpu *vcpu;
398 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
404 * With APIC virtualization enabled, all caching is disabled
405 * because the processor can modify ISR under the hood. Instead
408 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
409 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
412 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
414 * ISR (in service register) bit is set when injecting an interrupt.
415 * The highest vector is injected. Thus the latest bit set matches
416 * the highest bit in ISR.
418 apic->highest_isr_cache = vec;
422 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
427 * Note that isr_count is always 1, and highest_isr_cache
428 * is always -1, with APIC virtualization enabled.
430 if (!apic->isr_count)
432 if (likely(apic->highest_isr_cache != -1))
433 return apic->highest_isr_cache;
435 result = find_highest_vector(apic->regs + APIC_ISR);
436 ASSERT(result == -1 || result >= 16);
441 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
443 struct kvm_vcpu *vcpu;
444 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
450 * We do get here for APIC virtualization enabled if the guest
451 * uses the Hyper-V APIC enlightenment. In this case we may need
452 * to trigger a new interrupt delivery by writing the SVI field;
453 * on the other hand isr_count and highest_isr_cache are unused
454 * and must be left alone.
456 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
457 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
458 apic_find_highest_isr(apic));
461 BUG_ON(apic->isr_count < 0);
462 apic->highest_isr_cache = -1;
466 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
470 /* This may race with setting of irr in __apic_accept_irq() and
471 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
472 * will cause vmexit immediately and the value will be recalculated
473 * on the next vmentry.
475 if (!kvm_vcpu_has_lapic(vcpu))
477 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
482 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
483 int vector, int level, int trig_mode,
484 unsigned long *dest_map);
486 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
487 unsigned long *dest_map)
489 struct kvm_lapic *apic = vcpu->arch.apic;
491 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
492 irq->level, irq->trig_mode, dest_map);
495 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
498 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
502 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
505 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
509 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
511 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
514 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
517 if (pv_eoi_get_user(vcpu, &val) < 0)
518 apic_debug("Can't read EOI MSR value: 0x%llx\n",
519 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
523 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
525 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
526 apic_debug("Can't set EOI MSR value: 0x%llx\n",
527 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
530 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
533 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
535 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
536 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
537 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
540 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
543 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
545 struct kvm_lapic *apic = vcpu->arch.apic;
548 for (i = 0; i < 8; i++)
549 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
552 static void apic_update_ppr(struct kvm_lapic *apic)
554 u32 tpr, isrv, ppr, old_ppr;
557 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
558 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
559 isr = apic_find_highest_isr(apic);
560 isrv = (isr != -1) ? isr : 0;
562 if ((tpr & 0xf0) >= (isrv & 0xf0))
567 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
568 apic, ppr, isr, isrv);
570 if (old_ppr != ppr) {
571 apic_set_reg(apic, APIC_PROCPRI, ppr);
573 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
577 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
579 apic_set_reg(apic, APIC_TASKPRI, tpr);
580 apic_update_ppr(apic);
583 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
585 return dest == (apic_x2apic_mode(apic) ?
586 X2APIC_BROADCAST : APIC_BROADCAST);
589 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
591 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
594 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
599 if (kvm_apic_broadcast(apic, mda))
602 if (apic_x2apic_mode(apic)) {
603 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
604 return logical_id & mda;
607 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
609 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
611 if (logical_id & mda)
614 case APIC_DFR_CLUSTER:
615 if (((logical_id >> 4) == (mda >> 0x4))
616 && (logical_id & mda & 0xf))
620 apic_debug("Bad DFR vcpu %d: %08x\n",
621 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
628 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
629 int short_hand, unsigned int dest, int dest_mode)
632 struct kvm_lapic *target = vcpu->arch.apic;
634 apic_debug("target %p, source %p, dest 0x%x, "
635 "dest_mode 0x%x, short_hand 0x%x\n",
636 target, source, dest, dest_mode, short_hand);
639 switch (short_hand) {
640 case APIC_DEST_NOSHORT:
643 result = kvm_apic_match_physical_addr(target, dest);
646 result = kvm_apic_match_logical_addr(target, dest);
649 result = (target == source);
651 case APIC_DEST_ALLINC:
654 case APIC_DEST_ALLBUT:
655 result = (target != source);
658 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
666 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
667 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
669 struct kvm_apic_map *map;
670 unsigned long bitmap = 1;
671 struct kvm_lapic **dst;
677 if (irq->shorthand == APIC_DEST_SELF) {
678 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
686 map = rcu_dereference(kvm->arch.apic_map);
691 if (irq->dest_id == map->broadcast)
696 if (irq->dest_mode == 0) { /* physical mode */
697 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
700 dst = &map->phys_map[irq->dest_id];
702 u32 mda = irq->dest_id << (32 - map->ldr_bits);
703 u16 cid = apic_cluster_id(map, mda);
705 if (cid >= ARRAY_SIZE(map->logical_map))
708 dst = map->logical_map[cid];
710 bitmap = apic_logical_id(map, mda);
712 if (irq->delivery_mode == APIC_DM_LOWEST) {
714 for_each_set_bit(i, &bitmap, 16) {
719 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
723 bitmap = (l >= 0) ? 1 << l : 0;
727 for_each_set_bit(i, &bitmap, 16) {
732 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
740 * Add a pending IRQ into lapic.
741 * Return 1 if successfully added and 0 if discarded.
743 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
744 int vector, int level, int trig_mode,
745 unsigned long *dest_map)
748 struct kvm_vcpu *vcpu = apic->vcpu;
750 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
752 switch (delivery_mode) {
754 vcpu->arch.apic_arb_prio++;
756 /* FIXME add logic for vcpu on reset */
757 if (unlikely(!apic_enabled(apic)))
763 __set_bit(vcpu->vcpu_id, dest_map);
765 if (kvm_x86_ops->deliver_posted_interrupt)
766 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
768 apic_set_irr(vector, apic);
770 kvm_make_request(KVM_REQ_EVENT, vcpu);
777 vcpu->arch.pv.pv_unhalted = 1;
778 kvm_make_request(KVM_REQ_EVENT, vcpu);
783 apic_debug("Ignoring guest SMI\n");
788 kvm_inject_nmi(vcpu);
793 if (!trig_mode || level) {
795 /* assumes that there are only KVM_APIC_INIT/SIPI */
796 apic->pending_events = (1UL << KVM_APIC_INIT);
797 /* make sure pending_events is visible before sending
800 kvm_make_request(KVM_REQ_EVENT, vcpu);
803 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
808 case APIC_DM_STARTUP:
809 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
810 vcpu->vcpu_id, vector);
812 apic->sipi_vector = vector;
813 /* make sure sipi_vector is visible for the receiver */
815 set_bit(KVM_APIC_SIPI, &apic->pending_events);
816 kvm_make_request(KVM_REQ_EVENT, vcpu);
822 * Should only be called by kvm_apic_local_deliver() with LVT0,
823 * before NMI watchdog was enabled. Already handled by
824 * kvm_apic_accept_pic_intr().
829 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
836 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
838 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
841 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
843 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
844 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
846 if (apic_test_vector(vector, apic->regs + APIC_TMR))
847 trigger_mode = IOAPIC_LEVEL_TRIG;
849 trigger_mode = IOAPIC_EDGE_TRIG;
850 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
854 static int apic_set_eoi(struct kvm_lapic *apic)
856 int vector = apic_find_highest_isr(apic);
858 trace_kvm_eoi(apic, vector);
861 * Not every write EOI will has corresponding ISR,
862 * one example is when Kernel check timer on setup_IO_APIC
867 apic_clear_isr(vector, apic);
868 apic_update_ppr(apic);
870 kvm_ioapic_send_eoi(apic, vector);
871 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
876 * this interface assumes a trap-like exit, which has already finished
877 * desired side effect including vISR and vPPR update.
879 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
881 struct kvm_lapic *apic = vcpu->arch.apic;
883 trace_kvm_eoi(apic, vector);
885 kvm_ioapic_send_eoi(apic, vector);
886 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
888 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
890 static void apic_send_ipi(struct kvm_lapic *apic)
892 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
893 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
894 struct kvm_lapic_irq irq;
896 irq.vector = icr_low & APIC_VECTOR_MASK;
897 irq.delivery_mode = icr_low & APIC_MODE_MASK;
898 irq.dest_mode = icr_low & APIC_DEST_MASK;
899 irq.level = icr_low & APIC_INT_ASSERT;
900 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
901 irq.shorthand = icr_low & APIC_SHORT_MASK;
902 if (apic_x2apic_mode(apic))
903 irq.dest_id = icr_high;
905 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
907 trace_kvm_apic_ipi(icr_low, irq.dest_id);
909 apic_debug("icr_high 0x%x, icr_low 0x%x, "
910 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
911 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
912 icr_high, icr_low, irq.shorthand, irq.dest_id,
913 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
916 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
919 static u32 apic_get_tmcct(struct kvm_lapic *apic)
925 ASSERT(apic != NULL);
927 /* if initial count is 0, current count should also be 0 */
928 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
929 apic->lapic_timer.period == 0)
932 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
933 if (ktime_to_ns(remaining) < 0)
934 remaining = ktime_set(0, 0);
936 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
937 tmcct = div64_u64(ns,
938 (APIC_BUS_CYCLE_NS * apic->divide_count));
943 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
945 struct kvm_vcpu *vcpu = apic->vcpu;
946 struct kvm_run *run = vcpu->run;
948 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
949 run->tpr_access.rip = kvm_rip_read(vcpu);
950 run->tpr_access.is_write = write;
953 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
955 if (apic->vcpu->arch.tpr_access_reporting)
956 __report_tpr_access(apic, write);
959 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
963 if (offset >= LAPIC_MMIO_LENGTH)
968 if (apic_x2apic_mode(apic))
969 val = kvm_apic_id(apic);
971 val = kvm_apic_id(apic) << 24;
974 apic_debug("Access APIC ARBPRI register which is for P6\n");
977 case APIC_TMCCT: /* Timer CCR */
978 if (apic_lvtt_tscdeadline(apic))
981 val = apic_get_tmcct(apic);
984 apic_update_ppr(apic);
985 val = kvm_apic_get_reg(apic, offset);
988 report_tpr_access(apic, false);
991 val = kvm_apic_get_reg(apic, offset);
998 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1000 return container_of(dev, struct kvm_lapic, dev);
1003 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1006 unsigned char alignment = offset & 0xf;
1008 /* this bitmask has a bit cleared for each reserved register */
1009 static const u64 rmask = 0x43ff01ffffffe70cULL;
1011 if ((alignment + len) > 4) {
1012 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1017 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1018 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1023 result = __apic_read(apic, offset & ~0xf);
1025 trace_kvm_apic_read(offset, result);
1031 memcpy(data, (char *)&result + alignment, len);
1034 printk(KERN_ERR "Local APIC read with len = %x, "
1035 "should be 1,2, or 4 instead\n", len);
1041 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1043 return kvm_apic_hw_enabled(apic) &&
1044 addr >= apic->base_address &&
1045 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1048 static int apic_mmio_read(struct kvm_io_device *this,
1049 gpa_t address, int len, void *data)
1051 struct kvm_lapic *apic = to_lapic(this);
1052 u32 offset = address - apic->base_address;
1054 if (!apic_mmio_in_range(apic, address))
1057 apic_reg_read(apic, offset, len, data);
1062 static void update_divide_count(struct kvm_lapic *apic)
1064 u32 tmp1, tmp2, tdcr;
1066 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1068 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1069 apic->divide_count = 0x1 << (tmp2 & 0x7);
1071 apic_debug("timer divide count is 0x%x\n",
1072 apic->divide_count);
1075 static void apic_timer_expired(struct kvm_lapic *apic)
1077 struct kvm_vcpu *vcpu = apic->vcpu;
1078 wait_queue_head_t *q = &vcpu->wq;
1081 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1084 if (atomic_read(&apic->lapic_timer.pending))
1087 atomic_inc(&apic->lapic_timer.pending);
1088 /* FIXME: this code should not know anything about vcpus */
1089 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1091 if (waitqueue_active(q))
1092 wake_up_interruptible(q);
1095 static void start_apic_timer(struct kvm_lapic *apic)
1098 atomic_set(&apic->lapic_timer.pending, 0);
1100 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1101 /* lapic timer in oneshot or periodic mode */
1102 now = apic->lapic_timer.timer.base->get_time();
1103 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1104 * APIC_BUS_CYCLE_NS * apic->divide_count;
1106 if (!apic->lapic_timer.period)
1109 * Do not allow the guest to program periodic timers with small
1110 * interval, since the hrtimers are not throttled by the host
1113 if (apic_lvtt_period(apic)) {
1114 s64 min_period = min_timer_period_us * 1000LL;
1116 if (apic->lapic_timer.period < min_period) {
1117 pr_info_ratelimited(
1118 "kvm: vcpu %i: requested %lld ns "
1119 "lapic timer period limited to %lld ns\n",
1120 apic->vcpu->vcpu_id,
1121 apic->lapic_timer.period, min_period);
1122 apic->lapic_timer.period = min_period;
1126 hrtimer_start(&apic->lapic_timer.timer,
1127 ktime_add_ns(now, apic->lapic_timer.period),
1130 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1132 "timer initial count 0x%x, period %lldns, "
1133 "expire @ 0x%016" PRIx64 ".\n", __func__,
1134 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1135 kvm_apic_get_reg(apic, APIC_TMICT),
1136 apic->lapic_timer.period,
1137 ktime_to_ns(ktime_add_ns(now,
1138 apic->lapic_timer.period)));
1139 } else if (apic_lvtt_tscdeadline(apic)) {
1140 /* lapic timer in tsc deadline mode */
1141 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1143 struct kvm_vcpu *vcpu = apic->vcpu;
1144 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1145 unsigned long flags;
1147 if (unlikely(!tscdeadline || !this_tsc_khz))
1150 local_irq_save(flags);
1152 now = apic->lapic_timer.timer.base->get_time();
1153 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1154 if (likely(tscdeadline > guest_tsc)) {
1155 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1156 do_div(ns, this_tsc_khz);
1157 hrtimer_start(&apic->lapic_timer.timer,
1158 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1160 apic_timer_expired(apic);
1162 local_irq_restore(flags);
1166 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1168 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1170 if (apic_lvt_nmi_mode(lvt0_val)) {
1171 if (!nmi_wd_enabled) {
1172 apic_debug("Receive NMI setting on APIC_LVT0 "
1173 "for cpu %d\n", apic->vcpu->vcpu_id);
1174 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1176 } else if (nmi_wd_enabled)
1177 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1180 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1184 trace_kvm_apic_write(reg, val);
1187 case APIC_ID: /* Local APIC ID */
1188 if (!apic_x2apic_mode(apic))
1189 kvm_apic_set_id(apic, val >> 24);
1195 report_tpr_access(apic, true);
1196 apic_set_tpr(apic, val & 0xff);
1204 if (!apic_x2apic_mode(apic))
1205 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1211 if (!apic_x2apic_mode(apic)) {
1212 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1213 recalculate_apic_map(apic->vcpu->kvm);
1220 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1221 mask |= APIC_SPIV_DIRECTED_EOI;
1222 apic_set_spiv(apic, val & mask);
1223 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1227 for (i = 0; i < APIC_LVT_NUM; i++) {
1228 lvt_val = kvm_apic_get_reg(apic,
1229 APIC_LVTT + 0x10 * i);
1230 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1231 lvt_val | APIC_LVT_MASKED);
1233 atomic_set(&apic->lapic_timer.pending, 0);
1239 /* No delay here, so we always clear the pending bit */
1240 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1241 apic_send_ipi(apic);
1245 if (!apic_x2apic_mode(apic))
1247 apic_set_reg(apic, APIC_ICR2, val);
1251 apic_manage_nmi_watchdog(apic, val);
1256 /* TODO: Check vector */
1257 if (!kvm_apic_sw_enabled(apic))
1258 val |= APIC_LVT_MASKED;
1260 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1261 apic_set_reg(apic, reg, val);
1266 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1268 if (apic->lapic_timer.timer_mode != timer_mode) {
1269 apic->lapic_timer.timer_mode = timer_mode;
1270 hrtimer_cancel(&apic->lapic_timer.timer);
1273 if (!kvm_apic_sw_enabled(apic))
1274 val |= APIC_LVT_MASKED;
1275 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1276 apic_set_reg(apic, APIC_LVTT, val);
1281 if (apic_lvtt_tscdeadline(apic))
1284 hrtimer_cancel(&apic->lapic_timer.timer);
1285 apic_set_reg(apic, APIC_TMICT, val);
1286 start_apic_timer(apic);
1291 apic_debug("KVM_WRITE:TDCR %x\n", val);
1292 apic_set_reg(apic, APIC_TDCR, val);
1293 update_divide_count(apic);
1297 if (apic_x2apic_mode(apic) && val != 0) {
1298 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1304 if (apic_x2apic_mode(apic)) {
1305 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1314 apic_debug("Local APIC Write to read-only register %x\n", reg);
1318 static int apic_mmio_write(struct kvm_io_device *this,
1319 gpa_t address, int len, const void *data)
1321 struct kvm_lapic *apic = to_lapic(this);
1322 unsigned int offset = address - apic->base_address;
1325 if (!apic_mmio_in_range(apic, address))
1329 * APIC register must be aligned on 128-bits boundary.
1330 * 32/64/128 bits registers must be accessed thru 32 bits.
1333 if (len != 4 || (offset & 0xf)) {
1334 /* Don't shout loud, $infamous_os would cause only noise. */
1335 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1341 /* too common printing */
1342 if (offset != APIC_EOI)
1343 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1344 "0x%x\n", __func__, offset, len, val);
1346 apic_reg_write(apic, offset & 0xff0, val);
1351 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1353 if (kvm_vcpu_has_lapic(vcpu))
1354 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1356 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1358 /* emulate APIC access in a trap manner */
1359 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1363 /* hw has done the conditional check and inst decode */
1366 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1368 /* TODO: optimize to just emulate side effect w/o one more write */
1369 apic_reg_write(vcpu->arch.apic, offset, val);
1371 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1373 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1375 struct kvm_lapic *apic = vcpu->arch.apic;
1377 if (!vcpu->arch.apic)
1380 hrtimer_cancel(&apic->lapic_timer.timer);
1382 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1383 static_key_slow_dec_deferred(&apic_hw_disabled);
1385 if (!apic->sw_enabled)
1386 static_key_slow_dec_deferred(&apic_sw_disabled);
1389 free_page((unsigned long)apic->regs);
1395 *----------------------------------------------------------------------
1397 *----------------------------------------------------------------------
1400 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1402 struct kvm_lapic *apic = vcpu->arch.apic;
1404 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1405 apic_lvtt_period(apic))
1408 return apic->lapic_timer.tscdeadline;
1411 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1413 struct kvm_lapic *apic = vcpu->arch.apic;
1415 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1416 apic_lvtt_period(apic))
1419 hrtimer_cancel(&apic->lapic_timer.timer);
1420 apic->lapic_timer.tscdeadline = data;
1421 start_apic_timer(apic);
1424 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1426 struct kvm_lapic *apic = vcpu->arch.apic;
1428 if (!kvm_vcpu_has_lapic(vcpu))
1431 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1432 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1435 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1439 if (!kvm_vcpu_has_lapic(vcpu))
1442 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1444 return (tpr & 0xf0) >> 4;
1447 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1449 u64 old_value = vcpu->arch.apic_base;
1450 struct kvm_lapic *apic = vcpu->arch.apic;
1453 value |= MSR_IA32_APICBASE_BSP;
1454 vcpu->arch.apic_base = value;
1458 if (!kvm_vcpu_is_bsp(apic->vcpu))
1459 value &= ~MSR_IA32_APICBASE_BSP;
1460 vcpu->arch.apic_base = value;
1462 /* update jump label if enable bit changes */
1463 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1464 if (value & MSR_IA32_APICBASE_ENABLE)
1465 static_key_slow_dec_deferred(&apic_hw_disabled);
1467 static_key_slow_inc(&apic_hw_disabled.key);
1468 recalculate_apic_map(vcpu->kvm);
1471 if ((old_value ^ value) & X2APIC_ENABLE) {
1472 if (value & X2APIC_ENABLE) {
1473 u32 id = kvm_apic_id(apic);
1474 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1475 kvm_apic_set_ldr(apic, ldr);
1476 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1478 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1481 apic->base_address = apic->vcpu->arch.apic_base &
1482 MSR_IA32_APICBASE_BASE;
1484 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1485 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1486 pr_warn_once("APIC base relocation is unsupported by KVM");
1488 /* with FSB delivery interrupt, we can restart APIC functionality */
1489 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1490 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1494 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1496 struct kvm_lapic *apic;
1499 apic_debug("%s\n", __func__);
1502 apic = vcpu->arch.apic;
1503 ASSERT(apic != NULL);
1505 /* Stop the timer in case it's a reset to an active apic */
1506 hrtimer_cancel(&apic->lapic_timer.timer);
1508 kvm_apic_set_id(apic, vcpu->vcpu_id);
1509 kvm_apic_set_version(apic->vcpu);
1511 for (i = 0; i < APIC_LVT_NUM; i++)
1512 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1513 apic->lapic_timer.timer_mode = 0;
1514 apic_set_reg(apic, APIC_LVT0,
1515 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1517 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1518 apic_set_spiv(apic, 0xff);
1519 apic_set_reg(apic, APIC_TASKPRI, 0);
1520 kvm_apic_set_ldr(apic, 0);
1521 apic_set_reg(apic, APIC_ESR, 0);
1522 apic_set_reg(apic, APIC_ICR, 0);
1523 apic_set_reg(apic, APIC_ICR2, 0);
1524 apic_set_reg(apic, APIC_TDCR, 0);
1525 apic_set_reg(apic, APIC_TMICT, 0);
1526 for (i = 0; i < 8; i++) {
1527 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1528 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1529 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1531 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1532 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1533 apic->highest_isr_cache = -1;
1534 update_divide_count(apic);
1535 atomic_set(&apic->lapic_timer.pending, 0);
1536 if (kvm_vcpu_is_bsp(vcpu))
1537 kvm_lapic_set_base(vcpu,
1538 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1539 vcpu->arch.pv_eoi.msr_val = 0;
1540 apic_update_ppr(apic);
1542 vcpu->arch.apic_arb_prio = 0;
1543 vcpu->arch.apic_attention = 0;
1545 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1546 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1547 vcpu, kvm_apic_id(apic),
1548 vcpu->arch.apic_base, apic->base_address);
1552 *----------------------------------------------------------------------
1554 *----------------------------------------------------------------------
1557 static bool lapic_is_periodic(struct kvm_lapic *apic)
1559 return apic_lvtt_period(apic);
1562 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1564 struct kvm_lapic *apic = vcpu->arch.apic;
1566 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1567 apic_lvt_enabled(apic, APIC_LVTT))
1568 return atomic_read(&apic->lapic_timer.pending);
1573 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1575 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1576 int vector, mode, trig_mode;
1578 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1579 vector = reg & APIC_VECTOR_MASK;
1580 mode = reg & APIC_MODE_MASK;
1581 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1582 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1588 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1590 struct kvm_lapic *apic = vcpu->arch.apic;
1593 kvm_apic_local_deliver(apic, APIC_LVT0);
1596 static const struct kvm_io_device_ops apic_mmio_ops = {
1597 .read = apic_mmio_read,
1598 .write = apic_mmio_write,
1601 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1603 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1604 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1606 apic_timer_expired(apic);
1608 if (lapic_is_periodic(apic)) {
1609 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1610 return HRTIMER_RESTART;
1612 return HRTIMER_NORESTART;
1615 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1617 struct kvm_lapic *apic;
1619 ASSERT(vcpu != NULL);
1620 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1622 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1626 vcpu->arch.apic = apic;
1628 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1630 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1632 goto nomem_free_apic;
1636 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1638 apic->lapic_timer.timer.function = apic_timer_fn;
1641 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1642 * thinking that APIC satet has changed.
1644 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1645 kvm_lapic_set_base(vcpu,
1646 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1648 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1649 kvm_lapic_reset(vcpu);
1650 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1659 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1661 struct kvm_lapic *apic = vcpu->arch.apic;
1664 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1667 apic_update_ppr(apic);
1668 highest_irr = apic_find_highest_irr(apic);
1669 if ((highest_irr == -1) ||
1670 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1675 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1677 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1680 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1682 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1683 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1688 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1690 struct kvm_lapic *apic = vcpu->arch.apic;
1692 if (!kvm_vcpu_has_lapic(vcpu))
1695 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1696 kvm_apic_local_deliver(apic, APIC_LVTT);
1697 if (apic_lvtt_tscdeadline(apic))
1698 apic->lapic_timer.tscdeadline = 0;
1699 atomic_set(&apic->lapic_timer.pending, 0);
1703 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1705 int vector = kvm_apic_has_interrupt(vcpu);
1706 struct kvm_lapic *apic = vcpu->arch.apic;
1712 * We get here even with APIC virtualization enabled, if doing
1713 * nested virtualization and L1 runs with the "acknowledge interrupt
1714 * on exit" mode. Then we cannot inject the interrupt via RVI,
1715 * because the process would deliver it through the IDT.
1718 apic_set_isr(vector, apic);
1719 apic_update_ppr(apic);
1720 apic_clear_irr(vector, apic);
1724 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1725 struct kvm_lapic_state *s)
1727 struct kvm_lapic *apic = vcpu->arch.apic;
1729 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1730 /* set SPIV separately to get count of SW disabled APICs right */
1731 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1732 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1733 /* call kvm_apic_set_id() to put apic into apic_map */
1734 kvm_apic_set_id(apic, kvm_apic_id(apic));
1735 kvm_apic_set_version(vcpu);
1737 apic_update_ppr(apic);
1738 hrtimer_cancel(&apic->lapic_timer.timer);
1739 update_divide_count(apic);
1740 start_apic_timer(apic);
1741 apic->irr_pending = true;
1742 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1743 1 : count_vectors(apic->regs + APIC_ISR);
1744 apic->highest_isr_cache = -1;
1745 if (kvm_x86_ops->hwapic_irr_update)
1746 kvm_x86_ops->hwapic_irr_update(vcpu,
1747 apic_find_highest_irr(apic));
1748 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1749 kvm_make_request(KVM_REQ_EVENT, vcpu);
1750 kvm_rtc_eoi_tracking_restore_one(vcpu);
1753 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1755 struct hrtimer *timer;
1757 if (!kvm_vcpu_has_lapic(vcpu))
1760 timer = &vcpu->arch.apic->lapic_timer.timer;
1761 if (hrtimer_cancel(timer))
1762 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1766 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1768 * Detect whether guest triggered PV EOI since the
1769 * last entry. If yes, set EOI on guests's behalf.
1770 * Clear PV EOI in guest memory in any case.
1772 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1773 struct kvm_lapic *apic)
1778 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1779 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1781 * KVM_APIC_PV_EOI_PENDING is unset:
1782 * -> host disabled PV EOI.
1783 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1784 * -> host enabled PV EOI, guest did not execute EOI yet.
1785 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1786 * -> host enabled PV EOI, guest executed EOI.
1788 BUG_ON(!pv_eoi_enabled(vcpu));
1789 pending = pv_eoi_get_pending(vcpu);
1791 * Clear pending bit in any case: it will be set again on vmentry.
1792 * While this might not be ideal from performance point of view,
1793 * this makes sure pv eoi is only enabled when we know it's safe.
1795 pv_eoi_clr_pending(vcpu);
1798 vector = apic_set_eoi(apic);
1799 trace_kvm_pv_eoi(apic, vector);
1802 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1806 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1807 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1809 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1812 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1815 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1819 * apic_sync_pv_eoi_to_guest - called before vmentry
1821 * Detect whether it's safe to enable PV EOI and
1824 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1825 struct kvm_lapic *apic)
1827 if (!pv_eoi_enabled(vcpu) ||
1828 /* IRR set or many bits in ISR: could be nested. */
1829 apic->irr_pending ||
1830 /* Cache not set: could be safe but we don't bother. */
1831 apic->highest_isr_cache == -1 ||
1832 /* Need EOI to update ioapic. */
1833 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1835 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1836 * so we need not do anything here.
1841 pv_eoi_set_pending(apic->vcpu);
1844 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1847 int max_irr, max_isr;
1848 struct kvm_lapic *apic = vcpu->arch.apic;
1850 apic_sync_pv_eoi_to_guest(vcpu, apic);
1852 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1855 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1856 max_irr = apic_find_highest_irr(apic);
1859 max_isr = apic_find_highest_isr(apic);
1862 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1864 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1868 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1871 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1872 &vcpu->arch.apic->vapic_cache,
1873 vapic_addr, sizeof(u32)))
1875 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1877 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1880 vcpu->arch.apic->vapic_addr = vapic_addr;
1884 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1886 struct kvm_lapic *apic = vcpu->arch.apic;
1887 u32 reg = (msr - APIC_BASE_MSR) << 4;
1889 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1892 if (reg == APIC_ICR2)
1895 /* if this is ICR write vector before command */
1896 if (reg == APIC_ICR)
1897 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1898 return apic_reg_write(apic, reg, (u32)data);
1901 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1903 struct kvm_lapic *apic = vcpu->arch.apic;
1904 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1906 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1909 if (reg == APIC_DFR || reg == APIC_ICR2) {
1910 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1915 if (apic_reg_read(apic, reg, 4, &low))
1917 if (reg == APIC_ICR)
1918 apic_reg_read(apic, APIC_ICR2, 4, &high);
1920 *data = (((u64)high) << 32) | low;
1925 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1927 struct kvm_lapic *apic = vcpu->arch.apic;
1929 if (!kvm_vcpu_has_lapic(vcpu))
1932 /* if this is ICR write vector before command */
1933 if (reg == APIC_ICR)
1934 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1935 return apic_reg_write(apic, reg, (u32)data);
1938 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1940 struct kvm_lapic *apic = vcpu->arch.apic;
1943 if (!kvm_vcpu_has_lapic(vcpu))
1946 if (apic_reg_read(apic, reg, 4, &low))
1948 if (reg == APIC_ICR)
1949 apic_reg_read(apic, APIC_ICR2, 4, &high);
1951 *data = (((u64)high) << 32) | low;
1956 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1958 u64 addr = data & ~KVM_MSR_ENABLED;
1959 if (!IS_ALIGNED(addr, 4))
1962 vcpu->arch.pv_eoi.msr_val = data;
1963 if (!pv_eoi_enabled(vcpu))
1965 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1969 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1971 struct kvm_lapic *apic = vcpu->arch.apic;
1975 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1978 pe = xchg(&apic->pending_events, 0);
1980 if (test_bit(KVM_APIC_INIT, &pe)) {
1981 kvm_lapic_reset(vcpu);
1982 kvm_vcpu_reset(vcpu);
1983 if (kvm_vcpu_is_bsp(apic->vcpu))
1984 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1986 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1988 if (test_bit(KVM_APIC_SIPI, &pe) &&
1989 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1990 /* evaluate pending_events before reading the vector */
1992 sipi_vector = apic->sipi_vector;
1993 apic_debug("vcpu %d received sipi with vector # %x\n",
1994 vcpu->vcpu_id, sipi_vector);
1995 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2000 void kvm_lapic_init(void)
2002 /* do not patch jump label more than once per second */
2003 jump_label_rate_limit(&apic_hw_disabled, HZ);
2004 jump_label_rate_limit(&apic_sw_disabled, HZ);