3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define VEC_POS(v) ((v) & (32 - 1))
72 #define REG_POS(v) (((v) >> 5) << 4)
74 static unsigned int min_timer_period_us = 500;
75 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79 *((u32 *) (apic->regs + reg_off)) = val;
82 static inline int apic_test_and_set_vector(int vec, void *bitmap)
84 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
89 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92 static inline int apic_test_vector(int vec, void *bitmap)
94 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
99 struct kvm_lapic *apic = vcpu->arch.apic;
101 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
102 apic_test_vector(vector, apic->regs + APIC_IRR);
105 static inline void apic_set_vector(int vec, void *bitmap)
107 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
110 static inline void apic_clear_vector(int vec, void *bitmap)
112 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
115 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
117 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
120 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
122 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
125 struct static_key_deferred apic_hw_disabled __read_mostly;
126 struct static_key_deferred apic_sw_disabled __read_mostly;
128 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
130 if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
131 if (val & APIC_SPIV_APIC_ENABLED)
132 static_key_slow_dec_deferred(&apic_sw_disabled);
134 static_key_slow_inc(&apic_sw_disabled.key);
136 apic_set_reg(apic, APIC_SPIV, val);
139 static inline int apic_enabled(struct kvm_lapic *apic)
141 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
145 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
148 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
149 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
151 static inline int kvm_apic_id(struct kvm_lapic *apic)
153 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
156 static void recalculate_apic_map(struct kvm *kvm)
158 struct kvm_apic_map *new, *old = NULL;
159 struct kvm_vcpu *vcpu;
162 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
164 mutex_lock(&kvm->arch.apic_map_lock);
170 /* flat mode is default */
173 new->lid_mask = 0xff;
175 kvm_for_each_vcpu(i, vcpu, kvm) {
176 struct kvm_lapic *apic = vcpu->arch.apic;
180 if (!kvm_apic_present(vcpu))
184 * All APICs have to be configured in the same mode by an OS.
185 * We take advatage of this while building logical id loockup
186 * table. After reset APICs are in xapic/flat mode, so if we
187 * find apic with different setting we assume this is the mode
188 * OS wants all apics to be in; build lookup table accordingly.
190 if (apic_x2apic_mode(apic)) {
193 new->cid_mask = new->lid_mask = 0xffff;
194 } else if (kvm_apic_sw_enabled(apic) &&
195 !new->cid_mask /* flat mode */ &&
196 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
202 new->phys_map[kvm_apic_id(apic)] = apic;
204 ldr = kvm_apic_get_reg(apic, APIC_LDR);
205 cid = apic_cluster_id(new, ldr);
206 lid = apic_logical_id(new, ldr);
209 new->logical_map[cid][ffs(lid) - 1] = apic;
212 old = rcu_dereference_protected(kvm->arch.apic_map,
213 lockdep_is_held(&kvm->arch.apic_map_lock));
214 rcu_assign_pointer(kvm->arch.apic_map, new);
215 mutex_unlock(&kvm->arch.apic_map_lock);
220 kvm_vcpu_request_scan_ioapic(kvm);
223 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
225 apic_set_reg(apic, APIC_ID, id << 24);
226 recalculate_apic_map(apic->vcpu->kvm);
229 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
231 apic_set_reg(apic, APIC_LDR, id);
232 recalculate_apic_map(apic->vcpu->kvm);
235 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
237 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
240 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
242 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
245 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
247 return ((kvm_apic_get_reg(apic, APIC_LVTT) &
248 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
251 static inline int apic_lvtt_period(struct kvm_lapic *apic)
253 return ((kvm_apic_get_reg(apic, APIC_LVTT) &
254 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
257 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
259 return ((kvm_apic_get_reg(apic, APIC_LVTT) &
260 apic->lapic_timer.timer_mode_mask) ==
261 APIC_LVT_TIMER_TSCDEADLINE);
264 static inline int apic_lvt_nmi_mode(u32 lvt_val)
266 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
269 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
271 struct kvm_lapic *apic = vcpu->arch.apic;
272 struct kvm_cpuid_entry2 *feat;
273 u32 v = APIC_VERSION;
275 if (!kvm_vcpu_has_lapic(vcpu))
278 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
279 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
280 v |= APIC_LVR_DIRECTED_EOI;
281 apic_set_reg(apic, APIC_LVR, v);
284 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
285 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
286 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
287 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
288 LINT_MASK, LINT_MASK, /* LVT0-1 */
289 LVT_MASK /* LVTERR */
292 static int find_highest_vector(void *bitmap)
297 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
298 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
299 reg = bitmap + REG_POS(vec);
301 return fls(*reg) - 1 + vec;
307 static u8 count_vectors(void *bitmap)
313 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
314 reg = bitmap + REG_POS(vec);
315 count += hweight32(*reg);
321 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
324 struct kvm_lapic *apic = vcpu->arch.apic;
326 for (i = 0; i <= 7; i++) {
327 pir_val = xchg(&pir[i], 0);
329 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
332 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
334 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
336 apic->irr_pending = true;
337 apic_set_vector(vec, apic->regs + APIC_IRR);
340 static inline int apic_search_irr(struct kvm_lapic *apic)
342 return find_highest_vector(apic->regs + APIC_IRR);
345 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
350 * Note that irr_pending is just a hint. It will be always
351 * true with virtual interrupt delivery enabled.
353 if (!apic->irr_pending)
356 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
357 result = apic_search_irr(apic);
358 ASSERT(result == -1 || result >= 16);
363 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
365 apic->irr_pending = false;
366 apic_clear_vector(vec, apic->regs + APIC_IRR);
367 if (apic_search_irr(apic) != -1)
368 apic->irr_pending = true;
371 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
373 if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
375 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
377 * ISR (in service register) bit is set when injecting an interrupt.
378 * The highest vector is injected. Thus the latest bit set matches
379 * the highest bit in ISR.
381 apic->highest_isr_cache = vec;
384 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
386 if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
388 BUG_ON(apic->isr_count < 0);
389 apic->highest_isr_cache = -1;
392 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
396 /* This may race with setting of irr in __apic_accept_irq() and
397 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
398 * will cause vmexit immediately and the value will be recalculated
399 * on the next vmentry.
401 if (!kvm_vcpu_has_lapic(vcpu))
403 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
408 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
409 int vector, int level, int trig_mode,
410 unsigned long *dest_map);
412 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
413 unsigned long *dest_map)
415 struct kvm_lapic *apic = vcpu->arch.apic;
417 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
418 irq->level, irq->trig_mode, dest_map);
421 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
424 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
428 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
431 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
435 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
437 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
440 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
443 if (pv_eoi_get_user(vcpu, &val) < 0)
444 apic_debug("Can't read EOI MSR value: 0x%llx\n",
445 (unsigned long long)vcpi->arch.pv_eoi.msr_val);
449 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
451 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
452 apic_debug("Can't set EOI MSR value: 0x%llx\n",
453 (unsigned long long)vcpi->arch.pv_eoi.msr_val);
456 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
459 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
461 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
462 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
463 (unsigned long long)vcpi->arch.pv_eoi.msr_val);
466 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
469 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
473 /* Note that isr_count is always 1 with vid enabled */
474 if (!apic->isr_count)
476 if (likely(apic->highest_isr_cache != -1))
477 return apic->highest_isr_cache;
479 result = find_highest_vector(apic->regs + APIC_ISR);
480 ASSERT(result == -1 || result >= 16);
485 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
487 struct kvm_lapic *apic = vcpu->arch.apic;
490 for (i = 0; i < 8; i++)
491 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
494 static void apic_update_ppr(struct kvm_lapic *apic)
496 u32 tpr, isrv, ppr, old_ppr;
499 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
500 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
501 isr = apic_find_highest_isr(apic);
502 isrv = (isr != -1) ? isr : 0;
504 if ((tpr & 0xf0) >= (isrv & 0xf0))
509 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
510 apic, ppr, isr, isrv);
512 if (old_ppr != ppr) {
513 apic_set_reg(apic, APIC_PROCPRI, ppr);
515 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
519 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
521 apic_set_reg(apic, APIC_TASKPRI, tpr);
522 apic_update_ppr(apic);
525 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
527 return dest == 0xff || kvm_apic_id(apic) == dest;
530 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
535 if (apic_x2apic_mode(apic)) {
536 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
537 return logical_id & mda;
540 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
542 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
544 if (logical_id & mda)
547 case APIC_DFR_CLUSTER:
548 if (((logical_id >> 4) == (mda >> 0x4))
549 && (logical_id & mda & 0xf))
553 apic_debug("Bad DFR vcpu %d: %08x\n",
554 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
561 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
562 int short_hand, int dest, int dest_mode)
565 struct kvm_lapic *target = vcpu->arch.apic;
567 apic_debug("target %p, source %p, dest 0x%x, "
568 "dest_mode 0x%x, short_hand 0x%x\n",
569 target, source, dest, dest_mode, short_hand);
572 switch (short_hand) {
573 case APIC_DEST_NOSHORT:
576 result = kvm_apic_match_physical_addr(target, dest);
579 result = kvm_apic_match_logical_addr(target, dest);
582 result = (target == source);
584 case APIC_DEST_ALLINC:
587 case APIC_DEST_ALLBUT:
588 result = (target != source);
591 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
599 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
600 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
602 struct kvm_apic_map *map;
603 unsigned long bitmap = 1;
604 struct kvm_lapic **dst;
610 if (irq->shorthand == APIC_DEST_SELF) {
611 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
619 map = rcu_dereference(kvm->arch.apic_map);
624 if (irq->dest_mode == 0) { /* physical mode */
625 if (irq->delivery_mode == APIC_DM_LOWEST ||
626 irq->dest_id == 0xff)
628 dst = &map->phys_map[irq->dest_id & 0xff];
630 u32 mda = irq->dest_id << (32 - map->ldr_bits);
632 dst = map->logical_map[apic_cluster_id(map, mda)];
634 bitmap = apic_logical_id(map, mda);
636 if (irq->delivery_mode == APIC_DM_LOWEST) {
638 for_each_set_bit(i, &bitmap, 16) {
643 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
647 bitmap = (l >= 0) ? 1 << l : 0;
651 for_each_set_bit(i, &bitmap, 16) {
656 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
666 * Add a pending IRQ into lapic.
667 * Return 1 if successfully added and 0 if discarded.
669 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
670 int vector, int level, int trig_mode,
671 unsigned long *dest_map)
674 struct kvm_vcpu *vcpu = apic->vcpu;
676 switch (delivery_mode) {
678 vcpu->arch.apic_arb_prio++;
680 /* FIXME add logic for vcpu on reset */
681 if (unlikely(!apic_enabled(apic)))
687 __set_bit(vcpu->vcpu_id, dest_map);
689 if (kvm_x86_ops->deliver_posted_interrupt)
690 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
692 apic_set_irr(vector, apic);
694 kvm_make_request(KVM_REQ_EVENT, vcpu);
697 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
698 trig_mode, vector, false);
702 apic_debug("Ignoring delivery mode 3\n");
706 apic_debug("Ignoring guest SMI\n");
711 kvm_inject_nmi(vcpu);
716 if (!trig_mode || level) {
718 /* assumes that there are only KVM_APIC_INIT/SIPI */
719 apic->pending_events = (1UL << KVM_APIC_INIT);
720 /* make sure pending_events is visible before sending
723 kvm_make_request(KVM_REQ_EVENT, vcpu);
726 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
731 case APIC_DM_STARTUP:
732 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
733 vcpu->vcpu_id, vector);
735 apic->sipi_vector = vector;
736 /* make sure sipi_vector is visible for the receiver */
738 set_bit(KVM_APIC_SIPI, &apic->pending_events);
739 kvm_make_request(KVM_REQ_EVENT, vcpu);
745 * Should only be called by kvm_apic_local_deliver() with LVT0,
746 * before NMI watchdog was enabled. Already handled by
747 * kvm_apic_accept_pic_intr().
752 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
759 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
761 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
764 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
766 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
767 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
769 if (apic_test_vector(vector, apic->regs + APIC_TMR))
770 trigger_mode = IOAPIC_LEVEL_TRIG;
772 trigger_mode = IOAPIC_EDGE_TRIG;
773 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
777 static int apic_set_eoi(struct kvm_lapic *apic)
779 int vector = apic_find_highest_isr(apic);
781 trace_kvm_eoi(apic, vector);
784 * Not every write EOI will has corresponding ISR,
785 * one example is when Kernel check timer on setup_IO_APIC
790 apic_clear_isr(vector, apic);
791 apic_update_ppr(apic);
793 kvm_ioapic_send_eoi(apic, vector);
794 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
799 * this interface assumes a trap-like exit, which has already finished
800 * desired side effect including vISR and vPPR update.
802 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
804 struct kvm_lapic *apic = vcpu->arch.apic;
806 trace_kvm_eoi(apic, vector);
808 kvm_ioapic_send_eoi(apic, vector);
809 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
811 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
813 static void apic_send_ipi(struct kvm_lapic *apic)
815 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
816 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
817 struct kvm_lapic_irq irq;
819 irq.vector = icr_low & APIC_VECTOR_MASK;
820 irq.delivery_mode = icr_low & APIC_MODE_MASK;
821 irq.dest_mode = icr_low & APIC_DEST_MASK;
822 irq.level = icr_low & APIC_INT_ASSERT;
823 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
824 irq.shorthand = icr_low & APIC_SHORT_MASK;
825 if (apic_x2apic_mode(apic))
826 irq.dest_id = icr_high;
828 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
830 trace_kvm_apic_ipi(icr_low, irq.dest_id);
832 apic_debug("icr_high 0x%x, icr_low 0x%x, "
833 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
834 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
835 icr_high, icr_low, irq.shorthand, irq.dest_id,
836 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
839 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
842 static u32 apic_get_tmcct(struct kvm_lapic *apic)
848 ASSERT(apic != NULL);
850 /* if initial count is 0, current count should also be 0 */
851 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0)
854 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
855 if (ktime_to_ns(remaining) < 0)
856 remaining = ktime_set(0, 0);
858 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
859 tmcct = div64_u64(ns,
860 (APIC_BUS_CYCLE_NS * apic->divide_count));
865 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
867 struct kvm_vcpu *vcpu = apic->vcpu;
868 struct kvm_run *run = vcpu->run;
870 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
871 run->tpr_access.rip = kvm_rip_read(vcpu);
872 run->tpr_access.is_write = write;
875 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
877 if (apic->vcpu->arch.tpr_access_reporting)
878 __report_tpr_access(apic, write);
881 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
885 if (offset >= LAPIC_MMIO_LENGTH)
890 if (apic_x2apic_mode(apic))
891 val = kvm_apic_id(apic);
893 val = kvm_apic_id(apic) << 24;
896 apic_debug("Access APIC ARBPRI register which is for P6\n");
899 case APIC_TMCCT: /* Timer CCR */
900 if (apic_lvtt_tscdeadline(apic))
903 val = apic_get_tmcct(apic);
906 apic_update_ppr(apic);
907 val = kvm_apic_get_reg(apic, offset);
910 report_tpr_access(apic, false);
913 val = kvm_apic_get_reg(apic, offset);
920 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
922 return container_of(dev, struct kvm_lapic, dev);
925 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
928 unsigned char alignment = offset & 0xf;
930 /* this bitmask has a bit cleared for each reserved register */
931 static const u64 rmask = 0x43ff01ffffffe70cULL;
933 if ((alignment + len) > 4) {
934 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
939 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
940 apic_debug("KVM_APIC_READ: read reserved register %x\n",
945 result = __apic_read(apic, offset & ~0xf);
947 trace_kvm_apic_read(offset, result);
953 memcpy(data, (char *)&result + alignment, len);
956 printk(KERN_ERR "Local APIC read with len = %x, "
957 "should be 1,2, or 4 instead\n", len);
963 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
965 return kvm_apic_hw_enabled(apic) &&
966 addr >= apic->base_address &&
967 addr < apic->base_address + LAPIC_MMIO_LENGTH;
970 static int apic_mmio_read(struct kvm_io_device *this,
971 gpa_t address, int len, void *data)
973 struct kvm_lapic *apic = to_lapic(this);
974 u32 offset = address - apic->base_address;
976 if (!apic_mmio_in_range(apic, address))
979 apic_reg_read(apic, offset, len, data);
984 static void update_divide_count(struct kvm_lapic *apic)
986 u32 tmp1, tmp2, tdcr;
988 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
990 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
991 apic->divide_count = 0x1 << (tmp2 & 0x7);
993 apic_debug("timer divide count is 0x%x\n",
997 static void start_apic_timer(struct kvm_lapic *apic)
1000 atomic_set(&apic->lapic_timer.pending, 0);
1002 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1003 /* lapic timer in oneshot or periodic mode */
1004 now = apic->lapic_timer.timer.base->get_time();
1005 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1006 * APIC_BUS_CYCLE_NS * apic->divide_count;
1008 if (!apic->lapic_timer.period)
1011 * Do not allow the guest to program periodic timers with small
1012 * interval, since the hrtimers are not throttled by the host
1015 if (apic_lvtt_period(apic)) {
1016 s64 min_period = min_timer_period_us * 1000LL;
1018 if (apic->lapic_timer.period < min_period) {
1019 pr_info_ratelimited(
1020 "kvm: vcpu %i: requested %lld ns "
1021 "lapic timer period limited to %lld ns\n",
1022 apic->vcpu->vcpu_id,
1023 apic->lapic_timer.period, min_period);
1024 apic->lapic_timer.period = min_period;
1028 hrtimer_start(&apic->lapic_timer.timer,
1029 ktime_add_ns(now, apic->lapic_timer.period),
1032 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1034 "timer initial count 0x%x, period %lldns, "
1035 "expire @ 0x%016" PRIx64 ".\n", __func__,
1036 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1037 kvm_apic_get_reg(apic, APIC_TMICT),
1038 apic->lapic_timer.period,
1039 ktime_to_ns(ktime_add_ns(now,
1040 apic->lapic_timer.period)));
1041 } else if (apic_lvtt_tscdeadline(apic)) {
1042 /* lapic timer in tsc deadline mode */
1043 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1045 struct kvm_vcpu *vcpu = apic->vcpu;
1046 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1047 unsigned long flags;
1049 if (unlikely(!tscdeadline || !this_tsc_khz))
1052 local_irq_save(flags);
1054 now = apic->lapic_timer.timer.base->get_time();
1055 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1056 if (likely(tscdeadline > guest_tsc)) {
1057 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1058 do_div(ns, this_tsc_khz);
1060 hrtimer_start(&apic->lapic_timer.timer,
1061 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1063 local_irq_restore(flags);
1067 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1069 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1071 if (apic_lvt_nmi_mode(lvt0_val)) {
1072 if (!nmi_wd_enabled) {
1073 apic_debug("Receive NMI setting on APIC_LVT0 "
1074 "for cpu %d\n", apic->vcpu->vcpu_id);
1075 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1077 } else if (nmi_wd_enabled)
1078 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1081 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1085 trace_kvm_apic_write(reg, val);
1088 case APIC_ID: /* Local APIC ID */
1089 if (!apic_x2apic_mode(apic))
1090 kvm_apic_set_id(apic, val >> 24);
1096 report_tpr_access(apic, true);
1097 apic_set_tpr(apic, val & 0xff);
1105 if (!apic_x2apic_mode(apic))
1106 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1112 if (!apic_x2apic_mode(apic)) {
1113 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1114 recalculate_apic_map(apic->vcpu->kvm);
1121 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1122 mask |= APIC_SPIV_DIRECTED_EOI;
1123 apic_set_spiv(apic, val & mask);
1124 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1128 for (i = 0; i < APIC_LVT_NUM; i++) {
1129 lvt_val = kvm_apic_get_reg(apic,
1130 APIC_LVTT + 0x10 * i);
1131 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1132 lvt_val | APIC_LVT_MASKED);
1134 atomic_set(&apic->lapic_timer.pending, 0);
1140 /* No delay here, so we always clear the pending bit */
1141 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1142 apic_send_ipi(apic);
1146 if (!apic_x2apic_mode(apic))
1148 apic_set_reg(apic, APIC_ICR2, val);
1152 apic_manage_nmi_watchdog(apic, val);
1157 /* TODO: Check vector */
1158 if (!kvm_apic_sw_enabled(apic))
1159 val |= APIC_LVT_MASKED;
1161 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1162 apic_set_reg(apic, reg, val);
1167 if ((kvm_apic_get_reg(apic, APIC_LVTT) &
1168 apic->lapic_timer.timer_mode_mask) !=
1169 (val & apic->lapic_timer.timer_mode_mask))
1170 hrtimer_cancel(&apic->lapic_timer.timer);
1172 if (!kvm_apic_sw_enabled(apic))
1173 val |= APIC_LVT_MASKED;
1174 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1175 apic_set_reg(apic, APIC_LVTT, val);
1179 if (apic_lvtt_tscdeadline(apic))
1182 hrtimer_cancel(&apic->lapic_timer.timer);
1183 apic_set_reg(apic, APIC_TMICT, val);
1184 start_apic_timer(apic);
1189 apic_debug("KVM_WRITE:TDCR %x\n", val);
1190 apic_set_reg(apic, APIC_TDCR, val);
1191 update_divide_count(apic);
1195 if (apic_x2apic_mode(apic) && val != 0) {
1196 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1202 if (apic_x2apic_mode(apic)) {
1203 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1212 apic_debug("Local APIC Write to read-only register %x\n", reg);
1216 static int apic_mmio_write(struct kvm_io_device *this,
1217 gpa_t address, int len, const void *data)
1219 struct kvm_lapic *apic = to_lapic(this);
1220 unsigned int offset = address - apic->base_address;
1223 if (!apic_mmio_in_range(apic, address))
1227 * APIC register must be aligned on 128-bits boundary.
1228 * 32/64/128 bits registers must be accessed thru 32 bits.
1231 if (len != 4 || (offset & 0xf)) {
1232 /* Don't shout loud, $infamous_os would cause only noise. */
1233 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1239 /* too common printing */
1240 if (offset != APIC_EOI)
1241 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1242 "0x%x\n", __func__, offset, len, val);
1244 apic_reg_write(apic, offset & 0xff0, val);
1249 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1251 if (kvm_vcpu_has_lapic(vcpu))
1252 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1254 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1256 /* emulate APIC access in a trap manner */
1257 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1261 /* hw has done the conditional check and inst decode */
1264 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1266 /* TODO: optimize to just emulate side effect w/o one more write */
1267 apic_reg_write(vcpu->arch.apic, offset, val);
1269 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1271 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1273 struct kvm_lapic *apic = vcpu->arch.apic;
1275 if (!vcpu->arch.apic)
1278 hrtimer_cancel(&apic->lapic_timer.timer);
1280 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1281 static_key_slow_dec_deferred(&apic_hw_disabled);
1283 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1284 static_key_slow_dec_deferred(&apic_sw_disabled);
1287 free_page((unsigned long)apic->regs);
1293 *----------------------------------------------------------------------
1295 *----------------------------------------------------------------------
1298 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1300 struct kvm_lapic *apic = vcpu->arch.apic;
1302 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1303 apic_lvtt_period(apic))
1306 return apic->lapic_timer.tscdeadline;
1309 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1311 struct kvm_lapic *apic = vcpu->arch.apic;
1313 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1314 apic_lvtt_period(apic))
1317 hrtimer_cancel(&apic->lapic_timer.timer);
1318 apic->lapic_timer.tscdeadline = data;
1319 start_apic_timer(apic);
1322 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1324 struct kvm_lapic *apic = vcpu->arch.apic;
1326 if (!kvm_vcpu_has_lapic(vcpu))
1329 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1330 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1333 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1337 if (!kvm_vcpu_has_lapic(vcpu))
1340 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1342 return (tpr & 0xf0) >> 4;
1345 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1347 u64 old_value = vcpu->arch.apic_base;
1348 struct kvm_lapic *apic = vcpu->arch.apic;
1351 value |= MSR_IA32_APICBASE_BSP;
1352 vcpu->arch.apic_base = value;
1356 /* update jump label if enable bit changes */
1357 if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
1358 if (value & MSR_IA32_APICBASE_ENABLE)
1359 static_key_slow_dec_deferred(&apic_hw_disabled);
1361 static_key_slow_inc(&apic_hw_disabled.key);
1362 recalculate_apic_map(vcpu->kvm);
1365 if (!kvm_vcpu_is_bsp(apic->vcpu))
1366 value &= ~MSR_IA32_APICBASE_BSP;
1368 vcpu->arch.apic_base = value;
1369 if ((old_value ^ value) & X2APIC_ENABLE) {
1370 if (value & X2APIC_ENABLE) {
1371 u32 id = kvm_apic_id(apic);
1372 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1373 kvm_apic_set_ldr(apic, ldr);
1374 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1376 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1379 apic->base_address = apic->vcpu->arch.apic_base &
1380 MSR_IA32_APICBASE_BASE;
1382 /* with FSB delivery interrupt, we can restart APIC functionality */
1383 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1384 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1388 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1390 struct kvm_lapic *apic;
1393 apic_debug("%s\n", __func__);
1396 apic = vcpu->arch.apic;
1397 ASSERT(apic != NULL);
1399 /* Stop the timer in case it's a reset to an active apic */
1400 hrtimer_cancel(&apic->lapic_timer.timer);
1402 kvm_apic_set_id(apic, vcpu->vcpu_id);
1403 kvm_apic_set_version(apic->vcpu);
1405 for (i = 0; i < APIC_LVT_NUM; i++)
1406 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1407 apic_set_reg(apic, APIC_LVT0,
1408 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1410 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1411 apic_set_spiv(apic, 0xff);
1412 apic_set_reg(apic, APIC_TASKPRI, 0);
1413 kvm_apic_set_ldr(apic, 0);
1414 apic_set_reg(apic, APIC_ESR, 0);
1415 apic_set_reg(apic, APIC_ICR, 0);
1416 apic_set_reg(apic, APIC_ICR2, 0);
1417 apic_set_reg(apic, APIC_TDCR, 0);
1418 apic_set_reg(apic, APIC_TMICT, 0);
1419 for (i = 0; i < 8; i++) {
1420 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1421 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1422 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1424 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1425 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1426 apic->highest_isr_cache = -1;
1427 update_divide_count(apic);
1428 atomic_set(&apic->lapic_timer.pending, 0);
1429 if (kvm_vcpu_is_bsp(vcpu))
1430 kvm_lapic_set_base(vcpu,
1431 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1432 vcpu->arch.pv_eoi.msr_val = 0;
1433 apic_update_ppr(apic);
1435 vcpu->arch.apic_arb_prio = 0;
1436 vcpu->arch.apic_attention = 0;
1438 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1439 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1440 vcpu, kvm_apic_id(apic),
1441 vcpu->arch.apic_base, apic->base_address);
1445 *----------------------------------------------------------------------
1447 *----------------------------------------------------------------------
1450 static bool lapic_is_periodic(struct kvm_lapic *apic)
1452 return apic_lvtt_period(apic);
1455 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1457 struct kvm_lapic *apic = vcpu->arch.apic;
1459 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1460 apic_lvt_enabled(apic, APIC_LVTT))
1461 return atomic_read(&apic->lapic_timer.pending);
1466 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1468 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1469 int vector, mode, trig_mode;
1471 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1472 vector = reg & APIC_VECTOR_MASK;
1473 mode = reg & APIC_MODE_MASK;
1474 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1475 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1481 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1483 struct kvm_lapic *apic = vcpu->arch.apic;
1486 kvm_apic_local_deliver(apic, APIC_LVT0);
1489 static const struct kvm_io_device_ops apic_mmio_ops = {
1490 .read = apic_mmio_read,
1491 .write = apic_mmio_write,
1494 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1496 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1497 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1498 struct kvm_vcpu *vcpu = apic->vcpu;
1499 wait_queue_head_t *q = &vcpu->wq;
1502 * There is a race window between reading and incrementing, but we do
1503 * not care about potentially losing timer events in the !reinject
1504 * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1505 * in vcpu_enter_guest.
1507 if (!atomic_read(&ktimer->pending)) {
1508 atomic_inc(&ktimer->pending);
1509 /* FIXME: this code should not know anything about vcpus */
1510 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1513 if (waitqueue_active(q))
1514 wake_up_interruptible(q);
1516 if (lapic_is_periodic(apic)) {
1517 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1518 return HRTIMER_RESTART;
1520 return HRTIMER_NORESTART;
1523 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1525 struct kvm_lapic *apic;
1527 ASSERT(vcpu != NULL);
1528 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1530 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1534 vcpu->arch.apic = apic;
1536 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1538 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1540 goto nomem_free_apic;
1544 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1546 apic->lapic_timer.timer.function = apic_timer_fn;
1549 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1550 * thinking that APIC satet has changed.
1552 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1553 kvm_lapic_set_base(vcpu,
1554 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1556 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1557 kvm_lapic_reset(vcpu);
1558 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1567 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1569 struct kvm_lapic *apic = vcpu->arch.apic;
1572 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1575 apic_update_ppr(apic);
1576 highest_irr = apic_find_highest_irr(apic);
1577 if ((highest_irr == -1) ||
1578 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1583 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1585 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1588 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1590 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1591 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1596 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1598 struct kvm_lapic *apic = vcpu->arch.apic;
1600 if (!kvm_vcpu_has_lapic(vcpu))
1603 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1604 kvm_apic_local_deliver(apic, APIC_LVTT);
1605 atomic_set(&apic->lapic_timer.pending, 0);
1609 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1611 int vector = kvm_apic_has_interrupt(vcpu);
1612 struct kvm_lapic *apic = vcpu->arch.apic;
1617 apic_set_isr(vector, apic);
1618 apic_update_ppr(apic);
1619 apic_clear_irr(vector, apic);
1623 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1624 struct kvm_lapic_state *s)
1626 struct kvm_lapic *apic = vcpu->arch.apic;
1628 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1629 /* set SPIV separately to get count of SW disabled APICs right */
1630 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1631 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1632 /* call kvm_apic_set_id() to put apic into apic_map */
1633 kvm_apic_set_id(apic, kvm_apic_id(apic));
1634 kvm_apic_set_version(vcpu);
1636 apic_update_ppr(apic);
1637 hrtimer_cancel(&apic->lapic_timer.timer);
1638 update_divide_count(apic);
1639 start_apic_timer(apic);
1640 apic->irr_pending = true;
1641 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1642 1 : count_vectors(apic->regs + APIC_ISR);
1643 apic->highest_isr_cache = -1;
1644 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1645 kvm_make_request(KVM_REQ_EVENT, vcpu);
1646 kvm_rtc_eoi_tracking_restore_one(vcpu);
1649 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1651 struct hrtimer *timer;
1653 if (!kvm_vcpu_has_lapic(vcpu))
1656 timer = &vcpu->arch.apic->lapic_timer.timer;
1657 if (hrtimer_cancel(timer))
1658 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1662 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1664 * Detect whether guest triggered PV EOI since the
1665 * last entry. If yes, set EOI on guests's behalf.
1666 * Clear PV EOI in guest memory in any case.
1668 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1669 struct kvm_lapic *apic)
1674 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1675 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1677 * KVM_APIC_PV_EOI_PENDING is unset:
1678 * -> host disabled PV EOI.
1679 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1680 * -> host enabled PV EOI, guest did not execute EOI yet.
1681 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1682 * -> host enabled PV EOI, guest executed EOI.
1684 BUG_ON(!pv_eoi_enabled(vcpu));
1685 pending = pv_eoi_get_pending(vcpu);
1687 * Clear pending bit in any case: it will be set again on vmentry.
1688 * While this might not be ideal from performance point of view,
1689 * this makes sure pv eoi is only enabled when we know it's safe.
1691 pv_eoi_clr_pending(vcpu);
1694 vector = apic_set_eoi(apic);
1695 trace_kvm_pv_eoi(apic, vector);
1698 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1703 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1704 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1706 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1709 vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1710 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1711 kunmap_atomic(vapic);
1713 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1717 * apic_sync_pv_eoi_to_guest - called before vmentry
1719 * Detect whether it's safe to enable PV EOI and
1722 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1723 struct kvm_lapic *apic)
1725 if (!pv_eoi_enabled(vcpu) ||
1726 /* IRR set or many bits in ISR: could be nested. */
1727 apic->irr_pending ||
1728 /* Cache not set: could be safe but we don't bother. */
1729 apic->highest_isr_cache == -1 ||
1730 /* Need EOI to update ioapic. */
1731 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1733 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1734 * so we need not do anything here.
1739 pv_eoi_set_pending(apic->vcpu);
1742 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1745 int max_irr, max_isr;
1746 struct kvm_lapic *apic = vcpu->arch.apic;
1749 apic_sync_pv_eoi_to_guest(vcpu, apic);
1751 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1754 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1755 max_irr = apic_find_highest_irr(apic);
1758 max_isr = apic_find_highest_isr(apic);
1761 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1763 vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1764 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1765 kunmap_atomic(vapic);
1768 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1770 vcpu->arch.apic->vapic_addr = vapic_addr;
1772 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1774 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1777 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1779 struct kvm_lapic *apic = vcpu->arch.apic;
1780 u32 reg = (msr - APIC_BASE_MSR) << 4;
1782 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1785 /* if this is ICR write vector before command */
1787 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1788 return apic_reg_write(apic, reg, (u32)data);
1791 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1793 struct kvm_lapic *apic = vcpu->arch.apic;
1794 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1796 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1799 if (apic_reg_read(apic, reg, 4, &low))
1802 apic_reg_read(apic, APIC_ICR2, 4, &high);
1804 *data = (((u64)high) << 32) | low;
1809 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1811 struct kvm_lapic *apic = vcpu->arch.apic;
1813 if (!kvm_vcpu_has_lapic(vcpu))
1816 /* if this is ICR write vector before command */
1817 if (reg == APIC_ICR)
1818 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1819 return apic_reg_write(apic, reg, (u32)data);
1822 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1824 struct kvm_lapic *apic = vcpu->arch.apic;
1827 if (!kvm_vcpu_has_lapic(vcpu))
1830 if (apic_reg_read(apic, reg, 4, &low))
1832 if (reg == APIC_ICR)
1833 apic_reg_read(apic, APIC_ICR2, 4, &high);
1835 *data = (((u64)high) << 32) | low;
1840 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1842 u64 addr = data & ~KVM_MSR_ENABLED;
1843 if (!IS_ALIGNED(addr, 4))
1846 vcpu->arch.pv_eoi.msr_val = data;
1847 if (!pv_eoi_enabled(vcpu))
1849 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1853 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1855 struct kvm_lapic *apic = vcpu->arch.apic;
1856 unsigned int sipi_vector;
1859 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1862 pe = xchg(&apic->pending_events, 0);
1864 if (test_bit(KVM_APIC_INIT, &pe)) {
1865 kvm_lapic_reset(vcpu);
1866 kvm_vcpu_reset(vcpu);
1867 if (kvm_vcpu_is_bsp(apic->vcpu))
1868 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1870 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1872 if (test_bit(KVM_APIC_SIPI, &pe) &&
1873 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1874 /* evaluate pending_events before reading the vector */
1876 sipi_vector = apic->sipi_vector;
1877 pr_debug("vcpu %d received sipi with vector # %x\n",
1878 vcpu->vcpu_id, sipi_vector);
1879 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1880 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1884 void kvm_lapic_init(void)
1886 /* do not patch jump label more than once per second */
1887 jump_label_rate_limit(&apic_hw_disabled, HZ);
1888 jump_label_rate_limit(&apic_sw_disabled, HZ);