2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
67 #include <asm/setup.h>
68 #include <asm/uv/uv.h>
69 #include <linux/mc146818rtc.h>
71 #include <asm/smpboot_hooks.h>
72 #include <asm/i8259.h>
75 u8 apicid_2_node[MAX_APICID];
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
81 /* Store all idle threads, this can be reused instead of creating
82 * a new thread. Also avoids complicated thread destroy functionality
85 #ifdef CONFIG_HOTPLUG_CPU
87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
88 * removed after init for !CONFIG_HOTPLUG_CPU.
90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
95 * We need this for trampoline_base protection from concurrent accesses when
96 * off- and onlining cores wildly.
98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
100 void cpu_hotplug_driver_lock(void)
102 mutex_lock(&x86_cpu_hotplug_driver_mutex);
105 void cpu_hotplug_driver_unlock(void)
107 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
114 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
118 /* Number of siblings per CPU package */
119 int smp_num_siblings = 1;
120 EXPORT_SYMBOL(smp_num_siblings);
122 /* Last level cache ID of each logical CPU */
123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
125 /* representing HT siblings of each logical CPU */
126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
129 /* representing HT and core siblings of each logical CPU */
130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
131 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
133 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
135 /* Per CPU bogomips and other parameters */
136 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
137 EXPORT_PER_CPU_SYMBOL(cpu_info);
139 atomic_t init_deasserted;
141 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
142 /* which node each logical CPU is on */
143 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
144 EXPORT_SYMBOL(cpu_to_node_map);
146 /* set up a mapping between cpu and node. */
147 static void map_cpu_to_node(int cpu, int node)
149 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
150 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
151 cpu_to_node_map[cpu] = node;
154 /* undo a mapping between cpu and node. */
155 static void unmap_cpu_to_node(int cpu)
159 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
160 for (node = 0; node < MAX_NUMNODES; node++)
161 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
162 cpu_to_node_map[cpu] = 0;
164 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
165 #define map_cpu_to_node(cpu, node) ({})
166 #define unmap_cpu_to_node(cpu) ({})
170 static int boot_cpu_logical_apicid;
172 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
173 { [0 ... NR_CPUS-1] = BAD_APICID };
175 static void map_cpu_to_logical_apicid(void)
177 int cpu = smp_processor_id();
178 int apicid = logical_smp_processor_id();
179 int node = apic->apicid_to_node(apicid);
181 if (!node_online(node))
182 node = first_online_node;
184 cpu_2_logical_apicid[cpu] = apicid;
185 map_cpu_to_node(cpu, node);
188 void numa_remove_cpu(int cpu)
190 cpu_2_logical_apicid[cpu] = BAD_APICID;
191 unmap_cpu_to_node(cpu);
194 #define map_cpu_to_logical_apicid() do {} while (0)
198 * Report back to the Boot Processor.
201 static void __cpuinit smp_callin(void)
204 unsigned long timeout;
207 * If waken up by an INIT in an 82489DX configuration
208 * we may get here before an INIT-deassert IPI reaches
209 * our local APIC. We have to wait for the IPI or we'll
210 * lock up on an APIC access.
212 if (apic->wait_for_init_deassert)
213 apic->wait_for_init_deassert(&init_deasserted);
216 * (This works even if the APIC is not enabled.)
218 phys_id = read_apic_id();
219 cpuid = smp_processor_id();
220 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
221 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
224 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
227 * STARTUP IPIs are fragile beasts as they might sometimes
228 * trigger some glue motherboard logic. Complete APIC bus
229 * silence for 1 second, this overestimates the time the
230 * boot CPU is spending to send the up to 2 STARTUP IPIs
231 * by a factor of two. This should be enough.
235 * Waiting 2s total for startup (udelay is not yet working)
237 timeout = jiffies + 2*HZ;
238 while (time_before(jiffies, timeout)) {
240 * Has the boot CPU finished it's STARTUP sequence?
242 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
247 if (!time_before(jiffies, timeout)) {
248 panic("%s: CPU%d started up but did not get a callout!\n",
253 * the boot CPU has finished the init stage and is spinning
254 * on callin_map until we finish. We are free to set up this
255 * CPU, first the APIC. (this is probably redundant on most
259 pr_debug("CALLIN, before setup_local_APIC().\n");
260 if (apic->smp_callin_clear_local_apic)
261 apic->smp_callin_clear_local_apic();
263 end_local_APIC_setup();
264 map_cpu_to_logical_apicid();
267 * Need to setup vector mappings before we enable interrupts.
269 setup_vector_irq(smp_processor_id());
273 * Need to enable IRQs because it can take longer and then
274 * the NMI watchdog might kill us.
279 pr_debug("Stack at about %p\n", &cpuid);
282 * Save our processor parameters
284 smp_store_cpu_info(cpuid);
287 * This must be done before setting cpu_online_mask
288 * or calling notify_cpu_starting.
290 set_cpu_sibling_map(raw_smp_processor_id());
293 notify_cpu_starting(cpuid);
296 * Allow the master to continue.
298 cpumask_set_cpu(cpuid, cpu_callin_mask);
302 * Activate a secondary processor.
304 notrace static void __cpuinit start_secondary(void *unused)
307 * Don't put *anything* before cpu_init(), SMP booting is too
308 * fragile that we want to limit the things done here to the
309 * most necessary things.
316 /* switch away from the initial page table */
317 load_cr3(swapper_pg_dir);
321 /* otherwise gcc will move up smp_processor_id before the cpu_init */
324 * Check TSC synchronization with the BP:
326 check_tsc_sync_target();
329 * We need to hold call_lock, so there is no inconsistency
330 * between the time smp_call_function() determines number of
331 * IPI recipients, and the time when the determination is made
332 * for which cpus receive the IPI. Holding this
333 * lock helps us to not include this cpu in a currently in progress
334 * smp_call_function().
336 * We need to hold vector_lock so there the set of online cpus
337 * does not change while we are assigning vectors to cpus. Holding
338 * this lock ensures we don't half assign or remove an irq from a cpu.
342 set_cpu_online(smp_processor_id(), true);
343 unlock_vector_lock();
345 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
346 x86_platform.nmi_init();
348 /* enable local interrupts */
351 /* to prevent fake stack check failure in clock setup */
352 boot_init_stack_canary();
354 x86_cpuinit.setup_percpu_clockev();
361 * The bootstrap kernel entry code has set these up. Save them for
365 void __cpuinit smp_store_cpu_info(int id)
367 struct cpuinfo_x86 *c = &cpu_data(id);
372 identify_secondary_cpu(c);
375 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
377 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
378 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
379 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
380 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
381 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
382 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
386 void __cpuinit set_cpu_sibling_map(int cpu)
389 struct cpuinfo_x86 *c = &cpu_data(cpu);
391 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
393 if (smp_num_siblings > 1) {
394 for_each_cpu(i, cpu_sibling_setup_mask) {
395 struct cpuinfo_x86 *o = &cpu_data(i);
397 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
398 if (c->phys_proc_id == o->phys_proc_id &&
399 c->compute_unit_id == o->compute_unit_id)
400 link_thread_siblings(cpu, i);
401 } else if (c->phys_proc_id == o->phys_proc_id &&
402 c->cpu_core_id == o->cpu_core_id) {
403 link_thread_siblings(cpu, i);
407 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
410 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
412 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
413 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
418 for_each_cpu(i, cpu_sibling_setup_mask) {
419 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
420 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
421 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
422 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
424 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
425 cpumask_set_cpu(i, cpu_core_mask(cpu));
426 cpumask_set_cpu(cpu, cpu_core_mask(i));
428 * Does this new cpu bringup a new core?
430 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
432 * for each core in package, increment
433 * the booted_cores for this new cpu
435 if (cpumask_first(cpu_sibling_mask(i)) == i)
438 * increment the core count for all
439 * the other cpus in this package
442 cpu_data(i).booted_cores++;
443 } else if (i != cpu && !c->booted_cores)
444 c->booted_cores = cpu_data(i).booted_cores;
449 /* maps the cpu to the sched domain representing multi-core */
450 const struct cpumask *cpu_coregroup_mask(int cpu)
452 struct cpuinfo_x86 *c = &cpu_data(cpu);
454 * For perf, we return last level cache shared map.
455 * And for power savings, we return cpu_core_map
457 if ((sched_mc_power_savings || sched_smt_power_savings) &&
458 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
459 return cpu_core_mask(cpu);
461 return cpu_llc_shared_mask(cpu);
464 static void impress_friends(void)
467 unsigned long bogosum = 0;
469 * Allow the user to impress friends.
471 pr_debug("Before bogomips.\n");
472 for_each_possible_cpu(cpu)
473 if (cpumask_test_cpu(cpu, cpu_callout_mask))
474 bogosum += cpu_data(cpu).loops_per_jiffy;
476 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
479 (bogosum/(5000/HZ))%100);
481 pr_debug("Before bogocount - setting activated=1.\n");
484 void __inquire_remote_apic(int apicid)
486 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
487 char *names[] = { "ID", "VERSION", "SPIV" };
491 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
493 for (i = 0; i < ARRAY_SIZE(regs); i++) {
494 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
499 status = safe_apic_wait_icr_idle();
502 "a previous APIC delivery may have failed\n");
504 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
509 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
510 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
513 case APIC_ICR_RR_VALID:
514 status = apic_read(APIC_RRR);
515 printk(KERN_CONT "%08x\n", status);
518 printk(KERN_CONT "failed\n");
524 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
525 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
526 * won't ... remember to clear down the APIC, etc later.
529 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
531 unsigned long send_status, accept_status = 0;
535 /* Boot on the stack */
536 /* Kick the second */
537 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
539 pr_debug("Waiting for send to finish...\n");
540 send_status = safe_apic_wait_icr_idle();
543 * Give the other CPU some time to accept the IPI.
546 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
547 maxlvt = lapic_get_maxlvt();
548 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
549 apic_write(APIC_ESR, 0);
550 accept_status = (apic_read(APIC_ESR) & 0xEF);
552 pr_debug("NMI sent.\n");
555 printk(KERN_ERR "APIC never delivered???\n");
557 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
559 return (send_status | accept_status);
563 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
565 unsigned long send_status, accept_status = 0;
566 int maxlvt, num_starts, j;
568 maxlvt = lapic_get_maxlvt();
571 * Be paranoid about clearing APIC errors.
573 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
574 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
575 apic_write(APIC_ESR, 0);
579 pr_debug("Asserting INIT.\n");
582 * Turn INIT on target chip
587 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
590 pr_debug("Waiting for send to finish...\n");
591 send_status = safe_apic_wait_icr_idle();
595 pr_debug("Deasserting INIT.\n");
599 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
601 pr_debug("Waiting for send to finish...\n");
602 send_status = safe_apic_wait_icr_idle();
605 atomic_set(&init_deasserted, 1);
608 * Should we send STARTUP IPIs ?
610 * Determine this based on the APIC version.
611 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
613 if (APIC_INTEGRATED(apic_version[phys_apicid]))
619 * Paravirt / VMI wants a startup IPI hook here to set up the
620 * target processor state.
622 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
626 * Run STARTUP IPI loop.
628 pr_debug("#startup loops: %d.\n", num_starts);
630 for (j = 1; j <= num_starts; j++) {
631 pr_debug("Sending STARTUP #%d.\n", j);
632 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
633 apic_write(APIC_ESR, 0);
635 pr_debug("After apic_write.\n");
642 /* Boot on the stack */
643 /* Kick the second */
644 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
648 * Give the other CPU some time to accept the IPI.
652 pr_debug("Startup point 1.\n");
654 pr_debug("Waiting for send to finish...\n");
655 send_status = safe_apic_wait_icr_idle();
658 * Give the other CPU some time to accept the IPI.
661 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
662 apic_write(APIC_ESR, 0);
663 accept_status = (apic_read(APIC_ESR) & 0xEF);
664 if (send_status || accept_status)
667 pr_debug("After Startup.\n");
670 printk(KERN_ERR "APIC never delivered???\n");
672 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
674 return (send_status | accept_status);
678 struct work_struct work;
679 struct task_struct *idle;
680 struct completion done;
684 static void __cpuinit do_fork_idle(struct work_struct *work)
686 struct create_idle *c_idle =
687 container_of(work, struct create_idle, work);
689 c_idle->idle = fork_idle(c_idle->cpu);
690 complete(&c_idle->done);
693 /* reduce the number of lines printed when booting a large cpu count system */
694 static void __cpuinit announce_cpu(int cpu, int apicid)
696 static int current_node = -1;
697 int node = early_cpu_to_node(cpu);
699 if (system_state == SYSTEM_BOOTING) {
700 if (node != current_node) {
701 if (current_node > (-1))
704 pr_info("Booting Node %3d, Processors ", node);
706 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
709 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
714 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
715 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
716 * Returns zero if CPU booted OK, else error code from
717 * ->wakeup_secondary_cpu.
719 static int __cpuinit do_boot_cpu(int apicid, int cpu)
721 unsigned long boot_error = 0;
722 unsigned long start_ip;
724 struct create_idle c_idle = {
726 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
729 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
731 alternatives_smp_switch(1);
733 c_idle.idle = get_idle_for_cpu(cpu);
736 * We can't use kernel_thread since we must avoid to
737 * reschedule the child.
740 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
741 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
742 init_idle(c_idle.idle, cpu);
746 schedule_work(&c_idle.work);
747 wait_for_completion(&c_idle.done);
749 if (IS_ERR(c_idle.idle)) {
750 printk("failed fork for CPU %d\n", cpu);
751 destroy_work_on_stack(&c_idle.work);
752 return PTR_ERR(c_idle.idle);
755 set_idle_for_cpu(cpu, c_idle.idle);
757 per_cpu(current_task, cpu) = c_idle.idle;
759 /* Stack for startup_32 can be just as for start_secondary onwards */
762 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
763 initial_gs = per_cpu_offset(cpu);
764 per_cpu(kernel_stack, cpu) =
765 (unsigned long)task_stack_page(c_idle.idle) -
766 KERNEL_STACK_OFFSET + THREAD_SIZE;
768 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
769 initial_code = (unsigned long)start_secondary;
770 stack_start = c_idle.idle->thread.sp;
772 /* start_ip had better be page-aligned! */
773 start_ip = setup_trampoline();
775 /* So we see what's up */
776 announce_cpu(cpu, apicid);
779 * This grunge runs the startup process for
780 * the targeted processor.
783 atomic_set(&init_deasserted, 0);
785 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
787 pr_debug("Setting warm reset code and vector.\n");
789 smpboot_setup_warm_reset_vector(start_ip);
791 * Be paranoid about clearing APIC errors.
793 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
794 apic_write(APIC_ESR, 0);
800 * Kick the secondary CPU. Use the method in the APIC driver
801 * if it's defined - or use an INIT boot APIC message otherwise:
803 if (apic->wakeup_secondary_cpu)
804 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
806 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
810 * allow APs to start initializing.
812 pr_debug("Before Callout %d.\n", cpu);
813 cpumask_set_cpu(cpu, cpu_callout_mask);
814 pr_debug("After Callout %d.\n", cpu);
817 * Wait 5s total for a response
819 for (timeout = 0; timeout < 50000; timeout++) {
820 if (cpumask_test_cpu(cpu, cpu_callin_mask))
821 break; /* It has booted */
824 * Allow other tasks to run while we wait for the
825 * AP to come online. This also gives a chance
826 * for the MTRR work(triggered by the AP coming online)
827 * to be completed in the stop machine context.
832 if (cpumask_test_cpu(cpu, cpu_callin_mask))
833 pr_debug("CPU%d: has booted.\n", cpu);
836 if (*((volatile unsigned char *)trampoline_base)
838 /* trampoline started but...? */
839 pr_err("CPU%d: Stuck ??\n", cpu);
841 /* trampoline code not run */
842 pr_err("CPU%d: Not responding.\n", cpu);
843 if (apic->inquire_remote_apic)
844 apic->inquire_remote_apic(apicid);
849 /* Try to put things back the way they were before ... */
850 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
852 /* was set by do_boot_cpu() */
853 cpumask_clear_cpu(cpu, cpu_callout_mask);
855 /* was set by cpu_init() */
856 cpumask_clear_cpu(cpu, cpu_initialized_mask);
858 set_cpu_present(cpu, false);
859 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
862 /* mark "stuck" area as not stuck */
863 *((volatile unsigned long *)trampoline_base) = 0;
865 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
867 * Cleanup possible dangling ends...
869 smpboot_restore_warm_reset_vector();
872 destroy_work_on_stack(&c_idle.work);
876 int __cpuinit native_cpu_up(unsigned int cpu)
878 int apicid = apic->cpu_present_to_apicid(cpu);
882 WARN_ON(irqs_disabled());
884 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
886 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
887 !physid_isset(apicid, phys_cpu_present_map)) {
888 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
893 * Already booted CPU?
895 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
896 pr_debug("do_boot_cpu %d Already started\n", cpu);
901 * Save current MTRR state in case it was changed since early boot
902 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
906 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
908 err = do_boot_cpu(apicid, cpu);
910 pr_debug("do_boot_cpu failed %d\n", err);
915 * Check TSC synchronization with the AP (keep irqs disabled
918 local_irq_save(flags);
919 check_tsc_sync_source(cpu);
920 local_irq_restore(flags);
922 while (!cpu_online(cpu)) {
924 touch_nmi_watchdog();
931 * Fall back to non SMP mode after errors.
933 * RED-PEN audit/test this more. I bet there is more state messed up here.
935 static __init void disable_smp(void)
937 init_cpu_present(cpumask_of(0));
938 init_cpu_possible(cpumask_of(0));
939 smpboot_clear_io_apic_irqs();
941 if (smp_found_config)
942 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
944 physid_set_mask_of_physid(0, &phys_cpu_present_map);
945 map_cpu_to_logical_apicid();
946 cpumask_set_cpu(0, cpu_sibling_mask(0));
947 cpumask_set_cpu(0, cpu_core_mask(0));
951 * Various sanity checks.
953 static int __init smp_sanity_check(unsigned max_cpus)
957 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
958 if (def_to_bigsmp && nr_cpu_ids > 8) {
963 "More than 8 CPUs detected - skipping them.\n"
964 "Use CONFIG_X86_BIGSMP.\n");
967 for_each_present_cpu(cpu) {
969 set_cpu_present(cpu, false);
974 for_each_possible_cpu(cpu) {
976 set_cpu_possible(cpu, false);
984 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
986 "weird, boot CPU (#%d) not listed by the BIOS.\n",
987 hard_smp_processor_id());
989 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
993 * If we couldn't find an SMP configuration at boot time,
994 * get out of here now!
996 if (!smp_found_config && !acpi_lapic) {
998 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1000 if (APIC_init_uniprocessor())
1001 printk(KERN_NOTICE "Local APIC not detected."
1002 " Using dummy APIC emulation.\n");
1007 * Should not be necessary because the MP table should list the boot
1008 * CPU too, but we do it for the sake of robustness anyway.
1010 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1012 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1013 boot_cpu_physical_apicid);
1014 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1019 * If we couldn't find a local APIC, then get out of here now!
1021 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1023 if (!disable_apic) {
1024 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1025 boot_cpu_physical_apicid);
1026 pr_err("... forcing use of dummy APIC emulation."
1027 "(tell your hw vendor)\n");
1029 smpboot_clear_io_apic();
1030 arch_disable_smp_support();
1034 verify_local_APIC();
1037 * If SMP should be disabled, then really disable it!
1040 printk(KERN_INFO "SMP mode deactivated.\n");
1041 smpboot_clear_io_apic();
1045 bsp_end_local_APIC_setup();
1052 static void __init smp_cpu_index_default(void)
1055 struct cpuinfo_x86 *c;
1057 for_each_possible_cpu(i) {
1059 /* mark all to hotplug */
1060 c->cpu_index = nr_cpu_ids;
1065 * Prepare for SMP bootup. The MP table or ACPI has been read
1066 * earlier. Just do some sanity checking here and enable APIC mode.
1068 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1073 smp_cpu_index_default();
1076 * Setup boot CPU information
1078 smp_store_cpu_info(0); /* Final full version of the data */
1079 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1081 #ifdef CONFIG_X86_32
1082 boot_cpu_logical_apicid = logical_smp_processor_id();
1084 current_thread_info()->cpu = 0; /* needed? */
1085 for_each_possible_cpu(i) {
1086 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1087 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1088 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1090 set_cpu_sibling_map(0);
1093 if (smp_sanity_check(max_cpus) < 0) {
1094 printk(KERN_INFO "SMP disabled\n");
1099 default_setup_apic_routing();
1102 if (read_apic_id() != boot_cpu_physical_apicid) {
1103 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1104 read_apic_id(), boot_cpu_physical_apicid);
1105 /* Or can we switch back to PIC here? */
1112 * Switch from PIC to APIC mode.
1117 * Enable IO APIC before setting up error vector
1119 if (!skip_ioapic_setup && nr_ioapics)
1122 bsp_end_local_APIC_setup();
1124 map_cpu_to_logical_apicid();
1126 if (apic->setup_portio_remap)
1127 apic->setup_portio_remap();
1129 smpboot_setup_io_apic();
1131 * Set up local APIC timer on boot CPU.
1134 printk(KERN_INFO "CPU%d: ", 0);
1135 print_cpu_info(&cpu_data(0));
1136 x86_init.timers.setup_percpu_clockev();
1141 set_mtrr_aps_delayed_init();
1146 void arch_disable_nonboot_cpus_begin(void)
1149 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1150 * In the suspend path, we will be back in the SMP mode shortly anyways.
1152 skip_smp_alternatives = true;
1155 void arch_disable_nonboot_cpus_end(void)
1157 skip_smp_alternatives = false;
1160 void arch_enable_nonboot_cpus_begin(void)
1162 set_mtrr_aps_delayed_init();
1165 void arch_enable_nonboot_cpus_end(void)
1171 * Early setup to make printk work.
1173 void __init native_smp_prepare_boot_cpu(void)
1175 int me = smp_processor_id();
1176 switch_to_new_gdt(me);
1177 /* already set me in cpu_online_mask in boot_cpu_init() */
1178 cpumask_set_cpu(me, cpu_callout_mask);
1179 per_cpu(cpu_state, me) = CPU_ONLINE;
1182 void __init native_smp_cpus_done(unsigned int max_cpus)
1184 pr_debug("Boot done.\n");
1187 #ifdef CONFIG_X86_IO_APIC
1188 setup_ioapic_dest();
1193 static int __initdata setup_possible_cpus = -1;
1194 static int __init _setup_possible_cpus(char *str)
1196 get_option(&str, &setup_possible_cpus);
1199 early_param("possible_cpus", _setup_possible_cpus);
1203 * cpu_possible_mask should be static, it cannot change as cpu's
1204 * are onlined, or offlined. The reason is per-cpu data-structures
1205 * are allocated by some modules at init time, and dont expect to
1206 * do this dynamically on cpu arrival/departure.
1207 * cpu_present_mask on the other hand can change dynamically.
1208 * In case when cpu_hotplug is not compiled, then we resort to current
1209 * behaviour, which is cpu_possible == cpu_present.
1212 * Three ways to find out the number of additional hotplug CPUs:
1213 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1214 * - The user can overwrite it with possible_cpus=NUM
1215 * - Otherwise don't reserve additional CPUs.
1216 * We do this because additional CPUs waste a lot of memory.
1219 __init void prefill_possible_map(void)
1223 /* no processor from mptable or madt */
1224 if (!num_processors)
1227 i = setup_max_cpus ?: 1;
1228 if (setup_possible_cpus == -1) {
1229 possible = num_processors;
1230 #ifdef CONFIG_HOTPLUG_CPU
1232 possible += disabled_cpus;
1238 possible = setup_possible_cpus;
1240 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1242 /* nr_cpu_ids could be reduced via nr_cpus= */
1243 if (possible > nr_cpu_ids) {
1245 "%d Processors exceeds NR_CPUS limit of %d\n",
1246 possible, nr_cpu_ids);
1247 possible = nr_cpu_ids;
1250 #ifdef CONFIG_HOTPLUG_CPU
1251 if (!setup_max_cpus)
1255 "%d Processors exceeds max_cpus limit of %u\n",
1256 possible, setup_max_cpus);
1260 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1261 possible, max_t(int, possible - num_processors, 0));
1263 for (i = 0; i < possible; i++)
1264 set_cpu_possible(i, true);
1265 for (; i < NR_CPUS; i++)
1266 set_cpu_possible(i, false);
1268 nr_cpu_ids = possible;
1271 #ifdef CONFIG_HOTPLUG_CPU
1273 static void remove_siblinginfo(int cpu)
1276 struct cpuinfo_x86 *c = &cpu_data(cpu);
1278 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1279 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1281 * last thread sibling in this cpu core going down
1283 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1284 cpu_data(sibling).booted_cores--;
1287 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1288 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1289 cpumask_clear(cpu_sibling_mask(cpu));
1290 cpumask_clear(cpu_core_mask(cpu));
1291 c->phys_proc_id = 0;
1293 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1296 static void __ref remove_cpu_from_maps(int cpu)
1298 set_cpu_online(cpu, false);
1299 cpumask_clear_cpu(cpu, cpu_callout_mask);
1300 cpumask_clear_cpu(cpu, cpu_callin_mask);
1301 /* was set by cpu_init() */
1302 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1303 numa_remove_cpu(cpu);
1306 void cpu_disable_common(void)
1308 int cpu = smp_processor_id();
1310 remove_siblinginfo(cpu);
1312 /* It's now safe to remove this processor from the online map */
1314 remove_cpu_from_maps(cpu);
1315 unlock_vector_lock();
1319 int native_cpu_disable(void)
1321 int cpu = smp_processor_id();
1324 * Perhaps use cpufreq to drop frequency, but that could go
1325 * into generic code.
1327 * We won't take down the boot processor on i386 due to some
1328 * interrupts only being able to be serviced by the BSP.
1329 * Especially so if we're not using an IOAPIC -zwane
1336 cpu_disable_common();
1340 void native_cpu_die(unsigned int cpu)
1342 /* We don't do anything here: idle task is faking death itself. */
1345 for (i = 0; i < 10; i++) {
1346 /* They ack this in play_dead by setting CPU_DEAD */
1347 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1348 if (system_state == SYSTEM_RUNNING)
1349 pr_info("CPU %u is now offline\n", cpu);
1351 if (1 == num_online_cpus())
1352 alternatives_smp_switch(0);
1357 pr_err("CPU %u didn't die...\n", cpu);
1360 void play_dead_common(void)
1363 reset_lazy_tlbstate();
1364 c1e_remove_cpu(raw_smp_processor_id());
1368 __this_cpu_write(cpu_state, CPU_DEAD);
1371 * With physical CPU hotplug, we should halt the cpu
1373 local_irq_disable();
1377 * We need to flush the caches before going to sleep, lest we have
1378 * dirty data in our caches when we come back up.
1380 static inline void mwait_play_dead(void)
1382 unsigned int eax, ebx, ecx, edx;
1383 unsigned int highest_cstate = 0;
1384 unsigned int highest_subcstate = 0;
1387 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1389 if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)))
1391 if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH))
1393 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1396 eax = CPUID_MWAIT_LEAF;
1398 native_cpuid(&eax, &ebx, &ecx, &edx);
1401 * eax will be 0 if EDX enumeration is not valid.
1402 * Initialized below to cstate, sub_cstate value when EDX is valid.
1404 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1407 edx >>= MWAIT_SUBSTATE_SIZE;
1408 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1409 if (edx & MWAIT_SUBSTATE_MASK) {
1411 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1414 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1415 (highest_subcstate - 1);
1419 * This should be a memory location in a cache line which is
1420 * unlikely to be touched by other processors. The actual
1421 * content is immaterial as it is not actually modified in any way.
1423 mwait_ptr = ¤t_thread_info()->flags;
1429 * The CLFLUSH is a workaround for erratum AAI65 for
1430 * the Xeon 7400 series. It's not clear it is actually
1431 * needed, but it should be harmless in either case.
1432 * The WBINVD is insufficient due to the spurious-wakeup
1433 * case where we return around the loop.
1436 __monitor(mwait_ptr, 0, 0);
1442 static inline void hlt_play_dead(void)
1444 if (__this_cpu_read(cpu_info.x86) >= 4)
1452 void native_play_dead(void)
1455 tboot_shutdown(TB_SHUTDOWN_WFS);
1457 mwait_play_dead(); /* Only returns on failure */
1461 #else /* ... !CONFIG_HOTPLUG_CPU */
1462 int native_cpu_disable(void)
1467 void native_cpu_die(unsigned int cpu)
1469 /* We said "no" in __cpu_disable */
1473 void native_play_dead(void)