2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/smpboot_hooks.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* State of each CPU */
82 DEFINE_PER_CPU(int, cpu_state) = { 0 };
84 /* Number of siblings per CPU package */
85 int smp_num_siblings = 1;
86 EXPORT_SYMBOL(smp_num_siblings);
88 /* Last level cache ID of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
101 /* Per CPU bogomips and other parameters */
102 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
103 EXPORT_PER_CPU_SYMBOL(cpu_info);
105 atomic_t init_deasserted;
108 * Report back to the Boot Processor during boot time or to the caller processor
111 static void smp_callin(void)
114 unsigned long timeout;
117 * If waken up by an INIT in an 82489DX configuration
118 * we may get here before an INIT-deassert IPI reaches
119 * our local APIC. We have to wait for the IPI or we'll
120 * lock up on an APIC access.
122 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
124 cpuid = smp_processor_id();
125 if (apic->wait_for_init_deassert && cpuid)
126 while (!atomic_read(&init_deasserted))
130 * (This works even if the APIC is not enabled.)
132 phys_id = read_apic_id();
133 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
134 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
137 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
140 * STARTUP IPIs are fragile beasts as they might sometimes
141 * trigger some glue motherboard logic. Complete APIC bus
142 * silence for 1 second, this overestimates the time the
143 * boot CPU is spending to send the up to 2 STARTUP IPIs
144 * by a factor of two. This should be enough.
148 * Waiting 2s total for startup (udelay is not yet working)
150 timeout = jiffies + 2*HZ;
151 while (time_before(jiffies, timeout)) {
153 * Has the boot CPU finished it's STARTUP sequence?
155 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
160 if (!time_before(jiffies, timeout)) {
161 panic("%s: CPU%d started up but did not get a callout!\n",
166 * the boot CPU has finished the init stage and is spinning
167 * on callin_map until we finish. We are free to set up this
168 * CPU, first the APIC. (this is probably redundant on most
172 pr_debug("CALLIN, before setup_local_APIC()\n");
173 if (apic->smp_callin_clear_local_apic)
174 apic->smp_callin_clear_local_apic();
176 end_local_APIC_setup();
179 * Need to setup vector mappings before we enable interrupts.
181 setup_vector_irq(smp_processor_id());
184 * Save our processor parameters. Note: this information
185 * is needed for clock calibration.
187 smp_store_cpu_info(cpuid);
191 * Update loops_per_jiffy in cpu_data. Previous call to
192 * smp_store_cpu_info() stored a value that is close but not as
193 * accurate as the value just calculated.
196 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
197 pr_debug("Stack at about %p\n", &cpuid);
200 * This must be done before setting cpu_online_mask
201 * or calling notify_cpu_starting.
203 set_cpu_sibling_map(raw_smp_processor_id());
206 notify_cpu_starting(cpuid);
209 * Allow the master to continue.
211 cpumask_set_cpu(cpuid, cpu_callin_mask);
214 static int cpu0_logical_apicid;
215 static int enable_start_cpu0;
217 * Activate a secondary processor.
219 static void notrace start_secondary(void *unused)
222 * Don't put *anything* before cpu_init(), SMP booting is too
223 * fragile that we want to limit the things done here to the
224 * most necessary things.
227 x86_cpuinit.early_percpu_clock_init();
231 enable_start_cpu0 = 0;
234 /* switch away from the initial page table */
235 load_cr3(swapper_pg_dir);
239 /* otherwise gcc will move up smp_processor_id before the cpu_init */
242 * Check TSC synchronization with the BP:
244 check_tsc_sync_target();
247 * Enable the espfix hack for this CPU
249 #ifdef CONFIG_X86_ESPFIX64
254 * We need to hold vector_lock so there the set of online cpus
255 * does not change while we are assigning vectors to cpus. Holding
256 * this lock ensures we don't half assign or remove an irq from a cpu.
259 set_cpu_online(smp_processor_id(), true);
260 unlock_vector_lock();
261 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
262 x86_platform.nmi_init();
264 /* enable local interrupts */
267 /* to prevent fake stack check failure in clock setup */
268 boot_init_stack_canary();
270 x86_cpuinit.setup_percpu_clockev();
273 cpu_startup_entry(CPUHP_ONLINE);
276 void __init smp_store_boot_cpu_info(void)
278 int id = 0; /* CPU 0 */
279 struct cpuinfo_x86 *c = &cpu_data(id);
286 * The bootstrap kernel entry code has set these up. Save them for
289 void smp_store_cpu_info(int id)
291 struct cpuinfo_x86 *c = &cpu_data(id);
296 * During boot time, CPU0 has this setup already. Save the info when
297 * bringing up AP or offlined CPU0.
299 identify_secondary_cpu(c);
303 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
305 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
307 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
308 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
309 "[node: %d != %d]. Ignoring dependency.\n",
310 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
313 #define link_mask(_m, c1, c2) \
315 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
316 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
319 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
321 if (cpu_has_topoext) {
322 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
324 if (c->phys_proc_id == o->phys_proc_id &&
325 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
326 c->compute_unit_id == o->compute_unit_id)
327 return topology_sane(c, o, "smt");
329 } else if (c->phys_proc_id == o->phys_proc_id &&
330 c->cpu_core_id == o->cpu_core_id) {
331 return topology_sane(c, o, "smt");
337 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
339 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
341 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
342 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
343 return topology_sane(c, o, "llc");
348 static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
350 if (c->phys_proc_id == o->phys_proc_id) {
351 if (cpu_has(c, X86_FEATURE_AMD_DCM))
354 return topology_sane(c, o, "mc");
359 void set_cpu_sibling_map(int cpu)
361 bool has_smt = smp_num_siblings > 1;
362 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
363 struct cpuinfo_x86 *c = &cpu_data(cpu);
364 struct cpuinfo_x86 *o;
367 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
370 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
371 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
372 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
377 for_each_cpu(i, cpu_sibling_setup_mask) {
380 if ((i == cpu) || (has_smt && match_smt(c, o)))
381 link_mask(sibling, cpu, i);
383 if ((i == cpu) || (has_mp && match_llc(c, o)))
384 link_mask(llc_shared, cpu, i);
389 * This needs a separate iteration over the cpus because we rely on all
390 * cpu_sibling_mask links to be set-up.
392 for_each_cpu(i, cpu_sibling_setup_mask) {
395 if ((i == cpu) || (has_mp && match_mc(c, o))) {
396 link_mask(core, cpu, i);
399 * Does this new cpu bringup a new core?
401 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
403 * for each core in package, increment
404 * the booted_cores for this new cpu
406 if (cpumask_first(cpu_sibling_mask(i)) == i)
409 * increment the core count for all
410 * the other cpus in this package
413 cpu_data(i).booted_cores++;
414 } else if (i != cpu && !c->booted_cores)
415 c->booted_cores = cpu_data(i).booted_cores;
420 /* maps the cpu to the sched domain representing multi-core */
421 const struct cpumask *cpu_coregroup_mask(int cpu)
423 return cpu_llc_shared_mask(cpu);
426 static void impress_friends(void)
429 unsigned long bogosum = 0;
431 * Allow the user to impress friends.
433 pr_debug("Before bogomips\n");
434 for_each_possible_cpu(cpu)
435 if (cpumask_test_cpu(cpu, cpu_callout_mask))
436 bogosum += cpu_data(cpu).loops_per_jiffy;
437 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
440 (bogosum/(5000/HZ))%100);
442 pr_debug("Before bogocount - setting activated=1\n");
445 void __inquire_remote_apic(int apicid)
447 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
448 const char * const names[] = { "ID", "VERSION", "SPIV" };
452 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
454 for (i = 0; i < ARRAY_SIZE(regs); i++) {
455 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
460 status = safe_apic_wait_icr_idle();
462 pr_cont("a previous APIC delivery may have failed\n");
464 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
469 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
470 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
473 case APIC_ICR_RR_VALID:
474 status = apic_read(APIC_RRR);
475 pr_cont("%08x\n", status);
484 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
485 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
486 * won't ... remember to clear down the APIC, etc later.
489 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
491 unsigned long send_status, accept_status = 0;
495 /* Boot on the stack */
496 /* Kick the second */
497 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
499 pr_debug("Waiting for send to finish...\n");
500 send_status = safe_apic_wait_icr_idle();
503 * Give the other CPU some time to accept the IPI.
506 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
507 maxlvt = lapic_get_maxlvt();
508 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
509 apic_write(APIC_ESR, 0);
510 accept_status = (apic_read(APIC_ESR) & 0xEF);
512 pr_debug("NMI sent\n");
515 pr_err("APIC never delivered???\n");
517 pr_err("APIC delivery error (%lx)\n", accept_status);
519 return (send_status | accept_status);
523 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
525 unsigned long send_status, accept_status = 0;
526 int maxlvt, num_starts, j;
528 maxlvt = lapic_get_maxlvt();
531 * Be paranoid about clearing APIC errors.
533 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
534 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
535 apic_write(APIC_ESR, 0);
539 pr_debug("Asserting INIT\n");
542 * Turn INIT on target chip
547 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
550 pr_debug("Waiting for send to finish...\n");
551 send_status = safe_apic_wait_icr_idle();
555 pr_debug("Deasserting INIT\n");
559 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
561 pr_debug("Waiting for send to finish...\n");
562 send_status = safe_apic_wait_icr_idle();
565 atomic_set(&init_deasserted, 1);
568 * Should we send STARTUP IPIs ?
570 * Determine this based on the APIC version.
571 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
573 if (APIC_INTEGRATED(apic_version[phys_apicid]))
579 * Paravirt / VMI wants a startup IPI hook here to set up the
580 * target processor state.
582 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
586 * Run STARTUP IPI loop.
588 pr_debug("#startup loops: %d\n", num_starts);
590 for (j = 1; j <= num_starts; j++) {
591 pr_debug("Sending STARTUP #%d\n", j);
592 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
593 apic_write(APIC_ESR, 0);
595 pr_debug("After apic_write\n");
602 /* Boot on the stack */
603 /* Kick the second */
604 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
608 * Give the other CPU some time to accept the IPI.
612 pr_debug("Startup point 1\n");
614 pr_debug("Waiting for send to finish...\n");
615 send_status = safe_apic_wait_icr_idle();
618 * Give the other CPU some time to accept the IPI.
621 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
622 apic_write(APIC_ESR, 0);
623 accept_status = (apic_read(APIC_ESR) & 0xEF);
624 if (send_status || accept_status)
627 pr_debug("After Startup\n");
630 pr_err("APIC never delivered???\n");
632 pr_err("APIC delivery error (%lx)\n", accept_status);
634 return (send_status | accept_status);
637 void smp_announce(void)
639 int num_nodes = num_online_nodes();
641 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
642 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
645 /* reduce the number of lines printed when booting a large cpu count system */
646 static void announce_cpu(int cpu, int apicid)
648 static int current_node = -1;
649 int node = early_cpu_to_node(cpu);
650 static int width, node_width;
653 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
656 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
659 printk(KERN_INFO "x86: Booting SMP configuration:\n");
661 if (system_state == SYSTEM_BOOTING) {
662 if (node != current_node) {
663 if (current_node > (-1))
667 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
668 node_width - num_digits(node), " ", node);
671 /* Add padding for the BSP */
673 pr_cont("%*s", width + 1, " ");
675 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
678 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
682 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
686 cpu = smp_processor_id();
687 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
694 * Wake up AP by INIT, INIT, STARTUP sequence.
696 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
697 * boot-strap code which is not a desired behavior for waking up BSP. To
698 * void the boot-strap code, wake up CPU0 by NMI instead.
700 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
701 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
702 * We'll change this code in the future to wake up hard offlined CPU0 if
703 * real platform and request are available.
706 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
707 int *cpu0_nmi_registered)
715 * Wake up AP by INIT, INIT, STARTUP sequence.
718 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
723 * Wake up BSP by nmi.
725 * Register a NMI handler to help wake up CPU0.
727 boot_error = register_nmi_handler(NMI_LOCAL,
728 wakeup_cpu0_nmi, 0, "wake_cpu0");
731 enable_start_cpu0 = 1;
732 *cpu0_nmi_registered = 1;
733 if (apic->dest_logical == APIC_DEST_LOGICAL)
734 id = cpu0_logical_apicid;
737 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
747 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
748 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
749 * Returns zero if CPU booted OK, else error code from
750 * ->wakeup_secondary_cpu.
752 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
754 volatile u32 *trampoline_status =
755 (volatile u32 *) __va(real_mode_header->trampoline_status);
756 /* start_ip had better be page-aligned! */
757 unsigned long start_ip = real_mode_header->trampoline_start;
759 unsigned long boot_error = 0;
761 int cpu0_nmi_registered = 0;
763 /* Just in case we booted with a single CPU. */
764 alternatives_enable_smp();
766 idle->thread.sp = (unsigned long) (((struct pt_regs *)
767 (THREAD_SIZE + task_stack_page(idle))) - 1);
768 per_cpu(current_task, cpu) = idle;
771 /* Stack for startup_32 can be just as for start_secondary onwards */
774 clear_tsk_thread_flag(idle, TIF_FORK);
775 initial_gs = per_cpu_offset(cpu);
777 per_cpu(kernel_stack, cpu) =
778 (unsigned long)task_stack_page(idle) -
779 KERNEL_STACK_OFFSET + THREAD_SIZE;
780 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
781 initial_code = (unsigned long)start_secondary;
782 stack_start = idle->thread.sp;
784 /* So we see what's up */
785 announce_cpu(cpu, apicid);
788 * This grunge runs the startup process for
789 * the targeted processor.
792 atomic_set(&init_deasserted, 0);
794 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
796 pr_debug("Setting warm reset code and vector.\n");
798 smpboot_setup_warm_reset_vector(start_ip);
800 * Be paranoid about clearing APIC errors.
802 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
803 apic_write(APIC_ESR, 0);
809 * Wake up a CPU in difference cases:
810 * - Use the method in the APIC driver if it's defined
812 * - Use an INIT boot APIC message for APs or NMI for BSP.
814 if (apic->wakeup_secondary_cpu)
815 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
817 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
818 &cpu0_nmi_registered);
822 * allow APs to start initializing.
824 pr_debug("Before Callout %d\n", cpu);
825 cpumask_set_cpu(cpu, cpu_callout_mask);
826 pr_debug("After Callout %d\n", cpu);
829 * Wait 5s total for a response
831 for (timeout = 0; timeout < 50000; timeout++) {
832 if (cpumask_test_cpu(cpu, cpu_callin_mask))
833 break; /* It has booted */
836 * Allow other tasks to run while we wait for the
837 * AP to come online. This also gives a chance
838 * for the MTRR work(triggered by the AP coming online)
839 * to be completed in the stop machine context.
844 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
845 print_cpu_msr(&cpu_data(cpu));
846 pr_debug("CPU%d: has booted.\n", cpu);
849 if (*trampoline_status == 0xA5A5A5A5)
850 /* trampoline started but...? */
851 pr_err("CPU%d: Stuck ??\n", cpu);
853 /* trampoline code not run */
854 pr_err("CPU%d: Not responding\n", cpu);
855 if (apic->inquire_remote_apic)
856 apic->inquire_remote_apic(apicid);
861 /* Try to put things back the way they were before ... */
862 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
864 /* was set by do_boot_cpu() */
865 cpumask_clear_cpu(cpu, cpu_callout_mask);
867 /* was set by cpu_init() */
868 cpumask_clear_cpu(cpu, cpu_initialized_mask);
871 /* mark "stuck" area as not stuck */
872 *trampoline_status = 0;
874 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
876 * Cleanup possible dangling ends...
878 smpboot_restore_warm_reset_vector();
881 * Clean up the nmi handler. Do this after the callin and callout sync
882 * to avoid impact of possible long unregister time.
884 if (cpu0_nmi_registered)
885 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
890 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
892 int apicid = apic->cpu_present_to_apicid(cpu);
896 WARN_ON(irqs_disabled());
898 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
900 if (apicid == BAD_APICID ||
901 !physid_isset(apicid, phys_cpu_present_map) ||
902 !apic->apic_id_valid(apicid)) {
903 pr_err("%s: bad cpu %d\n", __func__, cpu);
908 * Already booted CPU?
910 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
911 pr_debug("do_boot_cpu %d Already started\n", cpu);
916 * Save current MTRR state in case it was changed since early boot
917 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
921 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
923 /* the FPU context is blank, nobody can own it */
924 __cpu_disable_lazy_restore(cpu);
926 err = do_boot_cpu(apicid, cpu, tidle);
928 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
933 * Check TSC synchronization with the AP (keep irqs disabled
936 local_irq_save(flags);
937 check_tsc_sync_source(cpu);
938 local_irq_restore(flags);
940 while (!cpu_online(cpu)) {
942 touch_nmi_watchdog();
949 * arch_disable_smp_support() - disables SMP support for x86 at runtime
951 void arch_disable_smp_support(void)
953 disable_ioapic_support();
957 * Fall back to non SMP mode after errors.
959 * RED-PEN audit/test this more. I bet there is more state messed up here.
961 static __init void disable_smp(void)
963 init_cpu_present(cpumask_of(0));
964 init_cpu_possible(cpumask_of(0));
965 smpboot_clear_io_apic_irqs();
967 if (smp_found_config)
968 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
970 physid_set_mask_of_physid(0, &phys_cpu_present_map);
971 cpumask_set_cpu(0, cpu_sibling_mask(0));
972 cpumask_set_cpu(0, cpu_core_mask(0));
976 * Various sanity checks.
978 static int __init smp_sanity_check(unsigned max_cpus)
982 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
983 if (def_to_bigsmp && nr_cpu_ids > 8) {
987 pr_warn("More than 8 CPUs detected - skipping them\n"
988 "Use CONFIG_X86_BIGSMP\n");
991 for_each_present_cpu(cpu) {
993 set_cpu_present(cpu, false);
998 for_each_possible_cpu(cpu) {
1000 set_cpu_possible(cpu, false);
1008 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1009 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1010 hard_smp_processor_id());
1012 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1016 * If we couldn't find an SMP configuration at boot time,
1017 * get out of here now!
1019 if (!smp_found_config && !acpi_lapic) {
1021 pr_notice("SMP motherboard not detected\n");
1023 if (APIC_init_uniprocessor())
1024 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1029 * Should not be necessary because the MP table should list the boot
1030 * CPU too, but we do it for the sake of robustness anyway.
1032 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1033 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1034 boot_cpu_physical_apicid);
1035 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1040 * If we couldn't find a local APIC, then get out of here now!
1042 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1044 if (!disable_apic) {
1045 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1046 boot_cpu_physical_apicid);
1047 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1049 smpboot_clear_io_apic();
1050 disable_ioapic_support();
1054 verify_local_APIC();
1057 * If SMP should be disabled, then really disable it!
1060 pr_info("SMP mode deactivated\n");
1061 smpboot_clear_io_apic();
1065 bsp_end_local_APIC_setup();
1072 static void __init smp_cpu_index_default(void)
1075 struct cpuinfo_x86 *c;
1077 for_each_possible_cpu(i) {
1079 /* mark all to hotplug */
1080 c->cpu_index = nr_cpu_ids;
1085 * Prepare for SMP bootup. The MP table or ACPI has been read
1086 * earlier. Just do some sanity checking here and enable APIC mode.
1088 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1093 smp_cpu_index_default();
1096 * Setup boot CPU information
1098 smp_store_boot_cpu_info(); /* Final full version of the data */
1099 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1102 current_thread_info()->cpu = 0; /* needed? */
1103 for_each_possible_cpu(i) {
1104 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1105 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1106 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1108 set_cpu_sibling_map(0);
1111 if (smp_sanity_check(max_cpus) < 0) {
1112 pr_info("SMP disabled\n");
1117 default_setup_apic_routing();
1120 if (read_apic_id() != boot_cpu_physical_apicid) {
1121 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1122 read_apic_id(), boot_cpu_physical_apicid);
1123 /* Or can we switch back to PIC here? */
1130 * Switch from PIC to APIC mode.
1135 cpu0_logical_apicid = apic_read(APIC_LDR);
1137 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1140 * Enable IO APIC before setting up error vector
1142 if (!skip_ioapic_setup && nr_ioapics)
1145 bsp_end_local_APIC_setup();
1147 if (apic->setup_portio_remap)
1148 apic->setup_portio_remap();
1150 smpboot_setup_io_apic();
1152 * Set up local APIC timer on boot CPU.
1155 pr_info("CPU%d: ", 0);
1156 print_cpu_info(&cpu_data(0));
1157 x86_init.timers.setup_percpu_clockev();
1162 set_mtrr_aps_delayed_init();
1167 void arch_enable_nonboot_cpus_begin(void)
1169 set_mtrr_aps_delayed_init();
1172 void arch_enable_nonboot_cpus_end(void)
1178 * Early setup to make printk work.
1180 void __init native_smp_prepare_boot_cpu(void)
1182 int me = smp_processor_id();
1183 switch_to_new_gdt(me);
1184 /* already set me in cpu_online_mask in boot_cpu_init() */
1185 cpumask_set_cpu(me, cpu_callout_mask);
1186 per_cpu(cpu_state, me) = CPU_ONLINE;
1189 void __init native_smp_cpus_done(unsigned int max_cpus)
1191 pr_debug("Boot done\n");
1195 #ifdef CONFIG_X86_IO_APIC
1196 setup_ioapic_dest();
1201 static int __initdata setup_possible_cpus = -1;
1202 static int __init _setup_possible_cpus(char *str)
1204 get_option(&str, &setup_possible_cpus);
1207 early_param("possible_cpus", _setup_possible_cpus);
1211 * cpu_possible_mask should be static, it cannot change as cpu's
1212 * are onlined, or offlined. The reason is per-cpu data-structures
1213 * are allocated by some modules at init time, and dont expect to
1214 * do this dynamically on cpu arrival/departure.
1215 * cpu_present_mask on the other hand can change dynamically.
1216 * In case when cpu_hotplug is not compiled, then we resort to current
1217 * behaviour, which is cpu_possible == cpu_present.
1220 * Three ways to find out the number of additional hotplug CPUs:
1221 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1222 * - The user can overwrite it with possible_cpus=NUM
1223 * - Otherwise don't reserve additional CPUs.
1224 * We do this because additional CPUs waste a lot of memory.
1227 __init void prefill_possible_map(void)
1231 /* no processor from mptable or madt */
1232 if (!num_processors)
1235 i = setup_max_cpus ?: 1;
1236 if (setup_possible_cpus == -1) {
1237 possible = num_processors;
1238 #ifdef CONFIG_HOTPLUG_CPU
1240 possible += disabled_cpus;
1246 possible = setup_possible_cpus;
1248 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1250 /* nr_cpu_ids could be reduced via nr_cpus= */
1251 if (possible > nr_cpu_ids) {
1252 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1253 possible, nr_cpu_ids);
1254 possible = nr_cpu_ids;
1257 #ifdef CONFIG_HOTPLUG_CPU
1258 if (!setup_max_cpus)
1261 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1262 possible, setup_max_cpus);
1266 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1267 possible, max_t(int, possible - num_processors, 0));
1269 for (i = 0; i < possible; i++)
1270 set_cpu_possible(i, true);
1271 for (; i < NR_CPUS; i++)
1272 set_cpu_possible(i, false);
1274 nr_cpu_ids = possible;
1277 #ifdef CONFIG_HOTPLUG_CPU
1279 static void remove_siblinginfo(int cpu)
1282 struct cpuinfo_x86 *c = &cpu_data(cpu);
1284 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1285 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1287 * last thread sibling in this cpu core going down
1289 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1290 cpu_data(sibling).booted_cores--;
1293 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1294 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1295 cpumask_clear(cpu_sibling_mask(cpu));
1296 cpumask_clear(cpu_core_mask(cpu));
1297 c->phys_proc_id = 0;
1299 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1302 static void __ref remove_cpu_from_maps(int cpu)
1304 set_cpu_online(cpu, false);
1305 cpumask_clear_cpu(cpu, cpu_callout_mask);
1306 cpumask_clear_cpu(cpu, cpu_callin_mask);
1307 /* was set by cpu_init() */
1308 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1309 numa_remove_cpu(cpu);
1312 void cpu_disable_common(void)
1314 int cpu = smp_processor_id();
1316 remove_siblinginfo(cpu);
1318 /* It's now safe to remove this processor from the online map */
1320 remove_cpu_from_maps(cpu);
1321 unlock_vector_lock();
1325 int native_cpu_disable(void)
1329 ret = check_irq_vectors_for_cpu_disable();
1335 cpu_disable_common();
1339 void native_cpu_die(unsigned int cpu)
1341 /* We don't do anything here: idle task is faking death itself. */
1344 for (i = 0; i < 10; i++) {
1345 /* They ack this in play_dead by setting CPU_DEAD */
1346 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1347 if (system_state == SYSTEM_RUNNING)
1348 pr_info("CPU %u is now offline\n", cpu);
1353 pr_err("CPU %u didn't die...\n", cpu);
1356 void play_dead_common(void)
1359 reset_lazy_tlbstate();
1360 amd_e400_remove_cpu(raw_smp_processor_id());
1364 __this_cpu_write(cpu_state, CPU_DEAD);
1367 * With physical CPU hotplug, we should halt the cpu
1369 local_irq_disable();
1372 static bool wakeup_cpu0(void)
1374 if (smp_processor_id() == 0 && enable_start_cpu0)
1381 * We need to flush the caches before going to sleep, lest we have
1382 * dirty data in our caches when we come back up.
1384 static inline void mwait_play_dead(void)
1386 unsigned int eax, ebx, ecx, edx;
1387 unsigned int highest_cstate = 0;
1388 unsigned int highest_subcstate = 0;
1392 if (!this_cpu_has(X86_FEATURE_MWAIT))
1394 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1396 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1399 eax = CPUID_MWAIT_LEAF;
1401 native_cpuid(&eax, &ebx, &ecx, &edx);
1404 * eax will be 0 if EDX enumeration is not valid.
1405 * Initialized below to cstate, sub_cstate value when EDX is valid.
1407 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1410 edx >>= MWAIT_SUBSTATE_SIZE;
1411 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1412 if (edx & MWAIT_SUBSTATE_MASK) {
1414 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1417 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1418 (highest_subcstate - 1);
1422 * This should be a memory location in a cache line which is
1423 * unlikely to be touched by other processors. The actual
1424 * content is immaterial as it is not actually modified in any way.
1426 mwait_ptr = ¤t_thread_info()->flags;
1432 * The CLFLUSH is a workaround for erratum AAI65 for
1433 * the Xeon 7400 series. It's not clear it is actually
1434 * needed, but it should be harmless in either case.
1435 * The WBINVD is insufficient due to the spurious-wakeup
1436 * case where we return around the loop.
1441 __monitor(mwait_ptr, 0, 0);
1445 * If NMI wants to wake up CPU0, start CPU0.
1452 static inline void hlt_play_dead(void)
1454 if (__this_cpu_read(cpu_info.x86) >= 4)
1460 * If NMI wants to wake up CPU0, start CPU0.
1467 void native_play_dead(void)
1470 tboot_shutdown(TB_SHUTDOWN_WFS);
1472 mwait_play_dead(); /* Only returns on failure */
1473 if (cpuidle_play_dead())
1477 #else /* ... !CONFIG_HOTPLUG_CPU */
1478 int native_cpu_disable(void)
1483 void native_cpu_die(unsigned int cpu)
1485 /* We said "no" in __cpu_disable */
1489 void native_play_dead(void)