2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
67 #include <asm/io_apic.h>
68 #include <asm/setup.h>
69 #include <asm/uv/uv.h>
70 #include <linux/mc146818rtc.h>
72 #include <asm/smpboot_hooks.h>
73 #include <asm/i8259.h>
76 u8 apicid_2_node[MAX_APICID];
79 /* State of each CPU */
80 DEFINE_PER_CPU(int, cpu_state) = { 0 };
82 /* Store all idle threads, this can be reused instead of creating
83 * a new thread. Also avoids complicated thread destroy functionality
86 #ifdef CONFIG_HOTPLUG_CPU
88 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
89 * removed after init for !CONFIG_HOTPLUG_CPU.
91 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
92 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
93 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
96 * We need this for trampoline_base protection from concurrent accesses when
97 * off- and onlining cores wildly.
99 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
101 void cpu_hotplug_driver_lock(void)
103 mutex_lock(&x86_cpu_hotplug_driver_mutex);
106 void cpu_hotplug_driver_unlock(void)
108 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
111 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
112 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
114 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
115 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
116 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
119 /* Number of siblings per CPU package */
120 int smp_num_siblings = 1;
121 EXPORT_SYMBOL(smp_num_siblings);
123 /* Last level cache ID of each logical CPU */
124 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
126 /* representing HT siblings of each logical CPU */
127 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
128 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
130 /* representing HT and core siblings of each logical CPU */
131 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
132 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
134 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
136 /* Per CPU bogomips and other parameters */
137 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
138 EXPORT_PER_CPU_SYMBOL(cpu_info);
140 atomic_t init_deasserted;
142 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
143 /* which node each logical CPU is on */
144 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
145 EXPORT_SYMBOL(cpu_to_node_map);
147 /* set up a mapping between cpu and node. */
148 static void map_cpu_to_node(int cpu, int node)
150 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
151 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
152 cpu_to_node_map[cpu] = node;
155 /* undo a mapping between cpu and node. */
156 static void unmap_cpu_to_node(int cpu)
160 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
161 for (node = 0; node < MAX_NUMNODES; node++)
162 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
163 cpu_to_node_map[cpu] = 0;
165 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
166 #define map_cpu_to_node(cpu, node) ({})
167 #define unmap_cpu_to_node(cpu) ({})
171 static int boot_cpu_logical_apicid;
173 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
174 { [0 ... NR_CPUS-1] = BAD_APICID };
176 static void map_cpu_to_logical_apicid(void)
178 int cpu = smp_processor_id();
179 int apicid = logical_smp_processor_id();
180 int node = apic->apicid_to_node(apicid);
182 if (!node_online(node))
183 node = first_online_node;
185 cpu_2_logical_apicid[cpu] = apicid;
186 map_cpu_to_node(cpu, node);
189 void numa_remove_cpu(int cpu)
191 cpu_2_logical_apicid[cpu] = BAD_APICID;
192 unmap_cpu_to_node(cpu);
195 #define map_cpu_to_logical_apicid() do {} while (0)
199 * Report back to the Boot Processor.
202 static void __cpuinit smp_callin(void)
205 unsigned long timeout;
208 * If waken up by an INIT in an 82489DX configuration
209 * we may get here before an INIT-deassert IPI reaches
210 * our local APIC. We have to wait for the IPI or we'll
211 * lock up on an APIC access.
213 if (apic->wait_for_init_deassert)
214 apic->wait_for_init_deassert(&init_deasserted);
217 * (This works even if the APIC is not enabled.)
219 phys_id = read_apic_id();
220 cpuid = smp_processor_id();
221 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
222 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
225 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
228 * STARTUP IPIs are fragile beasts as they might sometimes
229 * trigger some glue motherboard logic. Complete APIC bus
230 * silence for 1 second, this overestimates the time the
231 * boot CPU is spending to send the up to 2 STARTUP IPIs
232 * by a factor of two. This should be enough.
236 * Waiting 2s total for startup (udelay is not yet working)
238 timeout = jiffies + 2*HZ;
239 while (time_before(jiffies, timeout)) {
241 * Has the boot CPU finished it's STARTUP sequence?
243 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
248 if (!time_before(jiffies, timeout)) {
249 panic("%s: CPU%d started up but did not get a callout!\n",
254 * the boot CPU has finished the init stage and is spinning
255 * on callin_map until we finish. We are free to set up this
256 * CPU, first the APIC. (this is probably redundant on most
260 pr_debug("CALLIN, before setup_local_APIC().\n");
261 if (apic->smp_callin_clear_local_apic)
262 apic->smp_callin_clear_local_apic();
264 end_local_APIC_setup();
265 map_cpu_to_logical_apicid();
268 * Need to setup vector mappings before we enable interrupts.
270 setup_vector_irq(smp_processor_id());
274 * Need to enable IRQs because it can take longer and then
275 * the NMI watchdog might kill us.
280 pr_debug("Stack at about %p\n", &cpuid);
283 * Save our processor parameters
285 smp_store_cpu_info(cpuid);
288 * This must be done before setting cpu_online_mask
289 * or calling notify_cpu_starting.
291 set_cpu_sibling_map(raw_smp_processor_id());
294 notify_cpu_starting(cpuid);
297 * Allow the master to continue.
299 cpumask_set_cpu(cpuid, cpu_callin_mask);
303 * Activate a secondary processor.
305 notrace static void __cpuinit start_secondary(void *unused)
308 * Don't put *anything* before cpu_init(), SMP booting is too
309 * fragile that we want to limit the things done here to the
310 * most necessary things.
317 /* switch away from the initial page table */
318 load_cr3(swapper_pg_dir);
322 /* otherwise gcc will move up smp_processor_id before the cpu_init */
325 * Check TSC synchronization with the BP:
327 check_tsc_sync_target();
330 * We need to hold call_lock, so there is no inconsistency
331 * between the time smp_call_function() determines number of
332 * IPI recipients, and the time when the determination is made
333 * for which cpus receive the IPI. Holding this
334 * lock helps us to not include this cpu in a currently in progress
335 * smp_call_function().
337 * We need to hold vector_lock so there the set of online cpus
338 * does not change while we are assigning vectors to cpus. Holding
339 * this lock ensures we don't half assign or remove an irq from a cpu.
343 set_cpu_online(smp_processor_id(), true);
344 unlock_vector_lock();
346 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
347 x86_platform.nmi_init();
349 /* enable local interrupts */
352 /* to prevent fake stack check failure in clock setup */
353 boot_init_stack_canary();
355 x86_cpuinit.setup_percpu_clockev();
362 * The bootstrap kernel entry code has set these up. Save them for
366 void __cpuinit smp_store_cpu_info(int id)
368 struct cpuinfo_x86 *c = &cpu_data(id);
373 identify_secondary_cpu(c);
376 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
378 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
379 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
380 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
381 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
382 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
383 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
387 void __cpuinit set_cpu_sibling_map(int cpu)
390 struct cpuinfo_x86 *c = &cpu_data(cpu);
392 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
394 if (smp_num_siblings > 1) {
395 for_each_cpu(i, cpu_sibling_setup_mask) {
396 struct cpuinfo_x86 *o = &cpu_data(i);
398 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
399 if (c->phys_proc_id == o->phys_proc_id &&
400 c->compute_unit_id == o->compute_unit_id)
401 link_thread_siblings(cpu, i);
402 } else if (c->phys_proc_id == o->phys_proc_id &&
403 c->cpu_core_id == o->cpu_core_id) {
404 link_thread_siblings(cpu, i);
408 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
411 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
413 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
414 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
419 for_each_cpu(i, cpu_sibling_setup_mask) {
420 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
421 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
422 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
423 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
425 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
426 cpumask_set_cpu(i, cpu_core_mask(cpu));
427 cpumask_set_cpu(cpu, cpu_core_mask(i));
429 * Does this new cpu bringup a new core?
431 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
433 * for each core in package, increment
434 * the booted_cores for this new cpu
436 if (cpumask_first(cpu_sibling_mask(i)) == i)
439 * increment the core count for all
440 * the other cpus in this package
443 cpu_data(i).booted_cores++;
444 } else if (i != cpu && !c->booted_cores)
445 c->booted_cores = cpu_data(i).booted_cores;
450 /* maps the cpu to the sched domain representing multi-core */
451 const struct cpumask *cpu_coregroup_mask(int cpu)
453 struct cpuinfo_x86 *c = &cpu_data(cpu);
455 * For perf, we return last level cache shared map.
456 * And for power savings, we return cpu_core_map
458 if ((sched_mc_power_savings || sched_smt_power_savings) &&
459 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
460 return cpu_core_mask(cpu);
462 return cpu_llc_shared_mask(cpu);
465 static void impress_friends(void)
468 unsigned long bogosum = 0;
470 * Allow the user to impress friends.
472 pr_debug("Before bogomips.\n");
473 for_each_possible_cpu(cpu)
474 if (cpumask_test_cpu(cpu, cpu_callout_mask))
475 bogosum += cpu_data(cpu).loops_per_jiffy;
477 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
480 (bogosum/(5000/HZ))%100);
482 pr_debug("Before bogocount - setting activated=1.\n");
485 void __inquire_remote_apic(int apicid)
487 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
488 char *names[] = { "ID", "VERSION", "SPIV" };
492 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
494 for (i = 0; i < ARRAY_SIZE(regs); i++) {
495 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
500 status = safe_apic_wait_icr_idle();
503 "a previous APIC delivery may have failed\n");
505 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
510 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
511 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
514 case APIC_ICR_RR_VALID:
515 status = apic_read(APIC_RRR);
516 printk(KERN_CONT "%08x\n", status);
519 printk(KERN_CONT "failed\n");
525 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
526 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
527 * won't ... remember to clear down the APIC, etc later.
530 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
532 unsigned long send_status, accept_status = 0;
536 /* Boot on the stack */
537 /* Kick the second */
538 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
540 pr_debug("Waiting for send to finish...\n");
541 send_status = safe_apic_wait_icr_idle();
544 * Give the other CPU some time to accept the IPI.
547 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
548 maxlvt = lapic_get_maxlvt();
549 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
550 apic_write(APIC_ESR, 0);
551 accept_status = (apic_read(APIC_ESR) & 0xEF);
553 pr_debug("NMI sent.\n");
556 printk(KERN_ERR "APIC never delivered???\n");
558 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
560 return (send_status | accept_status);
564 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
566 unsigned long send_status, accept_status = 0;
567 int maxlvt, num_starts, j;
569 maxlvt = lapic_get_maxlvt();
572 * Be paranoid about clearing APIC errors.
574 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
575 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
576 apic_write(APIC_ESR, 0);
580 pr_debug("Asserting INIT.\n");
583 * Turn INIT on target chip
588 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
591 pr_debug("Waiting for send to finish...\n");
592 send_status = safe_apic_wait_icr_idle();
596 pr_debug("Deasserting INIT.\n");
600 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
602 pr_debug("Waiting for send to finish...\n");
603 send_status = safe_apic_wait_icr_idle();
606 atomic_set(&init_deasserted, 1);
609 * Should we send STARTUP IPIs ?
611 * Determine this based on the APIC version.
612 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
614 if (APIC_INTEGRATED(apic_version[phys_apicid]))
620 * Paravirt / VMI wants a startup IPI hook here to set up the
621 * target processor state.
623 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
627 * Run STARTUP IPI loop.
629 pr_debug("#startup loops: %d.\n", num_starts);
631 for (j = 1; j <= num_starts; j++) {
632 pr_debug("Sending STARTUP #%d.\n", j);
633 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
634 apic_write(APIC_ESR, 0);
636 pr_debug("After apic_write.\n");
643 /* Boot on the stack */
644 /* Kick the second */
645 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
649 * Give the other CPU some time to accept the IPI.
653 pr_debug("Startup point 1.\n");
655 pr_debug("Waiting for send to finish...\n");
656 send_status = safe_apic_wait_icr_idle();
659 * Give the other CPU some time to accept the IPI.
662 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
663 apic_write(APIC_ESR, 0);
664 accept_status = (apic_read(APIC_ESR) & 0xEF);
665 if (send_status || accept_status)
668 pr_debug("After Startup.\n");
671 printk(KERN_ERR "APIC never delivered???\n");
673 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
675 return (send_status | accept_status);
679 struct work_struct work;
680 struct task_struct *idle;
681 struct completion done;
685 static void __cpuinit do_fork_idle(struct work_struct *work)
687 struct create_idle *c_idle =
688 container_of(work, struct create_idle, work);
690 c_idle->idle = fork_idle(c_idle->cpu);
691 complete(&c_idle->done);
694 /* reduce the number of lines printed when booting a large cpu count system */
695 static void __cpuinit announce_cpu(int cpu, int apicid)
697 static int current_node = -1;
698 int node = early_cpu_to_node(cpu);
700 if (system_state == SYSTEM_BOOTING) {
701 if (node != current_node) {
702 if (current_node > (-1))
705 pr_info("Booting Node %3d, Processors ", node);
707 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
710 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
715 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
716 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
717 * Returns zero if CPU booted OK, else error code from
718 * ->wakeup_secondary_cpu.
720 static int __cpuinit do_boot_cpu(int apicid, int cpu)
722 unsigned long boot_error = 0;
723 unsigned long start_ip;
725 struct create_idle c_idle = {
727 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
730 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
732 alternatives_smp_switch(1);
734 c_idle.idle = get_idle_for_cpu(cpu);
737 * We can't use kernel_thread since we must avoid to
738 * reschedule the child.
741 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
742 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
743 init_idle(c_idle.idle, cpu);
747 schedule_work(&c_idle.work);
748 wait_for_completion(&c_idle.done);
750 if (IS_ERR(c_idle.idle)) {
751 printk("failed fork for CPU %d\n", cpu);
752 destroy_work_on_stack(&c_idle.work);
753 return PTR_ERR(c_idle.idle);
756 set_idle_for_cpu(cpu, c_idle.idle);
758 per_cpu(current_task, cpu) = c_idle.idle;
760 /* Stack for startup_32 can be just as for start_secondary onwards */
763 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
764 initial_gs = per_cpu_offset(cpu);
765 per_cpu(kernel_stack, cpu) =
766 (unsigned long)task_stack_page(c_idle.idle) -
767 KERNEL_STACK_OFFSET + THREAD_SIZE;
769 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
770 initial_code = (unsigned long)start_secondary;
771 stack_start = c_idle.idle->thread.sp;
773 /* start_ip had better be page-aligned! */
774 start_ip = setup_trampoline();
776 /* So we see what's up */
777 announce_cpu(cpu, apicid);
780 * This grunge runs the startup process for
781 * the targeted processor.
784 atomic_set(&init_deasserted, 0);
786 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
788 pr_debug("Setting warm reset code and vector.\n");
790 smpboot_setup_warm_reset_vector(start_ip);
792 * Be paranoid about clearing APIC errors.
794 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
795 apic_write(APIC_ESR, 0);
801 * Kick the secondary CPU. Use the method in the APIC driver
802 * if it's defined - or use an INIT boot APIC message otherwise:
804 if (apic->wakeup_secondary_cpu)
805 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
807 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
811 * allow APs to start initializing.
813 pr_debug("Before Callout %d.\n", cpu);
814 cpumask_set_cpu(cpu, cpu_callout_mask);
815 pr_debug("After Callout %d.\n", cpu);
818 * Wait 5s total for a response
820 for (timeout = 0; timeout < 50000; timeout++) {
821 if (cpumask_test_cpu(cpu, cpu_callin_mask))
822 break; /* It has booted */
825 * Allow other tasks to run while we wait for the
826 * AP to come online. This also gives a chance
827 * for the MTRR work(triggered by the AP coming online)
828 * to be completed in the stop machine context.
833 if (cpumask_test_cpu(cpu, cpu_callin_mask))
834 pr_debug("CPU%d: has booted.\n", cpu);
837 if (*((volatile unsigned char *)trampoline_base)
839 /* trampoline started but...? */
840 pr_err("CPU%d: Stuck ??\n", cpu);
842 /* trampoline code not run */
843 pr_err("CPU%d: Not responding.\n", cpu);
844 if (apic->inquire_remote_apic)
845 apic->inquire_remote_apic(apicid);
850 /* Try to put things back the way they were before ... */
851 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
853 /* was set by do_boot_cpu() */
854 cpumask_clear_cpu(cpu, cpu_callout_mask);
856 /* was set by cpu_init() */
857 cpumask_clear_cpu(cpu, cpu_initialized_mask);
859 set_cpu_present(cpu, false);
860 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
863 /* mark "stuck" area as not stuck */
864 *((volatile unsigned long *)trampoline_base) = 0;
866 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
868 * Cleanup possible dangling ends...
870 smpboot_restore_warm_reset_vector();
873 destroy_work_on_stack(&c_idle.work);
877 int __cpuinit native_cpu_up(unsigned int cpu)
879 int apicid = apic->cpu_present_to_apicid(cpu);
883 WARN_ON(irqs_disabled());
885 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
887 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
888 !physid_isset(apicid, phys_cpu_present_map)) {
889 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
894 * Already booted CPU?
896 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
897 pr_debug("do_boot_cpu %d Already started\n", cpu);
902 * Save current MTRR state in case it was changed since early boot
903 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
907 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
909 err = do_boot_cpu(apicid, cpu);
911 pr_debug("do_boot_cpu failed %d\n", err);
916 * Check TSC synchronization with the AP (keep irqs disabled
919 local_irq_save(flags);
920 check_tsc_sync_source(cpu);
921 local_irq_restore(flags);
923 while (!cpu_online(cpu)) {
925 touch_nmi_watchdog();
932 * arch_disable_smp_support() - disables SMP support for x86 at runtime
934 void arch_disable_smp_support(void)
936 disable_ioapic_support();
940 * Fall back to non SMP mode after errors.
942 * RED-PEN audit/test this more. I bet there is more state messed up here.
944 static __init void disable_smp(void)
946 init_cpu_present(cpumask_of(0));
947 init_cpu_possible(cpumask_of(0));
948 smpboot_clear_io_apic_irqs();
950 if (smp_found_config)
951 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
953 physid_set_mask_of_physid(0, &phys_cpu_present_map);
954 map_cpu_to_logical_apicid();
955 cpumask_set_cpu(0, cpu_sibling_mask(0));
956 cpumask_set_cpu(0, cpu_core_mask(0));
960 * Various sanity checks.
962 static int __init smp_sanity_check(unsigned max_cpus)
966 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
967 if (def_to_bigsmp && nr_cpu_ids > 8) {
972 "More than 8 CPUs detected - skipping them.\n"
973 "Use CONFIG_X86_BIGSMP.\n");
976 for_each_present_cpu(cpu) {
978 set_cpu_present(cpu, false);
983 for_each_possible_cpu(cpu) {
985 set_cpu_possible(cpu, false);
993 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
995 "weird, boot CPU (#%d) not listed by the BIOS.\n",
996 hard_smp_processor_id());
998 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1002 * If we couldn't find an SMP configuration at boot time,
1003 * get out of here now!
1005 if (!smp_found_config && !acpi_lapic) {
1007 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1009 if (APIC_init_uniprocessor())
1010 printk(KERN_NOTICE "Local APIC not detected."
1011 " Using dummy APIC emulation.\n");
1016 * Should not be necessary because the MP table should list the boot
1017 * CPU too, but we do it for the sake of robustness anyway.
1019 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1021 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1022 boot_cpu_physical_apicid);
1023 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1028 * If we couldn't find a local APIC, then get out of here now!
1030 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1032 if (!disable_apic) {
1033 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1034 boot_cpu_physical_apicid);
1035 pr_err("... forcing use of dummy APIC emulation."
1036 "(tell your hw vendor)\n");
1038 smpboot_clear_io_apic();
1039 disable_ioapic_support();
1043 verify_local_APIC();
1046 * If SMP should be disabled, then really disable it!
1049 printk(KERN_INFO "SMP mode deactivated.\n");
1050 smpboot_clear_io_apic();
1054 bsp_end_local_APIC_setup();
1061 static void __init smp_cpu_index_default(void)
1064 struct cpuinfo_x86 *c;
1066 for_each_possible_cpu(i) {
1068 /* mark all to hotplug */
1069 c->cpu_index = nr_cpu_ids;
1074 * Prepare for SMP bootup. The MP table or ACPI has been read
1075 * earlier. Just do some sanity checking here and enable APIC mode.
1077 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1082 smp_cpu_index_default();
1085 * Setup boot CPU information
1087 smp_store_cpu_info(0); /* Final full version of the data */
1088 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1090 #ifdef CONFIG_X86_32
1091 boot_cpu_logical_apicid = logical_smp_processor_id();
1093 current_thread_info()->cpu = 0; /* needed? */
1094 for_each_possible_cpu(i) {
1095 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1096 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1097 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1099 set_cpu_sibling_map(0);
1102 if (smp_sanity_check(max_cpus) < 0) {
1103 printk(KERN_INFO "SMP disabled\n");
1108 default_setup_apic_routing();
1111 if (read_apic_id() != boot_cpu_physical_apicid) {
1112 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1113 read_apic_id(), boot_cpu_physical_apicid);
1114 /* Or can we switch back to PIC here? */
1121 * Switch from PIC to APIC mode.
1126 * Enable IO APIC before setting up error vector
1128 if (!skip_ioapic_setup && nr_ioapics)
1131 bsp_end_local_APIC_setup();
1133 map_cpu_to_logical_apicid();
1135 if (apic->setup_portio_remap)
1136 apic->setup_portio_remap();
1138 smpboot_setup_io_apic();
1140 * Set up local APIC timer on boot CPU.
1143 printk(KERN_INFO "CPU%d: ", 0);
1144 print_cpu_info(&cpu_data(0));
1145 x86_init.timers.setup_percpu_clockev();
1150 set_mtrr_aps_delayed_init();
1155 void arch_disable_nonboot_cpus_begin(void)
1158 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1159 * In the suspend path, we will be back in the SMP mode shortly anyways.
1161 skip_smp_alternatives = true;
1164 void arch_disable_nonboot_cpus_end(void)
1166 skip_smp_alternatives = false;
1169 void arch_enable_nonboot_cpus_begin(void)
1171 set_mtrr_aps_delayed_init();
1174 void arch_enable_nonboot_cpus_end(void)
1180 * Early setup to make printk work.
1182 void __init native_smp_prepare_boot_cpu(void)
1184 int me = smp_processor_id();
1185 switch_to_new_gdt(me);
1186 /* already set me in cpu_online_mask in boot_cpu_init() */
1187 cpumask_set_cpu(me, cpu_callout_mask);
1188 per_cpu(cpu_state, me) = CPU_ONLINE;
1191 void __init native_smp_cpus_done(unsigned int max_cpus)
1193 pr_debug("Boot done.\n");
1196 #ifdef CONFIG_X86_IO_APIC
1197 setup_ioapic_dest();
1202 static int __initdata setup_possible_cpus = -1;
1203 static int __init _setup_possible_cpus(char *str)
1205 get_option(&str, &setup_possible_cpus);
1208 early_param("possible_cpus", _setup_possible_cpus);
1212 * cpu_possible_mask should be static, it cannot change as cpu's
1213 * are onlined, or offlined. The reason is per-cpu data-structures
1214 * are allocated by some modules at init time, and dont expect to
1215 * do this dynamically on cpu arrival/departure.
1216 * cpu_present_mask on the other hand can change dynamically.
1217 * In case when cpu_hotplug is not compiled, then we resort to current
1218 * behaviour, which is cpu_possible == cpu_present.
1221 * Three ways to find out the number of additional hotplug CPUs:
1222 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1223 * - The user can overwrite it with possible_cpus=NUM
1224 * - Otherwise don't reserve additional CPUs.
1225 * We do this because additional CPUs waste a lot of memory.
1228 __init void prefill_possible_map(void)
1232 /* no processor from mptable or madt */
1233 if (!num_processors)
1236 i = setup_max_cpus ?: 1;
1237 if (setup_possible_cpus == -1) {
1238 possible = num_processors;
1239 #ifdef CONFIG_HOTPLUG_CPU
1241 possible += disabled_cpus;
1247 possible = setup_possible_cpus;
1249 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1251 /* nr_cpu_ids could be reduced via nr_cpus= */
1252 if (possible > nr_cpu_ids) {
1254 "%d Processors exceeds NR_CPUS limit of %d\n",
1255 possible, nr_cpu_ids);
1256 possible = nr_cpu_ids;
1259 #ifdef CONFIG_HOTPLUG_CPU
1260 if (!setup_max_cpus)
1264 "%d Processors exceeds max_cpus limit of %u\n",
1265 possible, setup_max_cpus);
1269 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1270 possible, max_t(int, possible - num_processors, 0));
1272 for (i = 0; i < possible; i++)
1273 set_cpu_possible(i, true);
1274 for (; i < NR_CPUS; i++)
1275 set_cpu_possible(i, false);
1277 nr_cpu_ids = possible;
1280 #ifdef CONFIG_HOTPLUG_CPU
1282 static void remove_siblinginfo(int cpu)
1285 struct cpuinfo_x86 *c = &cpu_data(cpu);
1287 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1288 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1290 * last thread sibling in this cpu core going down
1292 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1293 cpu_data(sibling).booted_cores--;
1296 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1297 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1298 cpumask_clear(cpu_sibling_mask(cpu));
1299 cpumask_clear(cpu_core_mask(cpu));
1300 c->phys_proc_id = 0;
1302 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1305 static void __ref remove_cpu_from_maps(int cpu)
1307 set_cpu_online(cpu, false);
1308 cpumask_clear_cpu(cpu, cpu_callout_mask);
1309 cpumask_clear_cpu(cpu, cpu_callin_mask);
1310 /* was set by cpu_init() */
1311 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1312 numa_remove_cpu(cpu);
1315 void cpu_disable_common(void)
1317 int cpu = smp_processor_id();
1319 remove_siblinginfo(cpu);
1321 /* It's now safe to remove this processor from the online map */
1323 remove_cpu_from_maps(cpu);
1324 unlock_vector_lock();
1328 int native_cpu_disable(void)
1330 int cpu = smp_processor_id();
1333 * Perhaps use cpufreq to drop frequency, but that could go
1334 * into generic code.
1336 * We won't take down the boot processor on i386 due to some
1337 * interrupts only being able to be serviced by the BSP.
1338 * Especially so if we're not using an IOAPIC -zwane
1345 cpu_disable_common();
1349 void native_cpu_die(unsigned int cpu)
1351 /* We don't do anything here: idle task is faking death itself. */
1354 for (i = 0; i < 10; i++) {
1355 /* They ack this in play_dead by setting CPU_DEAD */
1356 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1357 if (system_state == SYSTEM_RUNNING)
1358 pr_info("CPU %u is now offline\n", cpu);
1360 if (1 == num_online_cpus())
1361 alternatives_smp_switch(0);
1366 pr_err("CPU %u didn't die...\n", cpu);
1369 void play_dead_common(void)
1372 reset_lazy_tlbstate();
1373 c1e_remove_cpu(raw_smp_processor_id());
1377 __this_cpu_write(cpu_state, CPU_DEAD);
1380 * With physical CPU hotplug, we should halt the cpu
1382 local_irq_disable();
1386 * We need to flush the caches before going to sleep, lest we have
1387 * dirty data in our caches when we come back up.
1389 static inline void mwait_play_dead(void)
1391 unsigned int eax, ebx, ecx, edx;
1392 unsigned int highest_cstate = 0;
1393 unsigned int highest_subcstate = 0;
1396 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1398 if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)))
1400 if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH))
1402 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1405 eax = CPUID_MWAIT_LEAF;
1407 native_cpuid(&eax, &ebx, &ecx, &edx);
1410 * eax will be 0 if EDX enumeration is not valid.
1411 * Initialized below to cstate, sub_cstate value when EDX is valid.
1413 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1416 edx >>= MWAIT_SUBSTATE_SIZE;
1417 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1418 if (edx & MWAIT_SUBSTATE_MASK) {
1420 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1423 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1424 (highest_subcstate - 1);
1428 * This should be a memory location in a cache line which is
1429 * unlikely to be touched by other processors. The actual
1430 * content is immaterial as it is not actually modified in any way.
1432 mwait_ptr = ¤t_thread_info()->flags;
1438 * The CLFLUSH is a workaround for erratum AAI65 for
1439 * the Xeon 7400 series. It's not clear it is actually
1440 * needed, but it should be harmless in either case.
1441 * The WBINVD is insufficient due to the spurious-wakeup
1442 * case where we return around the loop.
1445 __monitor(mwait_ptr, 0, 0);
1451 static inline void hlt_play_dead(void)
1453 if (__this_cpu_read(cpu_info.x86) >= 4)
1461 void native_play_dead(void)
1464 tboot_shutdown(TB_SHUTDOWN_WFS);
1466 mwait_play_dead(); /* Only returns on failure */
1470 #else /* ... !CONFIG_HOTPLUG_CPU */
1471 int native_cpu_disable(void)
1476 void native_cpu_die(unsigned int cpu)
1478 /* We said "no" in __cpu_disable */
1482 void native_play_dead(void)