arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  15 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  16
  17 /*
  18  * pebs_record_32 for p4 and core not supported
  19
  20 struct pebs_record_32 {
  21         u32 flags, ip;
  22         u32 ax, bc, cx, dx;
  23         u32 si, di, bp, sp;
  24 };
  25
  26  */
  27
  28 union intel_x86_pebs_dse {
  29         u64 val;
  30         struct {
  31                 unsigned int ld_dse:4;
  32                 unsigned int ld_stlb_miss:1;
  33                 unsigned int ld_locked:1;
  34                 unsigned int ld_reserved:26;
  35         };
  36         struct {
  37                 unsigned int st_l1d_hit:1;
  38                 unsigned int st_reserved1:3;
  39                 unsigned int st_stlb_miss:1;
  40                 unsigned int st_locked:1;
  41                 unsigned int st_reserved2:26;
  42         };
  43 };
  44
  45
  46 /*
  47  * Map PEBS Load Latency Data Source encodings to generic
  48  * memory data source information
  49  */
  50 #define P(a, b) PERF_MEM_S(a, b)
  51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  53
  54 static const u64 pebs_data_source[] = {
  55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  71 };
  72
  73 static u64 precise_store_data(u64 status)
  74 {
  75         union intel_x86_pebs_dse dse;
  76         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  77
  78         dse.val = status;
  79
  80         /*
  81          * bit 4: TLB access
  82          * 1 = stored missed 2nd level TLB
  83          *
  84          * so it either hit the walker or the OS
  85          * otherwise hit 2nd level TLB
  86          */
  87         if (dse.st_stlb_miss)
  88                 val |= P(TLB, MISS);
  89         else
  90                 val |= P(TLB, HIT);
  91
  92         /*
  93          * bit 0: hit L1 data cache
  94          * if not set, then all we know is that
  95          * it missed L1D
  96          */
  97         if (dse.st_l1d_hit)
  98                 val |= P(LVL, HIT);
  99         else
 100                 val |= P(LVL, MISS);
 101
 102         /*
 103          * bit 5: Locked prefix
 104          */
 105         if (dse.st_locked)
 106                 val |= P(LOCK, LOCKED);
 107
 108         return val;
 109 }
 110
 111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 112 {
 113         union perf_mem_data_src dse;
 114
 115         dse.val = PERF_MEM_NA;
 116
 117         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 118                 dse.mem_op = PERF_MEM_OP_STORE;
 119         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 120                 dse.mem_op = PERF_MEM_OP_LOAD;
 121
 122         /*
 123          * L1 info only valid for following events:
 124          *
 125          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 126          * MEM_UOPS_RETIRED.LOCK_STORES
 127          * MEM_UOPS_RETIRED.SPLIT_STORES
 128          * MEM_UOPS_RETIRED.ALL_STORES
 129          */
 130         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 131                 if (status & 1)
 132                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 133                 else
 134                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 135         }
 136         return dse.val;
 137 }
 138
 139 static u64 load_latency_data(u64 status)
 140 {
 141         union intel_x86_pebs_dse dse;
 142         u64 val;
 143         int model = boot_cpu_data.x86_model;
 144         int fam = boot_cpu_data.x86;
 145
 146         dse.val = status;
 147
 148         /*
 149          * use the mapping table for bit 0-3
 150          */
 151         val = pebs_data_source[dse.ld_dse];
 152
 153         /*
 154          * Nehalem models do not support TLB, Lock infos
 155          */
 156         if (fam == 0x6 && (model == 26 || model == 30
 157             || model == 31 || model == 46)) {
 158                 val |= P(TLB, NA) | P(LOCK, NA);
 159                 return val;
 160         }
 161         /*
 162          * bit 4: TLB access
 163          * 0 = did not miss 2nd level TLB
 164          * 1 = missed 2nd level TLB
 165          */
 166         if (dse.ld_stlb_miss)
 167                 val |= P(TLB, MISS) | P(TLB, L2);
 168         else
 169                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 170
 171         /*
 172          * bit 5: locked prefix
 173          */
 174         if (dse.ld_locked)
 175                 val |= P(LOCK, LOCKED);
 176
 177         return val;
 178 }
 179
 180 struct pebs_record_core {
 181         u64 flags, ip;
 182         u64 ax, bx, cx, dx;
 183         u64 si, di, bp, sp;
 184         u64 r8,  r9,  r10, r11;
 185         u64 r12, r13, r14, r15;
 186 };
 187
 188 struct pebs_record_nhm {
 189         u64 flags, ip;
 190         u64 ax, bx, cx, dx;
 191         u64 si, di, bp, sp;
 192         u64 r8,  r9,  r10, r11;
 193         u64 r12, r13, r14, r15;
 194         u64 status, dla, dse, lat;
 195 };
 196
 197 /*
 198  * Same as pebs_record_nhm, with two additional fields.
 199  */
 200 struct pebs_record_hsw {
 201         u64 flags, ip;
 202         u64 ax, bx, cx, dx;
 203         u64 si, di, bp, sp;
 204         u64 r8,  r9,  r10, r11;
 205         u64 r12, r13, r14, r15;
 206         u64 status, dla, dse, lat;
 207         u64 real_ip, tsx_tuning;
 208 };
 209
 210 union hsw_tsx_tuning {
 211         struct {
 212                 u32 cycles_last_block     : 32,
 213                     hle_abort             : 1,
 214                     rtm_abort             : 1,
 215                     instruction_abort     : 1,
 216                     non_instruction_abort : 1,
 217                     retry                 : 1,
 218                     data_conflict         : 1,
 219                     capacity_writes       : 1,
 220                     capacity_reads        : 1;
 221         };
 222         u64         value;
 223 };
 224
 225 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 226
 227 void init_debug_store_on_cpu(int cpu)
 228 {
 229         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 230
 231         if (!ds)
 232                 return;
 233
 234         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 235                      (u32)((u64)(unsigned long)ds),
 236                      (u32)((u64)(unsigned long)ds >> 32));
 237 }
 238
 239 void fini_debug_store_on_cpu(int cpu)
 240 {
 241         if (!per_cpu(cpu_hw_events, cpu).ds)
 242                 return;
 243
 244         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 245 }
 246
 247 static DEFINE_PER_CPU(void *, insn_buffer);
 248
 249 static int alloc_pebs_buffer(int cpu)
 250 {
 251         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 252         int node = cpu_to_node(cpu);
 253         int max, thresh = 1; /* always use a single PEBS record */
 254         void *buffer, *ibuffer;
 255
 256         if (!x86_pmu.pebs)
 257                 return 0;
 258
 259         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 260         if (unlikely(!buffer))
 261                 return -ENOMEM;
 262
 263         /*
 264          * HSW+ already provides us the eventing ip; no need to allocate this
 265          * buffer then.
 266          */
 267         if (x86_pmu.intel_cap.pebs_format < 2) {
 268                 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 269                 if (!ibuffer) {
 270                         kfree(buffer);
 271                         return -ENOMEM;
 272                 }
 273                 per_cpu(insn_buffer, cpu) = ibuffer;
 274         }
 275
 276         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 277
 278         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 279         ds->pebs_index = ds->pebs_buffer_base;
 280         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 281                 max * x86_pmu.pebs_record_size;
 282
 283         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 284                 thresh * x86_pmu.pebs_record_size;
 285
 286         return 0;
 287 }
 288
 289 static void release_pebs_buffer(int cpu)
 290 {
 291         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 292
 293         if (!ds || !x86_pmu.pebs)
 294                 return;
 295
 296         kfree(per_cpu(insn_buffer, cpu));
 297         per_cpu(insn_buffer, cpu) = NULL;
 298
 299         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 300         ds->pebs_buffer_base = 0;
 301 }
 302
 303 static int alloc_bts_buffer(int cpu)
 304 {
 305         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 306         int node = cpu_to_node(cpu);
 307         int max, thresh;
 308         void *buffer;
 309
 310         if (!x86_pmu.bts)
 311                 return 0;
 312
 313         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
 314         if (unlikely(!buffer)) {
 315                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 316                 return -ENOMEM;
 317         }
 318
 319         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 320         thresh = max / 16;
 321
 322         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 323         ds->bts_index = ds->bts_buffer_base;
 324         ds->bts_absolute_maximum = ds->bts_buffer_base +
 325                 max * BTS_RECORD_SIZE;
 326         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 327                 thresh * BTS_RECORD_SIZE;
 328
 329         return 0;
 330 }
 331
 332 static void release_bts_buffer(int cpu)
 333 {
 334         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 335
 336         if (!ds || !x86_pmu.bts)
 337                 return;
 338
 339         kfree((void *)(unsigned long)ds->bts_buffer_base);
 340         ds->bts_buffer_base = 0;
 341 }
 342
 343 static int alloc_ds_buffer(int cpu)
 344 {
 345         int node = cpu_to_node(cpu);
 346         struct debug_store *ds;
 347
 348         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 349         if (unlikely(!ds))
 350                 return -ENOMEM;
 351
 352         per_cpu(cpu_hw_events, cpu).ds = ds;
 353
 354         return 0;
 355 }
 356
 357 static void release_ds_buffer(int cpu)
 358 {
 359         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 360
 361         if (!ds)
 362                 return;
 363
 364         per_cpu(cpu_hw_events, cpu).ds = NULL;
 365         kfree(ds);
 366 }
 367
 368 void release_ds_buffers(void)
 369 {
 370         int cpu;
 371
 372         if (!x86_pmu.bts && !x86_pmu.pebs)
 373                 return;
 374
 375         get_online_cpus();
 376         for_each_online_cpu(cpu)
 377                 fini_debug_store_on_cpu(cpu);
 378
 379         for_each_possible_cpu(cpu) {
 380                 release_pebs_buffer(cpu);
 381                 release_bts_buffer(cpu);
 382                 release_ds_buffer(cpu);
 383         }
 384         put_online_cpus();
 385 }
 386
 387 void reserve_ds_buffers(void)
 388 {
 389         int bts_err = 0, pebs_err = 0;
 390         int cpu;
 391
 392         x86_pmu.bts_active = 0;
 393         x86_pmu.pebs_active = 0;
 394
 395         if (!x86_pmu.bts && !x86_pmu.pebs)
 396                 return;
 397
 398         if (!x86_pmu.bts)
 399                 bts_err = 1;
 400
 401         if (!x86_pmu.pebs)
 402                 pebs_err = 1;
 403
 404         get_online_cpus();
 405
 406         for_each_possible_cpu(cpu) {
 407                 if (alloc_ds_buffer(cpu)) {
 408                         bts_err = 1;
 409                         pebs_err = 1;
 410                 }
 411
 412                 if (!bts_err && alloc_bts_buffer(cpu))
 413                         bts_err = 1;
 414
 415                 if (!pebs_err && alloc_pebs_buffer(cpu))
 416                         pebs_err = 1;
 417
 418                 if (bts_err && pebs_err)
 419                         break;
 420         }
 421
 422         if (bts_err) {
 423                 for_each_possible_cpu(cpu)
 424                         release_bts_buffer(cpu);
 425         }
 426
 427         if (pebs_err) {
 428                 for_each_possible_cpu(cpu)
 429                         release_pebs_buffer(cpu);
 430         }
 431
 432         if (bts_err && pebs_err) {
 433                 for_each_possible_cpu(cpu)
 434                         release_ds_buffer(cpu);
 435         } else {
 436                 if (x86_pmu.bts && !bts_err)
 437                         x86_pmu.bts_active = 1;
 438
 439                 if (x86_pmu.pebs && !pebs_err)
 440                         x86_pmu.pebs_active = 1;
 441
 442                 for_each_online_cpu(cpu)
 443                         init_debug_store_on_cpu(cpu);
 444         }
 445
 446         put_online_cpus();
 447 }
 448
 449 /*
 450  * BTS
 451  */
 452
 453 struct event_constraint bts_constraint =
 454         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 455
 456 void intel_pmu_enable_bts(u64 config)
 457 {
 458         unsigned long debugctlmsr;
 459
 460         debugctlmsr = get_debugctlmsr();
 461
 462         debugctlmsr |= DEBUGCTLMSR_TR;
 463         debugctlmsr |= DEBUGCTLMSR_BTS;
 464         if (config & ARCH_PERFMON_EVENTSEL_INT)
 465                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 466
 467         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 468                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 469
 470         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 471                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 472
 473         update_debugctlmsr(debugctlmsr);
 474 }
 475
 476 void intel_pmu_disable_bts(void)
 477 {
 478         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 479         unsigned long debugctlmsr;
 480
 481         if (!cpuc->ds)
 482                 return;
 483
 484         debugctlmsr = get_debugctlmsr();
 485
 486         debugctlmsr &=
 487                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 488                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 489
 490         update_debugctlmsr(debugctlmsr);
 491 }
 492
 493 int intel_pmu_drain_bts_buffer(void)
 494 {
 495         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 496         struct debug_store *ds = cpuc->ds;
 497         struct bts_record {
 498                 u64     from;
 499                 u64     to;
 500                 u64     flags;
 501         };
 502         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 503         struct bts_record *at, *top;
 504         struct perf_output_handle handle;
 505         struct perf_event_header header;
 506         struct perf_sample_data data;
 507         struct pt_regs regs;
 508
 509         if (!event)
 510                 return 0;
 511
 512         if (!x86_pmu.bts_active)
 513                 return 0;
 514
 515         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 516         top = (struct bts_record *)(unsigned long)ds->bts_index;
 517
 518         if (top <= at)
 519                 return 0;
 520
 521         memset(&regs, 0, sizeof(regs));
 522
 523         ds->bts_index = ds->bts_buffer_base;
 524
 525         perf_sample_data_init(&data, 0, event->hw.last_period);
 526
 527         /*
 528          * Prepare a generic sample, i.e. fill in the invariant fields.
 529          * We will overwrite the from and to address before we output
 530          * the sample.
 531          */
 532         perf_prepare_sample(&header, &data, event, &regs);
 533
 534         if (perf_output_begin(&handle, event, header.size * (top - at)))
 535                 return 1;
 536
 537         for (; at < top; at++) {
 538                 data.ip         = at->from;
 539                 data.addr       = at->to;
 540
 541                 perf_output_sample(&handle, &header, &data, event);
 542         }
 543
 544         perf_output_end(&handle);
 545
 546         /* There's new data available. */
 547         event->hw.interrupts++;
 548         event->pending_kill = POLL_IN;
 549         return 1;
 550 }
 551
 552 /*
 553  * PEBS
 554  */
 555 struct event_constraint intel_core2_pebs_event_constraints[] = {
 556         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 557         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 558         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 559         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 560         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 561         EVENT_CONSTRAINT_END
 562 };
 563
 564 struct event_constraint intel_atom_pebs_event_constraints[] = {
 565         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 566         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 567         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 568         EVENT_CONSTRAINT_END
 569 };
 570
 571 struct event_constraint intel_slm_pebs_event_constraints[] = {
 572         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 573         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
 574         /* Allow all events as PEBS with no flags */
 575         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 576         EVENT_CONSTRAINT_END
 577 };
 578
 579 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 580         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 581         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 582         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 583         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 584         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 585         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 586         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 587         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 588         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 589         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 590         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 591         EVENT_CONSTRAINT_END
 592 };
 593
 594 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 595         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 596         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 597         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 598         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 599         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 600         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 601         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 602         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 603         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 604         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 605         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 606         EVENT_CONSTRAINT_END
 607 };
 608
 609 struct event_constraint intel_snb_pebs_event_constraints[] = {
 610         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 611         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 612         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 613         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 614         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 615         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 616         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 617         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 618         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 619         /* Allow all events as PEBS with no flags */
 620         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 621         EVENT_CONSTRAINT_END
 622 };
 623
 624 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 625         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 626         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 627         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 628         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 629         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 630         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 631         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 632         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 633         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 634         /* Allow all events as PEBS with no flags */
 635         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 636         EVENT_CONSTRAINT_END
 637 };
 638
 639 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 640         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 641         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 642         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 643         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 644         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 645         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 646         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 647         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 648         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 649         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 650         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 651         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 652         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 653         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 654         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 655         /* Allow all events as PEBS with no flags */
 656         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 657         EVENT_CONSTRAINT_END
 658 };
 659
 660 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 661 {
 662         struct event_constraint *c;
 663
 664         if (!event->attr.precise_ip)
 665                 return NULL;
 666
 667         if (x86_pmu.pebs_constraints) {
 668                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 669                         if ((event->hw.config & c->cmask) == c->code) {
 670                                 event->hw.flags |= c->flags;
 671                                 return c;
 672                         }
 673                 }
 674         }
 675
 676         return &emptyconstraint;
 677 }
 678
 679 void intel_pmu_pebs_enable(struct perf_event *event)
 680 {
 681         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 682         struct hw_perf_event *hwc = &event->hw;
 683
 684         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 685
 686         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 687
 688         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 689                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 690         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 691                 cpuc->pebs_enabled |= 1ULL << 63;
 692 }
 693
 694 void intel_pmu_pebs_disable(struct perf_event *event)
 695 {
 696         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 697         struct hw_perf_event *hwc = &event->hw;
 698
 699         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 700
 701         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
 702                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 703         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
 704                 cpuc->pebs_enabled &= ~(1ULL << 63);
 705
 706         if (cpuc->enabled)
 707                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 708
 709         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 710 }
 711
 712 void intel_pmu_pebs_enable_all(void)
 713 {
 714         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 715
 716         if (cpuc->pebs_enabled)
 717                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 718 }
 719
 720 void intel_pmu_pebs_disable_all(void)
 721 {
 722         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 723
 724         if (cpuc->pebs_enabled)
 725                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 726 }
 727
 728 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 729 {
 730         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 731         unsigned long from = cpuc->lbr_entries[0].from;
 732         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 733         unsigned long ip = regs->ip;
 734         int is_64bit = 0;
 735         void *kaddr;
 736         int size;
 737
 738         /*
 739          * We don't need to fixup if the PEBS assist is fault like
 740          */
 741         if (!x86_pmu.intel_cap.pebs_trap)
 742                 return 1;
 743
 744         /*
 745          * No LBR entry, no basic block, no rewinding
 746          */
 747         if (!cpuc->lbr_stack.nr || !from || !to)
 748                 return 0;
 749
 750         /*
 751          * Basic blocks should never cross user/kernel boundaries
 752          */
 753         if (kernel_ip(ip) != kernel_ip(to))
 754                 return 0;
 755
 756         /*
 757          * unsigned math, either ip is before the start (impossible) or
 758          * the basic block is larger than 1 page (sanity)
 759          */
 760         if ((ip - to) > PEBS_FIXUP_SIZE)
 761                 return 0;
 762
 763         /*
 764          * We sampled a branch insn, rewind using the LBR stack
 765          */
 766         if (ip == to) {
 767                 set_linear_ip(regs, from);
 768                 return 1;
 769         }
 770
 771         size = ip - to;
 772         if (!kernel_ip(ip)) {
 773                 int bytes;
 774                 u8 *buf = this_cpu_read(insn_buffer);
 775
 776                 /* 'size' must fit our buffer, see above */
 777                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 778                 if (bytes != 0)
 779                         return 0;
 780
 781                 kaddr = buf;
 782         } else {
 783                 kaddr = (void *)to;
 784         }
 785
 786         do {
 787                 struct insn insn;
 788
 789                 old_to = to;
 790
 791 #ifdef CONFIG_X86_64
 792                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 793 #endif
 794                 insn_init(&insn, kaddr, size, is_64bit);
 795                 insn_get_length(&insn);
 796                 /*
 797                  * Make sure there was not a problem decoding the
 798                  * instruction and getting the length.  This is
 799                  * doubly important because we have an infinite
 800                  * loop if insn.length=0.
 801                  */
 802                 if (!insn.length)
 803                         break;
 804
 805                 to += insn.length;
 806                 kaddr += insn.length;
 807                 size -= insn.length;
 808         } while (to < ip);
 809
 810         if (to == ip) {
 811                 set_linear_ip(regs, old_to);
 812                 return 1;
 813         }
 814
 815         /*
 816          * Even though we decoded the basic block, the instruction stream
 817          * never matched the given IP, either the TO or the IP got corrupted.
 818          */
 819         return 0;
 820 }
 821
 822 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
 823 {
 824         if (pebs->tsx_tuning) {
 825                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 826                 return tsx.cycles_last_block;
 827         }
 828         return 0;
 829 }
 830
 831 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
 832 {
 833         u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
 834
 835         /* For RTM XABORTs also log the abort code from AX */
 836         if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
 837                 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
 838         return txn;
 839 }
 840
 841 static void __intel_pmu_pebs_event(struct perf_event *event,
 842                                    struct pt_regs *iregs, void *__pebs)
 843 {
 844 #define PERF_X86_EVENT_PEBS_HSW_PREC \
 845                 (PERF_X86_EVENT_PEBS_ST_HSW | \
 846                  PERF_X86_EVENT_PEBS_LD_HSW | \
 847                  PERF_X86_EVENT_PEBS_NA_HSW)
 848         /*
 849          * We cast to the biggest pebs_record but are careful not to
 850          * unconditionally access the 'extra' entries.
 851          */
 852         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 853         struct pebs_record_hsw *pebs = __pebs;
 854         struct perf_sample_data data;
 855         struct pt_regs regs;
 856         u64 sample_type;
 857         int fll, fst, dsrc;
 858         int fl = event->hw.flags;
 859
 860         if (!intel_pmu_save_and_restart(event))
 861                 return;
 862
 863         sample_type = event->attr.sample_type;
 864         dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
 865
 866         fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
 867         fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
 868
 869         perf_sample_data_init(&data, 0, event->hw.last_period);
 870
 871         data.period = event->hw.last_period;
 872
 873         /*
 874          * Use latency for weight (only avail with PEBS-LL)
 875          */
 876         if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 877                 data.weight = pebs->lat;
 878
 879         /*
 880          * data.data_src encodes the data source
 881          */
 882         if (dsrc) {
 883                 u64 val = PERF_MEM_NA;
 884                 if (fll)
 885                         val = load_latency_data(pebs->dse);
 886                 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
 887                         val = precise_datala_hsw(event, pebs->dse);
 888                 else if (fst)
 889                         val = precise_store_data(pebs->dse);
 890                 data.data_src.val = val;
 891         }
 892
 893         /*
 894          * We use the interrupt regs as a base because the PEBS record
 895          * does not contain a full regs set, specifically it seems to
 896          * lack segment descriptors, which get used by things like
 897          * user_mode().
 898          *
 899          * In the simple case fix up only the IP and BP,SP regs, for
 900          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 901          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 902          */
 903         regs = *iregs;
 904         regs.flags = pebs->flags;
 905         set_linear_ip(&regs, pebs->ip);
 906         regs.bp = pebs->bp;
 907         regs.sp = pebs->sp;
 908
 909         if (sample_type & PERF_SAMPLE_REGS_INTR) {
 910                 regs.ax = pebs->ax;
 911                 regs.bx = pebs->bx;
 912                 regs.cx = pebs->cx;
 913                 regs.dx = pebs->dx;
 914                 regs.si = pebs->si;
 915                 regs.di = pebs->di;
 916                 regs.bp = pebs->bp;
 917                 regs.sp = pebs->sp;
 918
 919                 regs.flags = pebs->flags;
 920 #ifndef CONFIG_X86_32
 921                 regs.r8 = pebs->r8;
 922                 regs.r9 = pebs->r9;
 923                 regs.r10 = pebs->r10;
 924                 regs.r11 = pebs->r11;
 925                 regs.r12 = pebs->r12;
 926                 regs.r13 = pebs->r13;
 927                 regs.r14 = pebs->r14;
 928                 regs.r15 = pebs->r15;
 929 #endif
 930         }
 931
 932         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
 933                 regs.ip = pebs->real_ip;
 934                 regs.flags |= PERF_EFLAGS_EXACT;
 935         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 936                 regs.flags |= PERF_EFLAGS_EXACT;
 937         else
 938                 regs.flags &= ~PERF_EFLAGS_EXACT;
 939
 940         if ((sample_type & PERF_SAMPLE_ADDR) &&
 941             x86_pmu.intel_cap.pebs_format >= 1)
 942                 data.addr = pebs->dla;
 943
 944         if (x86_pmu.intel_cap.pebs_format >= 2) {
 945                 /* Only set the TSX weight when no memory weight. */
 946                 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
 947                         data.weight = intel_hsw_weight(pebs);
 948
 949                 if (sample_type & PERF_SAMPLE_TRANSACTION)
 950                         data.txn = intel_hsw_transaction(pebs);
 951         }
 952
 953         if (has_branch_stack(event))
 954                 data.br_stack = &cpuc->lbr_stack;
 955
 956         if (perf_event_overflow(event, &data, &regs))
 957                 x86_pmu_stop(event, 0);
 958 }
 959
 960 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 961 {
 962         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 963         struct debug_store *ds = cpuc->ds;
 964         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 965         struct pebs_record_core *at, *top;
 966         int n;
 967
 968         if (!x86_pmu.pebs_active)
 969                 return;
 970
 971         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 972         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 973
 974         /*
 975          * Whatever else happens, drain the thing
 976          */
 977         ds->pebs_index = ds->pebs_buffer_base;
 978
 979         if (!test_bit(0, cpuc->active_mask))
 980                 return;
 981
 982         WARN_ON_ONCE(!event);
 983
 984         if (!event->attr.precise_ip)
 985                 return;
 986
 987         n = top - at;
 988         if (n <= 0)
 989                 return;
 990
 991         /*
 992          * Should not happen, we program the threshold at 1 and do not
 993          * set a reset value.
 994          */
 995         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
 996         at += n - 1;
 997
 998         __intel_pmu_pebs_event(event, iregs, at);
 999 }
1000
1001 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1002 {
1003         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1004         struct debug_store *ds = cpuc->ds;
1005         struct perf_event *event = NULL;
1006         void *at, *top;
1007         u64 status = 0;
1008         int bit;
1009
1010         if (!x86_pmu.pebs_active)
1011                 return;
1012
1013         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1014         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1015
1016         ds->pebs_index = ds->pebs_buffer_base;
1017
1018         if (unlikely(at > top))
1019                 return;
1020
1021         /*
1022          * Should not happen, we program the threshold at 1 and do not
1023          * set a reset value.
1024          */
1025         WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
1026                   "Unexpected number of pebs records %ld\n",
1027                   (long)(top - at) / x86_pmu.pebs_record_size);
1028
1029         for (; at < top; at += x86_pmu.pebs_record_size) {
1030                 struct pebs_record_nhm *p = at;
1031
1032                 for_each_set_bit(bit, (unsigned long *)&p->status,
1033                                  x86_pmu.max_pebs_events) {
1034                         event = cpuc->events[bit];
1035                         if (!test_bit(bit, cpuc->active_mask))
1036                                 continue;
1037
1038                         WARN_ON_ONCE(!event);
1039
1040                         if (!event->attr.precise_ip)
1041                                 continue;
1042
1043                         if (__test_and_set_bit(bit, (unsigned long *)&status))
1044                                 continue;
1045
1046                         break;
1047                 }
1048
1049                 if (!event || bit >= x86_pmu.max_pebs_events)
1050                         continue;
1051
1052                 __intel_pmu_pebs_event(event, iregs, at);
1053         }
1054 }
1055
1056 /*
1057  * BTS, PEBS probe and setup
1058  */
1059
1060 void __init intel_ds_init(void)
1061 {
1062         /*
1063          * No support for 32bit formats
1064          */
1065         if (!boot_cpu_has(X86_FEATURE_DTES64))
1066                 return;
1067
1068         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1069         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1070         if (x86_pmu.pebs) {
1071                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1072                 int format = x86_pmu.intel_cap.pebs_format;
1073
1074                 switch (format) {
1075                 case 0:
1076                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1077                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1078                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1079                         break;
1080
1081                 case 1:
1082                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1083                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1084                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1085                         break;
1086
1087                 case 2:
1088                         pr_cont("PEBS fmt2%c, ", pebs_type);
1089                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1090                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1091                         break;
1092
1093                 default:
1094                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1095                         x86_pmu.pebs = 0;
1096                 }
1097         }
1098 }
1099
1100 void perf_restore_debug_store(void)
1101 {
1102         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1103
1104         if (!x86_pmu.bts && !x86_pmu.pebs)
1105                 return;
1106
1107         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1108 }