2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 #define wrmsrl(msr, val) \
21 unsigned int _msr = (msr); \
23 trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
24 (unsigned long long)(_val)); \
25 native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
31 * register -------------------------------
32 * | HT | no HT | HT | no HT |
33 *-----------------------------------------
34 * offcore | core | core | cpu | core |
35 * lbr_sel | core | core | cpu | core |
36 * ld_lat | cpu | core | cpu | core |
37 *-----------------------------------------
39 * Given that there is a small number of shared regs,
40 * we can pre-allocate their slot in the per-cpu
41 * per-core reg tables.
44 EXTRA_REG_NONE = -1, /* not used */
46 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
47 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
48 EXTRA_REG_LBR = 2, /* lbr_select */
49 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
51 EXTRA_REG_MAX /* number of entries needed */
54 struct event_constraint {
56 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style datala, store */
71 #define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */
72 #define PERF_X86_EVENT_PEBS_LD_HSW 0x10 /* haswell style datala, load */
73 #define PERF_X86_EVENT_PEBS_NA_HSW 0x20 /* haswell style datala, unknown */
76 int nb_id; /* NorthBridge id */
77 int refcnt; /* reference count */
78 struct perf_event *owners[X86_PMC_IDX_MAX];
79 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
82 /* The maximal number of PEBS events: */
83 #define MAX_PEBS_EVENTS 8
86 * A debug store configuration.
88 * We only support architectures that use 64bit fields.
93 u64 bts_absolute_maximum;
94 u64 bts_interrupt_threshold;
97 u64 pebs_absolute_maximum;
98 u64 pebs_interrupt_threshold;
99 u64 pebs_event_reset[MAX_PEBS_EVENTS];
103 * Per register state.
106 raw_spinlock_t lock; /* per-core: protect structure */
107 u64 config; /* extra MSR config */
108 u64 reg; /* extra MSR number */
109 atomic_t ref; /* reference count */
115 * Used to coordinate shared registers between HT threads or
116 * among events on a single PMU.
118 struct intel_shared_regs {
119 struct er_account regs[EXTRA_REG_MAX];
120 int refcnt; /* per-core: #HT threads */
121 unsigned core_id; /* per-core: core id */
124 #define MAX_LBR_ENTRIES 16
126 struct cpu_hw_events {
128 * Generic x86 PMC bits
130 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
131 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
132 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
135 int n_events; /* the # of events in the below arrays */
136 int n_added; /* the # last events in the below arrays;
137 they've never been enabled yet */
138 int n_txn; /* the # last events in the below arrays;
139 added in the current transaction */
140 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
141 u64 tags[X86_PMC_IDX_MAX];
142 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
144 unsigned int group_flag;
148 * Intel DebugStore bits
150 struct debug_store *ds;
158 struct perf_branch_stack lbr_stack;
159 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
160 struct er_account *lbr_sel;
164 * Intel host/guest exclude bits
166 u64 intel_ctrl_guest_mask;
167 u64 intel_ctrl_host_mask;
168 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
171 * Intel checkpoint mask
176 * manage shared (per-core, per-cpu) registers
177 * used on Intel NHM/WSM/SNB
179 struct intel_shared_regs *shared_regs;
184 struct amd_nb *amd_nb;
185 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
186 u64 perf_ctr_virt_mask;
188 void *kfree_on_online;
191 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
192 { .idxmsk64 = (n) }, \
200 #define EVENT_CONSTRAINT(c, n, m) \
201 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
204 * The overlap flag marks event constraints with overlapping counter
205 * masks. This is the case if the counter mask of such an event is not
206 * a subset of any other counter mask of a constraint with an equal or
207 * higher weight, e.g.:
209 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
210 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
211 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
213 * The event scheduler may not select the correct counter in the first
214 * cycle because it needs to know which subsequent events will be
215 * scheduled. It may fail to schedule the events then. So we set the
216 * overlap flag for such constraints to give the scheduler a hint which
217 * events to select for counter rescheduling.
219 * Care must be taken as the rescheduling algorithm is O(n!) which
220 * will increase scheduling cycles for an over-commited system
221 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
222 * and its counter masks must be kept at a minimum.
224 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
225 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
228 * Constraint on the Event code.
230 #define INTEL_EVENT_CONSTRAINT(c, n) \
231 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
234 * Constraint on the Event code + UMask + fixed-mask
236 * filter mask to validate fixed counter events.
237 * the following filters disqualify for fixed counters:
242 * - in_tx_checkpointed
243 * The other filters are supported by fixed counters.
244 * The any-thread option is supported starting with v3.
246 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
247 #define FIXED_EVENT_CONSTRAINT(c, n) \
248 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
251 * Constraint on the Event code + UMask
253 #define INTEL_UEVENT_CONSTRAINT(c, n) \
254 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
256 #define INTEL_PLD_CONSTRAINT(c, n) \
257 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
258 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
260 #define INTEL_PST_CONSTRAINT(c, n) \
261 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
262 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
264 /* Event constraint, but match on all event flags too. */
265 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
266 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
268 /* Check only flags, but allow all event/umask */
269 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
270 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
272 /* Check flags and event code, and set the HSW store flag */
273 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
274 __EVENT_CONSTRAINT(code, n, \
275 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
276 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
278 /* Check flags and event code, and set the HSW load flag */
279 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
280 __EVENT_CONSTRAINT(code, n, \
281 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
282 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
284 /* Check flags and event code/umask, and set the HSW store flag */
285 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
286 __EVENT_CONSTRAINT(code, n, \
287 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
288 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
290 /* Check flags and event code/umask, and set the HSW load flag */
291 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
292 __EVENT_CONSTRAINT(code, n, \
293 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
294 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
296 /* Check flags and event code/umask, and set the HSW N/A flag */
297 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
298 __EVENT_CONSTRAINT(code, n, \
299 INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \
300 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
304 * We define the end marker as having a weight of -1
305 * to enable blacklisting of events using a counter bitmask
306 * of zero and thus a weight of zero.
307 * The end marker has a weight that cannot possibly be
308 * obtained from counting the bits in the bitmask.
310 #define EVENT_CONSTRAINT_END { .weight = -1 }
313 * Check for end marker with weight == -1
315 #define for_each_event_constraint(e, c) \
316 for ((e) = (c); (e)->weight != -1; (e)++)
319 * Extra registers for specific events.
321 * Some events need large masks and require external MSRs.
322 * Those extra MSRs end up being shared for all events on
323 * a PMU and sometimes between PMU of sibling HT threads.
324 * In either case, the kernel needs to handle conflicting
325 * accesses to those extra, shared, regs. The data structure
326 * to manage those registers is stored in cpu_hw_event.
333 int idx; /* per_xxx->regs[] reg index */
334 bool extra_msr_access;
337 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
340 .config_mask = (m), \
341 .valid_mask = (vm), \
342 .idx = EXTRA_REG_##i, \
343 .extra_msr_access = true, \
346 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
347 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
349 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
350 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
351 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
353 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
354 INTEL_UEVENT_EXTRA_REG(c, \
355 MSR_PEBS_LD_LAT_THRESHOLD, \
359 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
361 union perf_capabilities {
369 * PMU supports separate counter range for writing
372 u64 full_width_write:1;
377 struct x86_pmu_quirk {
378 struct x86_pmu_quirk *next;
382 union x86_pmu_config {
403 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
406 * struct x86_pmu - generic x86 pmu
410 * Generic x86 PMC bits
414 int (*handle_irq)(struct pt_regs *);
415 void (*disable_all)(void);
416 void (*enable_all)(int added);
417 void (*enable)(struct perf_event *);
418 void (*disable)(struct perf_event *);
419 int (*hw_config)(struct perf_event *event);
420 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
423 int (*addr_offset)(int index, bool eventsel);
424 int (*rdpmc_index)(int index);
425 u64 (*event_map)(int);
428 int num_counters_fixed;
432 unsigned long events_maskl;
433 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
438 struct event_constraint *
439 (*get_event_constraints)(struct cpu_hw_events *cpuc,
440 struct perf_event *event);
442 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
443 struct perf_event *event);
444 struct event_constraint *event_constraints;
445 struct x86_pmu_quirk *quirks;
446 int perfctr_second_write;
452 int attr_rdpmc_broken;
454 struct attribute **format_attrs;
455 struct attribute **event_attrs;
457 ssize_t (*events_sysfs_show)(char *page, u64 config);
458 struct attribute **cpu_events;
463 int (*cpu_prepare)(int cpu);
464 void (*cpu_starting)(int cpu);
465 void (*cpu_dying)(int cpu);
466 void (*cpu_dead)(int cpu);
468 void (*check_microcode)(void);
469 void (*flush_branch_stack)(void);
472 * Intel Arch Perfmon v2+
475 union perf_capabilities intel_cap;
478 * Intel DebugStore bits
485 int pebs_record_size;
486 void (*drain_pebs)(struct pt_regs *regs);
487 struct event_constraint *pebs_constraints;
488 void (*pebs_aliases)(struct perf_event *event);
494 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
495 int lbr_nr; /* hardware stack size */
496 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
497 const int *lbr_sel_map; /* lbr_select mappings */
498 bool lbr_double_abort; /* duplicated lbr aborts */
501 * Extra registers for events
503 struct extra_reg *extra_regs;
504 unsigned int er_flags;
507 * Intel host/guest support (KVM)
509 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
512 #define x86_add_quirk(func_) \
514 static struct x86_pmu_quirk __quirk __initdata = { \
517 __quirk.next = x86_pmu.quirks; \
518 x86_pmu.quirks = &__quirk; \
521 #define ERF_NO_HT_SHARING 1
522 #define ERF_HAS_RSP_1 2
524 #define EVENT_VAR(_id) event_attr_##_id
525 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
527 #define EVENT_ATTR(_name, _id) \
528 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
529 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
530 .id = PERF_COUNT_HW_##_id, \
534 #define EVENT_ATTR_STR(_name, v, str) \
535 static struct perf_pmu_events_attr event_attr_##v = { \
536 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
541 extern struct x86_pmu x86_pmu __read_mostly;
543 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
545 int x86_perf_event_set_period(struct perf_event *event);
548 * Generalized hw caching related hw_event table, filled
549 * in on a per model basis. A value of 0 means
550 * 'not supported', -1 means 'hw_event makes no sense on
551 * this CPU', any other value means the raw hw_event
555 #define C(x) PERF_COUNT_HW_CACHE_##x
557 extern u64 __read_mostly hw_cache_event_ids
558 [PERF_COUNT_HW_CACHE_MAX]
559 [PERF_COUNT_HW_CACHE_OP_MAX]
560 [PERF_COUNT_HW_CACHE_RESULT_MAX];
561 extern u64 __read_mostly hw_cache_extra_regs
562 [PERF_COUNT_HW_CACHE_MAX]
563 [PERF_COUNT_HW_CACHE_OP_MAX]
564 [PERF_COUNT_HW_CACHE_RESULT_MAX];
566 u64 x86_perf_event_update(struct perf_event *event);
568 static inline unsigned int x86_pmu_config_addr(int index)
570 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
571 x86_pmu.addr_offset(index, true) : index);
574 static inline unsigned int x86_pmu_event_addr(int index)
576 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
577 x86_pmu.addr_offset(index, false) : index);
580 static inline int x86_pmu_rdpmc_index(int index)
582 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
585 int x86_setup_perfctr(struct perf_event *event);
587 int x86_pmu_hw_config(struct perf_event *event);
589 void x86_pmu_disable_all(void);
591 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
594 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
596 if (hwc->extra_reg.reg)
597 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
598 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
601 void x86_pmu_enable_all(int added);
603 int perf_assign_events(struct perf_event **events, int n,
604 int wmin, int wmax, int *assign);
605 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
607 void x86_pmu_stop(struct perf_event *event, int flags);
609 static inline void x86_pmu_disable_event(struct perf_event *event)
611 struct hw_perf_event *hwc = &event->hw;
613 wrmsrl(hwc->config_base, hwc->config);
616 void x86_pmu_enable_event(struct perf_event *event);
618 int x86_pmu_handle_irq(struct pt_regs *regs);
620 extern struct event_constraint emptyconstraint;
622 extern struct event_constraint unconstrained;
624 static inline bool kernel_ip(unsigned long ip)
627 return ip > PAGE_OFFSET;
634 * Not all PMUs provide the right context information to place the reported IP
635 * into full context. Specifically segment registers are typically not
638 * Assuming the address is a linear address (it is for IBS), we fake the CS and
639 * vm86 mode using the known zero-based code segment and 'fix up' the registers
642 * Intel PEBS/LBR appear to typically provide the effective address, nothing
643 * much we can do about that but pray and treat it like a linear address.
645 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
647 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
648 if (regs->flags & X86_VM_MASK)
649 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
653 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
654 ssize_t intel_event_sysfs_show(char *page, u64 config);
656 #ifdef CONFIG_CPU_SUP_AMD
658 int amd_pmu_init(void);
660 #else /* CONFIG_CPU_SUP_AMD */
662 static inline int amd_pmu_init(void)
667 #endif /* CONFIG_CPU_SUP_AMD */
669 #ifdef CONFIG_CPU_SUP_INTEL
671 int intel_pmu_save_and_restart(struct perf_event *event);
673 struct event_constraint *
674 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
676 struct intel_shared_regs *allocate_shared_regs(int cpu);
678 int intel_pmu_init(void);
680 void init_debug_store_on_cpu(int cpu);
682 void fini_debug_store_on_cpu(int cpu);
684 void release_ds_buffers(void);
686 void reserve_ds_buffers(void);
688 extern struct event_constraint bts_constraint;
690 void intel_pmu_enable_bts(u64 config);
692 void intel_pmu_disable_bts(void);
694 int intel_pmu_drain_bts_buffer(void);
696 extern struct event_constraint intel_core2_pebs_event_constraints[];
698 extern struct event_constraint intel_atom_pebs_event_constraints[];
700 extern struct event_constraint intel_slm_pebs_event_constraints[];
702 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
704 extern struct event_constraint intel_westmere_pebs_event_constraints[];
706 extern struct event_constraint intel_snb_pebs_event_constraints[];
708 extern struct event_constraint intel_ivb_pebs_event_constraints[];
710 extern struct event_constraint intel_hsw_pebs_event_constraints[];
712 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
714 void intel_pmu_pebs_enable(struct perf_event *event);
716 void intel_pmu_pebs_disable(struct perf_event *event);
718 void intel_pmu_pebs_enable_all(void);
720 void intel_pmu_pebs_disable_all(void);
722 void intel_ds_init(void);
724 void intel_pmu_lbr_reset(void);
726 void intel_pmu_lbr_enable(struct perf_event *event);
728 void intel_pmu_lbr_disable(struct perf_event *event);
730 void intel_pmu_lbr_enable_all(void);
732 void intel_pmu_lbr_disable_all(void);
734 void intel_pmu_lbr_read(void);
736 void intel_pmu_lbr_init_core(void);
738 void intel_pmu_lbr_init_nhm(void);
740 void intel_pmu_lbr_init_atom(void);
742 void intel_pmu_lbr_init_snb(void);
744 int intel_pmu_setup_lbr_filter(struct perf_event *event);
746 int p4_pmu_init(void);
748 int p6_pmu_init(void);
750 int knc_pmu_init(void);
752 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
755 #else /* CONFIG_CPU_SUP_INTEL */
757 static inline void reserve_ds_buffers(void)
761 static inline void release_ds_buffers(void)
765 static inline int intel_pmu_init(void)
770 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
775 #endif /* CONFIG_CPU_SUP_INTEL */