arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/timer.h>
  35 #include <asm/desc.h>
  36 #include <asm/ldt.h>
  37
  38 #include "perf_event.h"
  39
  40 struct x86_pmu x86_pmu __read_mostly;
  41
  42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  43         .enabled = 1,
  44 };
  45
  46 u64 __read_mostly hw_cache_event_ids
  47                                 [PERF_COUNT_HW_CACHE_MAX]
  48                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  49                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  50 u64 __read_mostly hw_cache_extra_regs
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54
  55 /*
  56  * Propagate event elapsed time into the generic event.
  57  * Can only be executed on the CPU where the event is active.
  58  * Returns the delta events processed.
  59  */
  60 u64 x86_perf_event_update(struct perf_event *event)
  61 {
  62         struct hw_perf_event *hwc = &event->hw;
  63         int shift = 64 - x86_pmu.cntval_bits;
  64         u64 prev_raw_count, new_raw_count;
  65         int idx = hwc->idx;
  66         s64 delta;
  67
  68         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  69                 return 0;
  70
  71         /*
  72          * Careful: an NMI might modify the previous event value.
  73          *
  74          * Our tactic to handle this is to first atomically read and
  75          * exchange a new raw count - then add that new-prev delta
  76          * count to the generic event atomically:
  77          */
  78 again:
  79         prev_raw_count = local64_read(&hwc->prev_count);
  80         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  81
  82         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  83                                         new_raw_count) != prev_raw_count)
  84                 goto again;
  85
  86         /*
  87          * Now we have the new raw value and have updated the prev
  88          * timestamp already. We can now calculate the elapsed delta
  89          * (event-)time and add that to the generic event.
  90          *
  91          * Careful, not all hw sign-extends above the physical width
  92          * of the count.
  93          */
  94         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  95         delta >>= shift;
  96
  97         local64_add(delta, &event->count);
  98         local64_sub(delta, &hwc->period_left);
  99
 100         return new_raw_count;
 101 }
 102
 103 /*
 104  * Find and validate any extra registers to set up.
 105  */
 106 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 107 {
 108         struct hw_perf_event_extra *reg;
 109         struct extra_reg *er;
 110
 111         reg = &event->hw.extra_reg;
 112
 113         if (!x86_pmu.extra_regs)
 114                 return 0;
 115
 116         for (er = x86_pmu.extra_regs; er->msr; er++) {
 117                 if (er->event != (config & er->config_mask))
 118                         continue;
 119                 if (event->attr.config1 & ~er->valid_mask)
 120                         return -EINVAL;
 121                 /* Check if the extra msrs can be safely accessed*/
 122                 if (!er->extra_msr_access)
 123                         return -ENXIO;
 124
 125                 reg->idx = er->idx;
 126                 reg->config = event->attr.config1;
 127                 reg->reg = er->msr;
 128                 break;
 129         }
 130         return 0;
 131 }
 132
 133 static atomic_t active_events;
 134 static DEFINE_MUTEX(pmc_reserve_mutex);
 135
 136 #ifdef CONFIG_X86_LOCAL_APIC
 137
 138 static bool reserve_pmc_hardware(void)
 139 {
 140         int i;
 141
 142         for (i = 0; i < x86_pmu.num_counters; i++) {
 143                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 144                         goto perfctr_fail;
 145         }
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 149                         goto eventsel_fail;
 150         }
 151
 152         return true;
 153
 154 eventsel_fail:
 155         for (i--; i >= 0; i--)
 156                 release_evntsel_nmi(x86_pmu_config_addr(i));
 157
 158         i = x86_pmu.num_counters;
 159
 160 perfctr_fail:
 161         for (i--; i >= 0; i--)
 162                 release_perfctr_nmi(x86_pmu_event_addr(i));
 163
 164         return false;
 165 }
 166
 167 static void release_pmc_hardware(void)
 168 {
 169         int i;
 170
 171         for (i = 0; i < x86_pmu.num_counters; i++) {
 172                 release_perfctr_nmi(x86_pmu_event_addr(i));
 173                 release_evntsel_nmi(x86_pmu_config_addr(i));
 174         }
 175 }
 176
 177 #else
 178
 179 static bool reserve_pmc_hardware(void) { return true; }
 180 static void release_pmc_hardware(void) {}
 181
 182 #endif
 183
 184 static bool check_hw_exists(void)
 185 {
 186         u64 val, val_fail, val_new= ~0;
 187         int i, reg, reg_fail, ret = 0;
 188         int bios_fail = 0;
 189
 190         /*
 191          * Check to see if the BIOS enabled any of the counters, if so
 192          * complain and bail.
 193          */
 194         for (i = 0; i < x86_pmu.num_counters; i++) {
 195                 reg = x86_pmu_config_addr(i);
 196                 ret = rdmsrl_safe(reg, &val);
 197                 if (ret)
 198                         goto msr_fail;
 199                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 200                         bios_fail = 1;
 201                         val_fail = val;
 202                         reg_fail = reg;
 203                 }
 204         }
 205
 206         if (x86_pmu.num_counters_fixed) {
 207                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 208                 ret = rdmsrl_safe(reg, &val);
 209                 if (ret)
 210                         goto msr_fail;
 211                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 212                         if (val & (0x03 << i*4)) {
 213                                 bios_fail = 1;
 214                                 val_fail = val;
 215                                 reg_fail = reg;
 216                         }
 217                 }
 218         }
 219
 220         /*
 221          * Read the current value, change it and read it back to see if it
 222          * matches, this is needed to detect certain hardware emulators
 223          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 224          */
 225         reg = x86_pmu_event_addr(0);
 226         if (rdmsrl_safe(reg, &val))
 227                 goto msr_fail;
 228         val ^= 0xffffUL;
 229         ret = wrmsrl_safe(reg, val);
 230         ret |= rdmsrl_safe(reg, &val_new);
 231         if (ret || val != val_new)
 232                 goto msr_fail;
 233
 234         /*
 235          * We still allow the PMU driver to operate:
 236          */
 237         if (bios_fail) {
 238                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 239                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 240         }
 241
 242         return true;
 243
 244 msr_fail:
 245         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 246         printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
 247
 248         return false;
 249 }
 250
 251 static void hw_perf_event_destroy(struct perf_event *event)
 252 {
 253         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 254                 release_pmc_hardware();
 255                 release_ds_buffers();
 256                 mutex_unlock(&pmc_reserve_mutex);
 257         }
 258 }
 259
 260 static inline int x86_pmu_initialized(void)
 261 {
 262         return x86_pmu.handle_irq != NULL;
 263 }
 264
 265 static inline int
 266 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 267 {
 268         struct perf_event_attr *attr = &event->attr;
 269         unsigned int cache_type, cache_op, cache_result;
 270         u64 config, val;
 271
 272         config = attr->config;
 273
 274         cache_type = (config >>  0) & 0xff;
 275         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 276                 return -EINVAL;
 277
 278         cache_op = (config >>  8) & 0xff;
 279         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 280                 return -EINVAL;
 281
 282         cache_result = (config >> 16) & 0xff;
 283         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 284                 return -EINVAL;
 285
 286         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 287
 288         if (val == 0)
 289                 return -ENOENT;
 290
 291         if (val == -1)
 292                 return -EINVAL;
 293
 294         hwc->config |= val;
 295         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 296         return x86_pmu_extra_regs(val, event);
 297 }
 298
 299 int x86_setup_perfctr(struct perf_event *event)
 300 {
 301         struct perf_event_attr *attr = &event->attr;
 302         struct hw_perf_event *hwc = &event->hw;
 303         u64 config;
 304
 305         if (!is_sampling_event(event)) {
 306                 hwc->sample_period = x86_pmu.max_period;
 307                 hwc->last_period = hwc->sample_period;
 308                 local64_set(&hwc->period_left, hwc->sample_period);
 309         }
 310
 311         if (attr->type == PERF_TYPE_RAW)
 312                 return x86_pmu_extra_regs(event->attr.config, event);
 313
 314         if (attr->type == PERF_TYPE_HW_CACHE)
 315                 return set_ext_hw_attr(hwc, event);
 316
 317         if (attr->config >= x86_pmu.max_events)
 318                 return -EINVAL;
 319
 320         /*
 321          * The generic map:
 322          */
 323         config = x86_pmu.event_map(attr->config);
 324
 325         if (config == 0)
 326                 return -ENOENT;
 327
 328         if (config == -1LL)
 329                 return -EINVAL;
 330
 331         /*
 332          * Branch tracing:
 333          */
 334         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 335             !attr->freq && hwc->sample_period == 1) {
 336                 /* BTS is not supported by this architecture. */
 337                 if (!x86_pmu.bts_active)
 338                         return -EOPNOTSUPP;
 339
 340                 /* BTS is currently only allowed for user-mode. */
 341                 if (!attr->exclude_kernel)
 342                         return -EOPNOTSUPP;
 343         }
 344
 345         hwc->config |= config;
 346
 347         return 0;
 348 }
 349
 350 /*
 351  * check that branch_sample_type is compatible with
 352  * settings needed for precise_ip > 1 which implies
 353  * using the LBR to capture ALL taken branches at the
 354  * priv levels of the measurement
 355  */
 356 static inline int precise_br_compat(struct perf_event *event)
 357 {
 358         u64 m = event->attr.branch_sample_type;
 359         u64 b = 0;
 360
 361         /* must capture all branches */
 362         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 363                 return 0;
 364
 365         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 366
 367         if (!event->attr.exclude_user)
 368                 b |= PERF_SAMPLE_BRANCH_USER;
 369
 370         if (!event->attr.exclude_kernel)
 371                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 372
 373         /*
 374          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 375          */
 376
 377         return m == b;
 378 }
 379
 380 int x86_pmu_hw_config(struct perf_event *event)
 381 {
 382         if (event->attr.precise_ip) {
 383                 int precise = 0;
 384
 385                 /* Support for constant skid */
 386                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 387                         precise++;
 388
 389                         /* Support for IP fixup */
 390                         if (x86_pmu.lbr_nr)
 391                                 precise++;
 392                 }
 393
 394                 if (event->attr.precise_ip > precise)
 395                         return -EOPNOTSUPP;
 396                 /*
 397                  * check that PEBS LBR correction does not conflict with
 398                  * whatever the user is asking with attr->branch_sample_type
 399                  */
 400                 if (event->attr.precise_ip > 1 &&
 401                     x86_pmu.intel_cap.pebs_format < 2) {
 402                         u64 *br_type = &event->attr.branch_sample_type;
 403
 404                         if (has_branch_stack(event)) {
 405                                 if (!precise_br_compat(event))
 406                                         return -EOPNOTSUPP;
 407
 408                                 /* branch_sample_type is compatible */
 409
 410                         } else {
 411                                 /*
 412                                  * user did not specify  branch_sample_type
 413                                  *
 414                                  * For PEBS fixups, we capture all
 415                                  * the branches at the priv level of the
 416                                  * event.
 417                                  */
 418                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 419
 420                                 if (!event->attr.exclude_user)
 421                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 422
 423                                 if (!event->attr.exclude_kernel)
 424                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 425                         }
 426                 }
 427         }
 428
 429         /*
 430          * Generate PMC IRQs:
 431          * (keep 'enabled' bit clear for now)
 432          */
 433         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 434
 435         /*
 436          * Count user and OS events unless requested not to
 437          */
 438         if (!event->attr.exclude_user)
 439                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 440         if (!event->attr.exclude_kernel)
 441                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 442
 443         if (event->attr.type == PERF_TYPE_RAW)
 444                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 445
 446         return x86_setup_perfctr(event);
 447 }
 448
 449 /*
 450  * Setup the hardware configuration for a given attr_type
 451  */
 452 static int __x86_pmu_event_init(struct perf_event *event)
 453 {
 454         int err;
 455
 456         if (!x86_pmu_initialized())
 457                 return -ENODEV;
 458
 459         err = 0;
 460         if (!atomic_inc_not_zero(&active_events)) {
 461                 mutex_lock(&pmc_reserve_mutex);
 462                 if (atomic_read(&active_events) == 0) {
 463                         if (!reserve_pmc_hardware())
 464                                 err = -EBUSY;
 465                         else
 466                                 reserve_ds_buffers();
 467                 }
 468                 if (!err)
 469                         atomic_inc(&active_events);
 470                 mutex_unlock(&pmc_reserve_mutex);
 471         }
 472         if (err)
 473                 return err;
 474
 475         event->destroy = hw_perf_event_destroy;
 476
 477         event->hw.idx = -1;
 478         event->hw.last_cpu = -1;
 479         event->hw.last_tag = ~0ULL;
 480
 481         /* mark unused */
 482         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 483         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 484
 485         return x86_pmu.hw_config(event);
 486 }
 487
 488 void x86_pmu_disable_all(void)
 489 {
 490         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 491         int idx;
 492
 493         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 494                 u64 val;
 495
 496                 if (!test_bit(idx, cpuc->active_mask))
 497                         continue;
 498                 rdmsrl(x86_pmu_config_addr(idx), val);
 499                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 500                         continue;
 501                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 502                 wrmsrl(x86_pmu_config_addr(idx), val);
 503         }
 504 }
 505
 506 static void x86_pmu_disable(struct pmu *pmu)
 507 {
 508         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 509
 510         if (!x86_pmu_initialized())
 511                 return;
 512
 513         if (!cpuc->enabled)
 514                 return;
 515
 516         cpuc->n_added = 0;
 517         cpuc->enabled = 0;
 518         barrier();
 519
 520         x86_pmu.disable_all();
 521 }
 522
 523 void x86_pmu_enable_all(int added)
 524 {
 525         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 526         int idx;
 527
 528         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 529                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 530
 531                 if (!test_bit(idx, cpuc->active_mask))
 532                         continue;
 533
 534                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 535         }
 536 }
 537
 538 static struct pmu pmu;
 539
 540 static inline int is_x86_event(struct perf_event *event)
 541 {
 542         return event->pmu == &pmu;
 543 }
 544
 545 /*
 546  * Event scheduler state:
 547  *
 548  * Assign events iterating over all events and counters, beginning
 549  * with events with least weights first. Keep the current iterator
 550  * state in struct sched_state.
 551  */
 552 struct sched_state {
 553         int     weight;
 554         int     event;          /* event index */
 555         int     counter;        /* counter index */
 556         int     unassigned;     /* number of events to be assigned left */
 557         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 558 };
 559
 560 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 561 #define SCHED_STATES_MAX        2
 562
 563 struct perf_sched {
 564         int                     max_weight;
 565         int                     max_events;
 566         struct perf_event       **events;
 567         struct sched_state      state;
 568         int                     saved_states;
 569         struct sched_state      saved[SCHED_STATES_MAX];
 570 };
 571
 572 /*
 573  * Initialize interator that runs through all events and counters.
 574  */
 575 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
 576                             int num, int wmin, int wmax)
 577 {
 578         int idx;
 579
 580         memset(sched, 0, sizeof(*sched));
 581         sched->max_events       = num;
 582         sched->max_weight       = wmax;
 583         sched->events           = events;
 584
 585         for (idx = 0; idx < num; idx++) {
 586                 if (events[idx]->hw.constraint->weight == wmin)
 587                         break;
 588         }
 589
 590         sched->state.event      = idx;          /* start with min weight */
 591         sched->state.weight     = wmin;
 592         sched->state.unassigned = num;
 593 }
 594
 595 static void perf_sched_save_state(struct perf_sched *sched)
 596 {
 597         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 598                 return;
 599
 600         sched->saved[sched->saved_states] = sched->state;
 601         sched->saved_states++;
 602 }
 603
 604 static bool perf_sched_restore_state(struct perf_sched *sched)
 605 {
 606         if (!sched->saved_states)
 607                 return false;
 608
 609         sched->saved_states--;
 610         sched->state = sched->saved[sched->saved_states];
 611
 612         /* continue with next counter: */
 613         clear_bit(sched->state.counter++, sched->state.used);
 614
 615         return true;
 616 }
 617
 618 /*
 619  * Select a counter for the current event to schedule. Return true on
 620  * success.
 621  */
 622 static bool __perf_sched_find_counter(struct perf_sched *sched)
 623 {
 624         struct event_constraint *c;
 625         int idx;
 626
 627         if (!sched->state.unassigned)
 628                 return false;
 629
 630         if (sched->state.event >= sched->max_events)
 631                 return false;
 632
 633         c = sched->events[sched->state.event]->hw.constraint;
 634         /* Prefer fixed purpose counters */
 635         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 636                 idx = INTEL_PMC_IDX_FIXED;
 637                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 638                         if (!__test_and_set_bit(idx, sched->state.used))
 639                                 goto done;
 640                 }
 641         }
 642         /* Grab the first unused counter starting with idx */
 643         idx = sched->state.counter;
 644         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 645                 if (!__test_and_set_bit(idx, sched->state.used))
 646                         goto done;
 647         }
 648
 649         return false;
 650
 651 done:
 652         sched->state.counter = idx;
 653
 654         if (c->overlap)
 655                 perf_sched_save_state(sched);
 656
 657         return true;
 658 }
 659
 660 static bool perf_sched_find_counter(struct perf_sched *sched)
 661 {
 662         while (!__perf_sched_find_counter(sched)) {
 663                 if (!perf_sched_restore_state(sched))
 664                         return false;
 665         }
 666
 667         return true;
 668 }
 669
 670 /*
 671  * Go through all unassigned events and find the next one to schedule.
 672  * Take events with the least weight first. Return true on success.
 673  */
 674 static bool perf_sched_next_event(struct perf_sched *sched)
 675 {
 676         struct event_constraint *c;
 677
 678         if (!sched->state.unassigned || !--sched->state.unassigned)
 679                 return false;
 680
 681         do {
 682                 /* next event */
 683                 sched->state.event++;
 684                 if (sched->state.event >= sched->max_events) {
 685                         /* next weight */
 686                         sched->state.event = 0;
 687                         sched->state.weight++;
 688                         if (sched->state.weight > sched->max_weight)
 689                                 return false;
 690                 }
 691                 c = sched->events[sched->state.event]->hw.constraint;
 692         } while (c->weight != sched->state.weight);
 693
 694         sched->state.counter = 0;       /* start with first counter */
 695
 696         return true;
 697 }
 698
 699 /*
 700  * Assign a counter for each event.
 701  */
 702 int perf_assign_events(struct perf_event **events, int n,
 703                         int wmin, int wmax, int *assign)
 704 {
 705         struct perf_sched sched;
 706
 707         perf_sched_init(&sched, events, n, wmin, wmax);
 708
 709         do {
 710                 if (!perf_sched_find_counter(&sched))
 711                         break;  /* failed */
 712                 if (assign)
 713                         assign[sched.state.event] = sched.state.counter;
 714         } while (perf_sched_next_event(&sched));
 715
 716         return sched.state.unassigned;
 717 }
 718 EXPORT_SYMBOL_GPL(perf_assign_events);
 719
 720 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 721 {
 722         struct event_constraint *c;
 723         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 724         struct perf_event *e;
 725         int i, wmin, wmax, num = 0;
 726         struct hw_perf_event *hwc;
 727
 728         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 729
 730         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 731                 hwc = &cpuc->event_list[i]->hw;
 732                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 733                 hwc->constraint = c;
 734
 735                 wmin = min(wmin, c->weight);
 736                 wmax = max(wmax, c->weight);
 737         }
 738
 739         /*
 740          * fastpath, try to reuse previous register
 741          */
 742         for (i = 0; i < n; i++) {
 743                 hwc = &cpuc->event_list[i]->hw;
 744                 c = hwc->constraint;
 745
 746                 /* never assigned */
 747                 if (hwc->idx == -1)
 748                         break;
 749
 750                 /* constraint still honored */
 751                 if (!test_bit(hwc->idx, c->idxmsk))
 752                         break;
 753
 754                 /* not already used */
 755                 if (test_bit(hwc->idx, used_mask))
 756                         break;
 757
 758                 __set_bit(hwc->idx, used_mask);
 759                 if (assign)
 760                         assign[i] = hwc->idx;
 761         }
 762
 763         /* slow path */
 764         if (i != n)
 765                 num = perf_assign_events(cpuc->event_list, n, wmin,
 766                                          wmax, assign);
 767
 768         /*
 769          * Mark the event as committed, so we do not put_constraint()
 770          * in case new events are added and fail scheduling.
 771          */
 772         if (!num && assign) {
 773                 for (i = 0; i < n; i++) {
 774                         e = cpuc->event_list[i];
 775                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 776                 }
 777         }
 778         /*
 779          * scheduling failed or is just a simulation,
 780          * free resources if necessary
 781          */
 782         if (!assign || num) {
 783                 for (i = 0; i < n; i++) {
 784                         e = cpuc->event_list[i];
 785                         /*
 786                          * do not put_constraint() on comitted events,
 787                          * because they are good to go
 788                          */
 789                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 790                                 continue;
 791
 792                         if (x86_pmu.put_event_constraints)
 793                                 x86_pmu.put_event_constraints(cpuc, e);
 794                 }
 795         }
 796         return num ? -EINVAL : 0;
 797 }
 798
 799 /*
 800  * dogrp: true if must collect siblings events (group)
 801  * returns total number of events and error code
 802  */
 803 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 804 {
 805         struct perf_event *event;
 806         int n, max_count;
 807
 808         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 809
 810         /* current number of events already accepted */
 811         n = cpuc->n_events;
 812
 813         if (is_x86_event(leader)) {
 814                 if (n >= max_count)
 815                         return -EINVAL;
 816                 cpuc->event_list[n] = leader;
 817                 n++;
 818         }
 819         if (!dogrp)
 820                 return n;
 821
 822         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 823                 if (!is_x86_event(event) ||
 824                     event->state <= PERF_EVENT_STATE_OFF)
 825                         continue;
 826
 827                 if (n >= max_count)
 828                         return -EINVAL;
 829
 830                 cpuc->event_list[n] = event;
 831                 n++;
 832         }
 833         return n;
 834 }
 835
 836 static inline void x86_assign_hw_event(struct perf_event *event,
 837                                 struct cpu_hw_events *cpuc, int i)
 838 {
 839         struct hw_perf_event *hwc = &event->hw;
 840
 841         hwc->idx = cpuc->assign[i];
 842         hwc->last_cpu = smp_processor_id();
 843         hwc->last_tag = ++cpuc->tags[i];
 844
 845         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 846                 hwc->config_base = 0;
 847                 hwc->event_base = 0;
 848         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 849                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 850                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 851                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 852         } else {
 853                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 854                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 855                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 856         }
 857 }
 858
 859 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 860                                         struct cpu_hw_events *cpuc,
 861                                         int i)
 862 {
 863         return hwc->idx == cpuc->assign[i] &&
 864                 hwc->last_cpu == smp_processor_id() &&
 865                 hwc->last_tag == cpuc->tags[i];
 866 }
 867
 868 static void x86_pmu_start(struct perf_event *event, int flags);
 869
 870 static void x86_pmu_enable(struct pmu *pmu)
 871 {
 872         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 873         struct perf_event *event;
 874         struct hw_perf_event *hwc;
 875         int i, added = cpuc->n_added;
 876
 877         if (!x86_pmu_initialized())
 878                 return;
 879
 880         if (cpuc->enabled)
 881                 return;
 882
 883         if (cpuc->n_added) {
 884                 int n_running = cpuc->n_events - cpuc->n_added;
 885                 /*
 886                  * apply assignment obtained either from
 887                  * hw_perf_group_sched_in() or x86_pmu_enable()
 888                  *
 889                  * step1: save events moving to new counters
 890                  */
 891                 for (i = 0; i < n_running; i++) {
 892                         event = cpuc->event_list[i];
 893                         hwc = &event->hw;
 894
 895                         /*
 896                          * we can avoid reprogramming counter if:
 897                          * - assigned same counter as last time
 898                          * - running on same CPU as last time
 899                          * - no other event has used the counter since
 900                          */
 901                         if (hwc->idx == -1 ||
 902                             match_prev_assignment(hwc, cpuc, i))
 903                                 continue;
 904
 905                         /*
 906                          * Ensure we don't accidentally enable a stopped
 907                          * counter simply because we rescheduled.
 908                          */
 909                         if (hwc->state & PERF_HES_STOPPED)
 910                                 hwc->state |= PERF_HES_ARCH;
 911
 912                         x86_pmu_stop(event, PERF_EF_UPDATE);
 913                 }
 914
 915                 /*
 916                  * step2: reprogram moved events into new counters
 917                  */
 918                 for (i = 0; i < cpuc->n_events; i++) {
 919                         event = cpuc->event_list[i];
 920                         hwc = &event->hw;
 921
 922                         if (!match_prev_assignment(hwc, cpuc, i))
 923                                 x86_assign_hw_event(event, cpuc, i);
 924                         else if (i < n_running)
 925                                 continue;
 926
 927                         if (hwc->state & PERF_HES_ARCH)
 928                                 continue;
 929
 930                         x86_pmu_start(event, PERF_EF_RELOAD);
 931                 }
 932                 cpuc->n_added = 0;
 933                 perf_events_lapic_init();
 934         }
 935
 936         cpuc->enabled = 1;
 937         barrier();
 938
 939         x86_pmu.enable_all(added);
 940 }
 941
 942 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 943
 944 /*
 945  * Set the next IRQ period, based on the hwc->period_left value.
 946  * To be called with the event disabled in hw:
 947  */
 948 int x86_perf_event_set_period(struct perf_event *event)
 949 {
 950         struct hw_perf_event *hwc = &event->hw;
 951         s64 left = local64_read(&hwc->period_left);
 952         s64 period = hwc->sample_period;
 953         int ret = 0, idx = hwc->idx;
 954
 955         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 956                 return 0;
 957
 958         /*
 959          * If we are way outside a reasonable range then just skip forward:
 960          */
 961         if (unlikely(left <= -period)) {
 962                 left = period;
 963                 local64_set(&hwc->period_left, left);
 964                 hwc->last_period = period;
 965                 ret = 1;
 966         }
 967
 968         if (unlikely(left <= 0)) {
 969                 left += period;
 970                 local64_set(&hwc->period_left, left);
 971                 hwc->last_period = period;
 972                 ret = 1;
 973         }
 974         /*
 975          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 976          */
 977         if (unlikely(left < 2))
 978                 left = 2;
 979
 980         if (left > x86_pmu.max_period)
 981                 left = x86_pmu.max_period;
 982
 983         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 984
 985         /*
 986          * The hw event starts counting from this event offset,
 987          * mark it to be able to extra future deltas:
 988          */
 989         local64_set(&hwc->prev_count, (u64)-left);
 990
 991         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 992
 993         /*
 994          * Due to erratum on certan cpu we need
 995          * a second write to be sure the register
 996          * is updated properly
 997          */
 998         if (x86_pmu.perfctr_second_write) {
 999                 wrmsrl(hwc->event_base,
1000                         (u64)(-left) & x86_pmu.cntval_mask);
1001         }
1002
1003         perf_event_update_userpage(event);
1004
1005         return ret;
1006 }
1007
1008 void x86_pmu_enable_event(struct perf_event *event)
1009 {
1010         if (__this_cpu_read(cpu_hw_events.enabled))
1011                 __x86_pmu_enable_event(&event->hw,
1012                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1013 }
1014
1015 /*
1016  * Add a single event to the PMU.
1017  *
1018  * The event is added to the group of enabled events
1019  * but only if it can be scehduled with existing events.
1020  */
1021 static int x86_pmu_add(struct perf_event *event, int flags)
1022 {
1023         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1024         struct hw_perf_event *hwc;
1025         int assign[X86_PMC_IDX_MAX];
1026         int n, n0, ret;
1027
1028         hwc = &event->hw;
1029
1030         perf_pmu_disable(event->pmu);
1031         n0 = cpuc->n_events;
1032         ret = n = collect_events(cpuc, event, false);
1033         if (ret < 0)
1034                 goto out;
1035
1036         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1037         if (!(flags & PERF_EF_START))
1038                 hwc->state |= PERF_HES_ARCH;
1039
1040         /*
1041          * If group events scheduling transaction was started,
1042          * skip the schedulability test here, it will be performed
1043          * at commit time (->commit_txn) as a whole.
1044          */
1045         if (cpuc->group_flag & PERF_EVENT_TXN)
1046                 goto done_collect;
1047
1048         ret = x86_pmu.schedule_events(cpuc, n, assign);
1049         if (ret)
1050                 goto out;
1051         /*
1052          * copy new assignment, now we know it is possible
1053          * will be used by hw_perf_enable()
1054          */
1055         memcpy(cpuc->assign, assign, n*sizeof(int));
1056
1057 done_collect:
1058         /*
1059          * Commit the collect_events() state. See x86_pmu_del() and
1060          * x86_pmu_*_txn().
1061          */
1062         cpuc->n_events = n;
1063         cpuc->n_added += n - n0;
1064         cpuc->n_txn += n - n0;
1065
1066         ret = 0;
1067 out:
1068         perf_pmu_enable(event->pmu);
1069         return ret;
1070 }
1071
1072 static void x86_pmu_start(struct perf_event *event, int flags)
1073 {
1074         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1075         int idx = event->hw.idx;
1076
1077         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1078                 return;
1079
1080         if (WARN_ON_ONCE(idx == -1))
1081                 return;
1082
1083         if (flags & PERF_EF_RELOAD) {
1084                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1085                 x86_perf_event_set_period(event);
1086         }
1087
1088         event->hw.state = 0;
1089
1090         cpuc->events[idx] = event;
1091         __set_bit(idx, cpuc->active_mask);
1092         __set_bit(idx, cpuc->running);
1093         x86_pmu.enable(event);
1094         perf_event_update_userpage(event);
1095 }
1096
1097 void perf_event_print_debug(void)
1098 {
1099         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1100         u64 pebs;
1101         struct cpu_hw_events *cpuc;
1102         unsigned long flags;
1103         int cpu, idx;
1104
1105         if (!x86_pmu.num_counters)
1106                 return;
1107
1108         local_irq_save(flags);
1109
1110         cpu = smp_processor_id();
1111         cpuc = &per_cpu(cpu_hw_events, cpu);
1112
1113         if (x86_pmu.version >= 2) {
1114                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1115                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1116                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1117                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1118                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1119
1120                 pr_info("\n");
1121                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1122                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1123                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1124                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1125                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1126         }
1127         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1128
1129         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1130                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1131                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1132
1133                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1134
1135                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1136                         cpu, idx, pmc_ctrl);
1137                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1138                         cpu, idx, pmc_count);
1139                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1140                         cpu, idx, prev_left);
1141         }
1142         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1143                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1144
1145                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1146                         cpu, idx, pmc_count);
1147         }
1148         local_irq_restore(flags);
1149 }
1150
1151 void x86_pmu_stop(struct perf_event *event, int flags)
1152 {
1153         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1154         struct hw_perf_event *hwc = &event->hw;
1155
1156         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1157                 x86_pmu.disable(event);
1158                 cpuc->events[hwc->idx] = NULL;
1159                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1160                 hwc->state |= PERF_HES_STOPPED;
1161         }
1162
1163         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1164                 /*
1165                  * Drain the remaining delta count out of a event
1166                  * that we are disabling:
1167                  */
1168                 x86_perf_event_update(event);
1169                 hwc->state |= PERF_HES_UPTODATE;
1170         }
1171 }
1172
1173 static void x86_pmu_del(struct perf_event *event, int flags)
1174 {
1175         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1176         int i;
1177
1178         /*
1179          * event is descheduled
1180          */
1181         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1182
1183         /*
1184          * If we're called during a txn, we don't need to do anything.
1185          * The events never got scheduled and ->cancel_txn will truncate
1186          * the event_list.
1187          *
1188          * XXX assumes any ->del() called during a TXN will only be on
1189          * an event added during that same TXN.
1190          */
1191         if (cpuc->group_flag & PERF_EVENT_TXN)
1192                 return;
1193
1194         /*
1195          * Not a TXN, therefore cleanup properly.
1196          */
1197         x86_pmu_stop(event, PERF_EF_UPDATE);
1198
1199         for (i = 0; i < cpuc->n_events; i++) {
1200                 if (event == cpuc->event_list[i])
1201                         break;
1202         }
1203
1204         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1205                 return;
1206
1207         /* If we have a newly added event; make sure to decrease n_added. */
1208         if (i >= cpuc->n_events - cpuc->n_added)
1209                 --cpuc->n_added;
1210
1211         if (x86_pmu.put_event_constraints)
1212                 x86_pmu.put_event_constraints(cpuc, event);
1213
1214         /* Delete the array entry. */
1215         while (++i < cpuc->n_events)
1216                 cpuc->event_list[i-1] = cpuc->event_list[i];
1217         --cpuc->n_events;
1218
1219         perf_event_update_userpage(event);
1220 }
1221
1222 int x86_pmu_handle_irq(struct pt_regs *regs)
1223 {
1224         struct perf_sample_data data;
1225         struct cpu_hw_events *cpuc;
1226         struct perf_event *event;
1227         int idx, handled = 0;
1228         u64 val;
1229
1230         cpuc = &__get_cpu_var(cpu_hw_events);
1231
1232         /*
1233          * Some chipsets need to unmask the LVTPC in a particular spot
1234          * inside the nmi handler.  As a result, the unmasking was pushed
1235          * into all the nmi handlers.
1236          *
1237          * This generic handler doesn't seem to have any issues where the
1238          * unmasking occurs so it was left at the top.
1239          */
1240         apic_write(APIC_LVTPC, APIC_DM_NMI);
1241
1242         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1243                 if (!test_bit(idx, cpuc->active_mask)) {
1244                         /*
1245                          * Though we deactivated the counter some cpus
1246                          * might still deliver spurious interrupts still
1247                          * in flight. Catch them:
1248                          */
1249                         if (__test_and_clear_bit(idx, cpuc->running))
1250                                 handled++;
1251                         continue;
1252                 }
1253
1254                 event = cpuc->events[idx];
1255
1256                 val = x86_perf_event_update(event);
1257                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1258                         continue;
1259
1260                 /*
1261                  * event overflow
1262                  */
1263                 handled++;
1264                 perf_sample_data_init(&data, 0, event->hw.last_period);
1265
1266                 if (!x86_perf_event_set_period(event))
1267                         continue;
1268
1269                 if (perf_event_overflow(event, &data, regs))
1270                         x86_pmu_stop(event, 0);
1271         }
1272
1273         if (handled)
1274                 inc_irq_stat(apic_perf_irqs);
1275
1276         return handled;
1277 }
1278
1279 void perf_events_lapic_init(void)
1280 {
1281         if (!x86_pmu.apic || !x86_pmu_initialized())
1282                 return;
1283
1284         /*
1285          * Always use NMI for PMU
1286          */
1287         apic_write(APIC_LVTPC, APIC_DM_NMI);
1288 }
1289
1290 static int
1291 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1292 {
1293         u64 start_clock;
1294         u64 finish_clock;
1295         int ret;
1296
1297         if (!atomic_read(&active_events))
1298                 return NMI_DONE;
1299
1300         start_clock = sched_clock();
1301         ret = x86_pmu.handle_irq(regs);
1302         finish_clock = sched_clock();
1303
1304         perf_sample_event_took(finish_clock - start_clock);
1305
1306         return ret;
1307 }
1308 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1309
1310 struct event_constraint emptyconstraint;
1311 struct event_constraint unconstrained;
1312
1313 static int
1314 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1315 {
1316         unsigned int cpu = (long)hcpu;
1317         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1318         int ret = NOTIFY_OK;
1319
1320         switch (action & ~CPU_TASKS_FROZEN) {
1321         case CPU_UP_PREPARE:
1322                 cpuc->kfree_on_online = NULL;
1323                 if (x86_pmu.cpu_prepare)
1324                         ret = x86_pmu.cpu_prepare(cpu);
1325                 break;
1326
1327         case CPU_STARTING:
1328                 if (x86_pmu.attr_rdpmc)
1329                         set_in_cr4(X86_CR4_PCE);
1330                 if (x86_pmu.cpu_starting)
1331                         x86_pmu.cpu_starting(cpu);
1332                 break;
1333
1334         case CPU_ONLINE:
1335                 kfree(cpuc->kfree_on_online);
1336                 break;
1337
1338         case CPU_DYING:
1339                 if (x86_pmu.cpu_dying)
1340                         x86_pmu.cpu_dying(cpu);
1341                 break;
1342
1343         case CPU_UP_CANCELED:
1344         case CPU_DEAD:
1345                 if (x86_pmu.cpu_dead)
1346                         x86_pmu.cpu_dead(cpu);
1347                 break;
1348
1349         default:
1350                 break;
1351         }
1352
1353         return ret;
1354 }
1355
1356 static void __init pmu_check_apic(void)
1357 {
1358         if (cpu_has_apic)
1359                 return;
1360
1361         x86_pmu.apic = 0;
1362         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1363         pr_info("no hardware sampling interrupt available.\n");
1364
1365         /*
1366          * If we have a PMU initialized but no APIC
1367          * interrupts, we cannot sample hardware
1368          * events (user-space has to fall back and
1369          * sample via a hrtimer based software event):
1370          */
1371         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1372
1373 }
1374
1375 static struct attribute_group x86_pmu_format_group = {
1376         .name = "format",
1377         .attrs = NULL,
1378 };
1379
1380 /*
1381  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1382  * out of events_attr attributes.
1383  */
1384 static void __init filter_events(struct attribute **attrs)
1385 {
1386         struct device_attribute *d;
1387         struct perf_pmu_events_attr *pmu_attr;
1388         int i, j;
1389
1390         for (i = 0; attrs[i]; i++) {
1391                 d = (struct device_attribute *)attrs[i];
1392                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1393                 /* str trumps id */
1394                 if (pmu_attr->event_str)
1395                         continue;
1396                 if (x86_pmu.event_map(i))
1397                         continue;
1398
1399                 for (j = i; attrs[j]; j++)
1400                         attrs[j] = attrs[j + 1];
1401
1402                 /* Check the shifted attr. */
1403                 i--;
1404         }
1405 }
1406
1407 /* Merge two pointer arrays */
1408 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1409 {
1410         struct attribute **new;
1411         int j, i;
1412
1413         for (j = 0; a[j]; j++)
1414                 ;
1415         for (i = 0; b[i]; i++)
1416                 j++;
1417         j++;
1418
1419         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1420         if (!new)
1421                 return NULL;
1422
1423         j = 0;
1424         for (i = 0; a[i]; i++)
1425                 new[j++] = a[i];
1426         for (i = 0; b[i]; i++)
1427                 new[j++] = b[i];
1428         new[j] = NULL;
1429
1430         return new;
1431 }
1432
1433 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1434                           char *page)
1435 {
1436         struct perf_pmu_events_attr *pmu_attr = \
1437                 container_of(attr, struct perf_pmu_events_attr, attr);
1438         u64 config = x86_pmu.event_map(pmu_attr->id);
1439
1440         /* string trumps id */
1441         if (pmu_attr->event_str)
1442                 return sprintf(page, "%s", pmu_attr->event_str);
1443
1444         return x86_pmu.events_sysfs_show(page, config);
1445 }
1446
1447 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1448 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1449 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1450 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1451 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1452 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1453 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1454 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1455 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1456 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1457
1458 static struct attribute *empty_attrs;
1459
1460 static struct attribute *events_attr[] = {
1461         EVENT_PTR(CPU_CYCLES),
1462         EVENT_PTR(INSTRUCTIONS),
1463         EVENT_PTR(CACHE_REFERENCES),
1464         EVENT_PTR(CACHE_MISSES),
1465         EVENT_PTR(BRANCH_INSTRUCTIONS),
1466         EVENT_PTR(BRANCH_MISSES),
1467         EVENT_PTR(BUS_CYCLES),
1468         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1469         EVENT_PTR(STALLED_CYCLES_BACKEND),
1470         EVENT_PTR(REF_CPU_CYCLES),
1471         NULL,
1472 };
1473
1474 static struct attribute_group x86_pmu_events_group = {
1475         .name = "events",
1476         .attrs = events_attr,
1477 };
1478
1479 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1480 {
1481         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1482         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1483         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1484         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1485         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1486         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1487         ssize_t ret;
1488
1489         /*
1490         * We have whole page size to spend and just little data
1491         * to write, so we can safely use sprintf.
1492         */
1493         ret = sprintf(page, "event=0x%02llx", event);
1494
1495         if (umask)
1496                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1497
1498         if (edge)
1499                 ret += sprintf(page + ret, ",edge");
1500
1501         if (pc)
1502                 ret += sprintf(page + ret, ",pc");
1503
1504         if (any)
1505                 ret += sprintf(page + ret, ",any");
1506
1507         if (inv)
1508                 ret += sprintf(page + ret, ",inv");
1509
1510         if (cmask)
1511                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1512
1513         ret += sprintf(page + ret, "\n");
1514
1515         return ret;
1516 }
1517
1518 static int __init init_hw_perf_events(void)
1519 {
1520         struct x86_pmu_quirk *quirk;
1521         int err;
1522
1523         pr_info("Performance Events: ");
1524
1525         switch (boot_cpu_data.x86_vendor) {
1526         case X86_VENDOR_INTEL:
1527                 err = intel_pmu_init();
1528                 break;
1529         case X86_VENDOR_AMD:
1530                 err = amd_pmu_init();
1531                 break;
1532         default:
1533                 err = -ENOTSUPP;
1534         }
1535         if (err != 0) {
1536                 pr_cont("no PMU driver, software events only.\n");
1537                 return 0;
1538         }
1539
1540         pmu_check_apic();
1541
1542         /* sanity check that the hardware exists or is emulated */
1543         if (!check_hw_exists())
1544                 return 0;
1545
1546         pr_cont("%s PMU driver.\n", x86_pmu.name);
1547
1548         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1549
1550         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1551                 quirk->func();
1552
1553         if (!x86_pmu.intel_ctrl)
1554                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1555
1556         perf_events_lapic_init();
1557         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1558
1559         unconstrained = (struct event_constraint)
1560                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1561                                    0, x86_pmu.num_counters, 0, 0);
1562
1563         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1564
1565         if (x86_pmu.event_attrs)
1566                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1567
1568         if (!x86_pmu.events_sysfs_show)
1569                 x86_pmu_events_group.attrs = &empty_attrs;
1570         else
1571                 filter_events(x86_pmu_events_group.attrs);
1572
1573         if (x86_pmu.cpu_events) {
1574                 struct attribute **tmp;
1575
1576                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1577                 if (!WARN_ON(!tmp))
1578                         x86_pmu_events_group.attrs = tmp;
1579         }
1580
1581         pr_info("... version:                %d\n",     x86_pmu.version);
1582         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1583         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1584         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1585         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1586         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1587         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1588
1589         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1590         perf_cpu_notifier(x86_pmu_notifier);
1591
1592         return 0;
1593 }
1594 early_initcall(init_hw_perf_events);
1595
1596 static inline void x86_pmu_read(struct perf_event *event)
1597 {
1598         x86_perf_event_update(event);
1599 }
1600
1601 /*
1602  * Start group events scheduling transaction
1603  * Set the flag to make pmu::enable() not perform the
1604  * schedulability test, it will be performed at commit time
1605  */
1606 static void x86_pmu_start_txn(struct pmu *pmu)
1607 {
1608         perf_pmu_disable(pmu);
1609         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1610         __this_cpu_write(cpu_hw_events.n_txn, 0);
1611 }
1612
1613 /*
1614  * Stop group events scheduling transaction
1615  * Clear the flag and pmu::enable() will perform the
1616  * schedulability test.
1617  */
1618 static void x86_pmu_cancel_txn(struct pmu *pmu)
1619 {
1620         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1621         /*
1622          * Truncate collected array by the number of events added in this
1623          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1624          */
1625         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1626         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1627         perf_pmu_enable(pmu);
1628 }
1629
1630 /*
1631  * Commit group events scheduling transaction
1632  * Perform the group schedulability test as a whole
1633  * Return 0 if success
1634  *
1635  * Does not cancel the transaction on failure; expects the caller to do this.
1636  */
1637 static int x86_pmu_commit_txn(struct pmu *pmu)
1638 {
1639         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1640         int assign[X86_PMC_IDX_MAX];
1641         int n, ret;
1642
1643         n = cpuc->n_events;
1644
1645         if (!x86_pmu_initialized())
1646                 return -EAGAIN;
1647
1648         ret = x86_pmu.schedule_events(cpuc, n, assign);
1649         if (ret)
1650                 return ret;
1651
1652         /*
1653          * copy new assignment, now we know it is possible
1654          * will be used by hw_perf_enable()
1655          */
1656         memcpy(cpuc->assign, assign, n*sizeof(int));
1657
1658         cpuc->group_flag &= ~PERF_EVENT_TXN;
1659         perf_pmu_enable(pmu);
1660         return 0;
1661 }
1662 /*
1663  * a fake_cpuc is used to validate event groups. Due to
1664  * the extra reg logic, we need to also allocate a fake
1665  * per_core and per_cpu structure. Otherwise, group events
1666  * using extra reg may conflict without the kernel being
1667  * able to catch this when the last event gets added to
1668  * the group.
1669  */
1670 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1671 {
1672         kfree(cpuc->shared_regs);
1673         kfree(cpuc);
1674 }
1675
1676 static struct cpu_hw_events *allocate_fake_cpuc(void)
1677 {
1678         struct cpu_hw_events *cpuc;
1679         int cpu = raw_smp_processor_id();
1680
1681         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1682         if (!cpuc)
1683                 return ERR_PTR(-ENOMEM);
1684
1685         /* only needed, if we have extra_regs */
1686         if (x86_pmu.extra_regs) {
1687                 cpuc->shared_regs = allocate_shared_regs(cpu);
1688                 if (!cpuc->shared_regs)
1689                         goto error;
1690         }
1691         cpuc->is_fake = 1;
1692         return cpuc;
1693 error:
1694         free_fake_cpuc(cpuc);
1695         return ERR_PTR(-ENOMEM);
1696 }
1697
1698 /*
1699  * validate that we can schedule this event
1700  */
1701 static int validate_event(struct perf_event *event)
1702 {
1703         struct cpu_hw_events *fake_cpuc;
1704         struct event_constraint *c;
1705         int ret = 0;
1706
1707         fake_cpuc = allocate_fake_cpuc();
1708         if (IS_ERR(fake_cpuc))
1709                 return PTR_ERR(fake_cpuc);
1710
1711         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1712
1713         if (!c || !c->weight)
1714                 ret = -EINVAL;
1715
1716         if (x86_pmu.put_event_constraints)
1717                 x86_pmu.put_event_constraints(fake_cpuc, event);
1718
1719         free_fake_cpuc(fake_cpuc);
1720
1721         return ret;
1722 }
1723
1724 /*
1725  * validate a single event group
1726  *
1727  * validation include:
1728  *      - check events are compatible which each other
1729  *      - events do not compete for the same counter
1730  *      - number of events <= number of counters
1731  *
1732  * validation ensures the group can be loaded onto the
1733  * PMU if it was the only group available.
1734  */
1735 static int validate_group(struct perf_event *event)
1736 {
1737         struct perf_event *leader = event->group_leader;
1738         struct cpu_hw_events *fake_cpuc;
1739         int ret = -EINVAL, n;
1740
1741         fake_cpuc = allocate_fake_cpuc();
1742         if (IS_ERR(fake_cpuc))
1743                 return PTR_ERR(fake_cpuc);
1744         /*
1745          * the event is not yet connected with its
1746          * siblings therefore we must first collect
1747          * existing siblings, then add the new event
1748          * before we can simulate the scheduling
1749          */
1750         n = collect_events(fake_cpuc, leader, true);
1751         if (n < 0)
1752                 goto out;
1753
1754         fake_cpuc->n_events = n;
1755         n = collect_events(fake_cpuc, event, false);
1756         if (n < 0)
1757                 goto out;
1758
1759         fake_cpuc->n_events = n;
1760
1761         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1762
1763 out:
1764         free_fake_cpuc(fake_cpuc);
1765         return ret;
1766 }
1767
1768 static int x86_pmu_event_init(struct perf_event *event)
1769 {
1770         struct pmu *tmp;
1771         int err;
1772
1773         switch (event->attr.type) {
1774         case PERF_TYPE_RAW:
1775         case PERF_TYPE_HARDWARE:
1776         case PERF_TYPE_HW_CACHE:
1777                 break;
1778
1779         default:
1780                 return -ENOENT;
1781         }
1782
1783         err = __x86_pmu_event_init(event);
1784         if (!err) {
1785                 /*
1786                  * we temporarily connect event to its pmu
1787                  * such that validate_group() can classify
1788                  * it as an x86 event using is_x86_event()
1789                  */
1790                 tmp = event->pmu;
1791                 event->pmu = &pmu;
1792
1793                 if (event->group_leader != event)
1794                         err = validate_group(event);
1795                 else
1796                         err = validate_event(event);
1797
1798                 event->pmu = tmp;
1799         }
1800         if (err) {
1801                 if (event->destroy)
1802                         event->destroy(event);
1803         }
1804
1805         return err;
1806 }
1807
1808 static int x86_pmu_event_idx(struct perf_event *event)
1809 {
1810         int idx = event->hw.idx;
1811
1812         if (!x86_pmu.attr_rdpmc)
1813                 return 0;
1814
1815         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1816                 idx -= INTEL_PMC_IDX_FIXED;
1817                 idx |= 1 << 30;
1818         }
1819
1820         return idx + 1;
1821 }
1822
1823 static ssize_t get_attr_rdpmc(struct device *cdev,
1824                               struct device_attribute *attr,
1825                               char *buf)
1826 {
1827         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1828 }
1829
1830 static void change_rdpmc(void *info)
1831 {
1832         bool enable = !!(unsigned long)info;
1833
1834         if (enable)
1835                 set_in_cr4(X86_CR4_PCE);
1836         else
1837                 clear_in_cr4(X86_CR4_PCE);
1838 }
1839
1840 static ssize_t set_attr_rdpmc(struct device *cdev,
1841                               struct device_attribute *attr,
1842                               const char *buf, size_t count)
1843 {
1844         unsigned long val;
1845         ssize_t ret;
1846
1847         ret = kstrtoul(buf, 0, &val);
1848         if (ret)
1849                 return ret;
1850
1851         if (x86_pmu.attr_rdpmc_broken)
1852                 return -ENOTSUPP;
1853
1854         if (!!val != !!x86_pmu.attr_rdpmc) {
1855                 x86_pmu.attr_rdpmc = !!val;
1856                 on_each_cpu(change_rdpmc, (void *)val, 1);
1857         }
1858
1859         return count;
1860 }
1861
1862 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1863
1864 static struct attribute *x86_pmu_attrs[] = {
1865         &dev_attr_rdpmc.attr,
1866         NULL,
1867 };
1868
1869 static struct attribute_group x86_pmu_attr_group = {
1870         .attrs = x86_pmu_attrs,
1871 };
1872
1873 static const struct attribute_group *x86_pmu_attr_groups[] = {
1874         &x86_pmu_attr_group,
1875         &x86_pmu_format_group,
1876         &x86_pmu_events_group,
1877         NULL,
1878 };
1879
1880 static void x86_pmu_flush_branch_stack(void)
1881 {
1882         if (x86_pmu.flush_branch_stack)
1883                 x86_pmu.flush_branch_stack();
1884 }
1885
1886 void perf_check_microcode(void)
1887 {
1888         if (x86_pmu.check_microcode)
1889                 x86_pmu.check_microcode();
1890 }
1891 EXPORT_SYMBOL_GPL(perf_check_microcode);
1892
1893 static struct pmu pmu = {
1894         .pmu_enable             = x86_pmu_enable,
1895         .pmu_disable            = x86_pmu_disable,
1896
1897         .attr_groups            = x86_pmu_attr_groups,
1898
1899         .event_init             = x86_pmu_event_init,
1900
1901         .add                    = x86_pmu_add,
1902         .del                    = x86_pmu_del,
1903         .start                  = x86_pmu_start,
1904         .stop                   = x86_pmu_stop,
1905         .read                   = x86_pmu_read,
1906
1907         .start_txn              = x86_pmu_start_txn,
1908         .cancel_txn             = x86_pmu_cancel_txn,
1909         .commit_txn             = x86_pmu_commit_txn,
1910
1911         .event_idx              = x86_pmu_event_idx,
1912         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1913 };
1914
1915 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1916 {
1917         struct cyc2ns_data *data;
1918
1919         userpg->cap_user_time = 0;
1920         userpg->cap_user_time_zero = 0;
1921         userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1922         userpg->pmc_width = x86_pmu.cntval_bits;
1923
1924         if (!sched_clock_stable())
1925                 return;
1926
1927         data = cyc2ns_read_begin();
1928
1929         userpg->cap_user_time = 1;
1930         userpg->time_mult = data->cyc2ns_mul;
1931         userpg->time_shift = data->cyc2ns_shift;
1932         userpg->time_offset = data->cyc2ns_offset - now;
1933
1934         userpg->cap_user_time_zero = 1;
1935         userpg->time_zero = data->cyc2ns_offset;
1936
1937         cyc2ns_read_end(data);
1938 }
1939
1940 /*
1941  * callchain support
1942  */
1943
1944 static int backtrace_stack(void *data, char *name)
1945 {
1946         return 0;
1947 }
1948
1949 static void backtrace_address(void *data, unsigned long addr, int reliable)
1950 {
1951         struct perf_callchain_entry *entry = data;
1952
1953         perf_callchain_store(entry, addr);
1954 }
1955
1956 static const struct stacktrace_ops backtrace_ops = {
1957         .stack                  = backtrace_stack,
1958         .address                = backtrace_address,
1959         .walk_stack             = print_context_stack_bp,
1960 };
1961
1962 void
1963 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1964 {
1965         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1966                 /* TODO: We don't support guest os callchain now */
1967                 return;
1968         }
1969
1970         perf_callchain_store(entry, regs->ip);
1971
1972         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1973 }
1974
1975 static inline int
1976 valid_user_frame(const void __user *fp, unsigned long size)
1977 {
1978         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1979 }
1980
1981 static unsigned long get_segment_base(unsigned int segment)
1982 {
1983         struct desc_struct *desc;
1984         int idx = segment >> 3;
1985
1986         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1987                 if (idx > LDT_ENTRIES)
1988                         return 0;
1989
1990                 if (idx > current->active_mm->context.size)
1991                         return 0;
1992
1993                 desc = current->active_mm->context.ldt;
1994         } else {
1995                 if (idx > GDT_ENTRIES)
1996                         return 0;
1997
1998                 desc = __this_cpu_ptr(&gdt_page.gdt[0]);
1999         }
2000
2001         return get_desc_base(desc + idx);
2002 }
2003
2004 #ifdef CONFIG_COMPAT
2005
2006 #include <asm/compat.h>
2007
2008 static inline int
2009 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2010 {
2011         /* 32-bit process in 64-bit kernel. */
2012         unsigned long ss_base, cs_base;
2013         struct stack_frame_ia32 frame;
2014         const void __user *fp;
2015
2016         if (!test_thread_flag(TIF_IA32))
2017                 return 0;
2018
2019         cs_base = get_segment_base(regs->cs);
2020         ss_base = get_segment_base(regs->ss);
2021
2022         fp = compat_ptr(ss_base + regs->bp);
2023         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2024                 unsigned long bytes;
2025                 frame.next_frame     = 0;
2026                 frame.return_address = 0;
2027
2028                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2029                 if (bytes != 0)
2030                         break;
2031
2032                 if (!valid_user_frame(fp, sizeof(frame)))
2033                         break;
2034
2035                 perf_callchain_store(entry, cs_base + frame.return_address);
2036                 fp = compat_ptr(ss_base + frame.next_frame);
2037         }
2038         return 1;
2039 }
2040 #else
2041 static inline int
2042 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2043 {
2044     return 0;
2045 }
2046 #endif
2047
2048 void
2049 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2050 {
2051         struct stack_frame frame;
2052         const void __user *fp;
2053
2054         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2055                 /* TODO: We don't support guest os callchain now */
2056                 return;
2057         }
2058
2059         /*
2060          * We don't know what to do with VM86 stacks.. ignore them for now.
2061          */
2062         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2063                 return;
2064
2065         fp = (void __user *)regs->bp;
2066
2067         perf_callchain_store(entry, regs->ip);
2068
2069         if (!current->mm)
2070                 return;
2071
2072         if (perf_callchain_user32(regs, entry))
2073                 return;
2074
2075         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2076                 unsigned long bytes;
2077                 frame.next_frame             = NULL;
2078                 frame.return_address = 0;
2079
2080                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2081                 if (bytes != 0)
2082                         break;
2083
2084                 if (!valid_user_frame(fp, sizeof(frame)))
2085                         break;
2086
2087                 perf_callchain_store(entry, frame.return_address);
2088                 fp = frame.next_frame;
2089         }
2090 }
2091
2092 /*
2093  * Deal with code segment offsets for the various execution modes:
2094  *
2095  *   VM86 - the good olde 16 bit days, where the linear address is
2096  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2097  *
2098  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2099  *          to figure out what the 32bit base address is.
2100  *
2101  *    X32 - has TIF_X32 set, but is running in x86_64
2102  *
2103  * X86_64 - CS,DS,SS,ES are all zero based.
2104  */
2105 static unsigned long code_segment_base(struct pt_regs *regs)
2106 {
2107         /*
2108          * If we are in VM86 mode, add the segment offset to convert to a
2109          * linear address.
2110          */
2111         if (regs->flags & X86_VM_MASK)
2112                 return 0x10 * regs->cs;
2113
2114         /*
2115          * For IA32 we look at the GDT/LDT segment base to convert the
2116          * effective IP to a linear address.
2117          */
2118 #ifdef CONFIG_X86_32
2119         if (user_mode(regs) && regs->cs != __USER_CS)
2120                 return get_segment_base(regs->cs);
2121 #else
2122         if (test_thread_flag(TIF_IA32)) {
2123                 if (user_mode(regs) && regs->cs != __USER32_CS)
2124                         return get_segment_base(regs->cs);
2125         }
2126 #endif
2127         return 0;
2128 }
2129
2130 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2131 {
2132         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2133                 return perf_guest_cbs->get_guest_ip();
2134
2135         return regs->ip + code_segment_base(regs);
2136 }
2137
2138 unsigned long perf_misc_flags(struct pt_regs *regs)
2139 {
2140         int misc = 0;
2141
2142         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2143                 if (perf_guest_cbs->is_user_mode())
2144                         misc |= PERF_RECORD_MISC_GUEST_USER;
2145                 else
2146                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2147         } else {
2148                 if (user_mode(regs))
2149                         misc |= PERF_RECORD_MISC_USER;
2150                 else
2151                         misc |= PERF_RECORD_MISC_KERNEL;
2152         }
2153
2154         if (regs->flags & PERF_EFLAGS_EXACT)
2155                 misc |= PERF_RECORD_MISC_EXACT_IP;
2156
2157         return misc;
2158 }
2159
2160 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2161 {
2162         cap->version            = x86_pmu.version;
2163         cap->num_counters_gp    = x86_pmu.num_counters;
2164         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2165         cap->bit_width_gp       = x86_pmu.cntval_bits;
2166         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2167         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2168         cap->events_mask_len    = x86_pmu.events_mask_len;
2169 }
2170 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);