arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/timer.h>
  35 #include <asm/desc.h>
  36 #include <asm/ldt.h>
  37
  38 #include "perf_event.h"
  39
  40 struct x86_pmu x86_pmu __read_mostly;
  41
  42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  43         .enabled = 1,
  44 };
  45
  46 u64 __read_mostly hw_cache_event_ids
  47                                 [PERF_COUNT_HW_CACHE_MAX]
  48                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  49                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  50 u64 __read_mostly hw_cache_extra_regs
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54
  55 /*
  56  * Propagate event elapsed time into the generic event.
  57  * Can only be executed on the CPU where the event is active.
  58  * Returns the delta events processed.
  59  */
  60 u64 x86_perf_event_update(struct perf_event *event)
  61 {
  62         struct hw_perf_event *hwc = &event->hw;
  63         int shift = 64 - x86_pmu.cntval_bits;
  64         u64 prev_raw_count, new_raw_count;
  65         int idx = hwc->idx;
  66         s64 delta;
  67
  68         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  69                 return 0;
  70
  71         /*
  72          * Careful: an NMI might modify the previous event value.
  73          *
  74          * Our tactic to handle this is to first atomically read and
  75          * exchange a new raw count - then add that new-prev delta
  76          * count to the generic event atomically:
  77          */
  78 again:
  79         prev_raw_count = local64_read(&hwc->prev_count);
  80         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  81
  82         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  83                                         new_raw_count) != prev_raw_count)
  84                 goto again;
  85
  86         /*
  87          * Now we have the new raw value and have updated the prev
  88          * timestamp already. We can now calculate the elapsed delta
  89          * (event-)time and add that to the generic event.
  90          *
  91          * Careful, not all hw sign-extends above the physical width
  92          * of the count.
  93          */
  94         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  95         delta >>= shift;
  96
  97         local64_add(delta, &event->count);
  98         local64_sub(delta, &hwc->period_left);
  99
 100         return new_raw_count;
 101 }
 102
 103 /*
 104  * Find and validate any extra registers to set up.
 105  */
 106 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 107 {
 108         struct hw_perf_event_extra *reg;
 109         struct extra_reg *er;
 110
 111         reg = &event->hw.extra_reg;
 112
 113         if (!x86_pmu.extra_regs)
 114                 return 0;
 115
 116         for (er = x86_pmu.extra_regs; er->msr; er++) {
 117                 if (er->event != (config & er->config_mask))
 118                         continue;
 119                 if (event->attr.config1 & ~er->valid_mask)
 120                         return -EINVAL;
 121
 122                 reg->idx = er->idx;
 123                 reg->config = event->attr.config1;
 124                 reg->reg = er->msr;
 125                 break;
 126         }
 127         return 0;
 128 }
 129
 130 static atomic_t active_events;
 131 static DEFINE_MUTEX(pmc_reserve_mutex);
 132
 133 #ifdef CONFIG_X86_LOCAL_APIC
 134
 135 static bool reserve_pmc_hardware(void)
 136 {
 137         int i;
 138
 139         for (i = 0; i < x86_pmu.num_counters; i++) {
 140                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 141                         goto perfctr_fail;
 142         }
 143
 144         for (i = 0; i < x86_pmu.num_counters; i++) {
 145                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 146                         goto eventsel_fail;
 147         }
 148
 149         return true;
 150
 151 eventsel_fail:
 152         for (i--; i >= 0; i--)
 153                 release_evntsel_nmi(x86_pmu_config_addr(i));
 154
 155         i = x86_pmu.num_counters;
 156
 157 perfctr_fail:
 158         for (i--; i >= 0; i--)
 159                 release_perfctr_nmi(x86_pmu_event_addr(i));
 160
 161         return false;
 162 }
 163
 164 static void release_pmc_hardware(void)
 165 {
 166         int i;
 167
 168         for (i = 0; i < x86_pmu.num_counters; i++) {
 169                 release_perfctr_nmi(x86_pmu_event_addr(i));
 170                 release_evntsel_nmi(x86_pmu_config_addr(i));
 171         }
 172 }
 173
 174 #else
 175
 176 static bool reserve_pmc_hardware(void) { return true; }
 177 static void release_pmc_hardware(void) {}
 178
 179 #endif
 180
 181 static bool check_hw_exists(void)
 182 {
 183         u64 val, val_fail, val_new= ~0;
 184         int i, reg, reg_fail, ret = 0;
 185         int bios_fail = 0;
 186
 187         /*
 188          * Check to see if the BIOS enabled any of the counters, if so
 189          * complain and bail.
 190          */
 191         for (i = 0; i < x86_pmu.num_counters; i++) {
 192                 reg = x86_pmu_config_addr(i);
 193                 ret = rdmsrl_safe(reg, &val);
 194                 if (ret)
 195                         goto msr_fail;
 196                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 197                         bios_fail = 1;
 198                         val_fail = val;
 199                         reg_fail = reg;
 200                 }
 201         }
 202
 203         if (x86_pmu.num_counters_fixed) {
 204                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 205                 ret = rdmsrl_safe(reg, &val);
 206                 if (ret)
 207                         goto msr_fail;
 208                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 209                         if (val & (0x03 << i*4)) {
 210                                 bios_fail = 1;
 211                                 val_fail = val;
 212                                 reg_fail = reg;
 213                         }
 214                 }
 215         }
 216
 217         /*
 218          * Read the current value, change it and read it back to see if it
 219          * matches, this is needed to detect certain hardware emulators
 220          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 221          */
 222         reg = x86_pmu_event_addr(0);
 223         if (rdmsrl_safe(reg, &val))
 224                 goto msr_fail;
 225         val ^= 0xffffUL;
 226         ret = wrmsrl_safe(reg, val);
 227         ret |= rdmsrl_safe(reg, &val_new);
 228         if (ret || val != val_new)
 229                 goto msr_fail;
 230
 231         /*
 232          * We still allow the PMU driver to operate:
 233          */
 234         if (bios_fail) {
 235                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 236                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 237         }
 238
 239         return true;
 240
 241 msr_fail:
 242         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 243         printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
 244
 245         return false;
 246 }
 247
 248 static void hw_perf_event_destroy(struct perf_event *event)
 249 {
 250         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 251                 release_pmc_hardware();
 252                 release_ds_buffers();
 253                 mutex_unlock(&pmc_reserve_mutex);
 254         }
 255 }
 256
 257 static inline int x86_pmu_initialized(void)
 258 {
 259         return x86_pmu.handle_irq != NULL;
 260 }
 261
 262 static inline int
 263 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 264 {
 265         struct perf_event_attr *attr = &event->attr;
 266         unsigned int cache_type, cache_op, cache_result;
 267         u64 config, val;
 268
 269         config = attr->config;
 270
 271         cache_type = (config >>  0) & 0xff;
 272         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 273                 return -EINVAL;
 274
 275         cache_op = (config >>  8) & 0xff;
 276         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 277                 return -EINVAL;
 278
 279         cache_result = (config >> 16) & 0xff;
 280         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 281                 return -EINVAL;
 282
 283         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 284
 285         if (val == 0)
 286                 return -ENOENT;
 287
 288         if (val == -1)
 289                 return -EINVAL;
 290
 291         hwc->config |= val;
 292         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 293         return x86_pmu_extra_regs(val, event);
 294 }
 295
 296 int x86_setup_perfctr(struct perf_event *event)
 297 {
 298         struct perf_event_attr *attr = &event->attr;
 299         struct hw_perf_event *hwc = &event->hw;
 300         u64 config;
 301
 302         if (!is_sampling_event(event)) {
 303                 hwc->sample_period = x86_pmu.max_period;
 304                 hwc->last_period = hwc->sample_period;
 305                 local64_set(&hwc->period_left, hwc->sample_period);
 306         } else {
 307                 /*
 308                  * If we have a PMU initialized but no APIC
 309                  * interrupts, we cannot sample hardware
 310                  * events (user-space has to fall back and
 311                  * sample via a hrtimer based software event):
 312                  */
 313                 if (!x86_pmu.apic)
 314                         return -EOPNOTSUPP;
 315         }
 316
 317         if (attr->type == PERF_TYPE_RAW)
 318                 return x86_pmu_extra_regs(event->attr.config, event);
 319
 320         if (attr->type == PERF_TYPE_HW_CACHE)
 321                 return set_ext_hw_attr(hwc, event);
 322
 323         if (attr->config >= x86_pmu.max_events)
 324                 return -EINVAL;
 325
 326         /*
 327          * The generic map:
 328          */
 329         config = x86_pmu.event_map(attr->config);
 330
 331         if (config == 0)
 332                 return -ENOENT;
 333
 334         if (config == -1LL)
 335                 return -EINVAL;
 336
 337         /*
 338          * Branch tracing:
 339          */
 340         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 341             !attr->freq && hwc->sample_period == 1) {
 342                 /* BTS is not supported by this architecture. */
 343                 if (!x86_pmu.bts_active)
 344                         return -EOPNOTSUPP;
 345
 346                 /* BTS is currently only allowed for user-mode. */
 347                 if (!attr->exclude_kernel)
 348                         return -EOPNOTSUPP;
 349         }
 350
 351         hwc->config |= config;
 352
 353         return 0;
 354 }
 355
 356 /*
 357  * check that branch_sample_type is compatible with
 358  * settings needed for precise_ip > 1 which implies
 359  * using the LBR to capture ALL taken branches at the
 360  * priv levels of the measurement
 361  */
 362 static inline int precise_br_compat(struct perf_event *event)
 363 {
 364         u64 m = event->attr.branch_sample_type;
 365         u64 b = 0;
 366
 367         /* must capture all branches */
 368         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 369                 return 0;
 370
 371         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 372
 373         if (!event->attr.exclude_user)
 374                 b |= PERF_SAMPLE_BRANCH_USER;
 375
 376         if (!event->attr.exclude_kernel)
 377                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 378
 379         /*
 380          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 381          */
 382
 383         return m == b;
 384 }
 385
 386 int x86_pmu_hw_config(struct perf_event *event)
 387 {
 388         if (event->attr.precise_ip) {
 389                 int precise = 0;
 390
 391                 /* Support for constant skid */
 392                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 393                         precise++;
 394
 395                         /* Support for IP fixup */
 396                         if (x86_pmu.lbr_nr)
 397                                 precise++;
 398                 }
 399
 400                 if (event->attr.precise_ip > precise)
 401                         return -EOPNOTSUPP;
 402                 /*
 403                  * check that PEBS LBR correction does not conflict with
 404                  * whatever the user is asking with attr->branch_sample_type
 405                  */
 406                 if (event->attr.precise_ip > 1) {
 407                         u64 *br_type = &event->attr.branch_sample_type;
 408
 409                         if (has_branch_stack(event)) {
 410                                 if (!precise_br_compat(event))
 411                                         return -EOPNOTSUPP;
 412
 413                                 /* branch_sample_type is compatible */
 414
 415                         } else {
 416                                 /*
 417                                  * user did not specify  branch_sample_type
 418                                  *
 419                                  * For PEBS fixups, we capture all
 420                                  * the branches at the priv level of the
 421                                  * event.
 422                                  */
 423                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 424
 425                                 if (!event->attr.exclude_user)
 426                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 427
 428                                 if (!event->attr.exclude_kernel)
 429                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 430                         }
 431                 }
 432         }
 433
 434         /*
 435          * Generate PMC IRQs:
 436          * (keep 'enabled' bit clear for now)
 437          */
 438         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 439
 440         /*
 441          * Count user and OS events unless requested not to
 442          */
 443         if (!event->attr.exclude_user)
 444                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 445         if (!event->attr.exclude_kernel)
 446                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 447
 448         if (event->attr.type == PERF_TYPE_RAW)
 449                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 450
 451         return x86_setup_perfctr(event);
 452 }
 453
 454 /*
 455  * Setup the hardware configuration for a given attr_type
 456  */
 457 static int __x86_pmu_event_init(struct perf_event *event)
 458 {
 459         int err;
 460
 461         if (!x86_pmu_initialized())
 462                 return -ENODEV;
 463
 464         err = 0;
 465         if (!atomic_inc_not_zero(&active_events)) {
 466                 mutex_lock(&pmc_reserve_mutex);
 467                 if (atomic_read(&active_events) == 0) {
 468                         if (!reserve_pmc_hardware())
 469                                 err = -EBUSY;
 470                         else
 471                                 reserve_ds_buffers();
 472                 }
 473                 if (!err)
 474                         atomic_inc(&active_events);
 475                 mutex_unlock(&pmc_reserve_mutex);
 476         }
 477         if (err)
 478                 return err;
 479
 480         event->destroy = hw_perf_event_destroy;
 481
 482         event->hw.idx = -1;
 483         event->hw.last_cpu = -1;
 484         event->hw.last_tag = ~0ULL;
 485
 486         /* mark unused */
 487         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 488         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 489
 490         return x86_pmu.hw_config(event);
 491 }
 492
 493 void x86_pmu_disable_all(void)
 494 {
 495         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 496         int idx;
 497
 498         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 499                 u64 val;
 500
 501                 if (!test_bit(idx, cpuc->active_mask))
 502                         continue;
 503                 rdmsrl(x86_pmu_config_addr(idx), val);
 504                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 505                         continue;
 506                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 507                 wrmsrl(x86_pmu_config_addr(idx), val);
 508         }
 509 }
 510
 511 static void x86_pmu_disable(struct pmu *pmu)
 512 {
 513         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 514
 515         if (!x86_pmu_initialized())
 516                 return;
 517
 518         if (!cpuc->enabled)
 519                 return;
 520
 521         cpuc->n_added = 0;
 522         cpuc->enabled = 0;
 523         barrier();
 524
 525         x86_pmu.disable_all();
 526 }
 527
 528 void x86_pmu_enable_all(int added)
 529 {
 530         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 531         int idx;
 532
 533         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 534                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 535
 536                 if (!test_bit(idx, cpuc->active_mask))
 537                         continue;
 538
 539                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 540         }
 541 }
 542
 543 static struct pmu pmu;
 544
 545 static inline int is_x86_event(struct perf_event *event)
 546 {
 547         return event->pmu == &pmu;
 548 }
 549
 550 /*
 551  * Event scheduler state:
 552  *
 553  * Assign events iterating over all events and counters, beginning
 554  * with events with least weights first. Keep the current iterator
 555  * state in struct sched_state.
 556  */
 557 struct sched_state {
 558         int     weight;
 559         int     event;          /* event index */
 560         int     counter;        /* counter index */
 561         int     unassigned;     /* number of events to be assigned left */
 562         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 563 };
 564
 565 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 566 #define SCHED_STATES_MAX        2
 567
 568 struct perf_sched {
 569         int                     max_weight;
 570         int                     max_events;
 571         struct event_constraint **constraints;
 572         struct sched_state      state;
 573         int                     saved_states;
 574         struct sched_state      saved[SCHED_STATES_MAX];
 575 };
 576
 577 /*
 578  * Initialize interator that runs through all events and counters.
 579  */
 580 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c,
 581                             int num, int wmin, int wmax)
 582 {
 583         int idx;
 584
 585         memset(sched, 0, sizeof(*sched));
 586         sched->max_events       = num;
 587         sched->max_weight       = wmax;
 588         sched->constraints      = c;
 589
 590         for (idx = 0; idx < num; idx++) {
 591                 if (c[idx]->weight == wmin)
 592                         break;
 593         }
 594
 595         sched->state.event      = idx;          /* start with min weight */
 596         sched->state.weight     = wmin;
 597         sched->state.unassigned = num;
 598 }
 599
 600 static void perf_sched_save_state(struct perf_sched *sched)
 601 {
 602         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 603                 return;
 604
 605         sched->saved[sched->saved_states] = sched->state;
 606         sched->saved_states++;
 607 }
 608
 609 static bool perf_sched_restore_state(struct perf_sched *sched)
 610 {
 611         if (!sched->saved_states)
 612                 return false;
 613
 614         sched->saved_states--;
 615         sched->state = sched->saved[sched->saved_states];
 616
 617         /* continue with next counter: */
 618         clear_bit(sched->state.counter++, sched->state.used);
 619
 620         return true;
 621 }
 622
 623 /*
 624  * Select a counter for the current event to schedule. Return true on
 625  * success.
 626  */
 627 static bool __perf_sched_find_counter(struct perf_sched *sched)
 628 {
 629         struct event_constraint *c;
 630         int idx;
 631
 632         if (!sched->state.unassigned)
 633                 return false;
 634
 635         if (sched->state.event >= sched->max_events)
 636                 return false;
 637
 638         c = sched->constraints[sched->state.event];
 639
 640         /* Prefer fixed purpose counters */
 641         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 642                 idx = INTEL_PMC_IDX_FIXED;
 643                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 644                         if (!__test_and_set_bit(idx, sched->state.used))
 645                                 goto done;
 646                 }
 647         }
 648         /* Grab the first unused counter starting with idx */
 649         idx = sched->state.counter;
 650         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 651                 if (!__test_and_set_bit(idx, sched->state.used))
 652                         goto done;
 653         }
 654
 655         return false;
 656
 657 done:
 658         sched->state.counter = idx;
 659
 660         if (c->overlap)
 661                 perf_sched_save_state(sched);
 662
 663         return true;
 664 }
 665
 666 static bool perf_sched_find_counter(struct perf_sched *sched)
 667 {
 668         while (!__perf_sched_find_counter(sched)) {
 669                 if (!perf_sched_restore_state(sched))
 670                         return false;
 671         }
 672
 673         return true;
 674 }
 675
 676 /*
 677  * Go through all unassigned events and find the next one to schedule.
 678  * Take events with the least weight first. Return true on success.
 679  */
 680 static bool perf_sched_next_event(struct perf_sched *sched)
 681 {
 682         struct event_constraint *c;
 683
 684         if (!sched->state.unassigned || !--sched->state.unassigned)
 685                 return false;
 686
 687         do {
 688                 /* next event */
 689                 sched->state.event++;
 690                 if (sched->state.event >= sched->max_events) {
 691                         /* next weight */
 692                         sched->state.event = 0;
 693                         sched->state.weight++;
 694                         if (sched->state.weight > sched->max_weight)
 695                                 return false;
 696                 }
 697                 c = sched->constraints[sched->state.event];
 698         } while (c->weight != sched->state.weight);
 699
 700         sched->state.counter = 0;       /* start with first counter */
 701
 702         return true;
 703 }
 704
 705 /*
 706  * Assign a counter for each event.
 707  */
 708 int perf_assign_events(struct event_constraint **constraints, int n,
 709                         int wmin, int wmax, int *assign)
 710 {
 711         struct perf_sched sched;
 712
 713         perf_sched_init(&sched, constraints, n, wmin, wmax);
 714
 715         do {
 716                 if (!perf_sched_find_counter(&sched))
 717                         break;  /* failed */
 718                 if (assign)
 719                         assign[sched.state.event] = sched.state.counter;
 720         } while (perf_sched_next_event(&sched));
 721
 722         return sched.state.unassigned;
 723 }
 724
 725 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 726 {
 727         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 728         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 729         int i, wmin, wmax, num = 0;
 730         struct hw_perf_event *hwc;
 731
 732         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 733
 734         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 735                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 736                 constraints[i] = c;
 737                 wmin = min(wmin, c->weight);
 738                 wmax = max(wmax, c->weight);
 739         }
 740
 741         /*
 742          * fastpath, try to reuse previous register
 743          */
 744         for (i = 0; i < n; i++) {
 745                 hwc = &cpuc->event_list[i]->hw;
 746                 c = constraints[i];
 747
 748                 /* never assigned */
 749                 if (hwc->idx == -1)
 750                         break;
 751
 752                 /* constraint still honored */
 753                 if (!test_bit(hwc->idx, c->idxmsk))
 754                         break;
 755
 756                 /* not already used */
 757                 if (test_bit(hwc->idx, used_mask))
 758                         break;
 759
 760                 __set_bit(hwc->idx, used_mask);
 761                 if (assign)
 762                         assign[i] = hwc->idx;
 763         }
 764
 765         /* slow path */
 766         if (i != n)
 767                 num = perf_assign_events(constraints, n, wmin, wmax, assign);
 768
 769         /*
 770          * scheduling failed or is just a simulation,
 771          * free resources if necessary
 772          */
 773         if (!assign || num) {
 774                 for (i = 0; i < n; i++) {
 775                         if (x86_pmu.put_event_constraints)
 776                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 777                 }
 778         }
 779         return num ? -EINVAL : 0;
 780 }
 781
 782 /*
 783  * dogrp: true if must collect siblings events (group)
 784  * returns total number of events and error code
 785  */
 786 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 787 {
 788         struct perf_event *event;
 789         int n, max_count;
 790
 791         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 792
 793         /* current number of events already accepted */
 794         n = cpuc->n_events;
 795
 796         if (is_x86_event(leader)) {
 797                 if (n >= max_count)
 798                         return -EINVAL;
 799                 cpuc->event_list[n] = leader;
 800                 n++;
 801         }
 802         if (!dogrp)
 803                 return n;
 804
 805         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 806                 if (!is_x86_event(event) ||
 807                     event->state <= PERF_EVENT_STATE_OFF)
 808                         continue;
 809
 810                 if (n >= max_count)
 811                         return -EINVAL;
 812
 813                 cpuc->event_list[n] = event;
 814                 n++;
 815         }
 816         return n;
 817 }
 818
 819 static inline void x86_assign_hw_event(struct perf_event *event,
 820                                 struct cpu_hw_events *cpuc, int i)
 821 {
 822         struct hw_perf_event *hwc = &event->hw;
 823
 824         hwc->idx = cpuc->assign[i];
 825         hwc->last_cpu = smp_processor_id();
 826         hwc->last_tag = ++cpuc->tags[i];
 827
 828         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 829                 hwc->config_base = 0;
 830                 hwc->event_base = 0;
 831         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 832                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 833                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 834                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 835         } else {
 836                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 837                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 838                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 839         }
 840 }
 841
 842 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 843                                         struct cpu_hw_events *cpuc,
 844                                         int i)
 845 {
 846         return hwc->idx == cpuc->assign[i] &&
 847                 hwc->last_cpu == smp_processor_id() &&
 848                 hwc->last_tag == cpuc->tags[i];
 849 }
 850
 851 static void x86_pmu_start(struct perf_event *event, int flags);
 852
 853 static void x86_pmu_enable(struct pmu *pmu)
 854 {
 855         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 856         struct perf_event *event;
 857         struct hw_perf_event *hwc;
 858         int i, added = cpuc->n_added;
 859
 860         if (!x86_pmu_initialized())
 861                 return;
 862
 863         if (cpuc->enabled)
 864                 return;
 865
 866         if (cpuc->n_added) {
 867                 int n_running = cpuc->n_events - cpuc->n_added;
 868                 /*
 869                  * apply assignment obtained either from
 870                  * hw_perf_group_sched_in() or x86_pmu_enable()
 871                  *
 872                  * step1: save events moving to new counters
 873                  * step2: reprogram moved events into new counters
 874                  */
 875                 for (i = 0; i < n_running; i++) {
 876                         event = cpuc->event_list[i];
 877                         hwc = &event->hw;
 878
 879                         /*
 880                          * we can avoid reprogramming counter if:
 881                          * - assigned same counter as last time
 882                          * - running on same CPU as last time
 883                          * - no other event has used the counter since
 884                          */
 885                         if (hwc->idx == -1 ||
 886                             match_prev_assignment(hwc, cpuc, i))
 887                                 continue;
 888
 889                         /*
 890                          * Ensure we don't accidentally enable a stopped
 891                          * counter simply because we rescheduled.
 892                          */
 893                         if (hwc->state & PERF_HES_STOPPED)
 894                                 hwc->state |= PERF_HES_ARCH;
 895
 896                         x86_pmu_stop(event, PERF_EF_UPDATE);
 897                 }
 898
 899                 for (i = 0; i < cpuc->n_events; i++) {
 900                         event = cpuc->event_list[i];
 901                         hwc = &event->hw;
 902
 903                         if (!match_prev_assignment(hwc, cpuc, i))
 904                                 x86_assign_hw_event(event, cpuc, i);
 905                         else if (i < n_running)
 906                                 continue;
 907
 908                         if (hwc->state & PERF_HES_ARCH)
 909                                 continue;
 910
 911                         x86_pmu_start(event, PERF_EF_RELOAD);
 912                 }
 913                 cpuc->n_added = 0;
 914                 perf_events_lapic_init();
 915         }
 916
 917         cpuc->enabled = 1;
 918         barrier();
 919
 920         x86_pmu.enable_all(added);
 921 }
 922
 923 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 924
 925 /*
 926  * Set the next IRQ period, based on the hwc->period_left value.
 927  * To be called with the event disabled in hw:
 928  */
 929 int x86_perf_event_set_period(struct perf_event *event)
 930 {
 931         struct hw_perf_event *hwc = &event->hw;
 932         s64 left = local64_read(&hwc->period_left);
 933         s64 period = hwc->sample_period;
 934         int ret = 0, idx = hwc->idx;
 935
 936         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 937                 return 0;
 938
 939         /*
 940          * If we are way outside a reasonable range then just skip forward:
 941          */
 942         if (unlikely(left <= -period)) {
 943                 left = period;
 944                 local64_set(&hwc->period_left, left);
 945                 hwc->last_period = period;
 946                 ret = 1;
 947         }
 948
 949         if (unlikely(left <= 0)) {
 950                 left += period;
 951                 local64_set(&hwc->period_left, left);
 952                 hwc->last_period = period;
 953                 ret = 1;
 954         }
 955         /*
 956          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 957          */
 958         if (unlikely(left < 2))
 959                 left = 2;
 960
 961         if (left > x86_pmu.max_period)
 962                 left = x86_pmu.max_period;
 963
 964         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 965
 966         /*
 967          * The hw event starts counting from this event offset,
 968          * mark it to be able to extra future deltas:
 969          */
 970         local64_set(&hwc->prev_count, (u64)-left);
 971
 972         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 973
 974         /*
 975          * Due to erratum on certan cpu we need
 976          * a second write to be sure the register
 977          * is updated properly
 978          */
 979         if (x86_pmu.perfctr_second_write) {
 980                 wrmsrl(hwc->event_base,
 981                         (u64)(-left) & x86_pmu.cntval_mask);
 982         }
 983
 984         perf_event_update_userpage(event);
 985
 986         return ret;
 987 }
 988
 989 void x86_pmu_enable_event(struct perf_event *event)
 990 {
 991         if (__this_cpu_read(cpu_hw_events.enabled))
 992                 __x86_pmu_enable_event(&event->hw,
 993                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 994 }
 995
 996 /*
 997  * Add a single event to the PMU.
 998  *
 999  * The event is added to the group of enabled events
1000  * but only if it can be scehduled with existing events.
1001  */
1002 static int x86_pmu_add(struct perf_event *event, int flags)
1003 {
1004         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1005         struct hw_perf_event *hwc;
1006         int assign[X86_PMC_IDX_MAX];
1007         int n, n0, ret;
1008
1009         hwc = &event->hw;
1010
1011         perf_pmu_disable(event->pmu);
1012         n0 = cpuc->n_events;
1013         ret = n = collect_events(cpuc, event, false);
1014         if (ret < 0)
1015                 goto out;
1016
1017         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1018         if (!(flags & PERF_EF_START))
1019                 hwc->state |= PERF_HES_ARCH;
1020
1021         /*
1022          * If group events scheduling transaction was started,
1023          * skip the schedulability test here, it will be performed
1024          * at commit time (->commit_txn) as a whole
1025          */
1026         if (cpuc->group_flag & PERF_EVENT_TXN)
1027                 goto done_collect;
1028
1029         ret = x86_pmu.schedule_events(cpuc, n, assign);
1030         if (ret)
1031                 goto out;
1032         /*
1033          * copy new assignment, now we know it is possible
1034          * will be used by hw_perf_enable()
1035          */
1036         memcpy(cpuc->assign, assign, n*sizeof(int));
1037
1038 done_collect:
1039         cpuc->n_events = n;
1040         cpuc->n_added += n - n0;
1041         cpuc->n_txn += n - n0;
1042
1043         ret = 0;
1044 out:
1045         perf_pmu_enable(event->pmu);
1046         return ret;
1047 }
1048
1049 static void x86_pmu_start(struct perf_event *event, int flags)
1050 {
1051         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1052         int idx = event->hw.idx;
1053
1054         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1055                 return;
1056
1057         if (WARN_ON_ONCE(idx == -1))
1058                 return;
1059
1060         if (flags & PERF_EF_RELOAD) {
1061                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1062                 x86_perf_event_set_period(event);
1063         }
1064
1065         event->hw.state = 0;
1066
1067         cpuc->events[idx] = event;
1068         __set_bit(idx, cpuc->active_mask);
1069         __set_bit(idx, cpuc->running);
1070         x86_pmu.enable(event);
1071         perf_event_update_userpage(event);
1072 }
1073
1074 void perf_event_print_debug(void)
1075 {
1076         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1077         u64 pebs;
1078         struct cpu_hw_events *cpuc;
1079         unsigned long flags;
1080         int cpu, idx;
1081
1082         if (!x86_pmu.num_counters)
1083                 return;
1084
1085         local_irq_save(flags);
1086
1087         cpu = smp_processor_id();
1088         cpuc = &per_cpu(cpu_hw_events, cpu);
1089
1090         if (x86_pmu.version >= 2) {
1091                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1092                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1093                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1094                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1095                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1096
1097                 pr_info("\n");
1098                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1099                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1100                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1101                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1102                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1103         }
1104         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1105
1106         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1107                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1108                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1109
1110                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1111
1112                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1113                         cpu, idx, pmc_ctrl);
1114                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1115                         cpu, idx, pmc_count);
1116                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1117                         cpu, idx, prev_left);
1118         }
1119         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1120                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1121
1122                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1123                         cpu, idx, pmc_count);
1124         }
1125         local_irq_restore(flags);
1126 }
1127
1128 void x86_pmu_stop(struct perf_event *event, int flags)
1129 {
1130         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1131         struct hw_perf_event *hwc = &event->hw;
1132
1133         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1134                 x86_pmu.disable(event);
1135                 cpuc->events[hwc->idx] = NULL;
1136                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1137                 hwc->state |= PERF_HES_STOPPED;
1138         }
1139
1140         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1141                 /*
1142                  * Drain the remaining delta count out of a event
1143                  * that we are disabling:
1144                  */
1145                 x86_perf_event_update(event);
1146                 hwc->state |= PERF_HES_UPTODATE;
1147         }
1148 }
1149
1150 static void x86_pmu_del(struct perf_event *event, int flags)
1151 {
1152         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1153         int i;
1154
1155         /*
1156          * If we're called during a txn, we don't need to do anything.
1157          * The events never got scheduled and ->cancel_txn will truncate
1158          * the event_list.
1159          */
1160         if (cpuc->group_flag & PERF_EVENT_TXN)
1161                 return;
1162
1163         x86_pmu_stop(event, PERF_EF_UPDATE);
1164
1165         for (i = 0; i < cpuc->n_events; i++) {
1166                 if (event == cpuc->event_list[i]) {
1167
1168                         if (i >= cpuc->n_events - cpuc->n_added)
1169                                 --cpuc->n_added;
1170
1171                         if (x86_pmu.put_event_constraints)
1172                                 x86_pmu.put_event_constraints(cpuc, event);
1173
1174                         while (++i < cpuc->n_events)
1175                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1176
1177                         --cpuc->n_events;
1178                         break;
1179                 }
1180         }
1181         perf_event_update_userpage(event);
1182 }
1183
1184 int x86_pmu_handle_irq(struct pt_regs *regs)
1185 {
1186         struct perf_sample_data data;
1187         struct cpu_hw_events *cpuc;
1188         struct perf_event *event;
1189         int idx, handled = 0;
1190         u64 val;
1191
1192         cpuc = &__get_cpu_var(cpu_hw_events);
1193
1194         /*
1195          * Some chipsets need to unmask the LVTPC in a particular spot
1196          * inside the nmi handler.  As a result, the unmasking was pushed
1197          * into all the nmi handlers.
1198          *
1199          * This generic handler doesn't seem to have any issues where the
1200          * unmasking occurs so it was left at the top.
1201          */
1202         apic_write(APIC_LVTPC, APIC_DM_NMI);
1203
1204         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1205                 if (!test_bit(idx, cpuc->active_mask)) {
1206                         /*
1207                          * Though we deactivated the counter some cpus
1208                          * might still deliver spurious interrupts still
1209                          * in flight. Catch them:
1210                          */
1211                         if (__test_and_clear_bit(idx, cpuc->running))
1212                                 handled++;
1213                         continue;
1214                 }
1215
1216                 event = cpuc->events[idx];
1217
1218                 val = x86_perf_event_update(event);
1219                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1220                         continue;
1221
1222                 /*
1223                  * event overflow
1224                  */
1225                 handled++;
1226                 perf_sample_data_init(&data, 0, event->hw.last_period);
1227
1228                 if (!x86_perf_event_set_period(event))
1229                         continue;
1230
1231                 if (perf_event_overflow(event, &data, regs))
1232                         x86_pmu_stop(event, 0);
1233         }
1234
1235         if (handled)
1236                 inc_irq_stat(apic_perf_irqs);
1237
1238         return handled;
1239 }
1240
1241 void perf_events_lapic_init(void)
1242 {
1243         if (!x86_pmu.apic || !x86_pmu_initialized())
1244                 return;
1245
1246         /*
1247          * Always use NMI for PMU
1248          */
1249         apic_write(APIC_LVTPC, APIC_DM_NMI);
1250 }
1251
1252 static int __kprobes
1253 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1254 {
1255         int ret;
1256         u64 start_clock;
1257         u64 finish_clock;
1258
1259         if (!atomic_read(&active_events))
1260                 return NMI_DONE;
1261
1262         start_clock = local_clock();
1263         ret = x86_pmu.handle_irq(regs);
1264         finish_clock = local_clock();
1265
1266         perf_sample_event_took(finish_clock - start_clock);
1267
1268         return ret;
1269 }
1270
1271 struct event_constraint emptyconstraint;
1272 struct event_constraint unconstrained;
1273
1274 static int __cpuinit
1275 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1276 {
1277         unsigned int cpu = (long)hcpu;
1278         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1279         int ret = NOTIFY_OK;
1280
1281         switch (action & ~CPU_TASKS_FROZEN) {
1282         case CPU_UP_PREPARE:
1283                 cpuc->kfree_on_online = NULL;
1284                 if (x86_pmu.cpu_prepare)
1285                         ret = x86_pmu.cpu_prepare(cpu);
1286                 break;
1287
1288         case CPU_STARTING:
1289                 if (x86_pmu.attr_rdpmc)
1290                         set_in_cr4(X86_CR4_PCE);
1291                 if (x86_pmu.cpu_starting)
1292                         x86_pmu.cpu_starting(cpu);
1293                 break;
1294
1295         case CPU_ONLINE:
1296                 kfree(cpuc->kfree_on_online);
1297                 break;
1298
1299         case CPU_DYING:
1300                 if (x86_pmu.cpu_dying)
1301                         x86_pmu.cpu_dying(cpu);
1302                 break;
1303
1304         case CPU_UP_CANCELED:
1305         case CPU_DEAD:
1306                 if (x86_pmu.cpu_dead)
1307                         x86_pmu.cpu_dead(cpu);
1308                 break;
1309
1310         default:
1311                 break;
1312         }
1313
1314         return ret;
1315 }
1316
1317 static void __init pmu_check_apic(void)
1318 {
1319         if (cpu_has_apic)
1320                 return;
1321
1322         x86_pmu.apic = 0;
1323         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1324         pr_info("no hardware sampling interrupt available.\n");
1325 }
1326
1327 static struct attribute_group x86_pmu_format_group = {
1328         .name = "format",
1329         .attrs = NULL,
1330 };
1331
1332 /*
1333  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1334  * out of events_attr attributes.
1335  */
1336 static void __init filter_events(struct attribute **attrs)
1337 {
1338         struct device_attribute *d;
1339         struct perf_pmu_events_attr *pmu_attr;
1340         int i, j;
1341
1342         for (i = 0; attrs[i]; i++) {
1343                 d = (struct device_attribute *)attrs[i];
1344                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1345                 /* str trumps id */
1346                 if (pmu_attr->event_str)
1347                         continue;
1348                 if (x86_pmu.event_map(i))
1349                         continue;
1350
1351                 for (j = i; attrs[j]; j++)
1352                         attrs[j] = attrs[j + 1];
1353
1354                 /* Check the shifted attr. */
1355                 i--;
1356         }
1357 }
1358
1359 /* Merge two pointer arrays */
1360 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1361 {
1362         struct attribute **new;
1363         int j, i;
1364
1365         for (j = 0; a[j]; j++)
1366                 ;
1367         for (i = 0; b[i]; i++)
1368                 j++;
1369         j++;
1370
1371         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1372         if (!new)
1373                 return NULL;
1374
1375         j = 0;
1376         for (i = 0; a[i]; i++)
1377                 new[j++] = a[i];
1378         for (i = 0; b[i]; i++)
1379                 new[j++] = b[i];
1380         new[j] = NULL;
1381
1382         return new;
1383 }
1384
1385 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1386                           char *page)
1387 {
1388         struct perf_pmu_events_attr *pmu_attr = \
1389                 container_of(attr, struct perf_pmu_events_attr, attr);
1390         u64 config = x86_pmu.event_map(pmu_attr->id);
1391
1392         /* string trumps id */
1393         if (pmu_attr->event_str)
1394                 return sprintf(page, "%s", pmu_attr->event_str);
1395
1396         return x86_pmu.events_sysfs_show(page, config);
1397 }
1398
1399 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1400 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1401 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1402 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1403 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1404 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1405 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1406 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1407 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1408 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1409
1410 static struct attribute *empty_attrs;
1411
1412 static struct attribute *events_attr[] = {
1413         EVENT_PTR(CPU_CYCLES),
1414         EVENT_PTR(INSTRUCTIONS),
1415         EVENT_PTR(CACHE_REFERENCES),
1416         EVENT_PTR(CACHE_MISSES),
1417         EVENT_PTR(BRANCH_INSTRUCTIONS),
1418         EVENT_PTR(BRANCH_MISSES),
1419         EVENT_PTR(BUS_CYCLES),
1420         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1421         EVENT_PTR(STALLED_CYCLES_BACKEND),
1422         EVENT_PTR(REF_CPU_CYCLES),
1423         NULL,
1424 };
1425
1426 static struct attribute_group x86_pmu_events_group = {
1427         .name = "events",
1428         .attrs = events_attr,
1429 };
1430
1431 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1432 {
1433         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1434         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1435         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1436         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1437         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1438         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1439         ssize_t ret;
1440
1441         /*
1442         * We have whole page size to spend and just little data
1443         * to write, so we can safely use sprintf.
1444         */
1445         ret = sprintf(page, "event=0x%02llx", event);
1446
1447         if (umask)
1448                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1449
1450         if (edge)
1451                 ret += sprintf(page + ret, ",edge");
1452
1453         if (pc)
1454                 ret += sprintf(page + ret, ",pc");
1455
1456         if (any)
1457                 ret += sprintf(page + ret, ",any");
1458
1459         if (inv)
1460                 ret += sprintf(page + ret, ",inv");
1461
1462         if (cmask)
1463                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1464
1465         ret += sprintf(page + ret, "\n");
1466
1467         return ret;
1468 }
1469
1470 static int __init init_hw_perf_events(void)
1471 {
1472         struct x86_pmu_quirk *quirk;
1473         int err;
1474
1475         pr_info("Performance Events: ");
1476
1477         switch (boot_cpu_data.x86_vendor) {
1478         case X86_VENDOR_INTEL:
1479                 err = intel_pmu_init();
1480                 break;
1481         case X86_VENDOR_AMD:
1482                 err = amd_pmu_init();
1483                 break;
1484         default:
1485                 return 0;
1486         }
1487         if (err != 0) {
1488                 pr_cont("no PMU driver, software events only.\n");
1489                 return 0;
1490         }
1491
1492         pmu_check_apic();
1493
1494         /* sanity check that the hardware exists or is emulated */
1495         if (!check_hw_exists())
1496                 return 0;
1497
1498         pr_cont("%s PMU driver.\n", x86_pmu.name);
1499
1500         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1501                 quirk->func();
1502
1503         if (!x86_pmu.intel_ctrl)
1504                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1505
1506         perf_events_lapic_init();
1507         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1508
1509         unconstrained = (struct event_constraint)
1510                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1511                                    0, x86_pmu.num_counters, 0, 0);
1512
1513         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1514         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1515
1516         if (x86_pmu.event_attrs)
1517                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1518
1519         if (!x86_pmu.events_sysfs_show)
1520                 x86_pmu_events_group.attrs = &empty_attrs;
1521         else
1522                 filter_events(x86_pmu_events_group.attrs);
1523
1524         if (x86_pmu.cpu_events) {
1525                 struct attribute **tmp;
1526
1527                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1528                 if (!WARN_ON(!tmp))
1529                         x86_pmu_events_group.attrs = tmp;
1530         }
1531
1532         pr_info("... version:                %d\n",     x86_pmu.version);
1533         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1534         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1535         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1536         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1537         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1538         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1539
1540         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1541         perf_cpu_notifier(x86_pmu_notifier);
1542
1543         return 0;
1544 }
1545 early_initcall(init_hw_perf_events);
1546
1547 static inline void x86_pmu_read(struct perf_event *event)
1548 {
1549         x86_perf_event_update(event);
1550 }
1551
1552 /*
1553  * Start group events scheduling transaction
1554  * Set the flag to make pmu::enable() not perform the
1555  * schedulability test, it will be performed at commit time
1556  */
1557 static void x86_pmu_start_txn(struct pmu *pmu)
1558 {
1559         perf_pmu_disable(pmu);
1560         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1561         __this_cpu_write(cpu_hw_events.n_txn, 0);
1562 }
1563
1564 /*
1565  * Stop group events scheduling transaction
1566  * Clear the flag and pmu::enable() will perform the
1567  * schedulability test.
1568  */
1569 static void x86_pmu_cancel_txn(struct pmu *pmu)
1570 {
1571         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1572         /*
1573          * Truncate the collected events.
1574          */
1575         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1576         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1577         perf_pmu_enable(pmu);
1578 }
1579
1580 /*
1581  * Commit group events scheduling transaction
1582  * Perform the group schedulability test as a whole
1583  * Return 0 if success
1584  */
1585 static int x86_pmu_commit_txn(struct pmu *pmu)
1586 {
1587         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1588         int assign[X86_PMC_IDX_MAX];
1589         int n, ret;
1590
1591         n = cpuc->n_events;
1592
1593         if (!x86_pmu_initialized())
1594                 return -EAGAIN;
1595
1596         ret = x86_pmu.schedule_events(cpuc, n, assign);
1597         if (ret)
1598                 return ret;
1599
1600         /*
1601          * copy new assignment, now we know it is possible
1602          * will be used by hw_perf_enable()
1603          */
1604         memcpy(cpuc->assign, assign, n*sizeof(int));
1605
1606         cpuc->group_flag &= ~PERF_EVENT_TXN;
1607         perf_pmu_enable(pmu);
1608         return 0;
1609 }
1610 /*
1611  * a fake_cpuc is used to validate event groups. Due to
1612  * the extra reg logic, we need to also allocate a fake
1613  * per_core and per_cpu structure. Otherwise, group events
1614  * using extra reg may conflict without the kernel being
1615  * able to catch this when the last event gets added to
1616  * the group.
1617  */
1618 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1619 {
1620         kfree(cpuc->shared_regs);
1621         kfree(cpuc);
1622 }
1623
1624 static struct cpu_hw_events *allocate_fake_cpuc(void)
1625 {
1626         struct cpu_hw_events *cpuc;
1627         int cpu = raw_smp_processor_id();
1628
1629         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1630         if (!cpuc)
1631                 return ERR_PTR(-ENOMEM);
1632
1633         /* only needed, if we have extra_regs */
1634         if (x86_pmu.extra_regs) {
1635                 cpuc->shared_regs = allocate_shared_regs(cpu);
1636                 if (!cpuc->shared_regs)
1637                         goto error;
1638         }
1639         cpuc->is_fake = 1;
1640         return cpuc;
1641 error:
1642         free_fake_cpuc(cpuc);
1643         return ERR_PTR(-ENOMEM);
1644 }
1645
1646 /*
1647  * validate that we can schedule this event
1648  */
1649 static int validate_event(struct perf_event *event)
1650 {
1651         struct cpu_hw_events *fake_cpuc;
1652         struct event_constraint *c;
1653         int ret = 0;
1654
1655         fake_cpuc = allocate_fake_cpuc();
1656         if (IS_ERR(fake_cpuc))
1657                 return PTR_ERR(fake_cpuc);
1658
1659         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1660
1661         if (!c || !c->weight)
1662                 ret = -EINVAL;
1663
1664         if (x86_pmu.put_event_constraints)
1665                 x86_pmu.put_event_constraints(fake_cpuc, event);
1666
1667         free_fake_cpuc(fake_cpuc);
1668
1669         return ret;
1670 }
1671
1672 /*
1673  * validate a single event group
1674  *
1675  * validation include:
1676  *      - check events are compatible which each other
1677  *      - events do not compete for the same counter
1678  *      - number of events <= number of counters
1679  *
1680  * validation ensures the group can be loaded onto the
1681  * PMU if it was the only group available.
1682  */
1683 static int validate_group(struct perf_event *event)
1684 {
1685         struct perf_event *leader = event->group_leader;
1686         struct cpu_hw_events *fake_cpuc;
1687         int ret = -EINVAL, n;
1688
1689         fake_cpuc = allocate_fake_cpuc();
1690         if (IS_ERR(fake_cpuc))
1691                 return PTR_ERR(fake_cpuc);
1692         /*
1693          * the event is not yet connected with its
1694          * siblings therefore we must first collect
1695          * existing siblings, then add the new event
1696          * before we can simulate the scheduling
1697          */
1698         n = collect_events(fake_cpuc, leader, true);
1699         if (n < 0)
1700                 goto out;
1701
1702         fake_cpuc->n_events = n;
1703         n = collect_events(fake_cpuc, event, false);
1704         if (n < 0)
1705                 goto out;
1706
1707         fake_cpuc->n_events = n;
1708
1709         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1710
1711 out:
1712         free_fake_cpuc(fake_cpuc);
1713         return ret;
1714 }
1715
1716 static int x86_pmu_event_init(struct perf_event *event)
1717 {
1718         struct pmu *tmp;
1719         int err;
1720
1721         switch (event->attr.type) {
1722         case PERF_TYPE_RAW:
1723         case PERF_TYPE_HARDWARE:
1724         case PERF_TYPE_HW_CACHE:
1725                 break;
1726
1727         default:
1728                 return -ENOENT;
1729         }
1730
1731         err = __x86_pmu_event_init(event);
1732         if (!err) {
1733                 /*
1734                  * we temporarily connect event to its pmu
1735                  * such that validate_group() can classify
1736                  * it as an x86 event using is_x86_event()
1737                  */
1738                 tmp = event->pmu;
1739                 event->pmu = &pmu;
1740
1741                 if (event->group_leader != event)
1742                         err = validate_group(event);
1743                 else
1744                         err = validate_event(event);
1745
1746                 event->pmu = tmp;
1747         }
1748         if (err) {
1749                 if (event->destroy)
1750                         event->destroy(event);
1751         }
1752
1753         return err;
1754 }
1755
1756 static int x86_pmu_event_idx(struct perf_event *event)
1757 {
1758         int idx = event->hw.idx;
1759
1760         if (!x86_pmu.attr_rdpmc)
1761                 return 0;
1762
1763         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1764                 idx -= INTEL_PMC_IDX_FIXED;
1765                 idx |= 1 << 30;
1766         }
1767
1768         return idx + 1;
1769 }
1770
1771 static ssize_t get_attr_rdpmc(struct device *cdev,
1772                               struct device_attribute *attr,
1773                               char *buf)
1774 {
1775         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1776 }
1777
1778 static void change_rdpmc(void *info)
1779 {
1780         bool enable = !!(unsigned long)info;
1781
1782         if (enable)
1783                 set_in_cr4(X86_CR4_PCE);
1784         else
1785                 clear_in_cr4(X86_CR4_PCE);
1786 }
1787
1788 static ssize_t set_attr_rdpmc(struct device *cdev,
1789                               struct device_attribute *attr,
1790                               const char *buf, size_t count)
1791 {
1792         unsigned long val;
1793         ssize_t ret;
1794
1795         ret = kstrtoul(buf, 0, &val);
1796         if (ret)
1797                 return ret;
1798
1799         if (!!val != !!x86_pmu.attr_rdpmc) {
1800                 x86_pmu.attr_rdpmc = !!val;
1801                 smp_call_function(change_rdpmc, (void *)val, 1);
1802         }
1803
1804         return count;
1805 }
1806
1807 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1808
1809 static struct attribute *x86_pmu_attrs[] = {
1810         &dev_attr_rdpmc.attr,
1811         NULL,
1812 };
1813
1814 static struct attribute_group x86_pmu_attr_group = {
1815         .attrs = x86_pmu_attrs,
1816 };
1817
1818 static const struct attribute_group *x86_pmu_attr_groups[] = {
1819         &x86_pmu_attr_group,
1820         &x86_pmu_format_group,
1821         &x86_pmu_events_group,
1822         NULL,
1823 };
1824
1825 static void x86_pmu_flush_branch_stack(void)
1826 {
1827         if (x86_pmu.flush_branch_stack)
1828                 x86_pmu.flush_branch_stack();
1829 }
1830
1831 void perf_check_microcode(void)
1832 {
1833         if (x86_pmu.check_microcode)
1834                 x86_pmu.check_microcode();
1835 }
1836 EXPORT_SYMBOL_GPL(perf_check_microcode);
1837
1838 static struct pmu pmu = {
1839         .pmu_enable             = x86_pmu_enable,
1840         .pmu_disable            = x86_pmu_disable,
1841
1842         .attr_groups            = x86_pmu_attr_groups,
1843
1844         .event_init             = x86_pmu_event_init,
1845
1846         .add                    = x86_pmu_add,
1847         .del                    = x86_pmu_del,
1848         .start                  = x86_pmu_start,
1849         .stop                   = x86_pmu_stop,
1850         .read                   = x86_pmu_read,
1851
1852         .start_txn              = x86_pmu_start_txn,
1853         .cancel_txn             = x86_pmu_cancel_txn,
1854         .commit_txn             = x86_pmu_commit_txn,
1855
1856         .event_idx              = x86_pmu_event_idx,
1857         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1858 };
1859
1860 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1861 {
1862         userpg->cap_usr_time = 0;
1863         userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc;
1864         userpg->pmc_width = x86_pmu.cntval_bits;
1865
1866         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1867                 return;
1868
1869         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1870                 return;
1871
1872         userpg->cap_usr_time = 1;
1873         userpg->time_mult = this_cpu_read(cyc2ns);
1874         userpg->time_shift = CYC2NS_SCALE_FACTOR;
1875         userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;
1876 }
1877
1878 /*
1879  * callchain support
1880  */
1881
1882 static int backtrace_stack(void *data, char *name)
1883 {
1884         return 0;
1885 }
1886
1887 static void backtrace_address(void *data, unsigned long addr, int reliable)
1888 {
1889         struct perf_callchain_entry *entry = data;
1890
1891         perf_callchain_store(entry, addr);
1892 }
1893
1894 static const struct stacktrace_ops backtrace_ops = {
1895         .stack                  = backtrace_stack,
1896         .address                = backtrace_address,
1897         .walk_stack             = print_context_stack_bp,
1898 };
1899
1900 void
1901 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1902 {
1903         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1904                 /* TODO: We don't support guest os callchain now */
1905                 return;
1906         }
1907
1908         perf_callchain_store(entry, regs->ip);
1909
1910         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1911 }
1912
1913 static inline int
1914 valid_user_frame(const void __user *fp, unsigned long size)
1915 {
1916         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1917 }
1918
1919 static unsigned long get_segment_base(unsigned int segment)
1920 {
1921         struct desc_struct *desc;
1922         int idx = segment >> 3;
1923
1924         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1925                 if (idx > LDT_ENTRIES)
1926                         return 0;
1927
1928                 if (idx > current->active_mm->context.size)
1929                         return 0;
1930
1931                 desc = current->active_mm->context.ldt;
1932         } else {
1933                 if (idx > GDT_ENTRIES)
1934                         return 0;
1935
1936                 desc = __this_cpu_ptr(&gdt_page.gdt[0]);
1937         }
1938
1939         return get_desc_base(desc + idx);
1940 }
1941
1942 #ifdef CONFIG_COMPAT
1943
1944 #include <asm/compat.h>
1945
1946 static inline int
1947 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1948 {
1949         /* 32-bit process in 64-bit kernel. */
1950         unsigned long ss_base, cs_base;
1951         struct stack_frame_ia32 frame;
1952         const void __user *fp;
1953
1954         if (!test_thread_flag(TIF_IA32))
1955                 return 0;
1956
1957         cs_base = get_segment_base(regs->cs);
1958         ss_base = get_segment_base(regs->ss);
1959
1960         fp = compat_ptr(ss_base + regs->bp);
1961         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1962                 unsigned long bytes;
1963                 frame.next_frame     = 0;
1964                 frame.return_address = 0;
1965
1966                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1967                 if (bytes != sizeof(frame))
1968                         break;
1969
1970                 if (!valid_user_frame(fp, sizeof(frame)))
1971                         break;
1972
1973                 perf_callchain_store(entry, cs_base + frame.return_address);
1974                 fp = compat_ptr(ss_base + frame.next_frame);
1975         }
1976         return 1;
1977 }
1978 #else
1979 static inline int
1980 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1981 {
1982     return 0;
1983 }
1984 #endif
1985
1986 void
1987 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1988 {
1989         struct stack_frame frame;
1990         const void __user *fp;
1991
1992         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1993                 /* TODO: We don't support guest os callchain now */
1994                 return;
1995         }
1996
1997         /*
1998          * We don't know what to do with VM86 stacks.. ignore them for now.
1999          */
2000         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2001                 return;
2002
2003         fp = (void __user *)regs->bp;
2004
2005         perf_callchain_store(entry, regs->ip);
2006
2007         if (!current->mm)
2008                 return;
2009
2010         if (perf_callchain_user32(regs, entry))
2011                 return;
2012
2013         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2014                 unsigned long bytes;
2015                 frame.next_frame             = NULL;
2016                 frame.return_address = 0;
2017
2018                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2019                 if (bytes != sizeof(frame))
2020                         break;
2021
2022                 if (!valid_user_frame(fp, sizeof(frame)))
2023                         break;
2024
2025                 perf_callchain_store(entry, frame.return_address);
2026                 fp = frame.next_frame;
2027         }
2028 }
2029
2030 /*
2031  * Deal with code segment offsets for the various execution modes:
2032  *
2033  *   VM86 - the good olde 16 bit days, where the linear address is
2034  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2035  *
2036  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2037  *          to figure out what the 32bit base address is.
2038  *
2039  *    X32 - has TIF_X32 set, but is running in x86_64
2040  *
2041  * X86_64 - CS,DS,SS,ES are all zero based.
2042  */
2043 static unsigned long code_segment_base(struct pt_regs *regs)
2044 {
2045         /*
2046          * If we are in VM86 mode, add the segment offset to convert to a
2047          * linear address.
2048          */
2049         if (regs->flags & X86_VM_MASK)
2050                 return 0x10 * regs->cs;
2051
2052         /*
2053          * For IA32 we look at the GDT/LDT segment base to convert the
2054          * effective IP to a linear address.
2055          */
2056 #ifdef CONFIG_X86_32
2057         if (user_mode(regs) && regs->cs != __USER_CS)
2058                 return get_segment_base(regs->cs);
2059 #else
2060         if (test_thread_flag(TIF_IA32)) {
2061                 if (user_mode(regs) && regs->cs != __USER32_CS)
2062                         return get_segment_base(regs->cs);
2063         }
2064 #endif
2065         return 0;
2066 }
2067
2068 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2069 {
2070         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2071                 return perf_guest_cbs->get_guest_ip();
2072
2073         return regs->ip + code_segment_base(regs);
2074 }
2075
2076 unsigned long perf_misc_flags(struct pt_regs *regs)
2077 {
2078         int misc = 0;
2079
2080         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2081                 if (perf_guest_cbs->is_user_mode())
2082                         misc |= PERF_RECORD_MISC_GUEST_USER;
2083                 else
2084                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2085         } else {
2086                 if (user_mode(regs))
2087                         misc |= PERF_RECORD_MISC_USER;
2088                 else
2089                         misc |= PERF_RECORD_MISC_KERNEL;
2090         }
2091
2092         if (regs->flags & PERF_EFLAGS_EXACT)
2093                 misc |= PERF_RECORD_MISC_EXACT_IP;
2094
2095         return misc;
2096 }
2097
2098 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2099 {
2100         cap->version            = x86_pmu.version;
2101         cap->num_counters_gp    = x86_pmu.num_counters;
2102         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2103         cap->bit_width_gp       = x86_pmu.cntval_bits;
2104         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2105         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2106         cap->events_mask_len    = x86_pmu.events_mask_len;
2107 }
2108 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);