2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
45 #include <asm/processor.h>
46 #include <asm/traps.h>
47 #include <asm/tlbflush.h>
51 #include "mce-internal.h"
53 static DEFINE_MUTEX(mce_chrdev_read_mutex);
55 #define rcu_dereference_check_mce(p) \
56 rcu_dereference_index_check((p), \
57 rcu_read_lock_sched_held() || \
58 lockdep_is_held(&mce_chrdev_read_mutex))
60 #define CREATE_TRACE_POINTS
61 #include <trace/events/mce.h>
63 #define SPINUNIT 100 /* 100ns */
65 DEFINE_PER_CPU(unsigned, mce_exception_count);
67 struct mce_bank *mce_banks __read_mostly;
68 struct mce_vendor_flags mce_flags __read_mostly;
70 struct mca_config mca_cfg __read_mostly = {
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
83 /* User mode helper program triggered by machine check event */
84 static unsigned long mce_need_notify;
85 static char mce_helper[128];
86 static char *mce_helper_argv[2] = { mce_helper, NULL };
88 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
90 static DEFINE_PER_CPU(struct mce, mces_seen);
91 static int cpu_missing;
94 * MCA banks polled by the period polling timer for corrected events.
95 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
97 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
98 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
102 * MCA banks controlled through firmware first for corrected errors.
103 * This is a global list of banks for which we won't enable CMCI and we
104 * won't poll. Firmware controls these banks and is responsible for
105 * reporting corrected errors through GHES. Uncorrected/recoverable
106 * errors are still notified through a machine check.
108 mce_banks_t mce_banks_ce_disabled;
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
115 * CPU/chipset specific EDAC code can register a notifier call here to print
116 * MCE errors in a human-readable form.
118 static ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
120 /* Do initial initialization of a struct mce */
121 void mce_setup(struct mce *m)
123 memset(m, 0, sizeof(struct mce));
124 m->cpu = m->extcpu = smp_processor_id();
126 /* We hope get_seconds stays lockless */
127 m->time = get_seconds();
128 m->cpuvendor = boot_cpu_data.x86_vendor;
129 m->cpuid = cpuid_eax(1);
130 m->socketid = cpu_data(m->extcpu).phys_proc_id;
131 m->apicid = cpu_data(m->extcpu).initial_apicid;
132 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
135 DEFINE_PER_CPU(struct mce, injectm);
136 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
139 * Lockless MCE logging infrastructure.
140 * This avoids deadlocks on printk locks without having to break locks. Also
141 * separate MCEs from kernel messages to avoid bogus bug reports.
144 static struct mce_log mcelog = {
145 .signature = MCE_LOG_SIGNATURE,
147 .recordlen = sizeof(struct mce),
150 void mce_log(struct mce *mce)
152 unsigned next, entry;
154 /* Emit the trace record: */
155 trace_mce_record(mce);
157 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
162 entry = rcu_dereference_check_mce(mcelog.next);
166 * When the buffer fills up discard new entries.
167 * Assume that the earlier errors are the more
170 if (entry >= MCE_LOG_LEN) {
171 set_bit(MCE_OVERFLOW,
172 (unsigned long *)&mcelog.flags);
175 /* Old left over entry. Skip: */
176 if (mcelog.entry[entry].finished) {
184 if (cmpxchg(&mcelog.next, entry, next) == entry)
187 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
189 mcelog.entry[entry].finished = 1;
193 set_bit(0, &mce_need_notify);
196 static void drain_mcelog_buffer(void)
198 unsigned int next, i, prev = 0;
200 next = ACCESS_ONCE(mcelog.next);
205 /* drain what was logged during boot */
206 for (i = prev; i < next; i++) {
207 unsigned long start = jiffies;
208 unsigned retries = 1;
210 m = &mcelog.entry[i];
212 while (!m->finished) {
213 if (time_after_eq(jiffies, start + 2*retries))
218 if (!m->finished && retries >= 4) {
219 pr_err("skipping error being logged currently!\n");
224 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
227 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
229 next = cmpxchg(&mcelog.next, prev, 0);
230 } while (next != prev);
234 void mce_register_decode_chain(struct notifier_block *nb)
236 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
237 drain_mcelog_buffer();
239 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
241 void mce_unregister_decode_chain(struct notifier_block *nb)
243 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
245 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
247 static void print_mce(struct mce *m)
251 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
252 m->extcpu, m->mcgstatus, m->bank, m->status);
255 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
256 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
259 if (m->cs == __KERNEL_CS)
260 print_symbol("{%s}", m->ip);
264 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
266 pr_cont("ADDR %llx ", m->addr);
268 pr_cont("MISC %llx ", m->misc);
272 * Note this output is parsed by external tools and old fields
273 * should not be changed.
275 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
276 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
277 cpu_data(m->extcpu).microcode);
280 * Print out human-readable details about the MCE error,
281 * (if the CPU has an implementation for that)
283 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
284 if (ret == NOTIFY_STOP)
287 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
290 #define PANIC_TIMEOUT 5 /* 5 seconds */
292 static atomic_t mce_panicked;
294 static int fake_panic;
295 static atomic_t mce_fake_panicked;
297 /* Panic in progress. Enable interrupts and wait for final IPI */
298 static void wait_for_panic(void)
300 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
304 while (timeout-- > 0)
306 if (panic_timeout == 0)
307 panic_timeout = mca_cfg.panic_timeout;
308 panic("Panicing machine check CPU died");
311 static void mce_panic(const char *msg, struct mce *final, char *exp)
317 * Make sure only one CPU runs in machine check panic
319 if (atomic_inc_return(&mce_panicked) > 1)
326 /* Don't log too much for fake panic */
327 if (atomic_inc_return(&mce_fake_panicked) > 1)
330 /* First print corrected ones that are still unlogged */
331 for (i = 0; i < MCE_LOG_LEN; i++) {
332 struct mce *m = &mcelog.entry[i];
333 if (!(m->status & MCI_STATUS_VAL))
335 if (!(m->status & MCI_STATUS_UC)) {
338 apei_err = apei_write_mce(m);
341 /* Now print uncorrected but with the final one last */
342 for (i = 0; i < MCE_LOG_LEN; i++) {
343 struct mce *m = &mcelog.entry[i];
344 if (!(m->status & MCI_STATUS_VAL))
346 if (!(m->status & MCI_STATUS_UC))
348 if (!final || memcmp(m, final, sizeof(struct mce))) {
351 apei_err = apei_write_mce(m);
357 apei_err = apei_write_mce(final);
360 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
362 pr_emerg(HW_ERR "Machine check: %s\n", exp);
364 if (panic_timeout == 0)
365 panic_timeout = mca_cfg.panic_timeout;
368 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
371 /* Support code for software error injection */
373 static int msr_to_offset(u32 msr)
375 unsigned bank = __this_cpu_read(injectm.bank);
377 if (msr == mca_cfg.rip_msr)
378 return offsetof(struct mce, ip);
379 if (msr == MSR_IA32_MCx_STATUS(bank))
380 return offsetof(struct mce, status);
381 if (msr == MSR_IA32_MCx_ADDR(bank))
382 return offsetof(struct mce, addr);
383 if (msr == MSR_IA32_MCx_MISC(bank))
384 return offsetof(struct mce, misc);
385 if (msr == MSR_IA32_MCG_STATUS)
386 return offsetof(struct mce, mcgstatus);
390 /* MSR access wrappers used for error injection */
391 static u64 mce_rdmsrl(u32 msr)
395 if (__this_cpu_read(injectm.finished)) {
396 int offset = msr_to_offset(msr);
400 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
403 if (rdmsrl_safe(msr, &v)) {
404 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
406 * Return zero in case the access faulted. This should
407 * not happen normally but can happen if the CPU does
408 * something weird, or if the code is buggy.
416 static void mce_wrmsrl(u32 msr, u64 v)
418 if (__this_cpu_read(injectm.finished)) {
419 int offset = msr_to_offset(msr);
422 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
429 * Collect all global (w.r.t. this processor) status about this machine
430 * check into our "mce" struct so that we can use it later to assess
431 * the severity of the problem as we read per-bank specific details.
433 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
437 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
440 * Get the address of the instruction at the time of
441 * the machine check error.
443 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
448 * When in VM86 mode make the cs look like ring 3
449 * always. This is a lie, but it's better than passing
450 * the additional vm86 bit around everywhere.
452 if (v8086_mode(regs))
455 /* Use accurate RIP reporting if available. */
457 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
462 * Simple lockless ring to communicate PFNs from the exception handler with the
463 * process context work function. This is vastly simplified because there's
464 * only a single reader and a single writer.
466 #define MCE_RING_SIZE 16 /* we use one entry less */
469 unsigned short start;
471 unsigned long ring[MCE_RING_SIZE];
473 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
475 /* Runs with CPU affinity in workqueue */
476 static int mce_ring_empty(void)
478 struct mce_ring *r = this_cpu_ptr(&mce_ring);
480 return r->start == r->end;
483 static int mce_ring_get(unsigned long *pfn)
490 r = this_cpu_ptr(&mce_ring);
491 if (r->start == r->end)
493 *pfn = r->ring[r->start];
494 r->start = (r->start + 1) % MCE_RING_SIZE;
501 /* Always runs in MCE context with preempt off */
502 static int mce_ring_add(unsigned long pfn)
504 struct mce_ring *r = this_cpu_ptr(&mce_ring);
507 next = (r->end + 1) % MCE_RING_SIZE;
508 if (next == r->start)
510 r->ring[r->end] = pfn;
516 int mce_available(struct cpuinfo_x86 *c)
518 if (mca_cfg.disabled)
520 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
523 static void mce_schedule_work(void)
525 if (!mce_ring_empty())
526 schedule_work(this_cpu_ptr(&mce_work));
529 static DEFINE_PER_CPU(struct irq_work, mce_irq_work);
531 static void mce_irq_work_cb(struct irq_work *entry)
537 static void mce_report_event(struct pt_regs *regs)
539 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
542 * Triggering the work queue here is just an insurance
543 * policy in case the syscall exit notify handler
544 * doesn't run soon enough or ends up running on the
545 * wrong CPU (can happen when audit sleeps)
551 irq_work_queue(this_cpu_ptr(&mce_irq_work));
555 * Read ADDR and MISC registers.
557 static void mce_read_aux(struct mce *m, int i)
559 if (m->status & MCI_STATUS_MISCV)
560 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
561 if (m->status & MCI_STATUS_ADDRV) {
562 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
565 * Mask the reported address by the reported granularity.
567 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
568 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
575 static bool memory_error(struct mce *m)
577 struct cpuinfo_x86 *c = &boot_cpu_data;
579 if (c->x86_vendor == X86_VENDOR_AMD) {
584 } else if (c->x86_vendor == X86_VENDOR_INTEL) {
586 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
588 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
589 * indicating a memory error. Bit 8 is used for indicating a
590 * cache hierarchy error. The combination of bit 2 and bit 3
591 * is used for indicating a `generic' cache hierarchy error
592 * But we can't just blindly check the above bits, because if
593 * bit 11 is set, then it is a bus/interconnect error - and
594 * either way the above bits just gives more detail on what
595 * bus/interconnect error happened. Note that bit 12 can be
596 * ignored, as it's the "filter" bit.
598 return (m->status & 0xef80) == BIT(7) ||
599 (m->status & 0xef00) == BIT(8) ||
600 (m->status & 0xeffc) == 0xc;
606 DEFINE_PER_CPU(unsigned, mce_poll_count);
609 * Poll for corrected events or events that happened before reset.
610 * Those are just logged through /dev/mcelog.
612 * This is executed in standard interrupt context.
614 * Note: spec recommends to panic for fatal unsignalled
615 * errors here. However this would be quite problematic --
616 * we would need to reimplement the Monarch handling and
617 * it would mess up the exclusion between exception handler
618 * and poll hander -- * so we skip this for now.
619 * These cases should not happen anyways, or only when the CPU
620 * is already totally * confused. In this case it's likely it will
621 * not fully execute the machine check handler either.
623 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
625 bool error_logged = false;
630 this_cpu_inc(mce_poll_count);
632 mce_gather_info(&m, NULL);
634 for (i = 0; i < mca_cfg.banks; i++) {
635 if (!mce_banks[i].ctl || !test_bit(i, *b))
644 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
645 if (!(m.status & MCI_STATUS_VAL))
650 * Uncorrected or signalled events are handled by the exception
651 * handler when it is enabled, so don't process those here.
653 * TBD do the same check for MCI_STATUS_EN here?
655 if (!(flags & MCP_UC) &&
656 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
661 if (!(flags & MCP_TIMESTAMP))
664 severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
667 * In the cases where we don't have a valid address after all,
668 * do not add it into the ring buffer.
670 if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) {
671 if (m.status & MCI_STATUS_ADDRV) {
672 mce_ring_add(m.addr >> PAGE_SHIFT);
678 * Don't get the IP here because it's unlikely to
679 * have anything to do with the actual error location.
681 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) {
687 * Clear state for this bank.
689 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
693 * Don't clear MCG_STATUS here because it's only defined for
701 EXPORT_SYMBOL_GPL(machine_check_poll);
704 * Do a quick check if any of the events requires a panic.
705 * This decides if we keep the events around or clear them.
707 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
708 struct pt_regs *regs)
712 for (i = 0; i < mca_cfg.banks; i++) {
713 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
714 if (m->status & MCI_STATUS_VAL) {
715 __set_bit(i, validp);
716 if (quirk_no_way_out)
717 quirk_no_way_out(i, m, regs);
719 if (mce_severity(m, mca_cfg.tolerant, msg, true) >=
727 * Variable to establish order between CPUs while scanning.
728 * Each CPU spins initially until executing is equal its number.
730 static atomic_t mce_executing;
733 * Defines order of CPUs on entry. First CPU becomes Monarch.
735 static atomic_t mce_callin;
738 * Check if a timeout waiting for other CPUs happened.
740 static int mce_timed_out(u64 *t, const char *msg)
743 * The others already did panic for some reason.
744 * Bail out like in a timeout.
745 * rmb() to tell the compiler that system_state
746 * might have been modified by someone else.
749 if (atomic_read(&mce_panicked))
751 if (!mca_cfg.monarch_timeout)
753 if ((s64)*t < SPINUNIT) {
754 if (mca_cfg.tolerant <= 1)
755 mce_panic(msg, NULL, NULL);
761 touch_nmi_watchdog();
766 * The Monarch's reign. The Monarch is the CPU who entered
767 * the machine check handler first. It waits for the others to
768 * raise the exception too and then grades them. When any
769 * error is fatal panic. Only then let the others continue.
771 * The other CPUs entering the MCE handler will be controlled by the
772 * Monarch. They are called Subjects.
774 * This way we prevent any potential data corruption in a unrecoverable case
775 * and also makes sure always all CPU's errors are examined.
777 * Also this detects the case of a machine check event coming from outer
778 * space (not detected by any CPUs) In this case some external agent wants
779 * us to shut down, so panic too.
781 * The other CPUs might still decide to panic if the handler happens
782 * in a unrecoverable place, but in this case the system is in a semi-stable
783 * state and won't corrupt anything by itself. It's ok to let the others
784 * continue for a bit first.
786 * All the spin loops have timeouts; when a timeout happens a CPU
787 * typically elects itself to be Monarch.
789 static void mce_reign(void)
792 struct mce *m = NULL;
793 int global_worst = 0;
798 * This CPU is the Monarch and the other CPUs have run
799 * through their handlers.
800 * Grade the severity of the errors of all the CPUs.
802 for_each_possible_cpu(cpu) {
803 int severity = mce_severity(&per_cpu(mces_seen, cpu),
806 if (severity > global_worst) {
808 global_worst = severity;
809 m = &per_cpu(mces_seen, cpu);
814 * Cannot recover? Panic here then.
815 * This dumps all the mces in the log buffer and stops the
818 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
819 mce_panic("Fatal machine check", m, msg);
822 * For UC somewhere we let the CPU who detects it handle it.
823 * Also must let continue the others, otherwise the handling
824 * CPU could deadlock on a lock.
828 * No machine check event found. Must be some external
829 * source or one CPU is hung. Panic.
831 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
832 mce_panic("Fatal machine check from unknown source", NULL, NULL);
835 * Now clear all the mces_seen so that they don't reappear on
838 for_each_possible_cpu(cpu)
839 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
842 static atomic_t global_nwo;
845 * Start of Monarch synchronization. This waits until all CPUs have
846 * entered the exception handler and then determines if any of them
847 * saw a fatal event that requires panic. Then it executes them
848 * in the entry order.
849 * TBD double check parallel CPU hotunplug
851 static int mce_start(int *no_way_out)
854 int cpus = num_online_cpus();
855 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
860 atomic_add(*no_way_out, &global_nwo);
862 * global_nwo should be updated before mce_callin
865 order = atomic_inc_return(&mce_callin);
870 while (atomic_read(&mce_callin) != cpus) {
871 if (mce_timed_out(&timeout,
872 "Timeout: Not all CPUs entered broadcast exception handler")) {
873 atomic_set(&global_nwo, 0);
880 * mce_callin should be read before global_nwo
886 * Monarch: Starts executing now, the others wait.
888 atomic_set(&mce_executing, 1);
891 * Subject: Now start the scanning loop one by one in
892 * the original callin order.
893 * This way when there are any shared banks it will be
894 * only seen by one CPU before cleared, avoiding duplicates.
896 while (atomic_read(&mce_executing) < order) {
897 if (mce_timed_out(&timeout,
898 "Timeout: Subject CPUs unable to finish machine check processing")) {
899 atomic_set(&global_nwo, 0);
907 * Cache the global no_way_out state.
909 *no_way_out = atomic_read(&global_nwo);
915 * Synchronize between CPUs after main scanning loop.
916 * This invokes the bulk of the Monarch processing.
918 static int mce_end(int order)
921 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
929 * Allow others to run.
931 atomic_inc(&mce_executing);
934 /* CHECKME: Can this race with a parallel hotplug? */
935 int cpus = num_online_cpus();
938 * Monarch: Wait for everyone to go through their scanning
941 while (atomic_read(&mce_executing) <= cpus) {
942 if (mce_timed_out(&timeout,
943 "Timeout: Monarch CPU unable to finish machine check processing"))
953 * Subject: Wait for Monarch to finish.
955 while (atomic_read(&mce_executing) != 0) {
956 if (mce_timed_out(&timeout,
957 "Timeout: Monarch CPU did not finish machine check processing"))
963 * Don't reset anything. That's done by the Monarch.
969 * Reset all global state.
972 atomic_set(&global_nwo, 0);
973 atomic_set(&mce_callin, 0);
977 * Let others run again.
979 atomic_set(&mce_executing, 0);
984 * Check if the address reported by the CPU is in a format we can parse.
985 * It would be possible to add code for most other cases, but all would
986 * be somewhat complicated (e.g. segment offset would require an instruction
987 * parser). So only support physical addresses up to page granuality for now.
989 static int mce_usable_address(struct mce *m)
991 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
993 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
995 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
1000 static void mce_clear_state(unsigned long *toclear)
1004 for (i = 0; i < mca_cfg.banks; i++) {
1005 if (test_bit(i, toclear))
1006 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1011 * The actual machine check handler. This only handles real
1012 * exceptions when something got corrupted coming in through int 18.
1014 * This is executed in NMI context not subject to normal locking rules. This
1015 * implies that most kernel services cannot be safely used. Don't even
1016 * think about putting a printk in there!
1018 * On Intel systems this is entered on all CPUs in parallel through
1019 * MCE broadcast. However some CPUs might be broken beyond repair,
1020 * so be always careful when synchronizing with others.
1022 void do_machine_check(struct pt_regs *regs, long error_code)
1024 struct mca_config *cfg = &mca_cfg;
1025 struct mce m, *final;
1026 enum ctx_state prev_state;
1031 * Establish sequential order between the CPUs entering the machine
1036 * If no_way_out gets set, there is no safe way to recover from this
1037 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1041 * If kill_it gets set, there might be a way to recover from this
1045 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1046 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1047 char *msg = "Unknown";
1048 u64 recover_paddr = ~0ull;
1049 int flags = MF_ACTION_REQUIRED;
1051 prev_state = ist_enter(regs);
1053 this_cpu_inc(mce_exception_count);
1058 mce_gather_info(&m, regs);
1060 final = this_cpu_ptr(&mces_seen);
1063 memset(valid_banks, 0, sizeof(valid_banks));
1064 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1069 * When no restart IP might need to kill or panic.
1070 * Assume the worst for now, but if we find the
1071 * severity is MCE_AR_SEVERITY we have other options.
1073 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1077 * Go through all the banks in exclusion of the other CPUs.
1078 * This way we don't report duplicated events on shared banks
1079 * because the first one to see it will clear it.
1081 order = mce_start(&no_way_out);
1082 for (i = 0; i < cfg->banks; i++) {
1083 __clear_bit(i, toclear);
1084 if (!test_bit(i, valid_banks))
1086 if (!mce_banks[i].ctl)
1093 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1094 if ((m.status & MCI_STATUS_VAL) == 0)
1098 * Non uncorrected or non signaled errors are handled by
1099 * machine_check_poll. Leave them alone, unless this panics.
1101 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1106 * Set taint even when machine check was not enabled.
1108 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1110 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1113 * When machine check was for corrected/deferred handler don't
1114 * touch, unless we're panicing.
1116 if ((severity == MCE_KEEP_SEVERITY ||
1117 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1119 __set_bit(i, toclear);
1120 if (severity == MCE_NO_SEVERITY) {
1122 * Machine check event was not enabled. Clear, but
1128 mce_read_aux(&m, i);
1131 * Action optional error. Queue address for later processing.
1132 * When the ring overflows we just ignore the AO error.
1133 * RED-PEN add some logging mechanism when
1134 * usable_address or mce_add_ring fails.
1135 * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0
1137 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1138 mce_ring_add(m.addr >> PAGE_SHIFT);
1142 if (severity > worst) {
1148 /* mce_clear_state will clear *final, save locally for use later */
1152 mce_clear_state(toclear);
1155 * Do most of the synchronization with other CPUs.
1156 * When there's any problem use only local no_way_out state.
1158 if (mce_end(order) < 0)
1159 no_way_out = worst >= MCE_PANIC_SEVERITY;
1162 * At insane "tolerant" levels we take no action. Otherwise
1163 * we only die if we have no other choice. For less serious
1164 * issues we try to recover, or limit damage to the current
1167 if (cfg->tolerant < 3) {
1169 mce_panic("Fatal machine check on current CPU", &m, msg);
1170 if (worst == MCE_AR_SEVERITY) {
1171 recover_paddr = m.addr;
1172 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1173 flags |= MF_MUST_KILL;
1174 } else if (kill_it) {
1175 force_sig(SIGBUS, current);
1180 mce_report_event(regs);
1181 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1185 if (recover_paddr == ~0ull)
1188 pr_err("Uncorrected hardware memory error in user-access at %llx",
1191 * We must call memory_failure() here even if the current process is
1192 * doomed. We still need to mark the page as poisoned and alert any
1193 * other users of the page.
1195 ist_begin_non_atomic(regs);
1197 if (memory_failure(recover_paddr >> PAGE_SHIFT, MCE_VECTOR, flags) < 0) {
1198 pr_err("Memory error not recovered");
1199 force_sig(SIGBUS, current);
1201 local_irq_disable();
1202 ist_end_non_atomic();
1204 ist_exit(regs, prev_state);
1206 EXPORT_SYMBOL_GPL(do_machine_check);
1208 #ifndef CONFIG_MEMORY_FAILURE
1209 int memory_failure(unsigned long pfn, int vector, int flags)
1211 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1212 BUG_ON(flags & MF_ACTION_REQUIRED);
1213 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1214 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1222 * Action optional processing happens here (picking up
1223 * from the list of faulting pages that do_machine_check()
1224 * placed into the "ring").
1226 static void mce_process_work(struct work_struct *dummy)
1230 while (mce_ring_get(&pfn))
1231 memory_failure(pfn, MCE_VECTOR, 0);
1234 #ifdef CONFIG_X86_MCE_INTEL
1236 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1237 * @cpu: The CPU on which the event occurred.
1238 * @status: Event status information
1240 * This function should be called by the thermal interrupt after the
1241 * event has been processed and the decision was made to log the event
1244 * The status parameter will be saved to the 'status' field of 'struct mce'
1245 * and historically has been the register value of the
1246 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1248 void mce_log_therm_throt_event(__u64 status)
1253 m.bank = MCE_THERMAL_BANK;
1257 #endif /* CONFIG_X86_MCE_INTEL */
1260 * Periodic polling timer for "silent" machine check errors. If the
1261 * poller finds an MCE, poll 2x faster. When the poller finds no more
1262 * errors, poll 2x slower (up to check_interval seconds).
1264 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1266 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1267 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1269 static unsigned long mce_adjust_timer_default(unsigned long interval)
1274 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1276 static void __restart_timer(struct timer_list *t, unsigned long interval)
1278 unsigned long when = jiffies + interval;
1279 unsigned long flags;
1281 local_irq_save(flags);
1283 if (timer_pending(t)) {
1284 if (time_before(when, t->expires))
1285 mod_timer_pinned(t, when);
1287 t->expires = round_jiffies(when);
1288 add_timer_on(t, smp_processor_id());
1291 local_irq_restore(flags);
1294 static void mce_timer_fn(unsigned long data)
1296 struct timer_list *t = this_cpu_ptr(&mce_timer);
1297 int cpu = smp_processor_id();
1300 WARN_ON(cpu != data);
1302 iv = __this_cpu_read(mce_next_interval);
1304 if (mce_available(this_cpu_ptr(&cpu_info))) {
1305 machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks));
1307 if (mce_intel_cmci_poll()) {
1308 iv = mce_adjust_timer(iv);
1314 * Alert userspace if needed. If we logged an MCE, reduce the polling
1315 * interval, otherwise increase the polling interval.
1317 if (mce_notify_irq())
1318 iv = max(iv / 2, (unsigned long) HZ/100);
1320 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1323 __this_cpu_write(mce_next_interval, iv);
1324 __restart_timer(t, iv);
1328 * Ensure that the timer is firing in @interval from now.
1330 void mce_timer_kick(unsigned long interval)
1332 struct timer_list *t = this_cpu_ptr(&mce_timer);
1333 unsigned long iv = __this_cpu_read(mce_next_interval);
1335 __restart_timer(t, interval);
1338 __this_cpu_write(mce_next_interval, interval);
1341 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1342 static void mce_timer_delete_all(void)
1346 for_each_online_cpu(cpu)
1347 del_timer_sync(&per_cpu(mce_timer, cpu));
1350 static void mce_do_trigger(struct work_struct *work)
1352 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1355 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1358 * Notify the user(s) about new machine check events.
1359 * Can be called from interrupt context, but not from machine check/NMI
1362 int mce_notify_irq(void)
1364 /* Not more than two messages every minute */
1365 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1367 if (test_and_clear_bit(0, &mce_need_notify)) {
1368 /* wake processes polling /dev/mcelog */
1369 wake_up_interruptible(&mce_chrdev_wait);
1372 schedule_work(&mce_trigger_work);
1374 if (__ratelimit(&ratelimit))
1375 pr_info(HW_ERR "Machine check events logged\n");
1381 EXPORT_SYMBOL_GPL(mce_notify_irq);
1383 static int __mcheck_cpu_mce_banks_init(void)
1386 u8 num_banks = mca_cfg.banks;
1388 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1392 for (i = 0; i < num_banks; i++) {
1393 struct mce_bank *b = &mce_banks[i];
1402 * Initialize Machine Checks for a CPU.
1404 static int __mcheck_cpu_cap_init(void)
1409 rdmsrl(MSR_IA32_MCG_CAP, cap);
1411 b = cap & MCG_BANKCNT_MASK;
1413 pr_info("CPU supports %d MCE banks\n", b);
1415 if (b > MAX_NR_BANKS) {
1416 pr_warn("Using only %u machine check banks out of %u\n",
1421 /* Don't support asymmetric configurations today */
1422 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1426 int err = __mcheck_cpu_mce_banks_init();
1432 /* Use accurate RIP reporting if available. */
1433 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1434 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1436 if (cap & MCG_SER_P)
1442 static void __mcheck_cpu_init_generic(void)
1444 enum mcp_flags m_fl = 0;
1445 mce_banks_t all_banks;
1449 if (!mca_cfg.bootlog)
1453 * Log the machine checks left over from the previous reset.
1455 bitmap_fill(all_banks, MAX_NR_BANKS);
1456 machine_check_poll(MCP_UC | m_fl, &all_banks);
1458 cr4_set_bits(X86_CR4_MCE);
1460 rdmsrl(MSR_IA32_MCG_CAP, cap);
1461 if (cap & MCG_CTL_P)
1462 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1464 for (i = 0; i < mca_cfg.banks; i++) {
1465 struct mce_bank *b = &mce_banks[i];
1469 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1470 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1475 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1476 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1477 * Vol 3B Table 15-20). But this confuses both the code that determines
1478 * whether the machine check occurred in kernel or user mode, and also
1479 * the severity assessment code. Pretend that EIPV was set, and take the
1480 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1482 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1486 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1488 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1489 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1490 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1492 (MCI_STATUS_UC|MCI_STATUS_EN|
1493 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1494 MCI_STATUS_AR|MCACOD_INSTR))
1497 m->mcgstatus |= MCG_STATUS_EIPV;
1502 /* Add per CPU specific workarounds here */
1503 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1505 struct mca_config *cfg = &mca_cfg;
1507 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1508 pr_info("unknown CPU type - not enabling MCE support\n");
1512 /* This should be disabled by the BIOS, but isn't always */
1513 if (c->x86_vendor == X86_VENDOR_AMD) {
1514 if (c->x86 == 15 && cfg->banks > 4) {
1516 * disable GART TBL walk error reporting, which
1517 * trips off incorrectly with the IOMMU & 3ware
1520 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1522 if (c->x86 <= 17 && cfg->bootlog < 0) {
1524 * Lots of broken BIOS around that don't clear them
1525 * by default and leave crap in there. Don't log:
1530 * Various K7s with broken bank 0 around. Always disable
1533 if (c->x86 == 6 && cfg->banks > 0)
1534 mce_banks[0].ctl = 0;
1537 * overflow_recov is supported for F15h Models 00h-0fh
1538 * even though we don't have a CPUID bit for it.
1540 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1541 mce_flags.overflow_recov = 1;
1544 * Turn off MC4_MISC thresholding banks on those models since
1545 * they're not supported there.
1547 if (c->x86 == 0x15 &&
1548 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1553 0x00000413, /* MC4_MISC0 */
1554 0xc0000408, /* MC4_MISC1 */
1557 rdmsrl(MSR_K7_HWCR, hwcr);
1559 /* McStatusWrEn has to be set */
1560 need_toggle = !(hwcr & BIT(18));
1563 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1565 /* Clear CntP bit safely */
1566 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1567 msr_clear_bit(msrs[i], 62);
1569 /* restore old settings */
1571 wrmsrl(MSR_K7_HWCR, hwcr);
1575 if (c->x86_vendor == X86_VENDOR_INTEL) {
1577 * SDM documents that on family 6 bank 0 should not be written
1578 * because it aliases to another special BIOS controlled
1580 * But it's not aliased anymore on model 0x1a+
1581 * Don't ignore bank 0 completely because there could be a
1582 * valid event later, merely don't write CTL0.
1585 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1586 mce_banks[0].init = 0;
1589 * All newer Intel systems support MCE broadcasting. Enable
1590 * synchronization with a one second timeout.
1592 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1593 cfg->monarch_timeout < 0)
1594 cfg->monarch_timeout = USEC_PER_SEC;
1597 * There are also broken BIOSes on some Pentium M and
1600 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1603 if (c->x86 == 6 && c->x86_model == 45)
1604 quirk_no_way_out = quirk_sandybridge_ifu;
1606 if (cfg->monarch_timeout < 0)
1607 cfg->monarch_timeout = 0;
1608 if (cfg->bootlog != 0)
1609 cfg->panic_timeout = 30;
1614 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1619 switch (c->x86_vendor) {
1620 case X86_VENDOR_INTEL:
1621 intel_p5_mcheck_init(c);
1624 case X86_VENDOR_CENTAUR:
1625 winchip_mcheck_init(c);
1633 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1635 switch (c->x86_vendor) {
1636 case X86_VENDOR_INTEL:
1637 mce_intel_feature_init(c);
1638 mce_adjust_timer = cmci_intel_adjust_timer;
1640 case X86_VENDOR_AMD:
1641 mce_amd_feature_init(c);
1642 mce_flags.overflow_recov = cpuid_ebx(0x80000007) & 0x1;
1649 static void mce_start_timer(unsigned int cpu, struct timer_list *t)
1651 unsigned long iv = check_interval * HZ;
1653 if (mca_cfg.ignore_ce || !iv)
1656 per_cpu(mce_next_interval, cpu) = iv;
1658 t->expires = round_jiffies(jiffies + iv);
1659 add_timer_on(t, cpu);
1662 static void __mcheck_cpu_init_timer(void)
1664 struct timer_list *t = this_cpu_ptr(&mce_timer);
1665 unsigned int cpu = smp_processor_id();
1667 setup_timer(t, mce_timer_fn, cpu);
1668 mce_start_timer(cpu, t);
1671 /* Handle unconfigured int18 (should never happen) */
1672 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1674 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1675 smp_processor_id());
1678 /* Call the installed machine check handler for this CPU setup. */
1679 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1680 unexpected_machine_check;
1683 * Called for each booted CPU to set up machine checks.
1684 * Must be called with preempt off:
1686 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1688 if (mca_cfg.disabled)
1691 if (__mcheck_cpu_ancient_init(c))
1694 if (!mce_available(c))
1697 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1698 mca_cfg.disabled = true;
1702 machine_check_vector = do_machine_check;
1704 __mcheck_cpu_init_generic();
1705 __mcheck_cpu_init_vendor(c);
1706 __mcheck_cpu_init_timer();
1707 INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work);
1708 init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb);
1712 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1715 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1716 static int mce_chrdev_open_count; /* #times opened */
1717 static int mce_chrdev_open_exclu; /* already open exclusive? */
1719 static int mce_chrdev_open(struct inode *inode, struct file *file)
1721 spin_lock(&mce_chrdev_state_lock);
1723 if (mce_chrdev_open_exclu ||
1724 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1725 spin_unlock(&mce_chrdev_state_lock);
1730 if (file->f_flags & O_EXCL)
1731 mce_chrdev_open_exclu = 1;
1732 mce_chrdev_open_count++;
1734 spin_unlock(&mce_chrdev_state_lock);
1736 return nonseekable_open(inode, file);
1739 static int mce_chrdev_release(struct inode *inode, struct file *file)
1741 spin_lock(&mce_chrdev_state_lock);
1743 mce_chrdev_open_count--;
1744 mce_chrdev_open_exclu = 0;
1746 spin_unlock(&mce_chrdev_state_lock);
1751 static void collect_tscs(void *data)
1753 unsigned long *cpu_tsc = (unsigned long *)data;
1755 rdtscll(cpu_tsc[smp_processor_id()]);
1758 static int mce_apei_read_done;
1760 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1761 static int __mce_read_apei(char __user **ubuf, size_t usize)
1767 if (usize < sizeof(struct mce))
1770 rc = apei_read_mce(&m, &record_id);
1771 /* Error or no more MCE record */
1773 mce_apei_read_done = 1;
1775 * When ERST is disabled, mce_chrdev_read() should return
1776 * "no record" instead of "no device."
1783 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1786 * In fact, we should have cleared the record after that has
1787 * been flushed to the disk or sent to network in
1788 * /sbin/mcelog, but we have no interface to support that now,
1789 * so just clear it to avoid duplication.
1791 rc = apei_clear_mce(record_id);
1793 mce_apei_read_done = 1;
1796 *ubuf += sizeof(struct mce);
1801 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1802 size_t usize, loff_t *off)
1804 char __user *buf = ubuf;
1805 unsigned long *cpu_tsc;
1806 unsigned prev, next;
1809 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1813 mutex_lock(&mce_chrdev_read_mutex);
1815 if (!mce_apei_read_done) {
1816 err = __mce_read_apei(&buf, usize);
1817 if (err || buf != ubuf)
1821 next = rcu_dereference_check_mce(mcelog.next);
1823 /* Only supports full reads right now */
1825 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1831 for (i = prev; i < next; i++) {
1832 unsigned long start = jiffies;
1833 struct mce *m = &mcelog.entry[i];
1835 while (!m->finished) {
1836 if (time_after_eq(jiffies, start + 2)) {
1837 memset(m, 0, sizeof(*m));
1843 err |= copy_to_user(buf, m, sizeof(*m));
1849 memset(mcelog.entry + prev, 0,
1850 (next - prev) * sizeof(struct mce));
1852 next = cmpxchg(&mcelog.next, prev, 0);
1853 } while (next != prev);
1855 synchronize_sched();
1858 * Collect entries that were still getting written before the
1861 on_each_cpu(collect_tscs, cpu_tsc, 1);
1863 for (i = next; i < MCE_LOG_LEN; i++) {
1864 struct mce *m = &mcelog.entry[i];
1866 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1867 err |= copy_to_user(buf, m, sizeof(*m));
1870 memset(m, 0, sizeof(*m));
1878 mutex_unlock(&mce_chrdev_read_mutex);
1881 return err ? err : buf - ubuf;
1884 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1886 poll_wait(file, &mce_chrdev_wait, wait);
1887 if (rcu_access_index(mcelog.next))
1888 return POLLIN | POLLRDNORM;
1889 if (!mce_apei_read_done && apei_check_mce())
1890 return POLLIN | POLLRDNORM;
1894 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1897 int __user *p = (int __user *)arg;
1899 if (!capable(CAP_SYS_ADMIN))
1903 case MCE_GET_RECORD_LEN:
1904 return put_user(sizeof(struct mce), p);
1905 case MCE_GET_LOG_LEN:
1906 return put_user(MCE_LOG_LEN, p);
1907 case MCE_GETCLEAR_FLAGS: {
1911 flags = mcelog.flags;
1912 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1914 return put_user(flags, p);
1921 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1922 size_t usize, loff_t *off);
1924 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1925 const char __user *ubuf,
1926 size_t usize, loff_t *off))
1930 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1932 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1933 size_t usize, loff_t *off)
1936 return mce_write(filp, ubuf, usize, off);
1941 static const struct file_operations mce_chrdev_ops = {
1942 .open = mce_chrdev_open,
1943 .release = mce_chrdev_release,
1944 .read = mce_chrdev_read,
1945 .write = mce_chrdev_write,
1946 .poll = mce_chrdev_poll,
1947 .unlocked_ioctl = mce_chrdev_ioctl,
1948 .llseek = no_llseek,
1951 static struct miscdevice mce_chrdev_device = {
1957 static void __mce_disable_bank(void *arg)
1959 int bank = *((int *)arg);
1960 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1961 cmci_disable_bank(bank);
1964 void mce_disable_bank(int bank)
1966 if (bank >= mca_cfg.banks) {
1968 "Ignoring request to disable invalid MCA bank %d.\n",
1972 set_bit(bank, mce_banks_ce_disabled);
1973 on_each_cpu(__mce_disable_bank, &bank, 1);
1977 * mce=off Disables machine check
1978 * mce=no_cmci Disables CMCI
1979 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1980 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1981 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1982 * monarchtimeout is how long to wait for other CPUs on machine
1983 * check, or 0 to not wait
1984 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1985 * mce=nobootlog Don't log MCEs from before booting.
1986 * mce=bios_cmci_threshold Don't program the CMCI threshold
1988 static int __init mcheck_enable(char *str)
1990 struct mca_config *cfg = &mca_cfg;
1998 if (!strcmp(str, "off"))
1999 cfg->disabled = true;
2000 else if (!strcmp(str, "no_cmci"))
2001 cfg->cmci_disabled = true;
2002 else if (!strcmp(str, "dont_log_ce"))
2003 cfg->dont_log_ce = true;
2004 else if (!strcmp(str, "ignore_ce"))
2005 cfg->ignore_ce = true;
2006 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2007 cfg->bootlog = (str[0] == 'b');
2008 else if (!strcmp(str, "bios_cmci_threshold"))
2009 cfg->bios_cmci_threshold = true;
2010 else if (isdigit(str[0])) {
2011 get_option(&str, &(cfg->tolerant));
2014 get_option(&str, &(cfg->monarch_timeout));
2017 pr_info("mce argument %s ignored. Please use /sys\n", str);
2022 __setup("mce", mcheck_enable);
2024 int __init mcheck_init(void)
2026 mcheck_intel_therm_init();
2027 mcheck_vendor_init_severity();
2033 * mce_syscore: PM support
2037 * Disable machine checks on suspend and shutdown. We can't really handle
2040 static int mce_disable_error_reporting(void)
2044 for (i = 0; i < mca_cfg.banks; i++) {
2045 struct mce_bank *b = &mce_banks[i];
2048 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2053 static int mce_syscore_suspend(void)
2055 return mce_disable_error_reporting();
2058 static void mce_syscore_shutdown(void)
2060 mce_disable_error_reporting();
2064 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2065 * Only one CPU is active at this time, the others get re-added later using
2068 static void mce_syscore_resume(void)
2070 __mcheck_cpu_init_generic();
2071 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2074 static struct syscore_ops mce_syscore_ops = {
2075 .suspend = mce_syscore_suspend,
2076 .shutdown = mce_syscore_shutdown,
2077 .resume = mce_syscore_resume,
2081 * mce_device: Sysfs support
2084 static void mce_cpu_restart(void *data)
2086 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2088 __mcheck_cpu_init_generic();
2089 __mcheck_cpu_init_timer();
2092 /* Reinit MCEs after user configuration changes */
2093 static void mce_restart(void)
2095 mce_timer_delete_all();
2096 on_each_cpu(mce_cpu_restart, NULL, 1);
2099 /* Toggle features for corrected errors */
2100 static void mce_disable_cmci(void *data)
2102 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2107 static void mce_enable_ce(void *all)
2109 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2114 __mcheck_cpu_init_timer();
2117 static struct bus_type mce_subsys = {
2118 .name = "machinecheck",
2119 .dev_name = "machinecheck",
2122 DEFINE_PER_CPU(struct device *, mce_device);
2124 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
2126 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2128 return container_of(attr, struct mce_bank, attr);
2131 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2134 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2137 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2138 const char *buf, size_t size)
2142 if (kstrtou64(buf, 0, &new) < 0)
2145 attr_to_bank(attr)->ctl = new;
2152 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2154 strcpy(buf, mce_helper);
2156 return strlen(mce_helper) + 1;
2159 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2160 const char *buf, size_t siz)
2164 strncpy(mce_helper, buf, sizeof(mce_helper));
2165 mce_helper[sizeof(mce_helper)-1] = 0;
2166 p = strchr(mce_helper, '\n');
2171 return strlen(mce_helper) + !!p;
2174 static ssize_t set_ignore_ce(struct device *s,
2175 struct device_attribute *attr,
2176 const char *buf, size_t size)
2180 if (kstrtou64(buf, 0, &new) < 0)
2183 if (mca_cfg.ignore_ce ^ !!new) {
2185 /* disable ce features */
2186 mce_timer_delete_all();
2187 on_each_cpu(mce_disable_cmci, NULL, 1);
2188 mca_cfg.ignore_ce = true;
2190 /* enable ce features */
2191 mca_cfg.ignore_ce = false;
2192 on_each_cpu(mce_enable_ce, (void *)1, 1);
2198 static ssize_t set_cmci_disabled(struct device *s,
2199 struct device_attribute *attr,
2200 const char *buf, size_t size)
2204 if (kstrtou64(buf, 0, &new) < 0)
2207 if (mca_cfg.cmci_disabled ^ !!new) {
2210 on_each_cpu(mce_disable_cmci, NULL, 1);
2211 mca_cfg.cmci_disabled = true;
2214 mca_cfg.cmci_disabled = false;
2215 on_each_cpu(mce_enable_ce, NULL, 1);
2221 static ssize_t store_int_with_restart(struct device *s,
2222 struct device_attribute *attr,
2223 const char *buf, size_t size)
2225 ssize_t ret = device_store_int(s, attr, buf, size);
2230 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2231 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2232 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2233 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2235 static struct dev_ext_attribute dev_attr_check_interval = {
2236 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2240 static struct dev_ext_attribute dev_attr_ignore_ce = {
2241 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2245 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2246 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2247 &mca_cfg.cmci_disabled
2250 static struct device_attribute *mce_device_attrs[] = {
2251 &dev_attr_tolerant.attr,
2252 &dev_attr_check_interval.attr,
2254 &dev_attr_monarch_timeout.attr,
2255 &dev_attr_dont_log_ce.attr,
2256 &dev_attr_ignore_ce.attr,
2257 &dev_attr_cmci_disabled.attr,
2261 static cpumask_var_t mce_device_initialized;
2263 static void mce_device_release(struct device *dev)
2268 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2269 static int mce_device_create(unsigned int cpu)
2275 if (!mce_available(&boot_cpu_data))
2278 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2282 dev->bus = &mce_subsys;
2283 dev->release = &mce_device_release;
2285 err = device_register(dev);
2291 for (i = 0; mce_device_attrs[i]; i++) {
2292 err = device_create_file(dev, mce_device_attrs[i]);
2296 for (j = 0; j < mca_cfg.banks; j++) {
2297 err = device_create_file(dev, &mce_banks[j].attr);
2301 cpumask_set_cpu(cpu, mce_device_initialized);
2302 per_cpu(mce_device, cpu) = dev;
2307 device_remove_file(dev, &mce_banks[j].attr);
2310 device_remove_file(dev, mce_device_attrs[i]);
2312 device_unregister(dev);
2317 static void mce_device_remove(unsigned int cpu)
2319 struct device *dev = per_cpu(mce_device, cpu);
2322 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2325 for (i = 0; mce_device_attrs[i]; i++)
2326 device_remove_file(dev, mce_device_attrs[i]);
2328 for (i = 0; i < mca_cfg.banks; i++)
2329 device_remove_file(dev, &mce_banks[i].attr);
2331 device_unregister(dev);
2332 cpumask_clear_cpu(cpu, mce_device_initialized);
2333 per_cpu(mce_device, cpu) = NULL;
2336 /* Make sure there are no machine checks on offlined CPUs. */
2337 static void mce_disable_cpu(void *h)
2339 unsigned long action = *(unsigned long *)h;
2342 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2345 if (!(action & CPU_TASKS_FROZEN))
2347 for (i = 0; i < mca_cfg.banks; i++) {
2348 struct mce_bank *b = &mce_banks[i];
2351 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2355 static void mce_reenable_cpu(void *h)
2357 unsigned long action = *(unsigned long *)h;
2360 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2363 if (!(action & CPU_TASKS_FROZEN))
2365 for (i = 0; i < mca_cfg.banks; i++) {
2366 struct mce_bank *b = &mce_banks[i];
2369 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2373 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2375 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2377 unsigned int cpu = (unsigned long)hcpu;
2378 struct timer_list *t = &per_cpu(mce_timer, cpu);
2380 switch (action & ~CPU_TASKS_FROZEN) {
2382 mce_device_create(cpu);
2383 if (threshold_cpu_callback)
2384 threshold_cpu_callback(action, cpu);
2387 if (threshold_cpu_callback)
2388 threshold_cpu_callback(action, cpu);
2389 mce_device_remove(cpu);
2390 mce_intel_hcpu_update(cpu);
2392 /* intentionally ignoring frozen here */
2393 if (!(action & CPU_TASKS_FROZEN))
2396 case CPU_DOWN_PREPARE:
2397 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2400 case CPU_DOWN_FAILED:
2401 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2402 mce_start_timer(cpu, t);
2409 static struct notifier_block mce_cpu_notifier = {
2410 .notifier_call = mce_cpu_callback,
2413 static __init void mce_init_banks(void)
2417 for (i = 0; i < mca_cfg.banks; i++) {
2418 struct mce_bank *b = &mce_banks[i];
2419 struct device_attribute *a = &b->attr;
2421 sysfs_attr_init(&a->attr);
2422 a->attr.name = b->attrname;
2423 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2425 a->attr.mode = 0644;
2426 a->show = show_bank;
2427 a->store = set_bank;
2431 static __init int mcheck_init_device(void)
2436 if (!mce_available(&boot_cpu_data)) {
2441 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2448 err = subsys_system_register(&mce_subsys, NULL);
2452 cpu_notifier_register_begin();
2453 for_each_online_cpu(i) {
2454 err = mce_device_create(i);
2457 * Register notifier anyway (and do not unreg it) so
2458 * that we don't leave undeleted timers, see notifier
2461 __register_hotcpu_notifier(&mce_cpu_notifier);
2462 cpu_notifier_register_done();
2463 goto err_device_create;
2467 __register_hotcpu_notifier(&mce_cpu_notifier);
2468 cpu_notifier_register_done();
2470 register_syscore_ops(&mce_syscore_ops);
2472 /* register character device /dev/mcelog */
2473 err = misc_register(&mce_chrdev_device);
2480 unregister_syscore_ops(&mce_syscore_ops);
2484 * We didn't keep track of which devices were created above, but
2485 * even if we had, the set of online cpus might have changed.
2486 * Play safe and remove for every possible cpu, since
2487 * mce_device_remove() will do the right thing.
2489 for_each_possible_cpu(i)
2490 mce_device_remove(i);
2493 free_cpumask_var(mce_device_initialized);
2496 pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err);
2500 device_initcall_sync(mcheck_init_device);
2503 * Old style boot options parsing. Only for compatibility.
2505 static int __init mcheck_disable(char *str)
2507 mca_cfg.disabled = true;
2510 __setup("nomce", mcheck_disable);
2512 #ifdef CONFIG_DEBUG_FS
2513 struct dentry *mce_get_debugfs_dir(void)
2515 static struct dentry *dmce;
2518 dmce = debugfs_create_dir("mce", NULL);
2523 static void mce_reset(void)
2526 atomic_set(&mce_fake_panicked, 0);
2527 atomic_set(&mce_executing, 0);
2528 atomic_set(&mce_callin, 0);
2529 atomic_set(&global_nwo, 0);
2532 static int fake_panic_get(void *data, u64 *val)
2538 static int fake_panic_set(void *data, u64 val)
2545 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2546 fake_panic_set, "%llu\n");
2548 static int __init mcheck_debugfs_init(void)
2550 struct dentry *dmce, *ffake_panic;
2552 dmce = mce_get_debugfs_dir();
2555 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2562 late_initcall(mcheck_debugfs_init);