1 #include <linux/kernel.h>
3 #include <linux/string.h>
4 #include <linux/bitops.h>
6 #include <linux/sched.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9 #include <linux/uaccess.h>
11 #include <asm/processor.h>
12 #include <asm/pgtable.h>
18 #include <linux/topology.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
28 static void early_init_intel(struct cpuinfo_x86 *c)
32 /* Unmask CPUID levels if masked: */
33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
36 c->cpuid_level = cpuid_eax(0);
41 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
42 (c->x86 == 0x6 && c->x86_model >= 0x0e))
43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
48 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
49 /* Required by the SDM */
51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
55 * Atom erratum AAE44/AAF40/AAG38/AAH41:
57 * A race condition between speculative fetches and invalidating
58 * a large page. This is worked around in microcode, but we
59 * need the microcode to have already been loaded... so if it is
60 * not, recommend a BIOS update and disable large pages.
62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
63 c->microcode < 0x20e) {
64 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
65 clear_cpu_cap(c, X86_FEATURE_PSE);
69 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
72 if (c->x86 == 15 && c->x86_cache_alignment == 64)
73 c->x86_cache_alignment = 128;
76 /* CPUID workaround for 0F33/0F34 CPU */
77 if (c->x86 == 0xF && c->x86_model == 0x3
78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
79 c->x86_phys_bits = 36;
82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83 * with P/T states and does not stop in deep C-states.
85 * It is also reliable across cores and sockets. (but not across
86 * cabinets - we turn it off in that case explicitly.)
88 if (c->x86_power & (1 << 8)) {
89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
91 if (!check_tsc_unstable())
92 set_sched_clock_stable();
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
97 switch (c->x86_model) {
98 case 0x27: /* Penwell */
99 case 0x35: /* Cloverview */
100 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
108 * There is a known erratum on Pentium III and Core Solo
110 * " Page with PAT set to WC while associated MTRR is UC
111 * may consolidate to UC "
112 * Because of this erratum, it is better to stick with
113 * setting WC in MTRR rather than using PAT on these CPUs.
115 * Enable PAT WC only on P4, Core 2 or later CPUs.
117 if (c->x86 == 6 && c->x86_model < 15)
118 clear_cpu_cap(c, X86_FEATURE_PAT);
120 #ifdef CONFIG_KMEMCHECK
122 * P4s have a "fast strings" feature which causes single-
123 * stepping REP instructions to only generate a #DB on
124 * cache-line boundaries.
126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
127 * (model 2) with the same problem.
130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
132 pr_info("kmemcheck: Disabling fast string operations\n");
136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
137 * clear the fast string and enhanced fast string CPU capabilities.
139 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
141 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
142 printk(KERN_INFO "Disabled fast string operations\n");
143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
144 setup_clear_cpu_cap(X86_FEATURE_ERMS);
149 * Intel Quark Core DevMan_001.pdf section 6.4.11
150 * "The operating system also is required to invalidate (i.e., flush)
151 * the TLB when any changes are made to any of the page table entries.
152 * The operating system must reload CR3 to cause the TLB to be flushed"
154 * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
155 * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
158 if (c->x86 == 5 && c->x86_model == 9) {
159 pr_info("Disabling PGE capability bit\n");
160 setup_clear_cpu_cap(X86_FEATURE_PGE);
166 * Early probe support logic for ppro memory erratum #50
168 * This is called before we do cpu ident work
171 int ppro_with_ram_bug(void)
173 /* Uses data from early_cpu_detect now */
174 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
175 boot_cpu_data.x86 == 6 &&
176 boot_cpu_data.x86_model == 1 &&
177 boot_cpu_data.x86_mask < 8) {
178 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
184 static void intel_smp_check(struct cpuinfo_x86 *c)
186 /* calling is from identify_secondary_cpu() ? */
191 * Mask B, Pentium, but not Pentium MMX
194 c->x86_mask >= 1 && c->x86_mask <= 4 &&
197 * Remember we have B step Pentia with bugs
199 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
200 "with B stepping processors.\n");
205 static int __init forcepae_setup(char *__unused)
210 __setup("forcepae", forcepae_setup);
212 static void intel_workarounds(struct cpuinfo_x86 *c)
214 #ifdef CONFIG_X86_F00F_BUG
216 * All current models of Pentium and Pentium with MMX technology CPUs
217 * have the F0 0F bug, which lets nonprivileged users lock up the
218 * system. Announce that the fault handler will be checking for it.
220 clear_cpu_bug(c, X86_BUG_F00F);
221 if (!paravirt_enabled() && c->x86 == 5) {
222 static int f00f_workaround_enabled;
224 set_cpu_bug(c, X86_BUG_F00F);
225 if (!f00f_workaround_enabled) {
226 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
227 f00f_workaround_enabled = 1;
233 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
236 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
237 clear_cpu_cap(c, X86_FEATURE_SEP);
240 * PAE CPUID issue: many Pentium M report no PAE but may have a
241 * functionally usable PAE implementation.
242 * Forcefully enable PAE if kernel parameter "forcepae" is present.
245 printk(KERN_WARNING "PAE forced!\n");
246 set_cpu_cap(c, X86_FEATURE_PAE);
247 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
251 * P4 Xeon errata 037 workaround.
252 * Hardware prefetcher may cause stale data to be loaded into the cache.
254 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
255 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
256 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
258 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
259 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
264 * See if we have a good local APIC by checking for buggy Pentia,
265 * i.e. all B steppings and the C2 stepping of P54C when using their
266 * integrated APIC (see 11AP erratum in "Pentium Processor
267 * Specification Update").
269 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
270 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
271 set_cpu_bug(c, X86_BUG_11AP);
274 #ifdef CONFIG_X86_INTEL_USERCOPY
276 * Set up the preferred alignment for movsl bulk memory moves
279 case 4: /* 486: untested */
281 case 5: /* Old Pentia: untested */
283 case 6: /* PII/PIII only like movsl with 8-byte alignment */
286 case 15: /* P4 is OK down to 8-byte alignment */
295 static void intel_workarounds(struct cpuinfo_x86 *c)
300 static void srat_detect_node(struct cpuinfo_x86 *c)
304 int cpu = smp_processor_id();
306 /* Don't do the funky fallback heuristics the AMD version employs
308 node = numa_cpu_node(cpu);
309 if (node == NUMA_NO_NODE || !node_online(node)) {
310 /* reuse the value from init_cpu_to_node() */
311 node = cpu_to_node(cpu);
313 numa_set_node(cpu, node);
318 * find out the number of processor cores on the die
320 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
322 unsigned int eax, ebx, ecx, edx;
324 if (c->cpuid_level < 4)
327 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
328 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
330 return (eax >> 26) + 1;
335 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
337 /* Intel VMX MSR indicated features */
338 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
339 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
340 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
341 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
342 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
343 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
345 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
347 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
348 clear_cpu_cap(c, X86_FEATURE_VNMI);
349 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
350 clear_cpu_cap(c, X86_FEATURE_EPT);
351 clear_cpu_cap(c, X86_FEATURE_VPID);
353 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
354 msr_ctl = vmx_msr_high | vmx_msr_low;
355 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
356 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
357 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
358 set_cpu_cap(c, X86_FEATURE_VNMI);
359 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
360 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
361 vmx_msr_low, vmx_msr_high);
362 msr_ctl2 = vmx_msr_high | vmx_msr_low;
363 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
364 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
365 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
366 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
367 set_cpu_cap(c, X86_FEATURE_EPT);
368 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
369 set_cpu_cap(c, X86_FEATURE_VPID);
373 static void init_intel(struct cpuinfo_x86 *c)
379 intel_workarounds(c);
382 * Detect the extended topology information if available. This
383 * will reinitialise the initial_apicid which will be used
384 * in init_intel_cacheinfo()
386 detect_extended_topology(c);
388 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
390 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
393 c->x86_max_cores = intel_num_cpu_cores(c);
399 l2 = init_intel_cacheinfo(c);
401 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
403 cpu_detect_cache_sizes(c);
404 l2 = c->x86_cache_size;
407 if (c->cpuid_level > 9) {
408 unsigned eax = cpuid_eax(10);
409 /* Check for version and the number of counters */
410 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
411 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
415 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
418 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
420 set_cpu_cap(c, X86_FEATURE_BTS);
422 set_cpu_cap(c, X86_FEATURE_PEBS);
425 if (c->x86 == 6 && cpu_has_clflush &&
426 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
427 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
431 c->x86_cache_alignment = c->x86_clflush_size * 2;
433 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
436 * Names for the Pentium II/Celeron processors
437 * detectable only by also checking the cache size.
438 * Dixon is NOT a Celeron.
443 switch (c->x86_model) {
446 p = "Celeron (Covington)";
448 p = "Mobile Pentium II (Dixon)";
453 p = "Celeron (Mendocino)";
454 else if (c->x86_mask == 0 || c->x86_mask == 5)
460 p = "Celeron (Coppermine)";
465 strcpy(c->x86_model_id, p);
469 set_cpu_cap(c, X86_FEATURE_P4);
471 set_cpu_cap(c, X86_FEATURE_P3);
474 /* Work around errata */
477 if (cpu_has(c, X86_FEATURE_VMX))
478 detect_vmx_virtcap(c);
481 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
482 * x86_energy_perf_policy(8) is available to change it at run-time
484 if (cpu_has(c, X86_FEATURE_EPB)) {
487 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
488 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
489 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
490 " Set to 'normal', was 'performance'\n"
491 "ENERGY_PERF_BIAS: View and update with"
492 " x86_energy_perf_policy(8)\n");
493 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
494 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
500 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
503 * Intel PIII Tualatin. This comes in two flavours.
504 * One has 256kb of cache, the other 512. We have no way
505 * to determine which, so we use a boottime override
506 * for the 512kb model, and assume 256 otherwise.
508 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
512 * Intel Quark SoC X1000 contains a 4-way set associative
513 * 16K cache with a 16 byte cache line and 256 lines per tag
515 if ((c->x86 == 5) && (c->x86_model == 9))
521 #define TLB_INST_4K 0x01
522 #define TLB_INST_4M 0x02
523 #define TLB_INST_2M_4M 0x03
525 #define TLB_INST_ALL 0x05
526 #define TLB_INST_1G 0x06
528 #define TLB_DATA_4K 0x11
529 #define TLB_DATA_4M 0x12
530 #define TLB_DATA_2M_4M 0x13
531 #define TLB_DATA_4K_4M 0x14
533 #define TLB_DATA_1G 0x16
535 #define TLB_DATA0_4K 0x21
536 #define TLB_DATA0_4M 0x22
537 #define TLB_DATA0_2M_4M 0x23
540 #define STLB_4K_2M 0x42
542 static const struct _tlb_table intel_tlb_table[] = {
543 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
544 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
545 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
546 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
547 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
548 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
549 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
550 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
551 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
552 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
553 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
554 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
555 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
556 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
557 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
558 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
559 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
560 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
561 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
562 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
563 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
564 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
565 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
566 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
567 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
568 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
569 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
570 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
571 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
572 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
573 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
574 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
575 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
579 static void intel_tlb_lookup(const unsigned char desc)
585 /* look up this descriptor in the table */
586 for (k = 0; intel_tlb_table[k].descriptor != desc && \
587 intel_tlb_table[k].descriptor != 0; k++)
590 if (intel_tlb_table[k].tlb_type == 0)
593 switch (intel_tlb_table[k].tlb_type) {
595 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
596 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
597 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
598 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
601 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
602 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
603 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
604 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
605 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
606 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
607 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
608 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
609 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
610 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
611 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
612 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
615 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
616 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
617 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
618 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
619 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
620 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
623 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
624 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
627 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
628 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
631 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
632 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
633 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
634 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
638 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
639 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
643 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
644 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
647 case TLB_DATA0_2M_4M:
648 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
649 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
650 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
651 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
654 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
655 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
656 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
657 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
660 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
661 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
666 static void intel_detect_tlb(struct cpuinfo_x86 *c)
669 unsigned int regs[4];
670 unsigned char *desc = (unsigned char *)regs;
672 if (c->cpuid_level < 2)
675 /* Number of times to iterate */
676 n = cpuid_eax(2) & 0xFF;
678 for (i = 0 ; i < n ; i++) {
679 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
681 /* If bit 31 is set, this is an unknown format */
682 for (j = 0 ; j < 3 ; j++)
683 if (regs[j] & (1 << 31))
686 /* Byte 0 is level count, not a descriptor */
687 for (j = 1 ; j < 16 ; j++)
688 intel_tlb_lookup(desc[j]);
692 static const struct cpu_dev intel_cpu_dev = {
694 .c_ident = { "GenuineIntel" },
697 { .family = 4, .model_names =
699 [0] = "486 DX-25/33",
710 { .family = 5, .model_names =
712 [0] = "Pentium 60/66 A-step",
713 [1] = "Pentium 60/66",
714 [2] = "Pentium 75 - 200",
715 [3] = "OverDrive PODP5V83",
717 [7] = "Mobile Pentium 75 - 200",
718 [8] = "Mobile Pentium MMX",
719 [9] = "Quark SoC X1000",
722 { .family = 6, .model_names =
724 [0] = "Pentium Pro A-step",
726 [3] = "Pentium II (Klamath)",
727 [4] = "Pentium II (Deschutes)",
728 [5] = "Pentium II (Deschutes)",
729 [6] = "Mobile Pentium II",
730 [7] = "Pentium III (Katmai)",
731 [8] = "Pentium III (Coppermine)",
732 [10] = "Pentium III (Cascades)",
733 [11] = "Pentium III (Tualatin)",
736 { .family = 15, .model_names =
738 [0] = "Pentium 4 (Unknown)",
739 [1] = "Pentium 4 (Willamette)",
740 [2] = "Pentium 4 (Northwood)",
741 [4] = "Pentium 4 (Foster)",
742 [5] = "Pentium 4 (Foster)",
746 .legacy_cache_size = intel_size_cache,
748 .c_detect_tlb = intel_detect_tlb,
749 .c_early_init = early_init_intel,
750 .c_init = init_intel,
751 .c_x86_vendor = X86_VENDOR_INTEL,
754 cpu_dev_register(intel_cpu_dev);