2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/slab.h>
17 #include <asm/irqdomain.h>
18 #include <asm/hw_irq.h>
20 #include <asm/i8259.h>
22 #include <asm/irq_remapping.h>
24 struct apic_chip_data {
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
31 struct irq_domain *x86_vector_domain;
32 static DEFINE_RAW_SPINLOCK(vector_lock);
33 static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
34 static struct irq_chip lapic_controller;
35 #ifdef CONFIG_X86_IO_APIC
36 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
39 void lock_vector_lock(void)
41 /* Used to the online set of cpus does not change
42 * during assign_irq_vector.
44 raw_spin_lock(&vector_lock);
47 void unlock_vector_lock(void)
49 raw_spin_unlock(&vector_lock);
52 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
57 while (irq_data->parent_data)
58 irq_data = irq_data->parent_data;
60 return irq_data->chip_data;
63 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
65 struct apic_chip_data *data = apic_chip_data(irq_data);
67 return data ? &data->cfg : NULL;
70 struct irq_cfg *irq_cfg(unsigned int irq)
72 return irqd_cfg(irq_get_irq_data(irq));
75 static struct apic_chip_data *alloc_apic_chip_data(int node)
77 struct apic_chip_data *data;
79 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
84 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
88 free_cpumask_var(data->domain);
94 static void free_apic_chip_data(struct apic_chip_data *data)
97 free_cpumask_var(data->domain);
98 free_cpumask_var(data->old_domain);
103 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
104 const struct cpumask *mask)
107 * NOTE! The local APIC isn't very good at handling
108 * multiple interrupts at the same interrupt level.
109 * As the interrupt level is determined by taking the
110 * vector number and shifting that right by 4, we
111 * want to spread these out a bit so that they don't
112 * all fall in the same interrupt level.
114 * Also, we've got to be careful not to trash gate
115 * 0x80, because int 0x80 is hm, kind of importantish. ;)
117 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
118 static int current_offset = VECTOR_OFFSET_START % 16;
121 if (d->move_in_progress)
124 /* Only try and allocate irqs on cpus that are present */
125 cpumask_clear(d->old_domain);
126 cpumask_clear(searched_cpumask);
127 cpu = cpumask_first_and(mask, cpu_online_mask);
128 while (cpu < nr_cpu_ids) {
131 /* Get the possible target cpus for @mask/@cpu from the apic */
132 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
135 * Clear the offline cpus from @vector_cpumask for searching
136 * and verify whether the result overlaps with @mask. If true,
137 * then the call to apic->cpu_mask_to_apicid_and() will
138 * succeed as well. If not, no point in trying to find a
139 * vector in this mask.
141 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
142 if (!cpumask_intersects(vector_searchmask, mask))
145 if (cpumask_subset(vector_cpumask, d->domain)) {
146 if (cpumask_equal(vector_cpumask, d->domain))
149 * Mark the cpus which are not longer in the mask for
152 cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
153 vector = d->cfg.vector;
157 vector = current_vector;
158 offset = current_offset;
161 if (vector >= first_system_vector) {
162 offset = (offset + 1) % 16;
163 vector = FIRST_EXTERNAL_VECTOR + offset;
166 /* If the search wrapped around, try the next cpu */
167 if (unlikely(current_vector == vector))
170 if (test_bit(vector, used_vectors))
173 for_each_cpu(new_cpu, vector_searchmask) {
174 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
178 current_vector = vector;
179 current_offset = offset;
180 /* Schedule the old vector for cleanup on all cpus */
182 cpumask_copy(d->old_domain, d->domain);
183 for_each_cpu(new_cpu, vector_searchmask)
184 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
189 * We exclude the current @vector_cpumask from the requested
190 * @mask and try again with the next online cpu in the
191 * result. We cannot modify @mask, so we use @vector_cpumask
192 * as a temporary buffer here as it will be reassigned when
193 * calling apic->vector_allocation_domain() above.
195 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
196 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
197 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
203 /* Cleanup required ? */
204 d->move_in_progress = cpumask_intersects(d->old_domain, cpu_online_mask);
205 d->cfg.vector = vector;
206 cpumask_copy(d->domain, vector_cpumask);
209 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
210 * as we already established, that mask & d->domain & cpu_online_mask
213 BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
214 &d->cfg.dest_apicid));
218 static int assign_irq_vector(int irq, struct apic_chip_data *data,
219 const struct cpumask *mask)
224 raw_spin_lock_irqsave(&vector_lock, flags);
225 err = __assign_irq_vector(irq, data, mask);
226 raw_spin_unlock_irqrestore(&vector_lock, flags);
230 static int assign_irq_vector_policy(int irq, int node,
231 struct apic_chip_data *data,
232 struct irq_alloc_info *info)
234 if (info && info->mask)
235 return assign_irq_vector(irq, data, info->mask);
236 if (node != NUMA_NO_NODE &&
237 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
239 return assign_irq_vector(irq, data, apic->target_cpus());
242 static void clear_irq_vector(int irq, struct apic_chip_data *data)
244 struct irq_desc *desc;
247 BUG_ON(!data->cfg.vector);
249 vector = data->cfg.vector;
250 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
251 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
253 data->cfg.vector = 0;
254 cpumask_clear(data->domain);
256 if (likely(!data->move_in_progress))
259 desc = irq_to_desc(irq);
260 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
261 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
263 if (per_cpu(vector_irq, cpu)[vector] != desc)
265 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
269 data->move_in_progress = 0;
272 void init_irq_alloc_info(struct irq_alloc_info *info,
273 const struct cpumask *mask)
275 memset(info, 0, sizeof(*info));
279 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
284 memset(dst, 0, sizeof(*dst));
287 static void x86_vector_free_irqs(struct irq_domain *domain,
288 unsigned int virq, unsigned int nr_irqs)
290 struct apic_chip_data *apic_data;
291 struct irq_data *irq_data;
295 for (i = 0; i < nr_irqs; i++) {
296 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
297 if (irq_data && irq_data->chip_data) {
298 raw_spin_lock_irqsave(&vector_lock, flags);
299 clear_irq_vector(virq + i, irq_data->chip_data);
300 apic_data = irq_data->chip_data;
301 irq_domain_reset_irq_data(irq_data);
302 raw_spin_unlock_irqrestore(&vector_lock, flags);
303 free_apic_chip_data(apic_data);
304 #ifdef CONFIG_X86_IO_APIC
305 if (virq + i < nr_legacy_irqs())
306 legacy_irq_data[virq + i] = NULL;
312 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
313 unsigned int nr_irqs, void *arg)
315 struct irq_alloc_info *info = arg;
316 struct apic_chip_data *data;
317 struct irq_data *irq_data;
323 /* Currently vector allocator can't guarantee contiguous allocations */
324 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
327 for (i = 0; i < nr_irqs; i++) {
328 irq_data = irq_domain_get_irq_data(domain, virq + i);
330 node = irq_data_get_node(irq_data);
331 #ifdef CONFIG_X86_IO_APIC
332 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
333 data = legacy_irq_data[virq + i];
336 data = alloc_apic_chip_data(node);
342 irq_data->chip = &lapic_controller;
343 irq_data->chip_data = data;
344 irq_data->hwirq = virq + i;
345 err = assign_irq_vector_policy(virq + i, node, data, info);
353 x86_vector_free_irqs(domain, virq, i + 1);
357 static const struct irq_domain_ops x86_vector_domain_ops = {
358 .alloc = x86_vector_alloc_irqs,
359 .free = x86_vector_free_irqs,
362 int __init arch_probe_nr_irqs(void)
366 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
367 nr_irqs = NR_VECTORS * nr_cpu_ids;
369 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
370 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
372 * for MSI and HT dyn irq
374 if (gsi_top <= NR_IRQS_LEGACY)
375 nr += 8 * nr_cpu_ids;
383 * We don't know if PIC is present at this point so we need to do
384 * probe() to get the right number of legacy IRQs.
386 return legacy_pic->probe();
389 #ifdef CONFIG_X86_IO_APIC
390 static void init_legacy_irqs(void)
392 int i, node = cpu_to_node(0);
393 struct apic_chip_data *data;
396 * For legacy IRQ's, start with assigning irq0 to irq15 to
397 * ISA_IRQ_VECTOR(i) for all cpu's.
399 for (i = 0; i < nr_legacy_irqs(); i++) {
400 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
403 data->cfg.vector = ISA_IRQ_VECTOR(i);
404 cpumask_setall(data->domain);
405 irq_set_chip_data(i, data);
409 static void init_legacy_irqs(void) { }
412 int __init arch_early_irq_init(void)
416 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
418 BUG_ON(x86_vector_domain == NULL);
419 irq_set_default_host(x86_vector_domain);
421 arch_init_msi_domain(x86_vector_domain);
422 arch_init_htirq_domain(x86_vector_domain);
424 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
425 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
426 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
428 return arch_early_ioapic_init();
431 /* Initialize vector_irq on a new cpu */
432 static void __setup_vector_irq(int cpu)
434 struct apic_chip_data *data;
435 struct irq_desc *desc;
438 /* Mark the inuse vectors */
439 for_each_irq_desc(irq, desc) {
440 struct irq_data *idata = irq_desc_get_irq_data(desc);
442 data = apic_chip_data(idata);
443 if (!data || !cpumask_test_cpu(cpu, data->domain))
445 vector = data->cfg.vector;
446 per_cpu(vector_irq, cpu)[vector] = desc;
448 /* Mark the free vectors */
449 for (vector = 0; vector < NR_VECTORS; ++vector) {
450 desc = per_cpu(vector_irq, cpu)[vector];
451 if (IS_ERR_OR_NULL(desc))
454 data = apic_chip_data(irq_desc_get_irq_data(desc));
455 if (!cpumask_test_cpu(cpu, data->domain))
456 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
461 * Setup the vector to irq mappings. Must be called with vector_lock held.
463 void setup_vector_irq(int cpu)
467 lockdep_assert_held(&vector_lock);
469 * On most of the platforms, legacy PIC delivers the interrupts on the
470 * boot cpu. But there are certain platforms where PIC interrupts are
471 * delivered to multiple cpu's. If the legacy IRQ is handled by the
472 * legacy PIC, for the new cpu that is coming online, setup the static
473 * legacy vector to irq mapping:
475 for (irq = 0; irq < nr_legacy_irqs(); irq++)
476 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
478 __setup_vector_irq(cpu);
481 static int apic_retrigger_irq(struct irq_data *irq_data)
483 struct apic_chip_data *data = apic_chip_data(irq_data);
487 raw_spin_lock_irqsave(&vector_lock, flags);
488 cpu = cpumask_first_and(data->domain, cpu_online_mask);
489 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
490 raw_spin_unlock_irqrestore(&vector_lock, flags);
495 void apic_ack_edge(struct irq_data *data)
497 irq_complete_move(irqd_cfg(data));
502 static int apic_set_affinity(struct irq_data *irq_data,
503 const struct cpumask *dest, bool force)
505 struct apic_chip_data *data = irq_data->chip_data;
506 int err, irq = irq_data->irq;
508 if (!config_enabled(CONFIG_SMP))
511 if (!cpumask_intersects(dest, cpu_online_mask))
514 err = assign_irq_vector(irq, data, dest);
515 return err ? err : IRQ_SET_MASK_OK;
518 static struct irq_chip lapic_controller = {
519 .irq_ack = apic_ack_edge,
520 .irq_set_affinity = apic_set_affinity,
521 .irq_retrigger = apic_retrigger_irq,
525 static void __send_cleanup_vector(struct apic_chip_data *data)
527 cpumask_var_t cleanup_mask;
529 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
532 for_each_cpu_and(i, data->old_domain, cpu_online_mask)
533 apic->send_IPI_mask(cpumask_of(i),
534 IRQ_MOVE_CLEANUP_VECTOR);
536 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
537 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
538 free_cpumask_var(cleanup_mask);
540 data->move_in_progress = 0;
543 void send_cleanup_vector(struct irq_cfg *cfg)
545 struct apic_chip_data *data;
547 data = container_of(cfg, struct apic_chip_data, cfg);
548 if (data->move_in_progress)
549 __send_cleanup_vector(data);
552 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
558 /* Prevent vectors vanishing under us */
559 raw_spin_lock(&vector_lock);
561 me = smp_processor_id();
562 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
563 struct apic_chip_data *data;
564 struct irq_desc *desc;
568 desc = __this_cpu_read(vector_irq[vector]);
569 if (IS_ERR_OR_NULL(desc))
572 if (!raw_spin_trylock(&desc->lock)) {
573 raw_spin_unlock(&vector_lock);
575 raw_spin_lock(&vector_lock);
579 data = apic_chip_data(irq_desc_get_irq_data(desc));
584 * Check if the irq migration is in progress. If so, we
585 * haven't received the cleanup request yet for this irq.
587 if (data->move_in_progress)
590 if (vector == data->cfg.vector &&
591 cpumask_test_cpu(me, data->domain))
594 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
596 * Check if the vector that needs to be cleanedup is
597 * registered at the cpu's IRR. If so, then this is not
598 * the best time to clean it up. Lets clean it up in the
599 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
602 if (irr & (1 << (vector % 32))) {
603 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
606 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
608 raw_spin_unlock(&desc->lock);
611 raw_spin_unlock(&vector_lock);
616 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
619 struct apic_chip_data *data;
621 data = container_of(cfg, struct apic_chip_data, cfg);
622 if (likely(!data->move_in_progress))
625 me = smp_processor_id();
626 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
627 __send_cleanup_vector(data);
630 void irq_complete_move(struct irq_cfg *cfg)
632 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
635 void irq_force_complete_move(int irq)
637 struct irq_cfg *cfg = irq_cfg(irq);
640 __irq_complete_move(cfg, cfg->vector);
644 static void __init print_APIC_field(int base)
650 for (i = 0; i < 8; i++)
651 pr_cont("%08x", apic_read(base + i*0x10));
656 static void __init print_local_APIC(void *dummy)
658 unsigned int i, v, ver, maxlvt;
661 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
662 smp_processor_id(), hard_smp_processor_id());
663 v = apic_read(APIC_ID);
664 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
665 v = apic_read(APIC_LVR);
666 pr_info("... APIC VERSION: %08x\n", v);
667 ver = GET_APIC_VERSION(v);
668 maxlvt = lapic_get_maxlvt();
670 v = apic_read(APIC_TASKPRI);
671 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
674 if (APIC_INTEGRATED(ver)) {
675 if (!APIC_XAPIC(ver)) {
676 v = apic_read(APIC_ARBPRI);
677 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
678 v, v & APIC_ARBPRI_MASK);
680 v = apic_read(APIC_PROCPRI);
681 pr_debug("... APIC PROCPRI: %08x\n", v);
685 * Remote read supported only in the 82489DX and local APIC for
686 * Pentium processors.
688 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
689 v = apic_read(APIC_RRR);
690 pr_debug("... APIC RRR: %08x\n", v);
693 v = apic_read(APIC_LDR);
694 pr_debug("... APIC LDR: %08x\n", v);
695 if (!x2apic_enabled()) {
696 v = apic_read(APIC_DFR);
697 pr_debug("... APIC DFR: %08x\n", v);
699 v = apic_read(APIC_SPIV);
700 pr_debug("... APIC SPIV: %08x\n", v);
702 pr_debug("... APIC ISR field:\n");
703 print_APIC_field(APIC_ISR);
704 pr_debug("... APIC TMR field:\n");
705 print_APIC_field(APIC_TMR);
706 pr_debug("... APIC IRR field:\n");
707 print_APIC_field(APIC_IRR);
710 if (APIC_INTEGRATED(ver)) {
711 /* Due to the Pentium erratum 3AP. */
713 apic_write(APIC_ESR, 0);
715 v = apic_read(APIC_ESR);
716 pr_debug("... APIC ESR: %08x\n", v);
719 icr = apic_icr_read();
720 pr_debug("... APIC ICR: %08x\n", (u32)icr);
721 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
723 v = apic_read(APIC_LVTT);
724 pr_debug("... APIC LVTT: %08x\n", v);
728 v = apic_read(APIC_LVTPC);
729 pr_debug("... APIC LVTPC: %08x\n", v);
731 v = apic_read(APIC_LVT0);
732 pr_debug("... APIC LVT0: %08x\n", v);
733 v = apic_read(APIC_LVT1);
734 pr_debug("... APIC LVT1: %08x\n", v);
738 v = apic_read(APIC_LVTERR);
739 pr_debug("... APIC LVTERR: %08x\n", v);
742 v = apic_read(APIC_TMICT);
743 pr_debug("... APIC TMICT: %08x\n", v);
744 v = apic_read(APIC_TMCCT);
745 pr_debug("... APIC TMCCT: %08x\n", v);
746 v = apic_read(APIC_TDCR);
747 pr_debug("... APIC TDCR: %08x\n", v);
749 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
750 v = apic_read(APIC_EFEAT);
751 maxlvt = (v >> 16) & 0xff;
752 pr_debug("... APIC EFEAT: %08x\n", v);
753 v = apic_read(APIC_ECTRL);
754 pr_debug("... APIC ECTRL: %08x\n", v);
755 for (i = 0; i < maxlvt; i++) {
756 v = apic_read(APIC_EILVTn(i));
757 pr_debug("... APIC EILVT%d: %08x\n", i, v);
763 static void __init print_local_APICs(int maxcpu)
771 for_each_online_cpu(cpu) {
774 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
779 static void __init print_PIC(void)
784 if (!nr_legacy_irqs())
787 pr_debug("\nprinting PIC contents\n");
789 raw_spin_lock_irqsave(&i8259A_lock, flags);
791 v = inb(0xa1) << 8 | inb(0x21);
792 pr_debug("... PIC IMR: %04x\n", v);
794 v = inb(0xa0) << 8 | inb(0x20);
795 pr_debug("... PIC IRR: %04x\n", v);
799 v = inb(0xa0) << 8 | inb(0x20);
803 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
805 pr_debug("... PIC ISR: %04x\n", v);
807 v = inb(0x4d1) << 8 | inb(0x4d0);
808 pr_debug("... PIC ELCR: %04x\n", v);
811 static int show_lapic __initdata = 1;
812 static __init int setup_show_lapic(char *arg)
816 if (strcmp(arg, "all") == 0) {
817 show_lapic = CONFIG_NR_CPUS;
819 get_option(&arg, &num);
826 __setup("show_lapic=", setup_show_lapic);
828 static int __init print_ICs(void)
830 if (apic_verbosity == APIC_QUIET)
835 /* don't print out if apic is not there */
836 if (!cpu_has_apic && !apic_from_smp_config())
839 print_local_APICs(show_lapic);
845 late_initcall(print_ICs);