2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/slab.h>
17 #include <asm/irqdomain.h>
18 #include <asm/hw_irq.h>
20 #include <asm/i8259.h>
22 #include <asm/irq_remapping.h>
24 struct apic_chip_data {
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
31 struct irq_domain *x86_vector_domain;
32 static DEFINE_RAW_SPINLOCK(vector_lock);
33 static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
34 static struct irq_chip lapic_controller;
35 #ifdef CONFIG_X86_IO_APIC
36 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
39 void lock_vector_lock(void)
41 /* Used to the online set of cpus does not change
42 * during assign_irq_vector.
44 raw_spin_lock(&vector_lock);
47 void unlock_vector_lock(void)
49 raw_spin_unlock(&vector_lock);
52 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
57 while (irq_data->parent_data)
58 irq_data = irq_data->parent_data;
60 return irq_data->chip_data;
63 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
65 struct apic_chip_data *data = apic_chip_data(irq_data);
67 return data ? &data->cfg : NULL;
70 struct irq_cfg *irq_cfg(unsigned int irq)
72 return irqd_cfg(irq_get_irq_data(irq));
75 static struct apic_chip_data *alloc_apic_chip_data(int node)
77 struct apic_chip_data *data;
79 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
84 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
88 free_cpumask_var(data->domain);
94 static void free_apic_chip_data(struct apic_chip_data *data)
97 free_cpumask_var(data->domain);
98 free_cpumask_var(data->old_domain);
103 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
104 const struct cpumask *mask)
107 * NOTE! The local APIC isn't very good at handling
108 * multiple interrupts at the same interrupt level.
109 * As the interrupt level is determined by taking the
110 * vector number and shifting that right by 4, we
111 * want to spread these out a bit so that they don't
112 * all fall in the same interrupt level.
114 * Also, we've got to be careful not to trash gate
115 * 0x80, because int 0x80 is hm, kind of importantish. ;)
117 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
118 static int current_offset = VECTOR_OFFSET_START % 16;
122 * If there is still a move in progress or the previous move has not
123 * been cleaned up completely, tell the caller to come back later.
125 if (d->move_in_progress ||
126 cpumask_intersects(d->old_domain, cpu_online_mask))
129 /* Only try and allocate irqs on cpus that are present */
130 cpumask_clear(d->old_domain);
131 cpumask_clear(searched_cpumask);
132 cpu = cpumask_first_and(mask, cpu_online_mask);
133 while (cpu < nr_cpu_ids) {
136 /* Get the possible target cpus for @mask/@cpu from the apic */
137 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
140 * Clear the offline cpus from @vector_cpumask for searching
141 * and verify whether the result overlaps with @mask. If true,
142 * then the call to apic->cpu_mask_to_apicid_and() will
143 * succeed as well. If not, no point in trying to find a
144 * vector in this mask.
146 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
147 if (!cpumask_intersects(vector_searchmask, mask))
150 if (cpumask_subset(vector_cpumask, d->domain)) {
151 if (cpumask_equal(vector_cpumask, d->domain))
154 * Mark the cpus which are not longer in the mask for
157 cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
158 vector = d->cfg.vector;
162 vector = current_vector;
163 offset = current_offset;
166 if (vector >= first_system_vector) {
167 offset = (offset + 1) % 16;
168 vector = FIRST_EXTERNAL_VECTOR + offset;
171 /* If the search wrapped around, try the next cpu */
172 if (unlikely(current_vector == vector))
175 if (test_bit(vector, used_vectors))
178 for_each_cpu(new_cpu, vector_searchmask) {
179 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
183 current_vector = vector;
184 current_offset = offset;
185 /* Schedule the old vector for cleanup on all cpus */
187 cpumask_copy(d->old_domain, d->domain);
188 for_each_cpu(new_cpu, vector_searchmask)
189 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
194 * We exclude the current @vector_cpumask from the requested
195 * @mask and try again with the next online cpu in the
196 * result. We cannot modify @mask, so we use @vector_cpumask
197 * as a temporary buffer here as it will be reassigned when
198 * calling apic->vector_allocation_domain() above.
200 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
201 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
202 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
209 * Exclude offline cpus from the cleanup mask and set the
210 * move_in_progress flag when the result is not empty.
212 cpumask_and(d->old_domain, d->old_domain, cpu_online_mask);
213 d->move_in_progress = !cpumask_empty(d->old_domain);
214 d->cfg.vector = vector;
215 cpumask_copy(d->domain, vector_cpumask);
218 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
219 * as we already established, that mask & d->domain & cpu_online_mask
222 BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
223 &d->cfg.dest_apicid));
227 static int assign_irq_vector(int irq, struct apic_chip_data *data,
228 const struct cpumask *mask)
233 raw_spin_lock_irqsave(&vector_lock, flags);
234 err = __assign_irq_vector(irq, data, mask);
235 raw_spin_unlock_irqrestore(&vector_lock, flags);
239 static int assign_irq_vector_policy(int irq, int node,
240 struct apic_chip_data *data,
241 struct irq_alloc_info *info)
243 if (info && info->mask)
244 return assign_irq_vector(irq, data, info->mask);
245 if (node != NUMA_NO_NODE &&
246 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
248 return assign_irq_vector(irq, data, apic->target_cpus());
251 static void clear_irq_vector(int irq, struct apic_chip_data *data)
253 struct irq_desc *desc;
256 BUG_ON(!data->cfg.vector);
258 vector = data->cfg.vector;
259 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
260 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
262 data->cfg.vector = 0;
263 cpumask_clear(data->domain);
266 * If move is in progress or the old_domain mask is not empty,
267 * i.e. the cleanup IPI has not been processed yet, we need to remove
268 * the old references to desc from all cpus vector tables.
270 if (!data->move_in_progress && cpumask_empty(data->old_domain))
273 desc = irq_to_desc(irq);
274 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
275 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
277 if (per_cpu(vector_irq, cpu)[vector] != desc)
279 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
283 data->move_in_progress = 0;
286 void init_irq_alloc_info(struct irq_alloc_info *info,
287 const struct cpumask *mask)
289 memset(info, 0, sizeof(*info));
293 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
298 memset(dst, 0, sizeof(*dst));
301 static void x86_vector_free_irqs(struct irq_domain *domain,
302 unsigned int virq, unsigned int nr_irqs)
304 struct apic_chip_data *apic_data;
305 struct irq_data *irq_data;
309 for (i = 0; i < nr_irqs; i++) {
310 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
311 if (irq_data && irq_data->chip_data) {
312 raw_spin_lock_irqsave(&vector_lock, flags);
313 clear_irq_vector(virq + i, irq_data->chip_data);
314 apic_data = irq_data->chip_data;
315 irq_domain_reset_irq_data(irq_data);
316 raw_spin_unlock_irqrestore(&vector_lock, flags);
317 free_apic_chip_data(apic_data);
318 #ifdef CONFIG_X86_IO_APIC
319 if (virq + i < nr_legacy_irqs())
320 legacy_irq_data[virq + i] = NULL;
326 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
327 unsigned int nr_irqs, void *arg)
329 struct irq_alloc_info *info = arg;
330 struct apic_chip_data *data;
331 struct irq_data *irq_data;
337 /* Currently vector allocator can't guarantee contiguous allocations */
338 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
341 for (i = 0; i < nr_irqs; i++) {
342 irq_data = irq_domain_get_irq_data(domain, virq + i);
344 node = irq_data_get_node(irq_data);
345 #ifdef CONFIG_X86_IO_APIC
346 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
347 data = legacy_irq_data[virq + i];
350 data = alloc_apic_chip_data(node);
356 irq_data->chip = &lapic_controller;
357 irq_data->chip_data = data;
358 irq_data->hwirq = virq + i;
359 err = assign_irq_vector_policy(virq + i, node, data, info);
367 x86_vector_free_irqs(domain, virq, i + 1);
371 static const struct irq_domain_ops x86_vector_domain_ops = {
372 .alloc = x86_vector_alloc_irqs,
373 .free = x86_vector_free_irqs,
376 int __init arch_probe_nr_irqs(void)
380 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
381 nr_irqs = NR_VECTORS * nr_cpu_ids;
383 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
384 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
386 * for MSI and HT dyn irq
388 if (gsi_top <= NR_IRQS_LEGACY)
389 nr += 8 * nr_cpu_ids;
397 * We don't know if PIC is present at this point so we need to do
398 * probe() to get the right number of legacy IRQs.
400 return legacy_pic->probe();
403 #ifdef CONFIG_X86_IO_APIC
404 static void init_legacy_irqs(void)
406 int i, node = cpu_to_node(0);
407 struct apic_chip_data *data;
410 * For legacy IRQ's, start with assigning irq0 to irq15 to
411 * ISA_IRQ_VECTOR(i) for all cpu's.
413 for (i = 0; i < nr_legacy_irqs(); i++) {
414 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
417 data->cfg.vector = ISA_IRQ_VECTOR(i);
418 cpumask_setall(data->domain);
419 irq_set_chip_data(i, data);
423 static void init_legacy_irqs(void) { }
426 int __init arch_early_irq_init(void)
430 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
432 BUG_ON(x86_vector_domain == NULL);
433 irq_set_default_host(x86_vector_domain);
435 arch_init_msi_domain(x86_vector_domain);
436 arch_init_htirq_domain(x86_vector_domain);
438 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
439 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
440 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
442 return arch_early_ioapic_init();
445 /* Initialize vector_irq on a new cpu */
446 static void __setup_vector_irq(int cpu)
448 struct apic_chip_data *data;
449 struct irq_desc *desc;
452 /* Mark the inuse vectors */
453 for_each_irq_desc(irq, desc) {
454 struct irq_data *idata = irq_desc_get_irq_data(desc);
456 data = apic_chip_data(idata);
457 if (!data || !cpumask_test_cpu(cpu, data->domain))
459 vector = data->cfg.vector;
460 per_cpu(vector_irq, cpu)[vector] = desc;
462 /* Mark the free vectors */
463 for (vector = 0; vector < NR_VECTORS; ++vector) {
464 desc = per_cpu(vector_irq, cpu)[vector];
465 if (IS_ERR_OR_NULL(desc))
468 data = apic_chip_data(irq_desc_get_irq_data(desc));
469 if (!cpumask_test_cpu(cpu, data->domain))
470 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
475 * Setup the vector to irq mappings. Must be called with vector_lock held.
477 void setup_vector_irq(int cpu)
481 lockdep_assert_held(&vector_lock);
483 * On most of the platforms, legacy PIC delivers the interrupts on the
484 * boot cpu. But there are certain platforms where PIC interrupts are
485 * delivered to multiple cpu's. If the legacy IRQ is handled by the
486 * legacy PIC, for the new cpu that is coming online, setup the static
487 * legacy vector to irq mapping:
489 for (irq = 0; irq < nr_legacy_irqs(); irq++)
490 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
492 __setup_vector_irq(cpu);
495 static int apic_retrigger_irq(struct irq_data *irq_data)
497 struct apic_chip_data *data = apic_chip_data(irq_data);
501 raw_spin_lock_irqsave(&vector_lock, flags);
502 cpu = cpumask_first_and(data->domain, cpu_online_mask);
503 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
504 raw_spin_unlock_irqrestore(&vector_lock, flags);
509 void apic_ack_edge(struct irq_data *data)
511 irq_complete_move(irqd_cfg(data));
516 static int apic_set_affinity(struct irq_data *irq_data,
517 const struct cpumask *dest, bool force)
519 struct apic_chip_data *data = irq_data->chip_data;
520 int err, irq = irq_data->irq;
522 if (!config_enabled(CONFIG_SMP))
525 if (!cpumask_intersects(dest, cpu_online_mask))
528 err = assign_irq_vector(irq, data, dest);
529 return err ? err : IRQ_SET_MASK_OK;
532 static struct irq_chip lapic_controller = {
533 .irq_ack = apic_ack_edge,
534 .irq_set_affinity = apic_set_affinity,
535 .irq_retrigger = apic_retrigger_irq,
539 static void __send_cleanup_vector(struct apic_chip_data *data)
541 raw_spin_lock(&vector_lock);
542 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
543 data->move_in_progress = 0;
544 if (!cpumask_empty(data->old_domain))
545 apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR);
546 raw_spin_unlock(&vector_lock);
549 void send_cleanup_vector(struct irq_cfg *cfg)
551 struct apic_chip_data *data;
553 data = container_of(cfg, struct apic_chip_data, cfg);
554 if (data->move_in_progress)
555 __send_cleanup_vector(data);
558 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
564 /* Prevent vectors vanishing under us */
565 raw_spin_lock(&vector_lock);
567 me = smp_processor_id();
568 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
569 struct apic_chip_data *data;
570 struct irq_desc *desc;
574 desc = __this_cpu_read(vector_irq[vector]);
575 if (IS_ERR_OR_NULL(desc))
578 if (!raw_spin_trylock(&desc->lock)) {
579 raw_spin_unlock(&vector_lock);
581 raw_spin_lock(&vector_lock);
585 data = apic_chip_data(irq_desc_get_irq_data(desc));
590 * Nothing to cleanup if irq migration is in progress
591 * or this cpu is not set in the cleanup mask.
593 if (data->move_in_progress ||
594 !cpumask_test_cpu(me, data->old_domain))
598 * We have two cases to handle here:
599 * 1) vector is unchanged but the target mask got reduced
600 * 2) vector and the target mask has changed
602 * #1 is obvious, but in #2 we have two vectors with the same
603 * irq descriptor: the old and the new vector. So we need to
604 * make sure that we only cleanup the old vector. The new
605 * vector has the current @vector number in the config and
606 * this cpu is part of the target mask. We better leave that
609 if (vector == data->cfg.vector &&
610 cpumask_test_cpu(me, data->domain))
613 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
615 * Check if the vector that needs to be cleanedup is
616 * registered at the cpu's IRR. If so, then this is not
617 * the best time to clean it up. Lets clean it up in the
618 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
621 if (irr & (1 << (vector % 32))) {
622 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
625 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
626 cpumask_clear_cpu(me, data->old_domain);
628 raw_spin_unlock(&desc->lock);
631 raw_spin_unlock(&vector_lock);
636 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
639 struct apic_chip_data *data;
641 data = container_of(cfg, struct apic_chip_data, cfg);
642 if (likely(!data->move_in_progress))
645 me = smp_processor_id();
646 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
647 __send_cleanup_vector(data);
650 void irq_complete_move(struct irq_cfg *cfg)
652 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
656 * Called with @desc->lock held and interrupts disabled.
658 void irq_force_complete_move(struct irq_desc *desc)
660 struct irq_data *irqdata = irq_desc_get_irq_data(desc);
661 struct apic_chip_data *data = apic_chip_data(irqdata);
662 struct irq_cfg *cfg = data ? &data->cfg : NULL;
667 __irq_complete_move(cfg, cfg->vector);
670 * This is tricky. If the cleanup of @data->old_domain has not been
671 * done yet, then the following setaffinity call will fail with
672 * -EBUSY. This can leave the interrupt in a stale state.
674 * The cleanup cannot make progress because we hold @desc->lock. So in
675 * case @data->old_domain is not yet cleaned up, we need to drop the
676 * lock and acquire it again. @desc cannot go away, because the
677 * hotplug code holds the sparse irq lock.
679 raw_spin_lock(&vector_lock);
680 /* Clean out all offline cpus (including ourself) first. */
681 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
682 while (!cpumask_empty(data->old_domain)) {
683 raw_spin_unlock(&vector_lock);
684 raw_spin_unlock(&desc->lock);
686 raw_spin_lock(&desc->lock);
688 * Reevaluate apic_chip_data. It might have been cleared after
689 * we dropped @desc->lock.
691 data = apic_chip_data(irqdata);
694 raw_spin_lock(&vector_lock);
696 raw_spin_unlock(&vector_lock);
700 static void __init print_APIC_field(int base)
706 for (i = 0; i < 8; i++)
707 pr_cont("%08x", apic_read(base + i*0x10));
712 static void __init print_local_APIC(void *dummy)
714 unsigned int i, v, ver, maxlvt;
717 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
718 smp_processor_id(), hard_smp_processor_id());
719 v = apic_read(APIC_ID);
720 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
721 v = apic_read(APIC_LVR);
722 pr_info("... APIC VERSION: %08x\n", v);
723 ver = GET_APIC_VERSION(v);
724 maxlvt = lapic_get_maxlvt();
726 v = apic_read(APIC_TASKPRI);
727 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
730 if (APIC_INTEGRATED(ver)) {
731 if (!APIC_XAPIC(ver)) {
732 v = apic_read(APIC_ARBPRI);
733 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
734 v, v & APIC_ARBPRI_MASK);
736 v = apic_read(APIC_PROCPRI);
737 pr_debug("... APIC PROCPRI: %08x\n", v);
741 * Remote read supported only in the 82489DX and local APIC for
742 * Pentium processors.
744 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
745 v = apic_read(APIC_RRR);
746 pr_debug("... APIC RRR: %08x\n", v);
749 v = apic_read(APIC_LDR);
750 pr_debug("... APIC LDR: %08x\n", v);
751 if (!x2apic_enabled()) {
752 v = apic_read(APIC_DFR);
753 pr_debug("... APIC DFR: %08x\n", v);
755 v = apic_read(APIC_SPIV);
756 pr_debug("... APIC SPIV: %08x\n", v);
758 pr_debug("... APIC ISR field:\n");
759 print_APIC_field(APIC_ISR);
760 pr_debug("... APIC TMR field:\n");
761 print_APIC_field(APIC_TMR);
762 pr_debug("... APIC IRR field:\n");
763 print_APIC_field(APIC_IRR);
766 if (APIC_INTEGRATED(ver)) {
767 /* Due to the Pentium erratum 3AP. */
769 apic_write(APIC_ESR, 0);
771 v = apic_read(APIC_ESR);
772 pr_debug("... APIC ESR: %08x\n", v);
775 icr = apic_icr_read();
776 pr_debug("... APIC ICR: %08x\n", (u32)icr);
777 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
779 v = apic_read(APIC_LVTT);
780 pr_debug("... APIC LVTT: %08x\n", v);
784 v = apic_read(APIC_LVTPC);
785 pr_debug("... APIC LVTPC: %08x\n", v);
787 v = apic_read(APIC_LVT0);
788 pr_debug("... APIC LVT0: %08x\n", v);
789 v = apic_read(APIC_LVT1);
790 pr_debug("... APIC LVT1: %08x\n", v);
794 v = apic_read(APIC_LVTERR);
795 pr_debug("... APIC LVTERR: %08x\n", v);
798 v = apic_read(APIC_TMICT);
799 pr_debug("... APIC TMICT: %08x\n", v);
800 v = apic_read(APIC_TMCCT);
801 pr_debug("... APIC TMCCT: %08x\n", v);
802 v = apic_read(APIC_TDCR);
803 pr_debug("... APIC TDCR: %08x\n", v);
805 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
806 v = apic_read(APIC_EFEAT);
807 maxlvt = (v >> 16) & 0xff;
808 pr_debug("... APIC EFEAT: %08x\n", v);
809 v = apic_read(APIC_ECTRL);
810 pr_debug("... APIC ECTRL: %08x\n", v);
811 for (i = 0; i < maxlvt; i++) {
812 v = apic_read(APIC_EILVTn(i));
813 pr_debug("... APIC EILVT%d: %08x\n", i, v);
819 static void __init print_local_APICs(int maxcpu)
827 for_each_online_cpu(cpu) {
830 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
835 static void __init print_PIC(void)
840 if (!nr_legacy_irqs())
843 pr_debug("\nprinting PIC contents\n");
845 raw_spin_lock_irqsave(&i8259A_lock, flags);
847 v = inb(0xa1) << 8 | inb(0x21);
848 pr_debug("... PIC IMR: %04x\n", v);
850 v = inb(0xa0) << 8 | inb(0x20);
851 pr_debug("... PIC IRR: %04x\n", v);
855 v = inb(0xa0) << 8 | inb(0x20);
859 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
861 pr_debug("... PIC ISR: %04x\n", v);
863 v = inb(0x4d1) << 8 | inb(0x4d0);
864 pr_debug("... PIC ELCR: %04x\n", v);
867 static int show_lapic __initdata = 1;
868 static __init int setup_show_lapic(char *arg)
872 if (strcmp(arg, "all") == 0) {
873 show_lapic = CONFIG_NR_CPUS;
875 get_option(&arg, &num);
882 __setup("show_lapic=", setup_show_lapic);
884 static int __init print_ICs(void)
886 if (apic_verbosity == APIC_QUIET)
891 /* don't print out if apic is not there */
892 if (!cpu_has_apic && !apic_from_smp_config())
895 print_local_APICs(show_lapic);
901 late_initcall(print_ICs);