2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/irqdomain.h>
17 #include <linux/slab.h>
18 #include <asm/hw_irq.h>
20 #include <asm/i8259.h>
22 #include <asm/irq_remapping.h>
24 struct apic_chip_data {
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
31 struct irq_domain *x86_vector_domain;
32 static DEFINE_RAW_SPINLOCK(vector_lock);
33 static struct irq_chip lapic_controller;
34 #ifdef CONFIG_X86_IO_APIC
35 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
38 void lock_vector_lock(void)
40 /* Used to the online set of cpus does not change
41 * during assign_irq_vector.
43 raw_spin_lock(&vector_lock);
46 void unlock_vector_lock(void)
48 raw_spin_unlock(&vector_lock);
51 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
56 while (irq_data->parent_data)
57 irq_data = irq_data->parent_data;
59 return irq_data->chip_data;
62 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
64 struct apic_chip_data *data = apic_chip_data(irq_data);
66 return data ? &data->cfg : NULL;
69 struct irq_cfg *irq_cfg(unsigned int irq)
71 return irqd_cfg(irq_get_irq_data(irq));
74 static struct apic_chip_data *alloc_apic_chip_data(int node)
76 struct apic_chip_data *data;
78 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
81 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
83 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
87 free_cpumask_var(data->domain);
93 static void free_apic_chip_data(struct apic_chip_data *data)
96 free_cpumask_var(data->domain);
97 free_cpumask_var(data->old_domain);
102 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
103 const struct cpumask *mask)
106 * NOTE! The local APIC isn't very good at handling
107 * multiple interrupts at the same interrupt level.
108 * As the interrupt level is determined by taking the
109 * vector number and shifting that right by 4, we
110 * want to spread these out a bit so that they don't
111 * all fall in the same interrupt level.
113 * Also, we've got to be careful not to trash gate
114 * 0x80, because int 0x80 is hm, kind of importantish. ;)
116 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
117 static int current_offset = VECTOR_OFFSET_START % 16;
119 cpumask_var_t tmp_mask;
121 if (d->move_in_progress)
124 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
127 /* Only try and allocate irqs on cpus that are present */
129 cpumask_clear(d->old_domain);
130 cpu = cpumask_first_and(mask, cpu_online_mask);
131 while (cpu < nr_cpu_ids) {
132 int new_cpu, vector, offset;
134 apic->vector_allocation_domain(cpu, tmp_mask, mask);
136 if (cpumask_subset(tmp_mask, d->domain)) {
138 if (cpumask_equal(tmp_mask, d->domain))
141 * New cpumask using the vector is a proper subset of
142 * the current in use mask. So cleanup the vector
143 * allocation for the members that are not used anymore.
145 cpumask_andnot(d->old_domain, d->domain, tmp_mask);
146 d->move_in_progress =
147 cpumask_intersects(d->old_domain, cpu_online_mask);
148 cpumask_and(d->domain, d->domain, tmp_mask);
152 vector = current_vector;
153 offset = current_offset;
156 if (vector >= first_system_vector) {
157 offset = (offset + 1) % 16;
158 vector = FIRST_EXTERNAL_VECTOR + offset;
161 if (unlikely(current_vector == vector)) {
162 cpumask_or(d->old_domain, d->old_domain, tmp_mask);
163 cpumask_andnot(tmp_mask, mask, d->old_domain);
164 cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
168 if (test_bit(vector, used_vectors))
171 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) {
172 if (per_cpu(vector_irq, new_cpu)[vector] >
177 current_vector = vector;
178 current_offset = offset;
180 cpumask_copy(d->old_domain, d->domain);
181 d->move_in_progress =
182 cpumask_intersects(d->old_domain, cpu_online_mask);
184 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
185 per_cpu(vector_irq, new_cpu)[vector] = irq;
186 d->cfg.vector = vector;
187 cpumask_copy(d->domain, tmp_mask);
191 free_cpumask_var(tmp_mask);
194 /* cache destination APIC IDs into cfg->dest_apicid */
195 err = apic->cpu_mask_to_apicid_and(mask, d->domain,
196 &d->cfg.dest_apicid);
202 static int assign_irq_vector(int irq, struct apic_chip_data *data,
203 const struct cpumask *mask)
208 raw_spin_lock_irqsave(&vector_lock, flags);
209 err = __assign_irq_vector(irq, data, mask);
210 raw_spin_unlock_irqrestore(&vector_lock, flags);
214 static void clear_irq_vector(int irq, struct apic_chip_data *data)
219 raw_spin_lock_irqsave(&vector_lock, flags);
220 BUG_ON(!data->cfg.vector);
222 vector = data->cfg.vector;
223 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
224 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
226 data->cfg.vector = 0;
227 cpumask_clear(data->domain);
229 if (likely(!data->move_in_progress)) {
230 raw_spin_unlock_irqrestore(&vector_lock, flags);
234 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
235 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
237 if (per_cpu(vector_irq, cpu)[vector] != irq)
239 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
243 data->move_in_progress = 0;
244 raw_spin_unlock_irqrestore(&vector_lock, flags);
247 void init_irq_alloc_info(struct irq_alloc_info *info,
248 const struct cpumask *mask)
250 memset(info, 0, sizeof(*info));
254 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
259 memset(dst, 0, sizeof(*dst));
262 static inline const struct cpumask *
263 irq_alloc_info_get_mask(struct irq_alloc_info *info)
265 return (!info || !info->mask) ? apic->target_cpus() : info->mask;
268 static void x86_vector_free_irqs(struct irq_domain *domain,
269 unsigned int virq, unsigned int nr_irqs)
271 struct irq_data *irq_data;
274 for (i = 0; i < nr_irqs; i++) {
275 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
276 if (irq_data && irq_data->chip_data) {
277 clear_irq_vector(virq + i, irq_data->chip_data);
278 free_apic_chip_data(irq_data->chip_data);
279 #ifdef CONFIG_X86_IO_APIC
280 if (virq + i < nr_legacy_irqs())
281 legacy_irq_data[virq + i] = NULL;
283 irq_domain_reset_irq_data(irq_data);
288 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
289 unsigned int nr_irqs, void *arg)
291 struct irq_alloc_info *info = arg;
292 struct apic_chip_data *data;
293 const struct cpumask *mask;
294 struct irq_data *irq_data;
300 /* Currently vector allocator can't guarantee contiguous allocations */
301 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
304 mask = irq_alloc_info_get_mask(info);
305 for (i = 0; i < nr_irqs; i++) {
306 irq_data = irq_domain_get_irq_data(domain, virq + i);
308 #ifdef CONFIG_X86_IO_APIC
309 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
310 data = legacy_irq_data[virq + i];
313 data = alloc_apic_chip_data(irq_data->node);
319 irq_data->chip = &lapic_controller;
320 irq_data->chip_data = data;
321 irq_data->hwirq = virq + i;
322 err = assign_irq_vector(virq, data, mask);
330 x86_vector_free_irqs(domain, virq, i + 1);
334 static struct irq_domain_ops x86_vector_domain_ops = {
335 .alloc = x86_vector_alloc_irqs,
336 .free = x86_vector_free_irqs,
339 int __init arch_probe_nr_irqs(void)
343 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
344 nr_irqs = NR_VECTORS * nr_cpu_ids;
346 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
347 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
349 * for MSI and HT dyn irq
351 if (gsi_top <= NR_IRQS_LEGACY)
352 nr += 8 * nr_cpu_ids;
359 return nr_legacy_irqs();
362 #ifdef CONFIG_X86_IO_APIC
363 static void init_legacy_irqs(void)
365 int i, node = cpu_to_node(0);
366 struct apic_chip_data *data;
369 * For legacy IRQ's, start with assigning irq0 to irq15 to
370 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
372 for (i = 0; i < nr_legacy_irqs(); i++) {
373 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
376 * For legacy IRQ's, start with assigning irq0 to irq15 to
377 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
379 data->cfg.vector = IRQ0_VECTOR + i;
380 cpumask_setall(data->domain);
381 irq_set_chip_data(i, data);
385 static void init_legacy_irqs(void) { }
388 int __init arch_early_irq_init(void)
392 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
394 BUG_ON(x86_vector_domain == NULL);
395 irq_set_default_host(x86_vector_domain);
397 arch_init_msi_domain(x86_vector_domain);
398 arch_init_htirq_domain(x86_vector_domain);
400 return arch_early_ioapic_init();
403 static void __setup_vector_irq(int cpu)
405 /* Initialize vector_irq on a new cpu */
407 struct apic_chip_data *data;
410 * vector_lock will make sure that we don't run into irq vector
411 * assignments that might be happening on another cpu in parallel,
412 * while we setup our initial vector to irq mappings.
414 raw_spin_lock(&vector_lock);
415 /* Mark the inuse vectors */
416 for_each_active_irq(irq) {
417 data = apic_chip_data(irq_get_irq_data(irq));
421 if (!cpumask_test_cpu(cpu, data->domain))
423 vector = data->cfg.vector;
424 per_cpu(vector_irq, cpu)[vector] = irq;
426 /* Mark the free vectors */
427 for (vector = 0; vector < NR_VECTORS; ++vector) {
428 irq = per_cpu(vector_irq, cpu)[vector];
429 if (irq <= VECTOR_UNDEFINED)
432 data = apic_chip_data(irq_get_irq_data(irq));
433 if (!cpumask_test_cpu(cpu, data->domain))
434 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
436 raw_spin_unlock(&vector_lock);
440 * Setup the vector to irq mappings.
442 void setup_vector_irq(int cpu)
447 * On most of the platforms, legacy PIC delivers the interrupts on the
448 * boot cpu. But there are certain platforms where PIC interrupts are
449 * delivered to multiple cpu's. If the legacy IRQ is handled by the
450 * legacy PIC, for the new cpu that is coming online, setup the static
451 * legacy vector to irq mapping:
453 for (irq = 0; irq < nr_legacy_irqs(); irq++)
454 per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
456 __setup_vector_irq(cpu);
459 static int apic_retrigger_irq(struct irq_data *irq_data)
461 struct apic_chip_data *data = apic_chip_data(irq_data);
465 raw_spin_lock_irqsave(&vector_lock, flags);
466 cpu = cpumask_first_and(data->domain, cpu_online_mask);
467 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
468 raw_spin_unlock_irqrestore(&vector_lock, flags);
473 void apic_ack_edge(struct irq_data *data)
475 irq_complete_move(irqd_cfg(data));
480 static int apic_set_affinity(struct irq_data *irq_data,
481 const struct cpumask *dest, bool force)
483 struct apic_chip_data *data = irq_data->chip_data;
484 int err, irq = irq_data->irq;
486 if (!config_enabled(CONFIG_SMP))
489 if (!cpumask_intersects(dest, cpu_online_mask))
492 err = assign_irq_vector(irq, data, dest);
494 struct irq_data *top = irq_get_irq_data(irq);
496 if (assign_irq_vector(irq, data, top->affinity))
497 pr_err("Failed to recover vector for irq %d\n", irq);
501 return IRQ_SET_MASK_OK;
504 static struct irq_chip lapic_controller = {
505 .irq_ack = apic_ack_edge,
506 .irq_set_affinity = apic_set_affinity,
507 .irq_retrigger = apic_retrigger_irq,
511 static void __send_cleanup_vector(struct apic_chip_data *data)
513 cpumask_var_t cleanup_mask;
515 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
518 for_each_cpu_and(i, data->old_domain, cpu_online_mask)
519 apic->send_IPI_mask(cpumask_of(i),
520 IRQ_MOVE_CLEANUP_VECTOR);
522 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
523 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
524 free_cpumask_var(cleanup_mask);
526 data->move_in_progress = 0;
529 void send_cleanup_vector(struct irq_cfg *cfg)
531 struct apic_chip_data *data;
533 data = container_of(cfg, struct apic_chip_data, cfg);
534 if (data->move_in_progress)
535 __send_cleanup_vector(data);
538 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
546 me = smp_processor_id();
547 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
550 struct irq_desc *desc;
551 struct apic_chip_data *data;
553 irq = __this_cpu_read(vector_irq[vector]);
555 if (irq <= VECTOR_UNDEFINED)
558 desc = irq_to_desc(irq);
562 data = apic_chip_data(&desc->irq_data);
566 raw_spin_lock(&desc->lock);
569 * Check if the irq migration is in progress. If so, we
570 * haven't received the cleanup request yet for this irq.
572 if (data->move_in_progress)
575 if (vector == data->cfg.vector &&
576 cpumask_test_cpu(me, data->domain))
579 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
581 * Check if the vector that needs to be cleanedup is
582 * registered at the cpu's IRR. If so, then this is not
583 * the best time to clean it up. Lets clean it up in the
584 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
587 if (irr & (1 << (vector % 32))) {
588 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
591 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
593 raw_spin_unlock(&desc->lock);
599 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
602 struct apic_chip_data *data;
604 data = container_of(cfg, struct apic_chip_data, cfg);
605 if (likely(!data->move_in_progress))
608 me = smp_processor_id();
609 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
610 __send_cleanup_vector(data);
613 void irq_complete_move(struct irq_cfg *cfg)
615 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
618 void irq_force_complete_move(int irq)
620 struct irq_cfg *cfg = irq_cfg(irq);
623 __irq_complete_move(cfg, cfg->vector);
627 static void __init print_APIC_field(int base)
633 for (i = 0; i < 8; i++)
634 pr_cont("%08x", apic_read(base + i*0x10));
639 static void __init print_local_APIC(void *dummy)
641 unsigned int i, v, ver, maxlvt;
644 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
645 smp_processor_id(), hard_smp_processor_id());
646 v = apic_read(APIC_ID);
647 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
648 v = apic_read(APIC_LVR);
649 pr_info("... APIC VERSION: %08x\n", v);
650 ver = GET_APIC_VERSION(v);
651 maxlvt = lapic_get_maxlvt();
653 v = apic_read(APIC_TASKPRI);
654 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
657 if (APIC_INTEGRATED(ver)) {
658 if (!APIC_XAPIC(ver)) {
659 v = apic_read(APIC_ARBPRI);
660 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
661 v, v & APIC_ARBPRI_MASK);
663 v = apic_read(APIC_PROCPRI);
664 pr_debug("... APIC PROCPRI: %08x\n", v);
668 * Remote read supported only in the 82489DX and local APIC for
669 * Pentium processors.
671 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
672 v = apic_read(APIC_RRR);
673 pr_debug("... APIC RRR: %08x\n", v);
676 v = apic_read(APIC_LDR);
677 pr_debug("... APIC LDR: %08x\n", v);
678 if (!x2apic_enabled()) {
679 v = apic_read(APIC_DFR);
680 pr_debug("... APIC DFR: %08x\n", v);
682 v = apic_read(APIC_SPIV);
683 pr_debug("... APIC SPIV: %08x\n", v);
685 pr_debug("... APIC ISR field:\n");
686 print_APIC_field(APIC_ISR);
687 pr_debug("... APIC TMR field:\n");
688 print_APIC_field(APIC_TMR);
689 pr_debug("... APIC IRR field:\n");
690 print_APIC_field(APIC_IRR);
693 if (APIC_INTEGRATED(ver)) {
694 /* Due to the Pentium erratum 3AP. */
696 apic_write(APIC_ESR, 0);
698 v = apic_read(APIC_ESR);
699 pr_debug("... APIC ESR: %08x\n", v);
702 icr = apic_icr_read();
703 pr_debug("... APIC ICR: %08x\n", (u32)icr);
704 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
706 v = apic_read(APIC_LVTT);
707 pr_debug("... APIC LVTT: %08x\n", v);
711 v = apic_read(APIC_LVTPC);
712 pr_debug("... APIC LVTPC: %08x\n", v);
714 v = apic_read(APIC_LVT0);
715 pr_debug("... APIC LVT0: %08x\n", v);
716 v = apic_read(APIC_LVT1);
717 pr_debug("... APIC LVT1: %08x\n", v);
721 v = apic_read(APIC_LVTERR);
722 pr_debug("... APIC LVTERR: %08x\n", v);
725 v = apic_read(APIC_TMICT);
726 pr_debug("... APIC TMICT: %08x\n", v);
727 v = apic_read(APIC_TMCCT);
728 pr_debug("... APIC TMCCT: %08x\n", v);
729 v = apic_read(APIC_TDCR);
730 pr_debug("... APIC TDCR: %08x\n", v);
732 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
733 v = apic_read(APIC_EFEAT);
734 maxlvt = (v >> 16) & 0xff;
735 pr_debug("... APIC EFEAT: %08x\n", v);
736 v = apic_read(APIC_ECTRL);
737 pr_debug("... APIC ECTRL: %08x\n", v);
738 for (i = 0; i < maxlvt; i++) {
739 v = apic_read(APIC_EILVTn(i));
740 pr_debug("... APIC EILVT%d: %08x\n", i, v);
746 static void __init print_local_APICs(int maxcpu)
754 for_each_online_cpu(cpu) {
757 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
762 static void __init print_PIC(void)
767 if (!nr_legacy_irqs())
770 pr_debug("\nprinting PIC contents\n");
772 raw_spin_lock_irqsave(&i8259A_lock, flags);
774 v = inb(0xa1) << 8 | inb(0x21);
775 pr_debug("... PIC IMR: %04x\n", v);
777 v = inb(0xa0) << 8 | inb(0x20);
778 pr_debug("... PIC IRR: %04x\n", v);
782 v = inb(0xa0) << 8 | inb(0x20);
786 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
788 pr_debug("... PIC ISR: %04x\n", v);
790 v = inb(0x4d1) << 8 | inb(0x4d0);
791 pr_debug("... PIC ELCR: %04x\n", v);
794 static int show_lapic __initdata = 1;
795 static __init int setup_show_lapic(char *arg)
799 if (strcmp(arg, "all") == 0) {
800 show_lapic = CONFIG_NR_CPUS;
802 get_option(&arg, &num);
809 __setup("show_lapic=", setup_show_lapic);
811 static int __init print_ICs(void)
813 if (apic_verbosity == APIC_QUIET)
818 /* don't print out if apic is not there */
819 if (!cpu_has_apic && !apic_from_smp_config())
822 print_local_APICs(show_lapic);
828 late_initcall(print_ICs);