arch/x86/kernel/apic/summit_32.c

   1 /*
   2  * IBM Summit-Specific Code
   3  *
   4  * Written By: Matthew Dobson, IBM Corporation
   5  *
   6  * Copyright (c) 2003 IBM Corp.
   7  *
   8  * All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  18  * NON INFRINGEMENT.  See the GNU General Public License for more
  19  * details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  * Send feedback to <colpatch@us.ibm.com>
  26  *
  27  */
  28
  29 #include <linux/mm.h>
  30 #include <linux/init.h>
  31 #include <asm/io.h>
  32 #include <asm/bios_ebda.h>
  33
  34 /*
  35  * APIC driver for the IBM "Summit" chipset.
  36  */
  37 #include <linux/threads.h>
  38 #include <linux/cpumask.h>
  39 #include <asm/mpspec.h>
  40 #include <asm/apic.h>
  41 #include <asm/smp.h>
  42 #include <asm/fixmap.h>
  43 #include <asm/apicdef.h>
  44 #include <asm/ipi.h>
  45 #include <linux/kernel.h>
  46 #include <linux/string.h>
  47 #include <linux/gfp.h>
  48 #include <linux/smp.h>
  49
  50 static unsigned summit_get_apic_id(unsigned long x)
  51 {
  52         return (x >> 24) & 0xFF;
  53 }
  54
  55 static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
  56 {
  57         default_send_IPI_mask_sequence_logical(mask, vector);
  58 }
  59
  60 static void summit_send_IPI_allbutself(int vector)
  61 {
  62         default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
  63 }
  64
  65 static void summit_send_IPI_all(int vector)
  66 {
  67         summit_send_IPI_mask(cpu_online_mask, vector);
  68 }
  69
  70 #include <asm/tsc.h>
  71
  72 extern int use_cyclone;
  73
  74 #ifdef CONFIG_X86_SUMMIT_NUMA
  75 static void setup_summit(void);
  76 #else
  77 static inline void setup_summit(void) {}
  78 #endif
  79
  80 static int summit_mps_oem_check(struct mpc_table *mpc, char *oem,
  81                 char *productid)
  82 {
  83         if (!strncmp(oem, "IBM ENSW", 8) &&
  84                         (!strncmp(productid, "VIGIL SMP", 9)
  85                          || !strncmp(productid, "EXA", 3)
  86                          || !strncmp(productid, "RUTHLESS SMP", 12))){
  87                 mark_tsc_unstable("Summit based system");
  88                 use_cyclone = 1; /*enable cyclone-timer*/
  89                 setup_summit();
  90                 return 1;
  91         }
  92         return 0;
  93 }
  94
  95 /* Hook from generic ACPI tables.c */
  96 static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  97 {
  98         if (!strncmp(oem_id, "IBM", 3) &&
  99             (!strncmp(oem_table_id, "SERVIGIL", 8)
 100              || !strncmp(oem_table_id, "EXA", 3))){
 101                 mark_tsc_unstable("Summit based system");
 102                 use_cyclone = 1; /*enable cyclone-timer*/
 103                 setup_summit();
 104                 return 1;
 105         }
 106         return 0;
 107 }
 108
 109 struct rio_table_hdr {
 110         unsigned char version;      /* Version number of this data structure           */
 111                                     /* Version 3 adds chassis_num & WP_index           */
 112         unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil)   */
 113         unsigned char num_rio_dev;  /* # of RIO I/O devices (Cyclones and Winnipegs)   */
 114 } __attribute__((packed));
 115
 116 struct scal_detail {
 117         unsigned char node_id;      /* Scalability Node ID                             */
 118         unsigned long CBAR;         /* Address of 1MB register space                   */
 119         unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
 120         unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 121         unsigned char port1node;    /* Node ID port connected to: 0xFF = None          */
 122         unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 123         unsigned char port2node;    /* Node ID port connected to: 0xFF = None          */
 124         unsigned char port2port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 125         unsigned char chassis_num;  /* 1 based Chassis number (1 = boot node)          */
 126 } __attribute__((packed));
 127
 128 struct rio_detail {
 129         unsigned char node_id;      /* RIO Node ID                                     */
 130         unsigned long BBAR;         /* Address of 1MB register space                   */
 131         unsigned char type;         /* Type of device                                  */
 132         unsigned char owner_id;     /* For WPEG: Node ID of Cyclone that owns this WPEG*/
 133                                     /* For CYC:  Node ID of Twister that owns this CYC */
 134         unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
 135         unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 136         unsigned char port1node;    /* Node ID port connected to: 0xFF=None            */
 137         unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 138         unsigned char first_slot;   /* For WPEG: Lowest slot number below this WPEG    */
 139                                     /* For CYC:  0                                     */
 140         unsigned char status;       /* For WPEG: Bit 0 = 1 : the XAPIC is used         */
 141                                     /*                 = 0 : the XAPIC is not used, ie:*/
 142                                     /*                     ints fwded to another XAPIC */
 143                                     /*           Bits1:7 Reserved                      */
 144                                     /* For CYC:  Bits0:7 Reserved                      */
 145         unsigned char WP_index;     /* For WPEG: WPEG instance index - lower ones have */
 146                                     /*           lower slot numbers/PCI bus numbers    */
 147                                     /* For CYC:  No meaning                            */
 148         unsigned char chassis_num;  /* 1 based Chassis number                          */
 149                                     /* For LookOut WPEGs this field indicates the      */
 150                                     /* Expansion Chassis #, enumerated from Boot       */
 151                                     /* Node WPEG external port, then Boot Node CYC     */
 152                                     /* external port, then Next Vigil chassis WPEG     */
 153                                     /* external port, etc.                             */
 154                                     /* Shared Lookouts have only 1 chassis number (the */
 155                                     /* first one assigned)                             */
 156 } __attribute__((packed));
 157
 158
 159 typedef enum {
 160         CompatTwister = 0,  /* Compatibility Twister               */
 161         AltTwister    = 1,  /* Alternate Twister of internal 8-way */
 162         CompatCyclone = 2,  /* Compatibility Cyclone               */
 163         AltCyclone    = 3,  /* Alternate Cyclone of internal 8-way */
 164         CompatWPEG    = 4,  /* Compatibility WPEG                  */
 165         AltWPEG       = 5,  /* Second Planar WPEG                  */
 166         LookOutAWPEG  = 6,  /* LookOut WPEG                        */
 167         LookOutBWPEG  = 7,  /* LookOut WPEG                        */
 168 } node_type;
 169
 170 static inline int is_WPEG(struct rio_detail *rio){
 171         return (rio->type == CompatWPEG || rio->type == AltWPEG ||
 172                 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
 173 }
 174
 175 #define SUMMIT_APIC_DFR_VALUE   (APIC_DFR_CLUSTER)
 176
 177 static const struct cpumask *summit_target_cpus(void)
 178 {
 179         /* CPU_MASK_ALL (0xff) has undefined behaviour with
 180          * dest_LowestPrio mode logical clustered apic interrupt routing
 181          * Just start on cpu 0.  IRQ balancing will spread load
 182          */
 183         return cpumask_of(0);
 184 }
 185
 186 static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid)
 187 {
 188         return 0;
 189 }
 190
 191 /* we don't use the phys_cpu_present_map to indicate apicid presence */
 192 static unsigned long summit_check_apicid_present(int bit)
 193 {
 194         return 1;
 195 }
 196
 197 static int summit_early_logical_apicid(int cpu)
 198 {
 199         int count = 0;
 200         u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu);
 201         u8 my_cluster = APIC_CLUSTER(my_id);
 202 #ifdef CONFIG_SMP
 203         u8 lid;
 204         int i;
 205
 206         /* Create logical APIC IDs by counting CPUs already in cluster. */
 207         for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
 208                 lid = early_per_cpu(x86_cpu_to_logical_apicid, i);
 209                 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
 210                         ++count;
 211         }
 212 #endif
 213         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
 214          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
 215         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
 216         return my_cluster | (1UL << count);
 217 }
 218
 219 static void summit_init_apic_ldr(void)
 220 {
 221         int cpu = smp_processor_id();
 222         unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
 223         unsigned long val;
 224
 225         apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
 226         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
 227         val |= SET_APIC_LOGICAL_ID(id);
 228         apic_write(APIC_LDR, val);
 229 }
 230
 231 static int summit_apic_id_registered(void)
 232 {
 233         return 1;
 234 }
 235
 236 static void summit_setup_apic_routing(void)
 237 {
 238         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
 239                                                 nr_ioapics);
 240 }
 241
 242 static int summit_cpu_present_to_apicid(int mps_cpu)
 243 {
 244         if (mps_cpu < nr_cpu_ids)
 245                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 246         else
 247                 return BAD_APICID;
 248 }
 249
 250 static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap)
 251 {
 252         /* For clustered we don't have a good way to do this yet - hack */
 253         physids_promote(0x0FL, retmap);
 254 }
 255
 256 static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap)
 257 {
 258         physid_set_mask_of_physid(0, retmap);
 259 }
 260
 261 static int summit_check_phys_apicid_present(int physical_apicid)
 262 {
 263         return 1;
 264 }
 265
 266 static inline int
 267 summit_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
 268 {
 269         unsigned int round = 0;
 270         unsigned int cpu, apicid = 0;
 271
 272         /*
 273          * The cpus in the mask must all be on the apic cluster.
 274          */
 275         for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
 276                 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
 277
 278                 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
 279                         printk("%s: Not a valid mask!\n", __func__);
 280                         return -EINVAL;
 281                 }
 282                 apicid |= new_apicid;
 283                 round++;
 284         }
 285         if (!round)
 286                 return -EINVAL;
 287         *dest_id = apicid;
 288         return 0;
 289 }
 290
 291 static int
 292 summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
 293                               const struct cpumask *andmask,
 294                               unsigned int *apicid)
 295 {
 296         cpumask_var_t cpumask;
 297         *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
 298
 299         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
 300                 return 0;
 301
 302         cpumask_and(cpumask, inmask, andmask);
 303         summit_cpu_mask_to_apicid(cpumask, apicid);
 304
 305         free_cpumask_var(cpumask);
 306
 307         return 0;
 308 }
 309
 310 /*
 311  * cpuid returns the value latched in the HW at reset, not the APIC ID
 312  * register's value.  For any box whose BIOS changes APIC IDs, like
 313  * clustered APIC systems, we must use hard_smp_processor_id.
 314  *
 315  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 316  */
 317 static int summit_phys_pkg_id(int cpuid_apic, int index_msb)
 318 {
 319         return hard_smp_processor_id() >> index_msb;
 320 }
 321
 322 static int probe_summit(void)
 323 {
 324         /* probed later in mptable/ACPI hooks */
 325         return 0;
 326 }
 327
 328 #ifdef CONFIG_X86_SUMMIT_NUMA
 329 static struct rio_table_hdr *rio_table_hdr;
 330 static struct scal_detail   *scal_devs[MAX_NUMNODES];
 331 static struct rio_detail    *rio_devs[MAX_NUMNODES*4];
 332
 333 #ifndef CONFIG_X86_NUMAQ
 334 static int mp_bus_id_to_node[MAX_MP_BUSSES];
 335 #endif
 336
 337 static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
 338 {
 339         int twister = 0, node = 0;
 340         int i, bus, num_buses;
 341
 342         for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
 343                 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
 344                         twister = rio_devs[i]->owner_id;
 345                         break;
 346                 }
 347         }
 348         if (i == rio_table_hdr->num_rio_dev) {
 349                 printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__);
 350                 return last_bus;
 351         }
 352
 353         for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
 354                 if (scal_devs[i]->node_id == twister) {
 355                         node = scal_devs[i]->node_id;
 356                         break;
 357                 }
 358         }
 359         if (i == rio_table_hdr->num_scal_dev) {
 360                 printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__);
 361                 return last_bus;
 362         }
 363
 364         switch (rio_devs[wpeg_num]->type) {
 365         case CompatWPEG:
 366                 /*
 367                  * The Compatibility Winnipeg controls the 2 legacy buses,
 368                  * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
 369                  * a PCI-PCI bridge card is used in either slot: total 5 buses.
 370                  */
 371                 num_buses = 5;
 372                 break;
 373         case AltWPEG:
 374                 /*
 375                  * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
 376                  * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
 377                  * the "extra" buses for each of those slots: total 7 buses.
 378                  */
 379                 num_buses = 7;
 380                 break;
 381         case LookOutAWPEG:
 382         case LookOutBWPEG:
 383                 /*
 384                  * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
 385                  * & the "extra" buses for each of those slots: total 9 buses.
 386                  */
 387                 num_buses = 9;
 388                 break;
 389         default:
 390                 printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__);
 391                 return last_bus;
 392         }
 393
 394         for (bus = last_bus; bus < last_bus + num_buses; bus++)
 395                 mp_bus_id_to_node[bus] = node;
 396         return bus;
 397 }
 398
 399 static int build_detail_arrays(void)
 400 {
 401         unsigned long ptr;
 402         int i, scal_detail_size, rio_detail_size;
 403
 404         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
 405                 printk(KERN_WARNING "%s: MAX_NUMNODES too low!  Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev);
 406                 return 0;
 407         }
 408
 409         switch (rio_table_hdr->version) {
 410         default:
 411                 printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version);
 412                 return 0;
 413         case 2:
 414                 scal_detail_size = 11;
 415                 rio_detail_size = 13;
 416                 break;
 417         case 3:
 418                 scal_detail_size = 12;
 419                 rio_detail_size = 15;
 420                 break;
 421         }
 422
 423         ptr = (unsigned long)rio_table_hdr + 3;
 424         for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
 425                 scal_devs[i] = (struct scal_detail *)ptr;
 426
 427         for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
 428                 rio_devs[i] = (struct rio_detail *)ptr;
 429
 430         return 1;
 431 }
 432
 433 void setup_summit(void)
 434 {
 435         unsigned long           ptr;
 436         unsigned short          offset;
 437         int                     i, next_wpeg, next_bus = 0;
 438
 439         /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
 440         ptr = get_bios_ebda();
 441         ptr = (unsigned long)phys_to_virt(ptr);
 442
 443         rio_table_hdr = NULL;
 444         offset = 0x180;
 445         while (offset) {
 446                 /* The block id is stored in the 2nd word */
 447                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
 448                         /* set the pointer past the offset & block id */
 449                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
 450                         break;
 451                 }
 452                 /* The next offset is stored in the 1st word.  0 means no more */
 453                 offset = *((unsigned short *)(ptr + offset));
 454         }
 455         if (!rio_table_hdr) {
 456                 printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__);
 457                 return;
 458         }
 459
 460         if (!build_detail_arrays())
 461                 return;
 462
 463         /* The first Winnipeg we're looking for has an index of 0 */
 464         next_wpeg = 0;
 465         do {
 466                 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
 467                         if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
 468                                 /* It's the Winnipeg we're looking for! */
 469                                 next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
 470                                 next_wpeg++;
 471                                 break;
 472                         }
 473                 }
 474                 /*
 475                  * If we go through all Rio devices and don't find one with
 476                  * the next index, it means we've found all the Winnipegs,
 477                  * and thus all the PCI buses.
 478                  */
 479                 if (i == rio_table_hdr->num_rio_dev)
 480                         next_wpeg = 0;
 481         } while (next_wpeg != 0);
 482 }
 483 #endif
 484
 485 static struct apic apic_summit = {
 486
 487         .name                           = "summit",
 488         .probe                          = probe_summit,
 489         .acpi_madt_oem_check            = summit_acpi_madt_oem_check,
 490         .apic_id_valid                  = default_apic_id_valid,
 491         .apic_id_registered             = summit_apic_id_registered,
 492
 493         .irq_delivery_mode              = dest_LowestPrio,
 494         /* logical delivery broadcast to all CPUs: */
 495         .irq_dest_mode                  = 1,
 496
 497         .target_cpus                    = summit_target_cpus,
 498         .disable_esr                    = 1,
 499         .dest_logical                   = APIC_DEST_LOGICAL,
 500         .check_apicid_used              = summit_check_apicid_used,
 501         .check_apicid_present           = summit_check_apicid_present,
 502
 503         .vector_allocation_domain       = flat_vector_allocation_domain,
 504         .init_apic_ldr                  = summit_init_apic_ldr,
 505
 506         .ioapic_phys_id_map             = summit_ioapic_phys_id_map,
 507         .setup_apic_routing             = summit_setup_apic_routing,
 508         .multi_timer_check              = NULL,
 509         .cpu_present_to_apicid          = summit_cpu_present_to_apicid,
 510         .apicid_to_cpu_present          = summit_apicid_to_cpu_present,
 511         .setup_portio_remap             = NULL,
 512         .check_phys_apicid_present      = summit_check_phys_apicid_present,
 513         .enable_apic_mode               = NULL,
 514         .phys_pkg_id                    = summit_phys_pkg_id,
 515         .mps_oem_check                  = summit_mps_oem_check,
 516
 517         .get_apic_id                    = summit_get_apic_id,
 518         .set_apic_id                    = NULL,
 519         .apic_id_mask                   = 0xFF << 24,
 520
 521         .cpu_mask_to_apicid_and         = summit_cpu_mask_to_apicid_and,
 522
 523         .send_IPI_mask                  = summit_send_IPI_mask,
 524         .send_IPI_mask_allbutself       = NULL,
 525         .send_IPI_allbutself            = summit_send_IPI_allbutself,
 526         .send_IPI_all                   = summit_send_IPI_all,
 527         .send_IPI_self                  = default_send_IPI_self,
 528
 529         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 530         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 531
 532         .wait_for_init_deassert         = default_wait_for_init_deassert,
 533
 534         .smp_callin_clear_local_apic    = NULL,
 535         .inquire_remote_apic            = default_inquire_remote_apic,
 536
 537         .read                           = native_apic_mem_read,
 538         .write                          = native_apic_mem_write,
 539         .eoi_write                      = native_apic_mem_write,
 540         .icr_read                       = native_apic_icr_read,
 541         .icr_write                      = native_apic_icr_write,
 542         .wait_icr_idle                  = native_apic_wait_icr_idle,
 543         .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
 544
 545         .x86_32_early_logical_apicid    = summit_early_logical_apicid,
 546 };
 547
 548 apic_driver(apic_summit);