2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug = -1;
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
79 * # of IRQ routing registers
81 int nr_ioapic_registers[MAX_IO_APICS];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99 int skip_ioapic_setup;
101 void arch_disable_smp_support(void)
105 noioapicreroute = -1;
107 skip_ioapic_setup = 1;
110 static int __init parse_noapic(char *str)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
134 struct irq_pin_list *pin;
137 node = cpu_to_node(cpu);
139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
145 struct irq_pin_list *irq_2_pin;
146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
148 unsigned move_cleanup_count;
150 u8 move_in_progress : 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx[] = {
160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
180 int __init arch_early_irq_init(void)
183 struct irq_desc *desc;
188 count = ARRAY_SIZE(irq_cfgx);
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg *irq_cfg(unsigned int irq)
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
208 desc = irq_to_desc(irq);
210 cfg = desc->chip_data;
215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
220 node = cpu_to_node(cpu);
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
229 free_cpumask_var(cfg->domain);
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
245 cfg = desc->chip_data;
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
269 entry = get_one_free_irq_2_pin(cpu);
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
277 old_entry = old_entry->next;
279 entry = get_one_free_irq_2_pin(cpu);
287 /* still use the old one */
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
294 old_entry = old_entry->next;
298 cfg->irq_2_pin = head;
301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
303 struct irq_pin_list *entry, *next;
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
308 entry = old_cfg->irq_2_pin;
315 old_cfg->irq_2_pin = NULL;
318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
322 struct irq_cfg *old_cfg;
324 cfg = get_one_free_irq_cfg(cpu);
329 desc->chip_data = cfg;
331 old_cfg = old_desc->chip_data;
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
338 static void free_irq_cfg(struct irq_cfg *old_cfg)
343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
345 struct irq_cfg *old_cfg, *cfg;
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
363 struct irq_cfg *cfg = desc->chip_data;
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc->affinity, mask))
368 cfg->move_desc_pending = 1;
374 static struct irq_cfg *irq_cfg(unsigned int irq)
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
390 unsigned int unused[3];
392 unsigned int unused2[11];
396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
398 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
399 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(vector, &io_apic->eoi);
408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
410 struct io_apic __iomem *io_apic = io_apic_base(apic);
411 writel(reg, &io_apic->index);
412 return readl(&io_apic->data);
415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
417 struct io_apic __iomem *io_apic = io_apic_base(apic);
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
430 struct io_apic __iomem *io_apic = io_apic_base(apic);
433 writel(reg, &io_apic->index);
434 writel(value, &io_apic->data);
437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
439 struct irq_pin_list *entry;
442 spin_lock_irqsave(&ioapic_lock, flags);
443 entry = cfg->irq_2_pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin*2);
452 /* Is the remote IRR bit set? */
453 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
454 spin_unlock_irqrestore(&ioapic_lock, flags);
461 spin_unlock_irqrestore(&ioapic_lock, flags);
467 struct { u32 w1, w2; };
468 struct IO_APIC_route_entry entry;
471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
473 union entry_union eu;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
477 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
478 spin_unlock_irqrestore(&ioapic_lock, flags);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
491 union entry_union eu;
493 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
494 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
500 spin_lock_irqsave(&ioapic_lock, flags);
501 __ioapic_write_entry(apic, pin, e);
502 spin_unlock_irqrestore(&ioapic_lock, flags);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic, int pin)
513 union entry_union eu = { .entry.mask = 1 };
515 spin_lock_irqsave(&ioapic_lock, flags);
516 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
517 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
518 spin_unlock_irqrestore(&ioapic_lock, flags);
522 static void send_cleanup_vector(struct irq_cfg *cfg)
524 cpumask_var_t cleanup_mask;
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
528 cfg->move_cleanup_count = 0;
529 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
530 cfg->move_cleanup_count++;
531 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
532 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
534 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
535 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
536 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
537 free_cpumask_var(cleanup_mask);
539 cfg->move_in_progress = 0;
542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
545 struct irq_pin_list *entry;
546 u8 vector = cfg->vector;
548 entry = cfg->irq_2_pin;
558 * With interrupt-remapping, destination information comes
559 * from interrupt-remapping table entry.
561 if (!irq_remapped(irq))
562 io_apic_write(apic, 0x11 + pin*2, dest);
563 reg = io_apic_read(apic, 0x10 + pin*2);
564 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
566 io_apic_modify(apic, 0x10 + pin*2, reg);
574 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
577 * Either sets desc->affinity to a valid value, and returns
578 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
579 * leaves desc->affinity untouched.
582 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
587 if (!cpumask_intersects(mask, cpu_online_mask))
591 cfg = desc->chip_data;
592 if (assign_irq_vector(irq, cfg, mask))
595 cpumask_and(desc->affinity, cfg->domain, mask);
596 set_extra_move_desc(desc, mask);
598 return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
602 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
610 cfg = desc->chip_data;
612 spin_lock_irqsave(&ioapic_lock, flags);
613 dest = set_desc_affinity(desc, mask);
614 if (dest != BAD_APICID) {
615 /* Only the high 8 bits are valid. */
616 dest = SET_APIC_LOGICAL_ID(dest);
617 __target_IO_APIC_irq(irq, dest, cfg);
619 spin_unlock_irqrestore(&ioapic_lock, flags);
623 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
625 struct irq_desc *desc;
627 desc = irq_to_desc(irq);
629 set_ioapic_affinity_irq_desc(desc, mask);
631 #endif /* CONFIG_SMP */
634 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
635 * shared ISA-space IRQs, so we have to support them. We are super
636 * fast in the common case, and fast for shared ISA-space IRQs.
638 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
640 struct irq_pin_list *entry;
642 entry = cfg->irq_2_pin;
644 entry = get_one_free_irq_2_pin(cpu);
646 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
650 cfg->irq_2_pin = entry;
656 while (entry->next) {
657 /* not again, please */
658 if (entry->apic == apic && entry->pin == pin)
664 entry->next = get_one_free_irq_2_pin(cpu);
671 * Reroute an IRQ to a different pin.
673 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
674 int oldapic, int oldpin,
675 int newapic, int newpin)
677 struct irq_pin_list *entry = cfg->irq_2_pin;
681 if (entry->apic == oldapic && entry->pin == oldpin) {
682 entry->apic = newapic;
685 /* every one is different, right? */
691 /* why? call replace before add? */
693 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
696 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
697 int mask_and, int mask_or,
698 void (*final)(struct irq_pin_list *entry))
701 struct irq_pin_list *entry;
703 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
706 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
709 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
715 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
717 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
721 static void io_apic_sync(struct irq_pin_list *entry)
724 * Synchronize the IO-APIC and the CPU by doing
725 * a dummy read from the IO-APIC
727 struct io_apic __iomem *io_apic;
728 io_apic = io_apic_base(entry->apic);
729 readl(&io_apic->data);
732 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
734 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
736 #else /* CONFIG_X86_32 */
737 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
739 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
742 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
744 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
745 IO_APIC_REDIR_MASKED, NULL);
748 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
750 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
751 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
753 #endif /* CONFIG_X86_32 */
755 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
757 struct irq_cfg *cfg = desc->chip_data;
762 spin_lock_irqsave(&ioapic_lock, flags);
763 __mask_IO_APIC_irq(cfg);
764 spin_unlock_irqrestore(&ioapic_lock, flags);
767 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
769 struct irq_cfg *cfg = desc->chip_data;
772 spin_lock_irqsave(&ioapic_lock, flags);
773 __unmask_IO_APIC_irq(cfg);
774 spin_unlock_irqrestore(&ioapic_lock, flags);
777 static void mask_IO_APIC_irq(unsigned int irq)
779 struct irq_desc *desc = irq_to_desc(irq);
781 mask_IO_APIC_irq_desc(desc);
783 static void unmask_IO_APIC_irq(unsigned int irq)
785 struct irq_desc *desc = irq_to_desc(irq);
787 unmask_IO_APIC_irq_desc(desc);
790 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
792 struct IO_APIC_route_entry entry;
794 /* Check delivery_mode to be sure we're not clearing an SMI pin */
795 entry = ioapic_read_entry(apic, pin);
796 if (entry.delivery_mode == dest_SMI)
799 * Disable it in the IO-APIC irq-routing table:
801 ioapic_mask_entry(apic, pin);
804 static void clear_IO_APIC (void)
808 for (apic = 0; apic < nr_ioapics; apic++)
809 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
810 clear_IO_APIC_pin(apic, pin);
815 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
816 * specific CPU-side IRQs.
820 static int pirq_entries[MAX_PIRQS] = {
821 [0 ... MAX_PIRQS - 1] = -1
824 static int __init ioapic_pirq_setup(char *str)
827 int ints[MAX_PIRQS+1];
829 get_options(str, ARRAY_SIZE(ints), ints);
831 apic_printk(APIC_VERBOSE, KERN_INFO
832 "PIRQ redirection, working around broken MP-BIOS.\n");
834 if (ints[0] < MAX_PIRQS)
837 for (i = 0; i < max; i++) {
838 apic_printk(APIC_VERBOSE, KERN_DEBUG
839 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
841 * PIRQs are mapped upside down, usually.
843 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
848 __setup("pirq=", ioapic_pirq_setup);
849 #endif /* CONFIG_X86_32 */
851 #ifdef CONFIG_INTR_REMAP
852 /* I/O APIC RTE contents at the OS boot up */
853 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
856 * Saves all the IO-APIC RTE's
858 int save_IO_APIC_setup(void)
860 union IO_APIC_reg_01 reg_01;
865 * The number of IO-APIC IRQ registers (== #pins):
867 for (apic = 0; apic < nr_ioapics; apic++) {
868 spin_lock_irqsave(&ioapic_lock, flags);
869 reg_01.raw = io_apic_read(apic, 1);
870 spin_unlock_irqrestore(&ioapic_lock, flags);
871 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
874 for (apic = 0; apic < nr_ioapics; apic++) {
875 early_ioapic_entries[apic] =
876 kzalloc(sizeof(struct IO_APIC_route_entry) *
877 nr_ioapic_registers[apic], GFP_KERNEL);
878 if (!early_ioapic_entries[apic])
882 for (apic = 0; apic < nr_ioapics; apic++)
883 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
884 early_ioapic_entries[apic][pin] =
885 ioapic_read_entry(apic, pin);
891 kfree(early_ioapic_entries[apic--]);
892 memset(early_ioapic_entries, 0,
893 ARRAY_SIZE(early_ioapic_entries));
898 void mask_IO_APIC_setup(void)
902 for (apic = 0; apic < nr_ioapics; apic++) {
903 if (!early_ioapic_entries[apic])
905 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
906 struct IO_APIC_route_entry entry;
908 entry = early_ioapic_entries[apic][pin];
911 ioapic_write_entry(apic, pin, entry);
917 void restore_IO_APIC_setup(void)
921 for (apic = 0; apic < nr_ioapics; apic++) {
922 if (!early_ioapic_entries[apic])
924 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
925 ioapic_write_entry(apic, pin,
926 early_ioapic_entries[apic][pin]);
927 kfree(early_ioapic_entries[apic]);
928 early_ioapic_entries[apic] = NULL;
932 void reinit_intr_remapped_IO_APIC(int intr_remapping)
935 * for now plain restore of previous settings.
936 * TBD: In the case of OS enabling interrupt-remapping,
937 * IO-APIC RTE's need to be setup to point to interrupt-remapping
938 * table entries. for now, do a plain restore, and wait for
939 * the setup_IO_APIC_irqs() to do proper initialization.
941 restore_IO_APIC_setup();
946 * Find the IRQ entry number of a certain pin.
948 static int find_irq_entry(int apic, int pin, int type)
952 for (i = 0; i < mp_irq_entries; i++)
953 if (mp_irqs[i].irqtype == type &&
954 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
955 mp_irqs[i].dstapic == MP_APIC_ALL) &&
956 mp_irqs[i].dstirq == pin)
963 * Find the pin to which IRQ[irq] (ISA) is connected
965 static int __init find_isa_irq_pin(int irq, int type)
969 for (i = 0; i < mp_irq_entries; i++) {
970 int lbus = mp_irqs[i].srcbus;
972 if (test_bit(lbus, mp_bus_not_pci) &&
973 (mp_irqs[i].irqtype == type) &&
974 (mp_irqs[i].srcbusirq == irq))
976 return mp_irqs[i].dstirq;
981 static int __init find_isa_irq_apic(int irq, int type)
985 for (i = 0; i < mp_irq_entries; i++) {
986 int lbus = mp_irqs[i].srcbus;
988 if (test_bit(lbus, mp_bus_not_pci) &&
989 (mp_irqs[i].irqtype == type) &&
990 (mp_irqs[i].srcbusirq == irq))
993 if (i < mp_irq_entries) {
995 for(apic = 0; apic < nr_ioapics; apic++) {
996 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
1005 * Find a specific PCI IRQ entry.
1006 * Not an __init, possibly needed by modules
1008 static int pin_2_irq(int idx, int apic, int pin);
1010 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1012 int apic, i, best_guess = -1;
1014 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1016 if (test_bit(bus, mp_bus_not_pci)) {
1017 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1020 for (i = 0; i < mp_irq_entries; i++) {
1021 int lbus = mp_irqs[i].srcbus;
1023 for (apic = 0; apic < nr_ioapics; apic++)
1024 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1025 mp_irqs[i].dstapic == MP_APIC_ALL)
1028 if (!test_bit(lbus, mp_bus_not_pci) &&
1029 !mp_irqs[i].irqtype &&
1031 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1032 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1034 if (!(apic || IO_APIC_IRQ(irq)))
1037 if (pin == (mp_irqs[i].srcbusirq & 3))
1040 * Use the first all-but-pin matching entry as a
1041 * best-guess fuzzy result for broken mptables.
1050 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1052 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1054 * EISA Edge/Level control register, ELCR
1056 static int EISA_ELCR(unsigned int irq)
1058 if (irq < NR_IRQS_LEGACY) {
1059 unsigned int port = 0x4d0 + (irq >> 3);
1060 return (inb(port) >> (irq & 7)) & 1;
1062 apic_printk(APIC_VERBOSE, KERN_INFO
1063 "Broken MPtable reports ISA irq %d\n", irq);
1069 /* ISA interrupts are always polarity zero edge triggered,
1070 * when listed as conforming in the MP table. */
1072 #define default_ISA_trigger(idx) (0)
1073 #define default_ISA_polarity(idx) (0)
1075 /* EISA interrupts are always polarity zero and can be edge or level
1076 * trigger depending on the ELCR value. If an interrupt is listed as
1077 * EISA conforming in the MP table, that means its trigger type must
1078 * be read in from the ELCR */
1080 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1081 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1083 /* PCI interrupts are always polarity one level triggered,
1084 * when listed as conforming in the MP table. */
1086 #define default_PCI_trigger(idx) (1)
1087 #define default_PCI_polarity(idx) (1)
1089 /* MCA interrupts are always polarity zero level triggered,
1090 * when listed as conforming in the MP table. */
1092 #define default_MCA_trigger(idx) (1)
1093 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1095 static int MPBIOS_polarity(int idx)
1097 int bus = mp_irqs[idx].srcbus;
1101 * Determine IRQ line polarity (high active or low active):
1103 switch (mp_irqs[idx].irqflag & 3)
1105 case 0: /* conforms, ie. bus-type dependent polarity */
1106 if (test_bit(bus, mp_bus_not_pci))
1107 polarity = default_ISA_polarity(idx);
1109 polarity = default_PCI_polarity(idx);
1111 case 1: /* high active */
1116 case 2: /* reserved */
1118 printk(KERN_WARNING "broken BIOS!!\n");
1122 case 3: /* low active */
1127 default: /* invalid */
1129 printk(KERN_WARNING "broken BIOS!!\n");
1137 static int MPBIOS_trigger(int idx)
1139 int bus = mp_irqs[idx].srcbus;
1143 * Determine IRQ trigger mode (edge or level sensitive):
1145 switch ((mp_irqs[idx].irqflag>>2) & 3)
1147 case 0: /* conforms, ie. bus-type dependent */
1148 if (test_bit(bus, mp_bus_not_pci))
1149 trigger = default_ISA_trigger(idx);
1151 trigger = default_PCI_trigger(idx);
1152 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1153 switch (mp_bus_id_to_type[bus]) {
1154 case MP_BUS_ISA: /* ISA pin */
1156 /* set before the switch */
1159 case MP_BUS_EISA: /* EISA pin */
1161 trigger = default_EISA_trigger(idx);
1164 case MP_BUS_PCI: /* PCI pin */
1166 /* set before the switch */
1169 case MP_BUS_MCA: /* MCA pin */
1171 trigger = default_MCA_trigger(idx);
1176 printk(KERN_WARNING "broken BIOS!!\n");
1188 case 2: /* reserved */
1190 printk(KERN_WARNING "broken BIOS!!\n");
1199 default: /* invalid */
1201 printk(KERN_WARNING "broken BIOS!!\n");
1209 static inline int irq_polarity(int idx)
1211 return MPBIOS_polarity(idx);
1214 static inline int irq_trigger(int idx)
1216 return MPBIOS_trigger(idx);
1219 int (*ioapic_renumber_irq)(int ioapic, int irq);
1220 static int pin_2_irq(int idx, int apic, int pin)
1223 int bus = mp_irqs[idx].srcbus;
1226 * Debugging check, we are in big trouble if this message pops up!
1228 if (mp_irqs[idx].dstirq != pin)
1229 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1231 if (test_bit(bus, mp_bus_not_pci)) {
1232 irq = mp_irqs[idx].srcbusirq;
1235 * PCI IRQs are mapped in order
1239 irq += nr_ioapic_registers[i++];
1242 * For MPS mode, so far only needed by ES7000 platform
1244 if (ioapic_renumber_irq)
1245 irq = ioapic_renumber_irq(apic, irq);
1248 #ifdef CONFIG_X86_32
1250 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1252 if ((pin >= 16) && (pin <= 23)) {
1253 if (pirq_entries[pin-16] != -1) {
1254 if (!pirq_entries[pin-16]) {
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256 "disabling PIRQ%d\n", pin-16);
1258 irq = pirq_entries[pin-16];
1259 apic_printk(APIC_VERBOSE, KERN_DEBUG
1260 "using PIRQ%d -> IRQ %d\n",
1270 void lock_vector_lock(void)
1272 /* Used to the online set of cpus does not change
1273 * during assign_irq_vector.
1275 spin_lock(&vector_lock);
1278 void unlock_vector_lock(void)
1280 spin_unlock(&vector_lock);
1284 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1287 * NOTE! The local APIC isn't very good at handling
1288 * multiple interrupts at the same interrupt level.
1289 * As the interrupt level is determined by taking the
1290 * vector number and shifting that right by 4, we
1291 * want to spread these out a bit so that they don't
1292 * all fall in the same interrupt level.
1294 * Also, we've got to be careful not to trash gate
1295 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1297 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1298 unsigned int old_vector;
1300 cpumask_var_t tmp_mask;
1302 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1305 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1308 old_vector = cfg->vector;
1310 cpumask_and(tmp_mask, mask, cpu_online_mask);
1311 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1312 if (!cpumask_empty(tmp_mask)) {
1313 free_cpumask_var(tmp_mask);
1318 /* Only try and allocate irqs on cpus that are present */
1320 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1324 apic->vector_allocation_domain(cpu, tmp_mask);
1326 vector = current_vector;
1327 offset = current_offset;
1330 if (vector >= first_system_vector) {
1331 /* If out of vectors on large boxen, must share them. */
1332 offset = (offset + 1) % 8;
1333 vector = FIRST_DEVICE_VECTOR + offset;
1335 if (unlikely(current_vector == vector))
1338 if (test_bit(vector, used_vectors))
1341 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1342 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1345 current_vector = vector;
1346 current_offset = offset;
1348 cfg->move_in_progress = 1;
1349 cpumask_copy(cfg->old_domain, cfg->domain);
1351 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1352 per_cpu(vector_irq, new_cpu)[vector] = irq;
1353 cfg->vector = vector;
1354 cpumask_copy(cfg->domain, tmp_mask);
1358 free_cpumask_var(tmp_mask);
1363 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1366 unsigned long flags;
1368 spin_lock_irqsave(&vector_lock, flags);
1369 err = __assign_irq_vector(irq, cfg, mask);
1370 spin_unlock_irqrestore(&vector_lock, flags);
1374 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1378 BUG_ON(!cfg->vector);
1380 vector = cfg->vector;
1381 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1382 per_cpu(vector_irq, cpu)[vector] = -1;
1385 cpumask_clear(cfg->domain);
1387 if (likely(!cfg->move_in_progress))
1389 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1390 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1392 if (per_cpu(vector_irq, cpu)[vector] != irq)
1394 per_cpu(vector_irq, cpu)[vector] = -1;
1398 cfg->move_in_progress = 0;
1401 void __setup_vector_irq(int cpu)
1403 /* Initialize vector_irq on a new cpu */
1404 /* This function must be called with vector_lock held */
1406 struct irq_cfg *cfg;
1407 struct irq_desc *desc;
1409 /* Mark the inuse vectors */
1410 for_each_irq_desc(irq, desc) {
1411 cfg = desc->chip_data;
1412 if (!cpumask_test_cpu(cpu, cfg->domain))
1414 vector = cfg->vector;
1415 per_cpu(vector_irq, cpu)[vector] = irq;
1417 /* Mark the free vectors */
1418 for (vector = 0; vector < NR_VECTORS; ++vector) {
1419 irq = per_cpu(vector_irq, cpu)[vector];
1424 if (!cpumask_test_cpu(cpu, cfg->domain))
1425 per_cpu(vector_irq, cpu)[vector] = -1;
1429 static struct irq_chip ioapic_chip;
1430 static struct irq_chip ir_ioapic_chip;
1432 #define IOAPIC_AUTO -1
1433 #define IOAPIC_EDGE 0
1434 #define IOAPIC_LEVEL 1
1436 #ifdef CONFIG_X86_32
1437 static inline int IO_APIC_irq_trigger(int irq)
1441 for (apic = 0; apic < nr_ioapics; apic++) {
1442 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1443 idx = find_irq_entry(apic, pin, mp_INT);
1444 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1445 return irq_trigger(idx);
1449 * nonexistent IRQs are edge default
1454 static inline int IO_APIC_irq_trigger(int irq)
1460 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1463 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1464 trigger == IOAPIC_LEVEL)
1465 desc->status |= IRQ_LEVEL;
1467 desc->status &= ~IRQ_LEVEL;
1469 if (irq_remapped(irq)) {
1470 desc->status |= IRQ_MOVE_PCNTXT;
1472 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1476 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1477 handle_edge_irq, "edge");
1481 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1482 trigger == IOAPIC_LEVEL)
1483 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1487 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1488 handle_edge_irq, "edge");
1491 int setup_ioapic_entry(int apic_id, int irq,
1492 struct IO_APIC_route_entry *entry,
1493 unsigned int destination, int trigger,
1494 int polarity, int vector, int pin)
1497 * add it to the IO-APIC irq-routing table:
1499 memset(entry,0,sizeof(*entry));
1501 if (intr_remapping_enabled) {
1502 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1504 struct IR_IO_APIC_route_entry *ir_entry =
1505 (struct IR_IO_APIC_route_entry *) entry;
1509 panic("No mapping iommu for ioapic %d\n", apic_id);
1511 index = alloc_irte(iommu, irq, 1);
1513 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1515 memset(&irte, 0, sizeof(irte));
1518 irte.dst_mode = apic->irq_dest_mode;
1520 * Trigger mode in the IRTE will always be edge, and the
1521 * actual level or edge trigger will be setup in the IO-APIC
1522 * RTE. This will help simplify level triggered irq migration.
1523 * For more details, see the comments above explainig IO-APIC
1524 * irq migration in the presence of interrupt-remapping.
1526 irte.trigger_mode = 0;
1527 irte.dlvry_mode = apic->irq_delivery_mode;
1528 irte.vector = vector;
1529 irte.dest_id = IRTE_DEST(destination);
1531 modify_irte(irq, &irte);
1533 ir_entry->index2 = (index >> 15) & 0x1;
1535 ir_entry->format = 1;
1536 ir_entry->index = (index & 0x7fff);
1538 * IO-APIC RTE will be configured with virtual vector.
1539 * irq handler will do the explicit EOI to the io-apic.
1541 ir_entry->vector = pin;
1543 entry->delivery_mode = apic->irq_delivery_mode;
1544 entry->dest_mode = apic->irq_dest_mode;
1545 entry->dest = destination;
1546 entry->vector = vector;
1549 entry->mask = 0; /* enable IRQ */
1550 entry->trigger = trigger;
1551 entry->polarity = polarity;
1553 /* Mask level triggered irqs.
1554 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1561 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1562 int trigger, int polarity)
1564 struct irq_cfg *cfg;
1565 struct IO_APIC_route_entry entry;
1568 if (!IO_APIC_IRQ(irq))
1571 cfg = desc->chip_data;
1573 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1576 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1578 apic_printk(APIC_VERBOSE,KERN_DEBUG
1579 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1580 "IRQ %d Mode:%i Active:%i)\n",
1581 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1582 irq, trigger, polarity);
1585 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1586 dest, trigger, polarity, cfg->vector, pin)) {
1587 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1588 mp_ioapics[apic_id].apicid, pin);
1589 __clear_irq_vector(irq, cfg);
1593 ioapic_register_intr(irq, desc, trigger);
1594 if (irq < NR_IRQS_LEGACY)
1595 disable_8259A_irq(irq);
1597 ioapic_write_entry(apic_id, pin, entry);
1600 static void __init setup_IO_APIC_irqs(void)
1602 int apic_id, pin, idx, irq;
1604 struct irq_desc *desc;
1605 struct irq_cfg *cfg;
1606 int cpu = boot_cpu_id;
1608 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1610 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1611 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1613 idx = find_irq_entry(apic_id, pin, mp_INT);
1617 apic_printk(APIC_VERBOSE,
1618 KERN_DEBUG " %d-%d",
1619 mp_ioapics[apic_id].apicid, pin);
1621 apic_printk(APIC_VERBOSE, " %d-%d",
1622 mp_ioapics[apic_id].apicid, pin);
1626 apic_printk(APIC_VERBOSE,
1627 " (apicid-pin) not connected\n");
1631 irq = pin_2_irq(idx, apic_id, pin);
1634 * Skip the timer IRQ if there's a quirk handler
1635 * installed and if it returns 1:
1637 if (apic->multi_timer_check &&
1638 apic->multi_timer_check(apic_id, irq))
1641 desc = irq_to_desc_alloc_cpu(irq, cpu);
1643 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1646 cfg = desc->chip_data;
1647 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1649 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1650 irq_trigger(idx), irq_polarity(idx));
1655 apic_printk(APIC_VERBOSE,
1656 " (apicid-pin) not connected\n");
1660 * Set up the timer pin, possibly with the 8259A-master behind.
1662 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1665 struct IO_APIC_route_entry entry;
1667 if (intr_remapping_enabled)
1670 memset(&entry, 0, sizeof(entry));
1673 * We use logical delivery to get the timer IRQ
1676 entry.dest_mode = apic->irq_dest_mode;
1677 entry.mask = 0; /* don't mask IRQ for edge */
1678 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1679 entry.delivery_mode = apic->irq_delivery_mode;
1682 entry.vector = vector;
1685 * The timer IRQ doesn't have to know that behind the
1686 * scene we may have a 8259A-master in AEOI mode ...
1688 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1691 * Add it to the IO-APIC irq-routing table:
1693 ioapic_write_entry(apic_id, pin, entry);
1697 __apicdebuginit(void) print_IO_APIC(void)
1700 union IO_APIC_reg_00 reg_00;
1701 union IO_APIC_reg_01 reg_01;
1702 union IO_APIC_reg_02 reg_02;
1703 union IO_APIC_reg_03 reg_03;
1704 unsigned long flags;
1705 struct irq_cfg *cfg;
1706 struct irq_desc *desc;
1709 if (apic_verbosity == APIC_QUIET)
1712 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1713 for (i = 0; i < nr_ioapics; i++)
1714 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1715 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1718 * We are a bit conservative about what we expect. We have to
1719 * know about every hardware change ASAP.
1721 printk(KERN_INFO "testing the IO APIC.......................\n");
1723 for (apic = 0; apic < nr_ioapics; apic++) {
1725 spin_lock_irqsave(&ioapic_lock, flags);
1726 reg_00.raw = io_apic_read(apic, 0);
1727 reg_01.raw = io_apic_read(apic, 1);
1728 if (reg_01.bits.version >= 0x10)
1729 reg_02.raw = io_apic_read(apic, 2);
1730 if (reg_01.bits.version >= 0x20)
1731 reg_03.raw = io_apic_read(apic, 3);
1732 spin_unlock_irqrestore(&ioapic_lock, flags);
1735 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1736 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1737 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1738 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1739 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1741 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1742 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1744 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1745 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1748 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1749 * but the value of reg_02 is read as the previous read register
1750 * value, so ignore it if reg_02 == reg_01.
1752 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1753 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1754 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1758 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1759 * or reg_03, but the value of reg_0[23] is read as the previous read
1760 * register value, so ignore it if reg_03 == reg_0[12].
1762 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1763 reg_03.raw != reg_01.raw) {
1764 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1765 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1768 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1770 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1771 " Stat Dmod Deli Vect: \n");
1773 for (i = 0; i <= reg_01.bits.entries; i++) {
1774 struct IO_APIC_route_entry entry;
1776 entry = ioapic_read_entry(apic, i);
1778 printk(KERN_DEBUG " %02x %03X ",
1783 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1788 entry.delivery_status,
1790 entry.delivery_mode,
1795 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1796 for_each_irq_desc(irq, desc) {
1797 struct irq_pin_list *entry;
1799 cfg = desc->chip_data;
1800 entry = cfg->irq_2_pin;
1803 printk(KERN_DEBUG "IRQ%d ", irq);
1805 printk("-> %d:%d", entry->apic, entry->pin);
1808 entry = entry->next;
1813 printk(KERN_INFO ".................................... done.\n");
1818 __apicdebuginit(void) print_APIC_bitfield(int base)
1823 if (apic_verbosity == APIC_QUIET)
1826 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1827 for (i = 0; i < 8; i++) {
1828 v = apic_read(base + i*0x10);
1829 for (j = 0; j < 32; j++) {
1839 __apicdebuginit(void) print_local_APIC(void *dummy)
1841 unsigned int v, ver, maxlvt;
1844 if (apic_verbosity == APIC_QUIET)
1847 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1848 smp_processor_id(), hard_smp_processor_id());
1849 v = apic_read(APIC_ID);
1850 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1851 v = apic_read(APIC_LVR);
1852 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1853 ver = GET_APIC_VERSION(v);
1854 maxlvt = lapic_get_maxlvt();
1856 v = apic_read(APIC_TASKPRI);
1857 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1859 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1860 if (!APIC_XAPIC(ver)) {
1861 v = apic_read(APIC_ARBPRI);
1862 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1863 v & APIC_ARBPRI_MASK);
1865 v = apic_read(APIC_PROCPRI);
1866 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1870 * Remote read supported only in the 82489DX and local APIC for
1871 * Pentium processors.
1873 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1874 v = apic_read(APIC_RRR);
1875 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1878 v = apic_read(APIC_LDR);
1879 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1880 if (!x2apic_enabled()) {
1881 v = apic_read(APIC_DFR);
1882 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1884 v = apic_read(APIC_SPIV);
1885 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1887 printk(KERN_DEBUG "... APIC ISR field:\n");
1888 print_APIC_bitfield(APIC_ISR);
1889 printk(KERN_DEBUG "... APIC TMR field:\n");
1890 print_APIC_bitfield(APIC_TMR);
1891 printk(KERN_DEBUG "... APIC IRR field:\n");
1892 print_APIC_bitfield(APIC_IRR);
1894 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1895 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1896 apic_write(APIC_ESR, 0);
1898 v = apic_read(APIC_ESR);
1899 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1902 icr = apic_icr_read();
1903 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1904 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1906 v = apic_read(APIC_LVTT);
1907 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1909 if (maxlvt > 3) { /* PC is LVT#4. */
1910 v = apic_read(APIC_LVTPC);
1911 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1913 v = apic_read(APIC_LVT0);
1914 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1915 v = apic_read(APIC_LVT1);
1916 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1918 if (maxlvt > 2) { /* ERR is LVT#3. */
1919 v = apic_read(APIC_LVTERR);
1920 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1923 v = apic_read(APIC_TMICT);
1924 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1925 v = apic_read(APIC_TMCCT);
1926 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1927 v = apic_read(APIC_TDCR);
1928 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1932 __apicdebuginit(void) print_all_local_APICs(void)
1937 for_each_online_cpu(cpu)
1938 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1942 __apicdebuginit(void) print_PIC(void)
1945 unsigned long flags;
1947 if (apic_verbosity == APIC_QUIET)
1950 printk(KERN_DEBUG "\nprinting PIC contents\n");
1952 spin_lock_irqsave(&i8259A_lock, flags);
1954 v = inb(0xa1) << 8 | inb(0x21);
1955 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1957 v = inb(0xa0) << 8 | inb(0x20);
1958 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1962 v = inb(0xa0) << 8 | inb(0x20);
1966 spin_unlock_irqrestore(&i8259A_lock, flags);
1968 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1970 v = inb(0x4d1) << 8 | inb(0x4d0);
1971 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1974 __apicdebuginit(int) print_all_ICs(void)
1977 print_all_local_APICs();
1983 fs_initcall(print_all_ICs);
1986 /* Where if anywhere is the i8259 connect in external int mode */
1987 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1989 void __init enable_IO_APIC(void)
1991 union IO_APIC_reg_01 reg_01;
1992 int i8259_apic, i8259_pin;
1994 unsigned long flags;
1997 * The number of IO-APIC IRQ registers (== #pins):
1999 for (apic = 0; apic < nr_ioapics; apic++) {
2000 spin_lock_irqsave(&ioapic_lock, flags);
2001 reg_01.raw = io_apic_read(apic, 1);
2002 spin_unlock_irqrestore(&ioapic_lock, flags);
2003 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2005 for(apic = 0; apic < nr_ioapics; apic++) {
2007 /* See if any of the pins is in ExtINT mode */
2008 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2009 struct IO_APIC_route_entry entry;
2010 entry = ioapic_read_entry(apic, pin);
2012 /* If the interrupt line is enabled and in ExtInt mode
2013 * I have found the pin where the i8259 is connected.
2015 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2016 ioapic_i8259.apic = apic;
2017 ioapic_i8259.pin = pin;
2023 /* Look to see what if the MP table has reported the ExtINT */
2024 /* If we could not find the appropriate pin by looking at the ioapic
2025 * the i8259 probably is not connected the ioapic but give the
2026 * mptable a chance anyway.
2028 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2029 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2030 /* Trust the MP table if nothing is setup in the hardware */
2031 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2032 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2033 ioapic_i8259.pin = i8259_pin;
2034 ioapic_i8259.apic = i8259_apic;
2036 /* Complain if the MP table and the hardware disagree */
2037 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2038 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2040 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2044 * Do not trust the IO-APIC being empty at bootup
2050 * Not an __init, needed by the reboot code
2052 void disable_IO_APIC(void)
2055 * Clear the IO-APIC before rebooting:
2060 * If the i8259 is routed through an IOAPIC
2061 * Put that IOAPIC in virtual wire mode
2062 * so legacy interrupts can be delivered.
2064 * With interrupt-remapping, for now we will use virtual wire A mode,
2065 * as virtual wire B is little complex (need to configure both
2066 * IOAPIC RTE aswell as interrupt-remapping table entry).
2067 * As this gets called during crash dump, keep this simple for now.
2069 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2070 struct IO_APIC_route_entry entry;
2072 memset(&entry, 0, sizeof(entry));
2073 entry.mask = 0; /* Enabled */
2074 entry.trigger = 0; /* Edge */
2076 entry.polarity = 0; /* High */
2077 entry.delivery_status = 0;
2078 entry.dest_mode = 0; /* Physical */
2079 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2081 entry.dest = read_apic_id();
2084 * Add it to the IO-APIC irq-routing table:
2086 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2090 * Use virtual wire A mode when interrupt remapping is enabled.
2092 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2095 #ifdef CONFIG_X86_32
2097 * function to set the IO-APIC physical IDs based on the
2098 * values stored in the MPC table.
2100 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2103 static void __init setup_ioapic_ids_from_mpc(void)
2105 union IO_APIC_reg_00 reg_00;
2106 physid_mask_t phys_id_present_map;
2109 unsigned char old_id;
2110 unsigned long flags;
2112 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2116 * Don't check I/O APIC IDs for xAPIC systems. They have
2117 * no meaning without the serial APIC bus.
2119 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2120 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2123 * This is broken; anything with a real cpu count has to
2124 * circumvent this idiocy regardless.
2126 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2129 * Set the IOAPIC ID to the value stored in the MPC table.
2131 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2133 /* Read the register 0 value */
2134 spin_lock_irqsave(&ioapic_lock, flags);
2135 reg_00.raw = io_apic_read(apic_id, 0);
2136 spin_unlock_irqrestore(&ioapic_lock, flags);
2138 old_id = mp_ioapics[apic_id].apicid;
2140 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2141 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2142 apic_id, mp_ioapics[apic_id].apicid);
2143 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2145 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2149 * Sanity check, is the ID really free? Every APIC in a
2150 * system must have a unique ID or we get lots of nice
2151 * 'stuck on smp_invalidate_needed IPI wait' messages.
2153 if (apic->check_apicid_used(phys_id_present_map,
2154 mp_ioapics[apic_id].apicid)) {
2155 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2156 apic_id, mp_ioapics[apic_id].apicid);
2157 for (i = 0; i < get_physical_broadcast(); i++)
2158 if (!physid_isset(i, phys_id_present_map))
2160 if (i >= get_physical_broadcast())
2161 panic("Max APIC ID exceeded!\n");
2162 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2164 physid_set(i, phys_id_present_map);
2165 mp_ioapics[apic_id].apicid = i;
2168 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2169 apic_printk(APIC_VERBOSE, "Setting %d in the "
2170 "phys_id_present_map\n",
2171 mp_ioapics[apic_id].apicid);
2172 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2177 * We need to adjust the IRQ routing table
2178 * if the ID changed.
2180 if (old_id != mp_ioapics[apic_id].apicid)
2181 for (i = 0; i < mp_irq_entries; i++)
2182 if (mp_irqs[i].dstapic == old_id)
2184 = mp_ioapics[apic_id].apicid;
2187 * Read the right value from the MPC table and
2188 * write it into the ID register.
2190 apic_printk(APIC_VERBOSE, KERN_INFO
2191 "...changing IO-APIC physical APIC ID to %d ...",
2192 mp_ioapics[apic_id].apicid);
2194 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2195 spin_lock_irqsave(&ioapic_lock, flags);
2196 io_apic_write(apic_id, 0, reg_00.raw);
2197 spin_unlock_irqrestore(&ioapic_lock, flags);
2202 spin_lock_irqsave(&ioapic_lock, flags);
2203 reg_00.raw = io_apic_read(apic_id, 0);
2204 spin_unlock_irqrestore(&ioapic_lock, flags);
2205 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2206 printk("could not set ID!\n");
2208 apic_printk(APIC_VERBOSE, " ok.\n");
2213 int no_timer_check __initdata;
2215 static int __init notimercheck(char *s)
2220 __setup("no_timer_check", notimercheck);
2223 * There is a nasty bug in some older SMP boards, their mptable lies
2224 * about the timer IRQ. We do the following to work around the situation:
2226 * - timer IRQ defaults to IO-APIC IRQ
2227 * - if this function detects that timer IRQs are defunct, then we fall
2228 * back to ISA timer IRQs
2230 static int __init timer_irq_works(void)
2232 unsigned long t1 = jiffies;
2233 unsigned long flags;
2238 local_save_flags(flags);
2240 /* Let ten ticks pass... */
2241 mdelay((10 * 1000) / HZ);
2242 local_irq_restore(flags);
2245 * Expect a few ticks at least, to be sure some possible
2246 * glue logic does not lock up after one or two first
2247 * ticks in a non-ExtINT mode. Also the local APIC
2248 * might have cached one ExtINT interrupt. Finally, at
2249 * least one tick may be lost due to delays.
2253 if (time_after(jiffies, t1 + 4))
2259 * In the SMP+IOAPIC case it might happen that there are an unspecified
2260 * number of pending IRQ events unhandled. These cases are very rare,
2261 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2262 * better to do it this way as thus we do not have to be aware of
2263 * 'pending' interrupts in the IRQ path, except at this point.
2266 * Edge triggered needs to resend any interrupt
2267 * that was delayed but this is now handled in the device
2272 * Starting up a edge-triggered IO-APIC interrupt is
2273 * nasty - we need to make sure that we get the edge.
2274 * If it is already asserted for some reason, we need
2275 * return 1 to indicate that is was pending.
2277 * This is not complete - we should be able to fake
2278 * an edge even if it isn't on the 8259A...
2281 static unsigned int startup_ioapic_irq(unsigned int irq)
2283 int was_pending = 0;
2284 unsigned long flags;
2285 struct irq_cfg *cfg;
2287 spin_lock_irqsave(&ioapic_lock, flags);
2288 if (irq < NR_IRQS_LEGACY) {
2289 disable_8259A_irq(irq);
2290 if (i8259A_irq_pending(irq))
2294 __unmask_IO_APIC_irq(cfg);
2295 spin_unlock_irqrestore(&ioapic_lock, flags);
2300 #ifdef CONFIG_X86_64
2301 static int ioapic_retrigger_irq(unsigned int irq)
2304 struct irq_cfg *cfg = irq_cfg(irq);
2305 unsigned long flags;
2307 spin_lock_irqsave(&vector_lock, flags);
2308 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2309 spin_unlock_irqrestore(&vector_lock, flags);
2314 static int ioapic_retrigger_irq(unsigned int irq)
2316 apic->send_IPI_self(irq_cfg(irq)->vector);
2323 * Level and edge triggered IO-APIC interrupts need different handling,
2324 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2325 * handled with the level-triggered descriptor, but that one has slightly
2326 * more overhead. Level-triggered interrupts cannot be handled with the
2327 * edge-triggered handler, without risking IRQ storms and other ugly
2333 #ifdef CONFIG_INTR_REMAP
2336 * Migrate the IO-APIC irq in the presence of intr-remapping.
2338 * For both level and edge triggered, irq migration is a simple atomic
2339 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2341 * For level triggered, we eliminate the io-apic RTE modification (with the
2342 * updated vector information), by using a virtual vector (io-apic pin number).
2343 * Real vector that is used for interrupting cpu will be coming from
2344 * the interrupt-remapping table entry.
2347 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2349 struct irq_cfg *cfg;
2354 if (!cpumask_intersects(mask, cpu_online_mask))
2358 if (get_irte(irq, &irte))
2361 cfg = desc->chip_data;
2362 if (assign_irq_vector(irq, cfg, mask))
2365 set_extra_move_desc(desc, mask);
2367 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2369 irte.vector = cfg->vector;
2370 irte.dest_id = IRTE_DEST(dest);
2373 * Modified the IRTE and flushes the Interrupt entry cache.
2375 modify_irte(irq, &irte);
2377 if (cfg->move_in_progress)
2378 send_cleanup_vector(cfg);
2380 cpumask_copy(desc->affinity, mask);
2384 * Migrates the IRQ destination in the process context.
2386 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2387 const struct cpumask *mask)
2389 migrate_ioapic_irq_desc(desc, mask);
2391 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2392 const struct cpumask *mask)
2394 struct irq_desc *desc = irq_to_desc(irq);
2396 set_ir_ioapic_affinity_irq_desc(desc, mask);
2399 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2400 const struct cpumask *mask)
2405 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2407 unsigned vector, me;
2413 me = smp_processor_id();
2414 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2417 struct irq_desc *desc;
2418 struct irq_cfg *cfg;
2419 irq = __get_cpu_var(vector_irq)[vector];
2424 desc = irq_to_desc(irq);
2429 spin_lock(&desc->lock);
2430 if (!cfg->move_cleanup_count)
2433 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2436 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2438 * Check if the vector that needs to be cleanedup is
2439 * registered at the cpu's IRR. If so, then this is not
2440 * the best time to clean it up. Lets clean it up in the
2441 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2444 if (irr & (1 << (vector % 32))) {
2445 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2448 __get_cpu_var(vector_irq)[vector] = -1;
2449 cfg->move_cleanup_count--;
2451 spin_unlock(&desc->lock);
2457 static void irq_complete_move(struct irq_desc **descp)
2459 struct irq_desc *desc = *descp;
2460 struct irq_cfg *cfg = desc->chip_data;
2461 unsigned vector, me;
2463 if (likely(!cfg->move_in_progress)) {
2464 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2465 if (likely(!cfg->move_desc_pending))
2468 /* domain has not changed, but affinity did */
2469 me = smp_processor_id();
2470 if (cpumask_test_cpu(me, desc->affinity)) {
2471 *descp = desc = move_irq_desc(desc, me);
2472 /* get the new one */
2473 cfg = desc->chip_data;
2474 cfg->move_desc_pending = 0;
2480 vector = ~get_irq_regs()->orig_ax;
2481 me = smp_processor_id();
2483 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2484 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2485 *descp = desc = move_irq_desc(desc, me);
2486 /* get the new one */
2487 cfg = desc->chip_data;
2489 send_cleanup_vector(cfg);
2493 static inline void irq_complete_move(struct irq_desc **descp) {}
2496 #ifdef CONFIG_INTR_REMAP
2497 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2500 struct irq_pin_list *entry;
2502 entry = cfg->irq_2_pin;
2510 io_apic_eoi(apic, pin);
2511 entry = entry->next;
2516 eoi_ioapic_irq(struct irq_desc *desc)
2518 struct irq_cfg *cfg;
2519 unsigned long flags;
2523 cfg = desc->chip_data;
2525 spin_lock_irqsave(&ioapic_lock, flags);
2526 __eoi_ioapic_irq(irq, cfg);
2527 spin_unlock_irqrestore(&ioapic_lock, flags);
2530 static void ack_x2apic_level(unsigned int irq)
2532 struct irq_desc *desc = irq_to_desc(irq);
2534 eoi_ioapic_irq(desc);
2537 static void ack_x2apic_edge(unsigned int irq)
2544 static void ack_apic_edge(unsigned int irq)
2546 struct irq_desc *desc = irq_to_desc(irq);
2548 irq_complete_move(&desc);
2549 move_native_irq(irq);
2553 atomic_t irq_mis_count;
2555 static void ack_apic_level(unsigned int irq)
2557 struct irq_desc *desc = irq_to_desc(irq);
2559 #ifdef CONFIG_X86_32
2563 struct irq_cfg *cfg;
2564 int do_unmask_irq = 0;
2566 irq_complete_move(&desc);
2567 #ifdef CONFIG_GENERIC_PENDING_IRQ
2568 /* If we are moving the irq we need to mask it */
2569 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2571 mask_IO_APIC_irq_desc(desc);
2575 #ifdef CONFIG_X86_32
2577 * It appears there is an erratum which affects at least version 0x11
2578 * of I/O APIC (that's the 82093AA and cores integrated into various
2579 * chipsets). Under certain conditions a level-triggered interrupt is
2580 * erroneously delivered as edge-triggered one but the respective IRR
2581 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2582 * message but it will never arrive and further interrupts are blocked
2583 * from the source. The exact reason is so far unknown, but the
2584 * phenomenon was observed when two consecutive interrupt requests
2585 * from a given source get delivered to the same CPU and the source is
2586 * temporarily disabled in between.
2588 * A workaround is to simulate an EOI message manually. We achieve it
2589 * by setting the trigger mode to edge and then to level when the edge
2590 * trigger mode gets detected in the TMR of a local APIC for a
2591 * level-triggered interrupt. We mask the source for the time of the
2592 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2593 * The idea is from Manfred Spraul. --macro
2595 cfg = desc->chip_data;
2598 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2602 * We must acknowledge the irq before we move it or the acknowledge will
2603 * not propagate properly.
2607 /* Now we can move and renable the irq */
2608 if (unlikely(do_unmask_irq)) {
2609 /* Only migrate the irq if the ack has been received.
2611 * On rare occasions the broadcast level triggered ack gets
2612 * delayed going to ioapics, and if we reprogram the
2613 * vector while Remote IRR is still set the irq will never
2616 * To prevent this scenario we read the Remote IRR bit
2617 * of the ioapic. This has two effects.
2618 * - On any sane system the read of the ioapic will
2619 * flush writes (and acks) going to the ioapic from
2621 * - We get to see if the ACK has actually been delivered.
2623 * Based on failed experiments of reprogramming the
2624 * ioapic entry from outside of irq context starting
2625 * with masking the ioapic entry and then polling until
2626 * Remote IRR was clear before reprogramming the
2627 * ioapic I don't trust the Remote IRR bit to be
2628 * completey accurate.
2630 * However there appears to be no other way to plug
2631 * this race, so if the Remote IRR bit is not
2632 * accurate and is causing problems then it is a hardware bug
2633 * and you can go talk to the chipset vendor about it.
2635 cfg = desc->chip_data;
2636 if (!io_apic_level_ack_pending(cfg))
2637 move_masked_irq(irq);
2638 unmask_IO_APIC_irq_desc(desc);
2641 #ifdef CONFIG_X86_32
2642 if (!(v & (1 << (i & 0x1f)))) {
2643 atomic_inc(&irq_mis_count);
2644 spin_lock(&ioapic_lock);
2645 __mask_and_edge_IO_APIC_irq(cfg);
2646 __unmask_and_level_IO_APIC_irq(cfg);
2647 spin_unlock(&ioapic_lock);
2652 static struct irq_chip ioapic_chip __read_mostly = {
2654 .startup = startup_ioapic_irq,
2655 .mask = mask_IO_APIC_irq,
2656 .unmask = unmask_IO_APIC_irq,
2657 .ack = ack_apic_edge,
2658 .eoi = ack_apic_level,
2660 .set_affinity = set_ioapic_affinity_irq,
2662 .retrigger = ioapic_retrigger_irq,
2665 static struct irq_chip ir_ioapic_chip __read_mostly = {
2666 .name = "IR-IO-APIC",
2667 .startup = startup_ioapic_irq,
2668 .mask = mask_IO_APIC_irq,
2669 .unmask = unmask_IO_APIC_irq,
2670 #ifdef CONFIG_INTR_REMAP
2671 .ack = ack_x2apic_edge,
2672 .eoi = ack_x2apic_level,
2674 .set_affinity = set_ir_ioapic_affinity_irq,
2677 .retrigger = ioapic_retrigger_irq,
2680 static inline void init_IO_APIC_traps(void)
2683 struct irq_desc *desc;
2684 struct irq_cfg *cfg;
2687 * NOTE! The local APIC isn't very good at handling
2688 * multiple interrupts at the same interrupt level.
2689 * As the interrupt level is determined by taking the
2690 * vector number and shifting that right by 4, we
2691 * want to spread these out a bit so that they don't
2692 * all fall in the same interrupt level.
2694 * Also, we've got to be careful not to trash gate
2695 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2697 for_each_irq_desc(irq, desc) {
2698 cfg = desc->chip_data;
2699 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2701 * Hmm.. We don't have an entry for this,
2702 * so default to an old-fashioned 8259
2703 * interrupt if we can..
2705 if (irq < NR_IRQS_LEGACY)
2706 make_8259A_irq(irq);
2708 /* Strange. Oh, well.. */
2709 desc->chip = &no_irq_chip;
2715 * The local APIC irq-chip implementation:
2718 static void mask_lapic_irq(unsigned int irq)
2722 v = apic_read(APIC_LVT0);
2723 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2726 static void unmask_lapic_irq(unsigned int irq)
2730 v = apic_read(APIC_LVT0);
2731 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2734 static void ack_lapic_irq(unsigned int irq)
2739 static struct irq_chip lapic_chip __read_mostly = {
2740 .name = "local-APIC",
2741 .mask = mask_lapic_irq,
2742 .unmask = unmask_lapic_irq,
2743 .ack = ack_lapic_irq,
2746 static void lapic_register_intr(int irq, struct irq_desc *desc)
2748 desc->status &= ~IRQ_LEVEL;
2749 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2753 static void __init setup_nmi(void)
2756 * Dirty trick to enable the NMI watchdog ...
2757 * We put the 8259A master into AEOI mode and
2758 * unmask on all local APICs LVT0 as NMI.
2760 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2761 * is from Maciej W. Rozycki - so we do not have to EOI from
2762 * the NMI handler or the timer interrupt.
2764 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2766 enable_NMI_through_LVT0();
2768 apic_printk(APIC_VERBOSE, " done.\n");
2772 * This looks a bit hackish but it's about the only one way of sending
2773 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2774 * not support the ExtINT mode, unfortunately. We need to send these
2775 * cycles as some i82489DX-based boards have glue logic that keeps the
2776 * 8259A interrupt line asserted until INTA. --macro
2778 static inline void __init unlock_ExtINT_logic(void)
2781 struct IO_APIC_route_entry entry0, entry1;
2782 unsigned char save_control, save_freq_select;
2784 pin = find_isa_irq_pin(8, mp_INT);
2789 apic = find_isa_irq_apic(8, mp_INT);
2795 entry0 = ioapic_read_entry(apic, pin);
2796 clear_IO_APIC_pin(apic, pin);
2798 memset(&entry1, 0, sizeof(entry1));
2800 entry1.dest_mode = 0; /* physical delivery */
2801 entry1.mask = 0; /* unmask IRQ now */
2802 entry1.dest = hard_smp_processor_id();
2803 entry1.delivery_mode = dest_ExtINT;
2804 entry1.polarity = entry0.polarity;
2808 ioapic_write_entry(apic, pin, entry1);
2810 save_control = CMOS_READ(RTC_CONTROL);
2811 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2812 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2814 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2819 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2823 CMOS_WRITE(save_control, RTC_CONTROL);
2824 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2825 clear_IO_APIC_pin(apic, pin);
2827 ioapic_write_entry(apic, pin, entry0);
2830 static int disable_timer_pin_1 __initdata;
2831 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2832 static int __init disable_timer_pin_setup(char *arg)
2834 disable_timer_pin_1 = 1;
2837 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2839 int timer_through_8259 __initdata;
2842 * This code may look a bit paranoid, but it's supposed to cooperate with
2843 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2844 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2845 * fanatically on his truly buggy board.
2847 * FIXME: really need to revamp this for all platforms.
2849 static inline void __init check_timer(void)
2851 struct irq_desc *desc = irq_to_desc(0);
2852 struct irq_cfg *cfg = desc->chip_data;
2853 int cpu = boot_cpu_id;
2854 int apic1, pin1, apic2, pin2;
2855 unsigned long flags;
2858 local_irq_save(flags);
2861 * get/set the timer IRQ vector:
2863 disable_8259A_irq(0);
2864 assign_irq_vector(0, cfg, apic->target_cpus());
2867 * As IRQ0 is to be enabled in the 8259A, the virtual
2868 * wire has to be disabled in the local APIC. Also
2869 * timer interrupts need to be acknowledged manually in
2870 * the 8259A for the i82489DX when using the NMI
2871 * watchdog as that APIC treats NMIs as level-triggered.
2872 * The AEOI mode will finish them in the 8259A
2875 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2877 #ifdef CONFIG_X86_32
2881 ver = apic_read(APIC_LVR);
2882 ver = GET_APIC_VERSION(ver);
2883 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2887 pin1 = find_isa_irq_pin(0, mp_INT);
2888 apic1 = find_isa_irq_apic(0, mp_INT);
2889 pin2 = ioapic_i8259.pin;
2890 apic2 = ioapic_i8259.apic;
2892 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2893 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2894 cfg->vector, apic1, pin1, apic2, pin2);
2897 * Some BIOS writers are clueless and report the ExtINTA
2898 * I/O APIC input from the cascaded 8259A as the timer
2899 * interrupt input. So just in case, if only one pin
2900 * was found above, try it both directly and through the
2904 if (intr_remapping_enabled)
2905 panic("BIOS bug: timer not connected to IO-APIC");
2909 } else if (pin2 == -1) {
2916 * Ok, does IRQ0 through the IOAPIC work?
2919 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2920 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2922 /* for edge trigger, setup_IO_APIC_irq already
2923 * leave it unmasked.
2924 * so only need to unmask if it is level-trigger
2925 * do we really have level trigger timer?
2928 idx = find_irq_entry(apic1, pin1, mp_INT);
2929 if (idx != -1 && irq_trigger(idx))
2930 unmask_IO_APIC_irq_desc(desc);
2932 if (timer_irq_works()) {
2933 if (nmi_watchdog == NMI_IO_APIC) {
2935 enable_8259A_irq(0);
2937 if (disable_timer_pin_1 > 0)
2938 clear_IO_APIC_pin(0, pin1);
2941 if (intr_remapping_enabled)
2942 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2943 local_irq_disable();
2944 clear_IO_APIC_pin(apic1, pin1);
2946 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2947 "8254 timer not connected to IO-APIC\n");
2949 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2950 "(IRQ0) through the 8259A ...\n");
2951 apic_printk(APIC_QUIET, KERN_INFO
2952 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2954 * legacy devices should be connected to IO APIC #0
2956 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2957 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2958 enable_8259A_irq(0);
2959 if (timer_irq_works()) {
2960 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2961 timer_through_8259 = 1;
2962 if (nmi_watchdog == NMI_IO_APIC) {
2963 disable_8259A_irq(0);
2965 enable_8259A_irq(0);
2970 * Cleanup, just in case ...
2972 local_irq_disable();
2973 disable_8259A_irq(0);
2974 clear_IO_APIC_pin(apic2, pin2);
2975 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2978 if (nmi_watchdog == NMI_IO_APIC) {
2979 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2980 "through the IO-APIC - disabling NMI Watchdog!\n");
2981 nmi_watchdog = NMI_NONE;
2983 #ifdef CONFIG_X86_32
2987 apic_printk(APIC_QUIET, KERN_INFO
2988 "...trying to set up timer as Virtual Wire IRQ...\n");
2990 lapic_register_intr(0, desc);
2991 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2992 enable_8259A_irq(0);
2994 if (timer_irq_works()) {
2995 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2998 local_irq_disable();
2999 disable_8259A_irq(0);
3000 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3001 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3003 apic_printk(APIC_QUIET, KERN_INFO
3004 "...trying to set up timer as ExtINT IRQ...\n");
3008 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3010 unlock_ExtINT_logic();
3012 if (timer_irq_works()) {
3013 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3016 local_irq_disable();
3017 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3018 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3019 "report. Then try booting with the 'noapic' option.\n");
3021 local_irq_restore(flags);
3025 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3026 * to devices. However there may be an I/O APIC pin available for
3027 * this interrupt regardless. The pin may be left unconnected, but
3028 * typically it will be reused as an ExtINT cascade interrupt for
3029 * the master 8259A. In the MPS case such a pin will normally be
3030 * reported as an ExtINT interrupt in the MP table. With ACPI
3031 * there is no provision for ExtINT interrupts, and in the absence
3032 * of an override it would be treated as an ordinary ISA I/O APIC
3033 * interrupt, that is edge-triggered and unmasked by default. We
3034 * used to do this, but it caused problems on some systems because
3035 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3036 * the same ExtINT cascade interrupt to drive the local APIC of the
3037 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3038 * the I/O APIC in all cases now. No actual device should request
3039 * it anyway. --macro
3041 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3043 void __init setup_IO_APIC(void)
3047 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3050 io_apic_irqs = ~PIC_IRQS;
3052 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3054 * Set up IO-APIC IRQ routing.
3056 #ifdef CONFIG_X86_32
3058 setup_ioapic_ids_from_mpc();
3061 setup_IO_APIC_irqs();
3062 init_IO_APIC_traps();
3067 * Called after all the initialization is done. If we didnt find any
3068 * APIC bugs then we can allow the modify fast path
3071 static int __init io_apic_bug_finalize(void)
3073 if (sis_apic_bug == -1)
3078 late_initcall(io_apic_bug_finalize);
3080 struct sysfs_ioapic_data {
3081 struct sys_device dev;
3082 struct IO_APIC_route_entry entry[0];
3084 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3086 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3088 struct IO_APIC_route_entry *entry;
3089 struct sysfs_ioapic_data *data;
3092 data = container_of(dev, struct sysfs_ioapic_data, dev);
3093 entry = data->entry;
3094 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3095 *entry = ioapic_read_entry(dev->id, i);
3100 static int ioapic_resume(struct sys_device *dev)
3102 struct IO_APIC_route_entry *entry;
3103 struct sysfs_ioapic_data *data;
3104 unsigned long flags;
3105 union IO_APIC_reg_00 reg_00;
3108 data = container_of(dev, struct sysfs_ioapic_data, dev);
3109 entry = data->entry;
3111 spin_lock_irqsave(&ioapic_lock, flags);
3112 reg_00.raw = io_apic_read(dev->id, 0);
3113 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3114 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3115 io_apic_write(dev->id, 0, reg_00.raw);
3117 spin_unlock_irqrestore(&ioapic_lock, flags);
3118 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3119 ioapic_write_entry(dev->id, i, entry[i]);
3124 static struct sysdev_class ioapic_sysdev_class = {
3126 .suspend = ioapic_suspend,
3127 .resume = ioapic_resume,
3130 static int __init ioapic_init_sysfs(void)
3132 struct sys_device * dev;
3135 error = sysdev_class_register(&ioapic_sysdev_class);
3139 for (i = 0; i < nr_ioapics; i++ ) {
3140 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3141 * sizeof(struct IO_APIC_route_entry);
3142 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3143 if (!mp_ioapic_data[i]) {
3144 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3147 dev = &mp_ioapic_data[i]->dev;
3149 dev->cls = &ioapic_sysdev_class;
3150 error = sysdev_register(dev);
3152 kfree(mp_ioapic_data[i]);
3153 mp_ioapic_data[i] = NULL;
3154 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3162 device_initcall(ioapic_init_sysfs);
3164 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3166 * Dynamic irq allocate and deallocation
3168 unsigned int create_irq_nr(unsigned int irq_want)
3170 /* Allocate an unused irq */
3173 unsigned long flags;
3174 struct irq_cfg *cfg_new = NULL;
3175 int cpu = boot_cpu_id;
3176 struct irq_desc *desc_new = NULL;
3179 if (irq_want < nr_irqs_gsi)
3180 irq_want = nr_irqs_gsi;
3182 spin_lock_irqsave(&vector_lock, flags);
3183 for (new = irq_want; new < nr_irqs; new++) {
3184 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3186 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3189 cfg_new = desc_new->chip_data;
3191 if (cfg_new->vector != 0)
3193 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3197 spin_unlock_irqrestore(&vector_lock, flags);
3200 dynamic_irq_init(irq);
3201 /* restore it, in case dynamic_irq_init clear it */
3203 desc_new->chip_data = cfg_new;
3208 int create_irq(void)
3210 unsigned int irq_want;
3213 irq_want = nr_irqs_gsi;
3214 irq = create_irq_nr(irq_want);
3222 void destroy_irq(unsigned int irq)
3224 unsigned long flags;
3225 struct irq_cfg *cfg;
3226 struct irq_desc *desc;
3228 /* store it, in case dynamic_irq_cleanup clear it */
3229 desc = irq_to_desc(irq);
3230 cfg = desc->chip_data;
3231 dynamic_irq_cleanup(irq);
3232 /* connect back irq_cfg */
3234 desc->chip_data = cfg;
3237 spin_lock_irqsave(&vector_lock, flags);
3238 __clear_irq_vector(irq, cfg);
3239 spin_unlock_irqrestore(&vector_lock, flags);
3243 * MSI message composition
3245 #ifdef CONFIG_PCI_MSI
3246 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3248 struct irq_cfg *cfg;
3256 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3260 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3262 if (irq_remapped(irq)) {
3267 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3268 BUG_ON(ir_index == -1);
3270 memset (&irte, 0, sizeof(irte));
3273 irte.dst_mode = apic->irq_dest_mode;
3274 irte.trigger_mode = 0; /* edge */
3275 irte.dlvry_mode = apic->irq_delivery_mode;
3276 irte.vector = cfg->vector;
3277 irte.dest_id = IRTE_DEST(dest);
3279 modify_irte(irq, &irte);
3281 msg->address_hi = MSI_ADDR_BASE_HI;
3282 msg->data = sub_handle;
3283 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3285 MSI_ADDR_IR_INDEX1(ir_index) |
3286 MSI_ADDR_IR_INDEX2(ir_index);
3288 if (x2apic_enabled())
3289 msg->address_hi = MSI_ADDR_BASE_HI |
3290 MSI_ADDR_EXT_DEST_ID(dest);
3292 msg->address_hi = MSI_ADDR_BASE_HI;
3296 ((apic->irq_dest_mode == 0) ?
3297 MSI_ADDR_DEST_MODE_PHYSICAL:
3298 MSI_ADDR_DEST_MODE_LOGICAL) |
3299 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3300 MSI_ADDR_REDIRECTION_CPU:
3301 MSI_ADDR_REDIRECTION_LOWPRI) |
3302 MSI_ADDR_DEST_ID(dest);
3305 MSI_DATA_TRIGGER_EDGE |
3306 MSI_DATA_LEVEL_ASSERT |
3307 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3308 MSI_DATA_DELIVERY_FIXED:
3309 MSI_DATA_DELIVERY_LOWPRI) |
3310 MSI_DATA_VECTOR(cfg->vector);
3316 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3318 struct irq_desc *desc = irq_to_desc(irq);
3319 struct irq_cfg *cfg;
3323 dest = set_desc_affinity(desc, mask);
3324 if (dest == BAD_APICID)
3327 cfg = desc->chip_data;
3329 read_msi_msg_desc(desc, &msg);
3331 msg.data &= ~MSI_DATA_VECTOR_MASK;
3332 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3333 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3334 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3336 write_msi_msg_desc(desc, &msg);
3338 #ifdef CONFIG_INTR_REMAP
3340 * Migrate the MSI irq to another cpumask. This migration is
3341 * done in the process context using interrupt-remapping hardware.
3344 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3346 struct irq_desc *desc = irq_to_desc(irq);
3347 struct irq_cfg *cfg = desc->chip_data;
3351 if (get_irte(irq, &irte))
3354 dest = set_desc_affinity(desc, mask);
3355 if (dest == BAD_APICID)
3358 irte.vector = cfg->vector;
3359 irte.dest_id = IRTE_DEST(dest);
3362 * atomically update the IRTE with the new destination and vector.
3364 modify_irte(irq, &irte);
3367 * After this point, all the interrupts will start arriving
3368 * at the new destination. So, time to cleanup the previous
3369 * vector allocation.
3371 if (cfg->move_in_progress)
3372 send_cleanup_vector(cfg);
3376 #endif /* CONFIG_SMP */
3379 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3380 * which implement the MSI or MSI-X Capability Structure.
3382 static struct irq_chip msi_chip = {
3384 .unmask = unmask_msi_irq,
3385 .mask = mask_msi_irq,
3386 .ack = ack_apic_edge,
3388 .set_affinity = set_msi_irq_affinity,
3390 .retrigger = ioapic_retrigger_irq,
3393 static struct irq_chip msi_ir_chip = {
3394 .name = "IR-PCI-MSI",
3395 .unmask = unmask_msi_irq,
3396 .mask = mask_msi_irq,
3397 #ifdef CONFIG_INTR_REMAP
3398 .ack = ack_x2apic_edge,
3400 .set_affinity = ir_set_msi_irq_affinity,
3403 .retrigger = ioapic_retrigger_irq,
3407 * Map the PCI dev to the corresponding remapping hardware unit
3408 * and allocate 'nvec' consecutive interrupt-remapping table entries
3411 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3413 struct intel_iommu *iommu;
3416 iommu = map_dev_to_ir(dev);
3419 "Unable to map PCI %s to iommu\n", pci_name(dev));
3423 index = alloc_irte(iommu, irq, nvec);
3426 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3433 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3438 ret = msi_compose_msg(dev, irq, &msg);
3442 set_irq_msi(irq, msidesc);
3443 write_msi_msg(irq, &msg);
3445 if (irq_remapped(irq)) {
3446 struct irq_desc *desc = irq_to_desc(irq);
3448 * irq migration in process context
3450 desc->status |= IRQ_MOVE_PCNTXT;
3451 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3453 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3455 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3460 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3463 int ret, sub_handle;
3464 struct msi_desc *msidesc;
3465 unsigned int irq_want;
3466 struct intel_iommu *iommu = NULL;
3469 irq_want = nr_irqs_gsi;
3471 list_for_each_entry(msidesc, &dev->msi_list, list) {
3472 irq = create_irq_nr(irq_want);
3476 if (!intr_remapping_enabled)
3481 * allocate the consecutive block of IRTE's
3484 index = msi_alloc_irte(dev, irq, nvec);
3490 iommu = map_dev_to_ir(dev);
3496 * setup the mapping between the irq and the IRTE
3497 * base index, the sub_handle pointing to the
3498 * appropriate interrupt remap table entry.
3500 set_irte_irq(irq, iommu, index, sub_handle);
3503 ret = setup_msi_irq(dev, msidesc, irq);
3515 void arch_teardown_msi_irq(unsigned int irq)
3520 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3522 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3524 struct irq_desc *desc = irq_to_desc(irq);
3525 struct irq_cfg *cfg;
3529 dest = set_desc_affinity(desc, mask);
3530 if (dest == BAD_APICID)
3533 cfg = desc->chip_data;
3535 dmar_msi_read(irq, &msg);
3537 msg.data &= ~MSI_DATA_VECTOR_MASK;
3538 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3539 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3540 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3542 dmar_msi_write(irq, &msg);
3545 #endif /* CONFIG_SMP */
3547 struct irq_chip dmar_msi_type = {
3549 .unmask = dmar_msi_unmask,
3550 .mask = dmar_msi_mask,
3551 .ack = ack_apic_edge,
3553 .set_affinity = dmar_msi_set_affinity,
3555 .retrigger = ioapic_retrigger_irq,
3558 int arch_setup_dmar_msi(unsigned int irq)
3563 ret = msi_compose_msg(NULL, irq, &msg);
3566 dmar_msi_write(irq, &msg);
3567 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3573 #ifdef CONFIG_HPET_TIMER
3576 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3578 struct irq_desc *desc = irq_to_desc(irq);
3579 struct irq_cfg *cfg;
3583 dest = set_desc_affinity(desc, mask);
3584 if (dest == BAD_APICID)
3587 cfg = desc->chip_data;
3589 hpet_msi_read(irq, &msg);
3591 msg.data &= ~MSI_DATA_VECTOR_MASK;
3592 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3593 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3594 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3596 hpet_msi_write(irq, &msg);
3599 #endif /* CONFIG_SMP */
3601 static struct irq_chip hpet_msi_type = {
3603 .unmask = hpet_msi_unmask,
3604 .mask = hpet_msi_mask,
3605 .ack = ack_apic_edge,
3607 .set_affinity = hpet_msi_set_affinity,
3609 .retrigger = ioapic_retrigger_irq,
3612 int arch_setup_hpet_msi(unsigned int irq)
3617 ret = msi_compose_msg(NULL, irq, &msg);
3621 hpet_msi_write(irq, &msg);
3622 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3629 #endif /* CONFIG_PCI_MSI */
3631 * Hypertransport interrupt support
3633 #ifdef CONFIG_HT_IRQ
3637 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3639 struct ht_irq_msg msg;
3640 fetch_ht_irq_msg(irq, &msg);
3642 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3643 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3645 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3646 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3648 write_ht_irq_msg(irq, &msg);
3651 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3653 struct irq_desc *desc = irq_to_desc(irq);
3654 struct irq_cfg *cfg;
3657 dest = set_desc_affinity(desc, mask);
3658 if (dest == BAD_APICID)
3661 cfg = desc->chip_data;
3663 target_ht_irq(irq, dest, cfg->vector);
3668 static struct irq_chip ht_irq_chip = {
3670 .mask = mask_ht_irq,
3671 .unmask = unmask_ht_irq,
3672 .ack = ack_apic_edge,
3674 .set_affinity = set_ht_irq_affinity,
3676 .retrigger = ioapic_retrigger_irq,
3679 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3681 struct irq_cfg *cfg;
3688 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3690 struct ht_irq_msg msg;
3693 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3694 apic->target_cpus());
3696 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3700 HT_IRQ_LOW_DEST_ID(dest) |
3701 HT_IRQ_LOW_VECTOR(cfg->vector) |
3702 ((apic->irq_dest_mode == 0) ?
3703 HT_IRQ_LOW_DM_PHYSICAL :
3704 HT_IRQ_LOW_DM_LOGICAL) |
3705 HT_IRQ_LOW_RQEOI_EDGE |
3706 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3707 HT_IRQ_LOW_MT_FIXED :
3708 HT_IRQ_LOW_MT_ARBITRATED) |
3709 HT_IRQ_LOW_IRQ_MASKED;
3711 write_ht_irq_msg(irq, &msg);
3713 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3714 handle_edge_irq, "edge");
3716 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3720 #endif /* CONFIG_HT_IRQ */
3722 #ifdef CONFIG_X86_UV
3724 * Re-target the irq to the specified CPU and enable the specified MMR located
3725 * on the specified blade to allow the sending of MSIs to the specified CPU.
3727 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3728 unsigned long mmr_offset)
3730 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3731 struct irq_cfg *cfg;
3733 unsigned long mmr_value;
3734 struct uv_IO_APIC_route_entry *entry;
3735 unsigned long flags;
3740 err = assign_irq_vector(irq, cfg, eligible_cpu);
3744 spin_lock_irqsave(&vector_lock, flags);
3745 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3747 spin_unlock_irqrestore(&vector_lock, flags);
3750 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3751 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3753 entry->vector = cfg->vector;
3754 entry->delivery_mode = apic->irq_delivery_mode;
3755 entry->dest_mode = apic->irq_dest_mode;
3756 entry->polarity = 0;
3759 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3761 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3762 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3768 * Disable the specified MMR located on the specified blade so that MSIs are
3769 * longer allowed to be sent.
3771 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3773 unsigned long mmr_value;
3774 struct uv_IO_APIC_route_entry *entry;
3778 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3779 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3783 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3784 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3786 #endif /* CONFIG_X86_64 */
3788 int __init io_apic_get_redir_entries (int ioapic)
3790 union IO_APIC_reg_01 reg_01;
3791 unsigned long flags;
3793 spin_lock_irqsave(&ioapic_lock, flags);
3794 reg_01.raw = io_apic_read(ioapic, 1);
3795 spin_unlock_irqrestore(&ioapic_lock, flags);
3797 return reg_01.bits.entries;
3800 void __init probe_nr_irqs_gsi(void)
3804 nr = acpi_probe_gsi();
3805 if (nr > nr_irqs_gsi) {
3808 /* for acpi=off or acpi is not compiled in */
3812 for (idx = 0; idx < nr_ioapics; idx++)
3813 nr += io_apic_get_redir_entries(idx) + 1;
3815 if (nr > nr_irqs_gsi)
3819 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3822 #ifdef CONFIG_SPARSE_IRQ
3823 int __init arch_probe_nr_irqs(void)
3827 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3828 nr_irqs = NR_VECTORS * nr_cpu_ids;
3830 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3831 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3833 * for MSI and HT dyn irq
3835 nr += nr_irqs_gsi * 16;
3844 /* --------------------------------------------------------------------------
3845 ACPI-based IOAPIC Configuration
3846 -------------------------------------------------------------------------- */
3850 #ifdef CONFIG_X86_32
3851 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3853 union IO_APIC_reg_00 reg_00;
3854 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3856 unsigned long flags;
3860 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3861 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3862 * supports up to 16 on one shared APIC bus.
3864 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3865 * advantage of new APIC bus architecture.
3868 if (physids_empty(apic_id_map))
3869 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3871 spin_lock_irqsave(&ioapic_lock, flags);
3872 reg_00.raw = io_apic_read(ioapic, 0);
3873 spin_unlock_irqrestore(&ioapic_lock, flags);
3875 if (apic_id >= get_physical_broadcast()) {
3876 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3877 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3878 apic_id = reg_00.bits.ID;
3882 * Every APIC in a system must have a unique ID or we get lots of nice
3883 * 'stuck on smp_invalidate_needed IPI wait' messages.
3885 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3887 for (i = 0; i < get_physical_broadcast(); i++) {
3888 if (!apic->check_apicid_used(apic_id_map, i))
3892 if (i == get_physical_broadcast())
3893 panic("Max apic_id exceeded!\n");
3895 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3896 "trying %d\n", ioapic, apic_id, i);
3901 tmp = apic->apicid_to_cpu_present(apic_id);
3902 physids_or(apic_id_map, apic_id_map, tmp);
3904 if (reg_00.bits.ID != apic_id) {
3905 reg_00.bits.ID = apic_id;
3907 spin_lock_irqsave(&ioapic_lock, flags);
3908 io_apic_write(ioapic, 0, reg_00.raw);
3909 reg_00.raw = io_apic_read(ioapic, 0);
3910 spin_unlock_irqrestore(&ioapic_lock, flags);
3913 if (reg_00.bits.ID != apic_id) {
3914 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3919 apic_printk(APIC_VERBOSE, KERN_INFO
3920 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3925 int __init io_apic_get_version(int ioapic)
3927 union IO_APIC_reg_01 reg_01;
3928 unsigned long flags;
3930 spin_lock_irqsave(&ioapic_lock, flags);
3931 reg_01.raw = io_apic_read(ioapic, 1);
3932 spin_unlock_irqrestore(&ioapic_lock, flags);
3934 return reg_01.bits.version;
3938 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3940 struct irq_desc *desc;
3941 struct irq_cfg *cfg;
3942 int cpu = boot_cpu_id;
3944 if (!IO_APIC_IRQ(irq)) {
3945 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3950 desc = irq_to_desc_alloc_cpu(irq, cpu);
3952 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3957 * IRQs < 16 are already in the irq_2_pin[] map
3959 if (irq >= NR_IRQS_LEGACY) {
3960 cfg = desc->chip_data;
3961 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3964 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3970 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3974 if (skip_ioapic_setup)
3977 for (i = 0; i < mp_irq_entries; i++)
3978 if (mp_irqs[i].irqtype == mp_INT &&
3979 mp_irqs[i].srcbusirq == bus_irq)
3981 if (i >= mp_irq_entries)
3984 *trigger = irq_trigger(i);
3985 *polarity = irq_polarity(i);
3989 #endif /* CONFIG_ACPI */
3992 * This function currently is only a helper for the i386 smp boot process where
3993 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3994 * so mask in all cases should simply be apic->target_cpus()
3997 void __init setup_ioapic_dest(void)
3999 int pin, ioapic, irq, irq_entry;
4000 struct irq_desc *desc;
4001 struct irq_cfg *cfg;
4002 const struct cpumask *mask;
4004 if (skip_ioapic_setup == 1)
4007 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4008 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4009 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4010 if (irq_entry == -1)
4012 irq = pin_2_irq(irq_entry, ioapic, pin);
4014 /* setup_IO_APIC_irqs could fail to get vector for some device
4015 * when you have too many devices, because at that time only boot
4018 desc = irq_to_desc(irq);
4019 cfg = desc->chip_data;
4021 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4022 irq_trigger(irq_entry),
4023 irq_polarity(irq_entry));
4029 * Honour affinities which have been set in early boot
4032 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4033 mask = desc->affinity;
4035 mask = apic->target_cpus();
4037 if (intr_remapping_enabled)
4038 set_ir_ioapic_affinity_irq_desc(desc, mask);
4040 set_ioapic_affinity_irq_desc(desc, mask);
4047 #define IOAPIC_RESOURCE_NAME_SIZE 11
4049 static struct resource *ioapic_resources;
4051 static struct resource * __init ioapic_setup_resources(void)
4054 struct resource *res;
4058 if (nr_ioapics <= 0)
4061 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4064 mem = alloc_bootmem(n);
4068 mem += sizeof(struct resource) * nr_ioapics;
4070 for (i = 0; i < nr_ioapics; i++) {
4072 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4073 sprintf(mem, "IOAPIC %u", i);
4074 mem += IOAPIC_RESOURCE_NAME_SIZE;
4078 ioapic_resources = res;
4083 void __init ioapic_init_mappings(void)
4085 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4086 struct resource *ioapic_res;
4089 ioapic_res = ioapic_setup_resources();
4090 for (i = 0; i < nr_ioapics; i++) {
4091 if (smp_found_config) {
4092 ioapic_phys = mp_ioapics[i].apicaddr;
4093 #ifdef CONFIG_X86_32
4096 "WARNING: bogus zero IO-APIC "
4097 "address found in MPTABLE, "
4098 "disabling IO/APIC support!\n");
4099 smp_found_config = 0;
4100 skip_ioapic_setup = 1;
4101 goto fake_ioapic_page;
4105 #ifdef CONFIG_X86_32
4108 ioapic_phys = (unsigned long)
4109 alloc_bootmem_pages(PAGE_SIZE);
4110 ioapic_phys = __pa(ioapic_phys);
4112 set_fixmap_nocache(idx, ioapic_phys);
4113 apic_printk(APIC_VERBOSE,
4114 "mapped IOAPIC to %08lx (%08lx)\n",
4115 __fix_to_virt(idx), ioapic_phys);
4118 if (ioapic_res != NULL) {
4119 ioapic_res->start = ioapic_phys;
4120 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4126 static int __init ioapic_insert_resources(void)
4129 struct resource *r = ioapic_resources;
4132 if (nr_ioapics > 0) {
4134 "IO APIC resources couldn't be allocated.\n");
4140 for (i = 0; i < nr_ioapics; i++) {
4141 insert_resource(&iomem_resource, r);
4148 /* Insert the IO APIC resources after PCI initialization has occured to handle
4149 * IO APICS that are mapped in on a BAR in PCI space. */
4150 late_initcall(ioapic_insert_resources);