2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
71 #ifdef CONFIG_IRQ_REMAP
72 static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
73 static inline bool irq_remapped(struct irq_cfg *cfg)
75 return cfg->irq_2_iommu.iommu != NULL;
78 static inline bool irq_remapped(struct irq_cfg *cfg)
82 static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
88 * Is the SiS APIC rmw bug present ?
89 * -1 = don't know, 0 = no, 1 = yes
91 int sis_apic_bug = -1;
93 static DEFINE_RAW_SPINLOCK(ioapic_lock);
94 static DEFINE_RAW_SPINLOCK(vector_lock);
96 static struct ioapic {
98 * # of IRQ routing registers
102 * Saved state during suspend/resume, or while enabling intr-remap.
104 struct IO_APIC_route_entry *saved_registers;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config;
109 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
110 } ioapics[MAX_IO_APICS];
112 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
114 int mpc_ioapic_id(int ioapic_idx)
116 return ioapics[ioapic_idx].mp_config.apicid;
119 unsigned int mpc_ioapic_addr(int ioapic_idx)
121 return ioapics[ioapic_idx].mp_config.apicaddr;
124 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
126 return &ioapics[ioapic_idx].gsi_config;
131 /* The one past the highest gsi number used */
134 /* MP IRQ source entries */
135 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
137 /* # of MP IRQ source entries */
141 static int nr_irqs_gsi = NR_IRQS_LEGACY;
144 int mp_bus_id_to_type[MAX_MP_BUSSES];
147 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
149 int skip_ioapic_setup;
152 * disable_ioapic_support() - disables ioapic support at runtime
154 void disable_ioapic_support(void)
158 noioapicreroute = -1;
160 skip_ioapic_setup = 1;
163 static int __init parse_noapic(char *str)
165 /* disable IO-APIC */
166 disable_ioapic_support();
169 early_param("noapic", parse_noapic);
171 static int io_apic_setup_irq_pin(unsigned int irq, int node,
172 struct io_apic_irq_attr *attr);
174 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
175 void mp_save_irq(struct mpc_intsrc *m)
179 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
180 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
181 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
182 m->srcbusirq, m->dstapic, m->dstirq);
184 for (i = 0; i < mp_irq_entries; i++) {
185 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
189 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
190 if (++mp_irq_entries == MAX_IRQ_SOURCES)
191 panic("Max # of irq sources exceeded!!\n");
194 struct irq_pin_list {
196 struct irq_pin_list *next;
199 static struct irq_pin_list *alloc_irq_pin_list(int node)
201 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
205 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
206 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
208 int __init arch_early_irq_init(void)
213 if (!legacy_pic->nr_legacy_irqs)
216 for (i = 0; i < nr_ioapics; i++) {
217 ioapics[i].saved_registers =
218 kzalloc(sizeof(struct IO_APIC_route_entry) *
219 ioapics[i].nr_registers, GFP_KERNEL);
220 if (!ioapics[i].saved_registers)
221 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
225 count = ARRAY_SIZE(irq_cfgx);
226 node = cpu_to_node(0);
228 /* Make sure the legacy interrupts are marked in the bitmap */
229 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
231 for (i = 0; i < count; i++) {
232 irq_set_chip_data(i, &cfg[i]);
233 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
234 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
236 * For legacy IRQ's, start with assigning irq0 to irq15 to
237 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
239 if (i < legacy_pic->nr_legacy_irqs) {
240 cfg[i].vector = IRQ0_VECTOR + i;
241 cpumask_setall(cfg[i].domain);
248 static struct irq_cfg *irq_cfg(unsigned int irq)
250 return irq_get_chip_data(irq);
253 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
257 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
260 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
262 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
266 free_cpumask_var(cfg->domain);
272 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
276 irq_set_chip_data(at, NULL);
277 free_cpumask_var(cfg->domain);
278 free_cpumask_var(cfg->old_domain);
282 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
284 int res = irq_alloc_desc_at(at, node);
290 cfg = irq_get_chip_data(at);
295 cfg = alloc_irq_cfg(at, node);
297 irq_set_chip_data(at, cfg);
303 static int alloc_irqs_from(unsigned int from, unsigned int count, int node)
305 return irq_alloc_descs_from(from, count, node);
308 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
310 free_irq_cfg(at, cfg);
317 unsigned int unused[3];
319 unsigned int unused2[11];
323 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
325 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
326 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
329 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
331 struct io_apic __iomem *io_apic = io_apic_base(apic);
332 writel(vector, &io_apic->eoi);
335 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
337 struct io_apic __iomem *io_apic = io_apic_base(apic);
338 writel(reg, &io_apic->index);
339 return readl(&io_apic->data);
342 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
344 struct io_apic __iomem *io_apic = io_apic_base(apic);
346 writel(reg, &io_apic->index);
347 writel(value, &io_apic->data);
351 * Re-write a value: to be used for read-modify-write
352 * cycles where the read already set up the index register.
354 * Older SiS APIC requires we rewrite the index register
356 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 writel(value, &io_apic->data);
366 struct { u32 w1, w2; };
367 struct IO_APIC_route_entry entry;
370 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
372 union entry_union eu;
374 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
375 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
380 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
382 union entry_union eu;
385 raw_spin_lock_irqsave(&ioapic_lock, flags);
386 eu.entry = __ioapic_read_entry(apic, pin);
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
393 * When we write a new IO APIC routing entry, we need to write the high
394 * word first! If the mask bit in the low word is clear, we will enable
395 * the interrupt, and we need to make sure the entry is fully populated
396 * before that happens.
398 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
400 union entry_union eu = {{0, 0}};
403 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
404 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
407 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
411 raw_spin_lock_irqsave(&ioapic_lock, flags);
412 __ioapic_write_entry(apic, pin, e);
413 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
417 * When we mask an IO APIC routing entry, we need to write the low
418 * word first, in order to set the mask bit before we change the
421 static void ioapic_mask_entry(int apic, int pin)
424 union entry_union eu = { .entry.mask = 1 };
426 raw_spin_lock_irqsave(&ioapic_lock, flags);
427 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
428 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
433 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
434 * shared ISA-space IRQs, so we have to support them. We are super
435 * fast in the common case, and fast for shared ISA-space IRQs.
437 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
439 struct irq_pin_list **last, *entry;
441 /* don't allow duplicates */
442 last = &cfg->irq_2_pin;
443 for_each_irq_pin(entry, cfg->irq_2_pin) {
444 if (entry->apic == apic && entry->pin == pin)
449 entry = alloc_irq_pin_list(node);
451 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
462 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
464 if (__add_pin_to_irq_node(cfg, node, apic, pin))
465 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
469 * Reroute an IRQ to a different pin.
471 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
472 int oldapic, int oldpin,
473 int newapic, int newpin)
475 struct irq_pin_list *entry;
477 for_each_irq_pin(entry, cfg->irq_2_pin) {
478 if (entry->apic == oldapic && entry->pin == oldpin) {
479 entry->apic = newapic;
481 /* every one is different, right? */
486 /* old apic/pin didn't exist, so just add new ones */
487 add_pin_to_irq_node(cfg, node, newapic, newpin);
490 static void __io_apic_modify_irq(struct irq_pin_list *entry,
491 int mask_and, int mask_or,
492 void (*final)(struct irq_pin_list *entry))
494 unsigned int reg, pin;
497 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
500 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
505 static void io_apic_modify_irq(struct irq_cfg *cfg,
506 int mask_and, int mask_or,
507 void (*final)(struct irq_pin_list *entry))
509 struct irq_pin_list *entry;
511 for_each_irq_pin(entry, cfg->irq_2_pin)
512 __io_apic_modify_irq(entry, mask_and, mask_or, final);
515 static void io_apic_sync(struct irq_pin_list *entry)
518 * Synchronize the IO-APIC and the CPU by doing
519 * a dummy read from the IO-APIC
521 struct io_apic __iomem *io_apic;
523 io_apic = io_apic_base(entry->apic);
524 readl(&io_apic->data);
527 static void mask_ioapic(struct irq_cfg *cfg)
531 raw_spin_lock_irqsave(&ioapic_lock, flags);
532 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
533 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
536 static void mask_ioapic_irq(struct irq_data *data)
538 mask_ioapic(data->chip_data);
541 static void __unmask_ioapic(struct irq_cfg *cfg)
543 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
546 static void unmask_ioapic(struct irq_cfg *cfg)
550 raw_spin_lock_irqsave(&ioapic_lock, flags);
551 __unmask_ioapic(cfg);
552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
555 static void unmask_ioapic_irq(struct irq_data *data)
557 unmask_ioapic(data->chip_data);
561 * IO-APIC versions below 0x20 don't support EOI register.
562 * For the record, here is the information about various versions:
564 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
565 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
568 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
569 * version as 0x2. This is an error with documentation and these ICH chips
570 * use io-apic's of version 0x20.
572 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
573 * Otherwise, we simulate the EOI message manually by changing the trigger
574 * mode to edge and then back to level, with RTE being masked during this.
576 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
578 if (mpc_ioapic_ver(apic) >= 0x20) {
580 * Intr-remapping uses pin number as the virtual vector
581 * in the RTE. Actual vector is programmed in
582 * intr-remapping table entry. Hence for the io-apic
583 * EOI we use the pin number.
585 if (cfg && irq_remapped(cfg))
586 io_apic_eoi(apic, pin);
588 io_apic_eoi(apic, vector);
590 struct IO_APIC_route_entry entry, entry1;
592 entry = entry1 = __ioapic_read_entry(apic, pin);
595 * Mask the entry and change the trigger mode to edge.
598 entry1.trigger = IOAPIC_EDGE;
600 __ioapic_write_entry(apic, pin, entry1);
603 * Restore the previous level triggered entry.
605 __ioapic_write_entry(apic, pin, entry);
609 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
611 struct irq_pin_list *entry;
614 raw_spin_lock_irqsave(&ioapic_lock, flags);
615 for_each_irq_pin(entry, cfg->irq_2_pin)
616 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
617 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
620 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
622 struct IO_APIC_route_entry entry;
624 /* Check delivery_mode to be sure we're not clearing an SMI pin */
625 entry = ioapic_read_entry(apic, pin);
626 if (entry.delivery_mode == dest_SMI)
630 * Make sure the entry is masked and re-read the contents to check
631 * if it is a level triggered pin and if the remote-IRR is set.
635 ioapic_write_entry(apic, pin, entry);
636 entry = ioapic_read_entry(apic, pin);
643 * Make sure the trigger mode is set to level. Explicit EOI
644 * doesn't clear the remote-IRR if the trigger mode is not
647 if (!entry.trigger) {
648 entry.trigger = IOAPIC_LEVEL;
649 ioapic_write_entry(apic, pin, entry);
652 raw_spin_lock_irqsave(&ioapic_lock, flags);
653 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
654 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
658 * Clear the rest of the bits in the IO-APIC RTE except for the mask
661 ioapic_mask_entry(apic, pin);
662 entry = ioapic_read_entry(apic, pin);
664 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
665 mpc_ioapic_id(apic), pin);
668 static void clear_IO_APIC (void)
672 for (apic = 0; apic < nr_ioapics; apic++)
673 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
674 clear_IO_APIC_pin(apic, pin);
679 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680 * specific CPU-side IRQs.
684 static int pirq_entries[MAX_PIRQS] = {
685 [0 ... MAX_PIRQS - 1] = -1
688 static int __init ioapic_pirq_setup(char *str)
691 int ints[MAX_PIRQS+1];
693 get_options(str, ARRAY_SIZE(ints), ints);
695 apic_printk(APIC_VERBOSE, KERN_INFO
696 "PIRQ redirection, working around broken MP-BIOS.\n");
698 if (ints[0] < MAX_PIRQS)
701 for (i = 0; i < max; i++) {
702 apic_printk(APIC_VERBOSE, KERN_DEBUG
703 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
705 * PIRQs are mapped upside down, usually.
707 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
712 __setup("pirq=", ioapic_pirq_setup);
713 #endif /* CONFIG_X86_32 */
716 * Saves all the IO-APIC RTE's
718 int save_ioapic_entries(void)
723 for (apic = 0; apic < nr_ioapics; apic++) {
724 if (!ioapics[apic].saved_registers) {
729 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
730 ioapics[apic].saved_registers[pin] =
731 ioapic_read_entry(apic, pin);
738 * Mask all IO APIC entries.
740 void mask_ioapic_entries(void)
744 for (apic = 0; apic < nr_ioapics; apic++) {
745 if (!ioapics[apic].saved_registers)
748 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
749 struct IO_APIC_route_entry entry;
751 entry = ioapics[apic].saved_registers[pin];
754 ioapic_write_entry(apic, pin, entry);
761 * Restore IO APIC entries which was saved in the ioapic structure.
763 int restore_ioapic_entries(void)
767 for (apic = 0; apic < nr_ioapics; apic++) {
768 if (!ioapics[apic].saved_registers)
771 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
772 ioapic_write_entry(apic, pin,
773 ioapics[apic].saved_registers[pin]);
779 * Find the IRQ entry number of a certain pin.
781 static int find_irq_entry(int ioapic_idx, int pin, int type)
785 for (i = 0; i < mp_irq_entries; i++)
786 if (mp_irqs[i].irqtype == type &&
787 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
788 mp_irqs[i].dstapic == MP_APIC_ALL) &&
789 mp_irqs[i].dstirq == pin)
796 * Find the pin to which IRQ[irq] (ISA) is connected
798 static int __init find_isa_irq_pin(int irq, int type)
802 for (i = 0; i < mp_irq_entries; i++) {
803 int lbus = mp_irqs[i].srcbus;
805 if (test_bit(lbus, mp_bus_not_pci) &&
806 (mp_irqs[i].irqtype == type) &&
807 (mp_irqs[i].srcbusirq == irq))
809 return mp_irqs[i].dstirq;
814 static int __init find_isa_irq_apic(int irq, int type)
818 for (i = 0; i < mp_irq_entries; i++) {
819 int lbus = mp_irqs[i].srcbus;
821 if (test_bit(lbus, mp_bus_not_pci) &&
822 (mp_irqs[i].irqtype == type) &&
823 (mp_irqs[i].srcbusirq == irq))
827 if (i < mp_irq_entries) {
830 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
831 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
840 * EISA Edge/Level control register, ELCR
842 static int EISA_ELCR(unsigned int irq)
844 if (irq < legacy_pic->nr_legacy_irqs) {
845 unsigned int port = 0x4d0 + (irq >> 3);
846 return (inb(port) >> (irq & 7)) & 1;
848 apic_printk(APIC_VERBOSE, KERN_INFO
849 "Broken MPtable reports ISA irq %d\n", irq);
855 /* ISA interrupts are always polarity zero edge triggered,
856 * when listed as conforming in the MP table. */
858 #define default_ISA_trigger(idx) (0)
859 #define default_ISA_polarity(idx) (0)
861 /* EISA interrupts are always polarity zero and can be edge or level
862 * trigger depending on the ELCR value. If an interrupt is listed as
863 * EISA conforming in the MP table, that means its trigger type must
864 * be read in from the ELCR */
866 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
867 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
869 /* PCI interrupts are always polarity one level triggered,
870 * when listed as conforming in the MP table. */
872 #define default_PCI_trigger(idx) (1)
873 #define default_PCI_polarity(idx) (1)
875 static int irq_polarity(int idx)
877 int bus = mp_irqs[idx].srcbus;
881 * Determine IRQ line polarity (high active or low active):
883 switch (mp_irqs[idx].irqflag & 3)
885 case 0: /* conforms, ie. bus-type dependent polarity */
886 if (test_bit(bus, mp_bus_not_pci))
887 polarity = default_ISA_polarity(idx);
889 polarity = default_PCI_polarity(idx);
891 case 1: /* high active */
896 case 2: /* reserved */
898 pr_warn("broken BIOS!!\n");
902 case 3: /* low active */
907 default: /* invalid */
909 pr_warn("broken BIOS!!\n");
917 static int irq_trigger(int idx)
919 int bus = mp_irqs[idx].srcbus;
923 * Determine IRQ trigger mode (edge or level sensitive):
925 switch ((mp_irqs[idx].irqflag>>2) & 3)
927 case 0: /* conforms, ie. bus-type dependent */
928 if (test_bit(bus, mp_bus_not_pci))
929 trigger = default_ISA_trigger(idx);
931 trigger = default_PCI_trigger(idx);
933 switch (mp_bus_id_to_type[bus]) {
934 case MP_BUS_ISA: /* ISA pin */
936 /* set before the switch */
939 case MP_BUS_EISA: /* EISA pin */
941 trigger = default_EISA_trigger(idx);
944 case MP_BUS_PCI: /* PCI pin */
946 /* set before the switch */
951 pr_warn("broken BIOS!!\n");
963 case 2: /* reserved */
965 pr_warn("broken BIOS!!\n");
974 default: /* invalid */
976 pr_warn("broken BIOS!!\n");
984 static int pin_2_irq(int idx, int apic, int pin)
987 int bus = mp_irqs[idx].srcbus;
988 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
991 * Debugging check, we are in big trouble if this message pops up!
993 if (mp_irqs[idx].dstirq != pin)
994 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
996 if (test_bit(bus, mp_bus_not_pci)) {
997 irq = mp_irqs[idx].srcbusirq;
999 u32 gsi = gsi_cfg->gsi_base + pin;
1001 if (gsi >= NR_IRQS_LEGACY)
1004 irq = gsi_top + gsi;
1007 #ifdef CONFIG_X86_32
1009 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1011 if ((pin >= 16) && (pin <= 23)) {
1012 if (pirq_entries[pin-16] != -1) {
1013 if (!pirq_entries[pin-16]) {
1014 apic_printk(APIC_VERBOSE, KERN_DEBUG
1015 "disabling PIRQ%d\n", pin-16);
1017 irq = pirq_entries[pin-16];
1018 apic_printk(APIC_VERBOSE, KERN_DEBUG
1019 "using PIRQ%d -> IRQ %d\n",
1030 * Find a specific PCI IRQ entry.
1031 * Not an __init, possibly needed by modules
1033 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1034 struct io_apic_irq_attr *irq_attr)
1036 int ioapic_idx, i, best_guess = -1;
1038 apic_printk(APIC_DEBUG,
1039 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1041 if (test_bit(bus, mp_bus_not_pci)) {
1042 apic_printk(APIC_VERBOSE,
1043 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1046 for (i = 0; i < mp_irq_entries; i++) {
1047 int lbus = mp_irqs[i].srcbus;
1049 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1050 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1051 mp_irqs[i].dstapic == MP_APIC_ALL)
1054 if (!test_bit(lbus, mp_bus_not_pci) &&
1055 !mp_irqs[i].irqtype &&
1057 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1058 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1060 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1063 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1064 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1071 * Use the first all-but-pin matching entry as a
1072 * best-guess fuzzy result for broken mptables.
1074 if (best_guess < 0) {
1075 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1085 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1087 void lock_vector_lock(void)
1089 /* Used to the online set of cpus does not change
1090 * during assign_irq_vector.
1092 raw_spin_lock(&vector_lock);
1095 void unlock_vector_lock(void)
1097 raw_spin_unlock(&vector_lock);
1101 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1104 * NOTE! The local APIC isn't very good at handling
1105 * multiple interrupts at the same interrupt level.
1106 * As the interrupt level is determined by taking the
1107 * vector number and shifting that right by 4, we
1108 * want to spread these out a bit so that they don't
1109 * all fall in the same interrupt level.
1111 * Also, we've got to be careful not to trash gate
1112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1114 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1115 static int current_offset = VECTOR_OFFSET_START % 16;
1117 cpumask_var_t tmp_mask;
1119 if (cfg->move_in_progress)
1122 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1125 /* Only try and allocate irqs on cpus that are present */
1127 cpumask_clear(cfg->old_domain);
1128 cpu = cpumask_first_and(mask, cpu_online_mask);
1129 while (cpu < nr_cpu_ids) {
1130 int new_cpu, vector, offset;
1132 apic->vector_allocation_domain(cpu, tmp_mask, mask);
1134 if (cpumask_subset(tmp_mask, cfg->domain)) {
1136 if (cpumask_equal(tmp_mask, cfg->domain))
1139 * New cpumask using the vector is a proper subset of
1140 * the current in use mask. So cleanup the vector
1141 * allocation for the members that are not used anymore.
1143 cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
1144 cfg->move_in_progress =
1145 cpumask_intersects(cfg->old_domain, cpu_online_mask);
1146 cpumask_and(cfg->domain, cfg->domain, tmp_mask);
1150 vector = current_vector;
1151 offset = current_offset;
1154 if (vector >= first_system_vector) {
1155 offset = (offset + 1) % 16;
1156 vector = FIRST_EXTERNAL_VECTOR + offset;
1159 if (unlikely(current_vector == vector)) {
1160 cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
1161 cpumask_andnot(tmp_mask, mask, cfg->old_domain);
1162 cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
1166 if (test_bit(vector, used_vectors))
1169 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1170 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1173 current_vector = vector;
1174 current_offset = offset;
1176 cpumask_copy(cfg->old_domain, cfg->domain);
1177 cfg->move_in_progress =
1178 cpumask_intersects(cfg->old_domain, cpu_online_mask);
1180 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1181 per_cpu(vector_irq, new_cpu)[vector] = irq;
1182 cfg->vector = vector;
1183 cpumask_copy(cfg->domain, tmp_mask);
1187 free_cpumask_var(tmp_mask);
1191 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1194 unsigned long flags;
1196 raw_spin_lock_irqsave(&vector_lock, flags);
1197 err = __assign_irq_vector(irq, cfg, mask);
1198 raw_spin_unlock_irqrestore(&vector_lock, flags);
1202 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1206 BUG_ON(!cfg->vector);
1208 vector = cfg->vector;
1209 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1210 per_cpu(vector_irq, cpu)[vector] = -1;
1213 cpumask_clear(cfg->domain);
1215 if (likely(!cfg->move_in_progress))
1217 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1218 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1220 if (per_cpu(vector_irq, cpu)[vector] != irq)
1222 per_cpu(vector_irq, cpu)[vector] = -1;
1226 cfg->move_in_progress = 0;
1229 void __setup_vector_irq(int cpu)
1231 /* Initialize vector_irq on a new cpu */
1233 struct irq_cfg *cfg;
1236 * vector_lock will make sure that we don't run into irq vector
1237 * assignments that might be happening on another cpu in parallel,
1238 * while we setup our initial vector to irq mappings.
1240 raw_spin_lock(&vector_lock);
1241 /* Mark the inuse vectors */
1242 for_each_active_irq(irq) {
1243 cfg = irq_get_chip_data(irq);
1247 if (!cpumask_test_cpu(cpu, cfg->domain))
1249 vector = cfg->vector;
1250 per_cpu(vector_irq, cpu)[vector] = irq;
1252 /* Mark the free vectors */
1253 for (vector = 0; vector < NR_VECTORS; ++vector) {
1254 irq = per_cpu(vector_irq, cpu)[vector];
1259 if (!cpumask_test_cpu(cpu, cfg->domain))
1260 per_cpu(vector_irq, cpu)[vector] = -1;
1262 raw_spin_unlock(&vector_lock);
1265 static struct irq_chip ioapic_chip;
1267 #ifdef CONFIG_X86_32
1268 static inline int IO_APIC_irq_trigger(int irq)
1272 for (apic = 0; apic < nr_ioapics; apic++) {
1273 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1274 idx = find_irq_entry(apic, pin, mp_INT);
1275 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1276 return irq_trigger(idx);
1280 * nonexistent IRQs are edge default
1285 static inline int IO_APIC_irq_trigger(int irq)
1291 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1292 unsigned long trigger)
1294 struct irq_chip *chip = &ioapic_chip;
1295 irq_flow_handler_t hdl;
1298 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1299 trigger == IOAPIC_LEVEL) {
1300 irq_set_status_flags(irq, IRQ_LEVEL);
1303 irq_clear_status_flags(irq, IRQ_LEVEL);
1307 if (irq_remapped(cfg)) {
1308 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1309 irq_remap_modify_chip_defaults(chip);
1310 fasteoi = trigger != 0;
1313 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1314 irq_set_chip_and_handler_name(irq, chip, hdl,
1315 fasteoi ? "fasteoi" : "edge");
1318 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1319 unsigned int destination, int vector,
1320 struct io_apic_irq_attr *attr)
1322 memset(entry, 0, sizeof(*entry));
1324 entry->delivery_mode = apic->irq_delivery_mode;
1325 entry->dest_mode = apic->irq_dest_mode;
1326 entry->dest = destination;
1327 entry->vector = vector;
1328 entry->mask = 0; /* enable IRQ */
1329 entry->trigger = attr->trigger;
1330 entry->polarity = attr->polarity;
1333 * Mask level triggered irqs.
1334 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1342 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1343 struct io_apic_irq_attr *attr)
1345 struct IO_APIC_route_entry entry;
1348 if (!IO_APIC_IRQ(irq))
1351 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1354 if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1356 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1357 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1358 __clear_irq_vector(irq, cfg);
1363 apic_printk(APIC_VERBOSE,KERN_DEBUG
1364 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1365 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1366 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1367 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1369 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
1370 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1371 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1372 __clear_irq_vector(irq, cfg);
1377 ioapic_register_intr(irq, cfg, attr->trigger);
1378 if (irq < legacy_pic->nr_legacy_irqs)
1379 legacy_pic->mask(irq);
1381 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1384 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1389 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1390 mpc_ioapic_id(ioapic_idx), pin);
1394 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1396 int idx, node = cpu_to_node(0);
1397 struct io_apic_irq_attr attr;
1398 unsigned int pin, irq;
1400 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1401 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1402 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1405 irq = pin_2_irq(idx, ioapic_idx, pin);
1407 if ((ioapic_idx > 0) && (irq > 16))
1411 * Skip the timer IRQ if there's a quirk handler
1412 * installed and if it returns 1:
1414 if (apic->multi_timer_check &&
1415 apic->multi_timer_check(ioapic_idx, irq))
1418 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1421 io_apic_setup_irq_pin(irq, node, &attr);
1425 static void __init setup_IO_APIC_irqs(void)
1427 unsigned int ioapic_idx;
1429 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1431 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1432 __io_apic_setup_irqs(ioapic_idx);
1436 * for the gsit that is not in first ioapic
1437 * but could not use acpi_register_gsi()
1438 * like some special sci in IBM x3330
1440 void setup_IO_APIC_irq_extra(u32 gsi)
1442 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1443 struct io_apic_irq_attr attr;
1446 * Convert 'gsi' to 'ioapic.pin'.
1448 ioapic_idx = mp_find_ioapic(gsi);
1452 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1453 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1457 irq = pin_2_irq(idx, ioapic_idx, pin);
1459 /* Only handle the non legacy irqs on secondary ioapics */
1460 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1463 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1466 io_apic_setup_irq_pin_once(irq, node, &attr);
1470 * Set up the timer pin, possibly with the 8259A-master behind.
1472 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1473 unsigned int pin, int vector)
1475 struct IO_APIC_route_entry entry;
1478 memset(&entry, 0, sizeof(entry));
1481 * We use logical delivery to get the timer IRQ
1484 if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1485 apic->target_cpus(), &dest)))
1488 entry.dest_mode = apic->irq_dest_mode;
1489 entry.mask = 0; /* don't mask IRQ for edge */
1491 entry.delivery_mode = apic->irq_delivery_mode;
1494 entry.vector = vector;
1497 * The timer IRQ doesn't have to know that behind the
1498 * scene we may have a 8259A-master in AEOI mode ...
1500 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1504 * Add it to the IO-APIC irq-routing table:
1506 ioapic_write_entry(ioapic_idx, pin, entry);
1509 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1513 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1515 for (i = 0; i <= nr_entries; i++) {
1516 struct IO_APIC_route_entry entry;
1518 entry = ioapic_read_entry(apic, i);
1520 pr_debug(" %02x %02X ", i, entry.dest);
1521 pr_cont("%1d %1d %1d %1d %1d "
1527 entry.delivery_status,
1529 entry.delivery_mode,
1534 void intel_ir_io_apic_print_entries(unsigned int apic,
1535 unsigned int nr_entries)
1539 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1541 for (i = 0; i <= nr_entries; i++) {
1542 struct IR_IO_APIC_route_entry *ir_entry;
1543 struct IO_APIC_route_entry entry;
1545 entry = ioapic_read_entry(apic, i);
1547 ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
1549 pr_debug(" %02x %04X ", i, ir_entry->index);
1550 pr_cont("%1d %1d %1d %1d %1d "
1551 "%1d %1d %X %02X\n",
1557 ir_entry->delivery_status,
1564 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1566 union IO_APIC_reg_00 reg_00;
1567 union IO_APIC_reg_01 reg_01;
1568 union IO_APIC_reg_02 reg_02;
1569 union IO_APIC_reg_03 reg_03;
1570 unsigned long flags;
1572 raw_spin_lock_irqsave(&ioapic_lock, flags);
1573 reg_00.raw = io_apic_read(ioapic_idx, 0);
1574 reg_01.raw = io_apic_read(ioapic_idx, 1);
1575 if (reg_01.bits.version >= 0x10)
1576 reg_02.raw = io_apic_read(ioapic_idx, 2);
1577 if (reg_01.bits.version >= 0x20)
1578 reg_03.raw = io_apic_read(ioapic_idx, 3);
1579 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1581 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1582 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1583 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1584 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1585 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1587 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1588 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1589 reg_01.bits.entries);
1591 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1592 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1593 reg_01.bits.version);
1596 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1597 * but the value of reg_02 is read as the previous read register
1598 * value, so ignore it if reg_02 == reg_01.
1600 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1601 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1602 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1606 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1607 * or reg_03, but the value of reg_0[23] is read as the previous read
1608 * register value, so ignore it if reg_03 == reg_0[12].
1610 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1611 reg_03.raw != reg_01.raw) {
1612 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1613 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1616 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1618 x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
1621 __apicdebuginit(void) print_IO_APICs(void)
1624 struct irq_cfg *cfg;
1626 struct irq_chip *chip;
1628 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1629 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1630 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1631 mpc_ioapic_id(ioapic_idx),
1632 ioapics[ioapic_idx].nr_registers);
1635 * We are a bit conservative about what we expect. We have to
1636 * know about every hardware change ASAP.
1638 printk(KERN_INFO "testing the IO APIC.......................\n");
1640 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1641 print_IO_APIC(ioapic_idx);
1643 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1644 for_each_active_irq(irq) {
1645 struct irq_pin_list *entry;
1647 chip = irq_get_chip(irq);
1648 if (chip != &ioapic_chip)
1651 cfg = irq_get_chip_data(irq);
1654 entry = cfg->irq_2_pin;
1657 printk(KERN_DEBUG "IRQ%d ", irq);
1658 for_each_irq_pin(entry, cfg->irq_2_pin)
1659 pr_cont("-> %d:%d", entry->apic, entry->pin);
1663 printk(KERN_INFO ".................................... done.\n");
1666 __apicdebuginit(void) print_APIC_field(int base)
1672 for (i = 0; i < 8; i++)
1673 pr_cont("%08x", apic_read(base + i*0x10));
1678 __apicdebuginit(void) print_local_APIC(void *dummy)
1680 unsigned int i, v, ver, maxlvt;
1683 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1684 smp_processor_id(), hard_smp_processor_id());
1685 v = apic_read(APIC_ID);
1686 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1687 v = apic_read(APIC_LVR);
1688 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1689 ver = GET_APIC_VERSION(v);
1690 maxlvt = lapic_get_maxlvt();
1692 v = apic_read(APIC_TASKPRI);
1693 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1695 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1696 if (!APIC_XAPIC(ver)) {
1697 v = apic_read(APIC_ARBPRI);
1698 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1699 v & APIC_ARBPRI_MASK);
1701 v = apic_read(APIC_PROCPRI);
1702 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1706 * Remote read supported only in the 82489DX and local APIC for
1707 * Pentium processors.
1709 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1710 v = apic_read(APIC_RRR);
1711 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1714 v = apic_read(APIC_LDR);
1715 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1716 if (!x2apic_enabled()) {
1717 v = apic_read(APIC_DFR);
1718 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1720 v = apic_read(APIC_SPIV);
1721 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1723 printk(KERN_DEBUG "... APIC ISR field:\n");
1724 print_APIC_field(APIC_ISR);
1725 printk(KERN_DEBUG "... APIC TMR field:\n");
1726 print_APIC_field(APIC_TMR);
1727 printk(KERN_DEBUG "... APIC IRR field:\n");
1728 print_APIC_field(APIC_IRR);
1730 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1731 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1732 apic_write(APIC_ESR, 0);
1734 v = apic_read(APIC_ESR);
1735 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1738 icr = apic_icr_read();
1739 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1740 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1742 v = apic_read(APIC_LVTT);
1743 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1745 if (maxlvt > 3) { /* PC is LVT#4. */
1746 v = apic_read(APIC_LVTPC);
1747 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1749 v = apic_read(APIC_LVT0);
1750 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1751 v = apic_read(APIC_LVT1);
1752 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1754 if (maxlvt > 2) { /* ERR is LVT#3. */
1755 v = apic_read(APIC_LVTERR);
1756 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1759 v = apic_read(APIC_TMICT);
1760 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1761 v = apic_read(APIC_TMCCT);
1762 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1763 v = apic_read(APIC_TDCR);
1764 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1766 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1767 v = apic_read(APIC_EFEAT);
1768 maxlvt = (v >> 16) & 0xff;
1769 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1770 v = apic_read(APIC_ECTRL);
1771 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1772 for (i = 0; i < maxlvt; i++) {
1773 v = apic_read(APIC_EILVTn(i));
1774 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1780 __apicdebuginit(void) print_local_APICs(int maxcpu)
1788 for_each_online_cpu(cpu) {
1791 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1796 __apicdebuginit(void) print_PIC(void)
1799 unsigned long flags;
1801 if (!legacy_pic->nr_legacy_irqs)
1804 printk(KERN_DEBUG "\nprinting PIC contents\n");
1806 raw_spin_lock_irqsave(&i8259A_lock, flags);
1808 v = inb(0xa1) << 8 | inb(0x21);
1809 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1811 v = inb(0xa0) << 8 | inb(0x20);
1812 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1816 v = inb(0xa0) << 8 | inb(0x20);
1820 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1822 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1824 v = inb(0x4d1) << 8 | inb(0x4d0);
1825 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1828 static int __initdata show_lapic = 1;
1829 static __init int setup_show_lapic(char *arg)
1833 if (strcmp(arg, "all") == 0) {
1834 show_lapic = CONFIG_NR_CPUS;
1836 get_option(&arg, &num);
1843 __setup("show_lapic=", setup_show_lapic);
1845 __apicdebuginit(int) print_ICs(void)
1847 if (apic_verbosity == APIC_QUIET)
1852 /* don't print out if apic is not there */
1853 if (!cpu_has_apic && !apic_from_smp_config())
1856 print_local_APICs(show_lapic);
1862 late_initcall(print_ICs);
1865 /* Where if anywhere is the i8259 connect in external int mode */
1866 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1868 void __init enable_IO_APIC(void)
1870 int i8259_apic, i8259_pin;
1873 if (!legacy_pic->nr_legacy_irqs)
1876 for(apic = 0; apic < nr_ioapics; apic++) {
1878 /* See if any of the pins is in ExtINT mode */
1879 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1880 struct IO_APIC_route_entry entry;
1881 entry = ioapic_read_entry(apic, pin);
1883 /* If the interrupt line is enabled and in ExtInt mode
1884 * I have found the pin where the i8259 is connected.
1886 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1887 ioapic_i8259.apic = apic;
1888 ioapic_i8259.pin = pin;
1894 /* Look to see what if the MP table has reported the ExtINT */
1895 /* If we could not find the appropriate pin by looking at the ioapic
1896 * the i8259 probably is not connected the ioapic but give the
1897 * mptable a chance anyway.
1899 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1900 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1901 /* Trust the MP table if nothing is setup in the hardware */
1902 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1903 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1904 ioapic_i8259.pin = i8259_pin;
1905 ioapic_i8259.apic = i8259_apic;
1907 /* Complain if the MP table and the hardware disagree */
1908 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1909 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1911 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1915 * Do not trust the IO-APIC being empty at bootup
1920 void native_disable_io_apic(void)
1923 * If the i8259 is routed through an IOAPIC
1924 * Put that IOAPIC in virtual wire mode
1925 * so legacy interrupts can be delivered.
1927 if (ioapic_i8259.pin != -1) {
1928 struct IO_APIC_route_entry entry;
1930 memset(&entry, 0, sizeof(entry));
1931 entry.mask = 0; /* Enabled */
1932 entry.trigger = 0; /* Edge */
1934 entry.polarity = 0; /* High */
1935 entry.delivery_status = 0;
1936 entry.dest_mode = 0; /* Physical */
1937 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1939 entry.dest = read_apic_id();
1942 * Add it to the IO-APIC irq-routing table:
1944 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1947 if (cpu_has_apic || apic_from_smp_config())
1948 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1953 * Not an __init, needed by the reboot code
1955 void disable_IO_APIC(void)
1958 * Clear the IO-APIC before rebooting:
1962 if (!legacy_pic->nr_legacy_irqs)
1965 x86_io_apic_ops.disable();
1968 #ifdef CONFIG_X86_32
1970 * function to set the IO-APIC physical IDs based on the
1971 * values stored in the MPC table.
1973 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1975 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1977 union IO_APIC_reg_00 reg_00;
1978 physid_mask_t phys_id_present_map;
1981 unsigned char old_id;
1982 unsigned long flags;
1985 * This is broken; anything with a real cpu count has to
1986 * circumvent this idiocy regardless.
1988 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1991 * Set the IOAPIC ID to the value stored in the MPC table.
1993 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1994 /* Read the register 0 value */
1995 raw_spin_lock_irqsave(&ioapic_lock, flags);
1996 reg_00.raw = io_apic_read(ioapic_idx, 0);
1997 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1999 old_id = mpc_ioapic_id(ioapic_idx);
2001 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2002 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2003 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2004 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2006 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2010 * Sanity check, is the ID really free? Every APIC in a
2011 * system must have a unique ID or we get lots of nice
2012 * 'stuck on smp_invalidate_needed IPI wait' messages.
2014 if (apic->check_apicid_used(&phys_id_present_map,
2015 mpc_ioapic_id(ioapic_idx))) {
2016 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2017 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2018 for (i = 0; i < get_physical_broadcast(); i++)
2019 if (!physid_isset(i, phys_id_present_map))
2021 if (i >= get_physical_broadcast())
2022 panic("Max APIC ID exceeded!\n");
2023 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2025 physid_set(i, phys_id_present_map);
2026 ioapics[ioapic_idx].mp_config.apicid = i;
2029 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2031 apic_printk(APIC_VERBOSE, "Setting %d in the "
2032 "phys_id_present_map\n",
2033 mpc_ioapic_id(ioapic_idx));
2034 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2038 * We need to adjust the IRQ routing table
2039 * if the ID changed.
2041 if (old_id != mpc_ioapic_id(ioapic_idx))
2042 for (i = 0; i < mp_irq_entries; i++)
2043 if (mp_irqs[i].dstapic == old_id)
2045 = mpc_ioapic_id(ioapic_idx);
2048 * Update the ID register according to the right value
2049 * from the MPC table if they are different.
2051 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2054 apic_printk(APIC_VERBOSE, KERN_INFO
2055 "...changing IO-APIC physical APIC ID to %d ...",
2056 mpc_ioapic_id(ioapic_idx));
2058 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2059 raw_spin_lock_irqsave(&ioapic_lock, flags);
2060 io_apic_write(ioapic_idx, 0, reg_00.raw);
2061 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2066 raw_spin_lock_irqsave(&ioapic_lock, flags);
2067 reg_00.raw = io_apic_read(ioapic_idx, 0);
2068 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2069 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2070 pr_cont("could not set ID!\n");
2072 apic_printk(APIC_VERBOSE, " ok.\n");
2076 void __init setup_ioapic_ids_from_mpc(void)
2082 * Don't check I/O APIC IDs for xAPIC systems. They have
2083 * no meaning without the serial APIC bus.
2085 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2086 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2088 setup_ioapic_ids_from_mpc_nocheck();
2092 int no_timer_check __initdata;
2094 static int __init notimercheck(char *s)
2099 __setup("no_timer_check", notimercheck);
2102 * There is a nasty bug in some older SMP boards, their mptable lies
2103 * about the timer IRQ. We do the following to work around the situation:
2105 * - timer IRQ defaults to IO-APIC IRQ
2106 * - if this function detects that timer IRQs are defunct, then we fall
2107 * back to ISA timer IRQs
2109 static int __init timer_irq_works(void)
2111 unsigned long t1 = jiffies;
2112 unsigned long flags;
2117 local_save_flags(flags);
2119 /* Let ten ticks pass... */
2120 mdelay((10 * 1000) / HZ);
2121 local_irq_restore(flags);
2124 * Expect a few ticks at least, to be sure some possible
2125 * glue logic does not lock up after one or two first
2126 * ticks in a non-ExtINT mode. Also the local APIC
2127 * might have cached one ExtINT interrupt. Finally, at
2128 * least one tick may be lost due to delays.
2132 if (time_after(jiffies, t1 + 4))
2138 * In the SMP+IOAPIC case it might happen that there are an unspecified
2139 * number of pending IRQ events unhandled. These cases are very rare,
2140 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2141 * better to do it this way as thus we do not have to be aware of
2142 * 'pending' interrupts in the IRQ path, except at this point.
2145 * Edge triggered needs to resend any interrupt
2146 * that was delayed but this is now handled in the device
2151 * Starting up a edge-triggered IO-APIC interrupt is
2152 * nasty - we need to make sure that we get the edge.
2153 * If it is already asserted for some reason, we need
2154 * return 1 to indicate that is was pending.
2156 * This is not complete - we should be able to fake
2157 * an edge even if it isn't on the 8259A...
2160 static unsigned int startup_ioapic_irq(struct irq_data *data)
2162 int was_pending = 0, irq = data->irq;
2163 unsigned long flags;
2165 raw_spin_lock_irqsave(&ioapic_lock, flags);
2166 if (irq < legacy_pic->nr_legacy_irqs) {
2167 legacy_pic->mask(irq);
2168 if (legacy_pic->irq_pending(irq))
2171 __unmask_ioapic(data->chip_data);
2172 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2177 static int ioapic_retrigger_irq(struct irq_data *data)
2179 struct irq_cfg *cfg = data->chip_data;
2180 unsigned long flags;
2183 raw_spin_lock_irqsave(&vector_lock, flags);
2184 cpu = cpumask_first_and(cfg->domain, cpu_online_mask);
2185 apic->send_IPI_mask(cpumask_of(cpu), cfg->vector);
2186 raw_spin_unlock_irqrestore(&vector_lock, flags);
2192 * Level and edge triggered IO-APIC interrupts need different handling,
2193 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2194 * handled with the level-triggered descriptor, but that one has slightly
2195 * more overhead. Level-triggered interrupts cannot be handled with the
2196 * edge-triggered handler, without risking IRQ storms and other ugly
2201 void send_cleanup_vector(struct irq_cfg *cfg)
2203 cpumask_var_t cleanup_mask;
2205 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2207 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2208 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2210 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2211 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2212 free_cpumask_var(cleanup_mask);
2214 cfg->move_in_progress = 0;
2217 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2219 unsigned vector, me;
2225 me = smp_processor_id();
2226 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2229 struct irq_desc *desc;
2230 struct irq_cfg *cfg;
2231 irq = __this_cpu_read(vector_irq[vector]);
2236 desc = irq_to_desc(irq);
2244 raw_spin_lock(&desc->lock);
2247 * Check if the irq migration is in progress. If so, we
2248 * haven't received the cleanup request yet for this irq.
2250 if (cfg->move_in_progress)
2253 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2256 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2258 * Check if the vector that needs to be cleanedup is
2259 * registered at the cpu's IRR. If so, then this is not
2260 * the best time to clean it up. Lets clean it up in the
2261 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2264 if (irr & (1 << (vector % 32))) {
2265 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2268 __this_cpu_write(vector_irq[vector], -1);
2270 raw_spin_unlock(&desc->lock);
2276 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2280 if (likely(!cfg->move_in_progress))
2283 me = smp_processor_id();
2285 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2286 send_cleanup_vector(cfg);
2289 static void irq_complete_move(struct irq_cfg *cfg)
2291 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2294 void irq_force_complete_move(int irq)
2296 struct irq_cfg *cfg = irq_get_chip_data(irq);
2301 __irq_complete_move(cfg, cfg->vector);
2304 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2307 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2310 struct irq_pin_list *entry;
2311 u8 vector = cfg->vector;
2313 for_each_irq_pin(entry, cfg->irq_2_pin) {
2319 * With interrupt-remapping, destination information comes
2320 * from interrupt-remapping table entry.
2322 if (!irq_remapped(cfg))
2323 io_apic_write(apic, 0x11 + pin*2, dest);
2324 reg = io_apic_read(apic, 0x10 + pin*2);
2325 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2327 io_apic_modify(apic, 0x10 + pin*2, reg);
2332 * Either sets data->affinity to a valid value, and returns
2333 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2334 * leaves data->affinity untouched.
2336 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2337 unsigned int *dest_id)
2339 struct irq_cfg *cfg = data->chip_data;
2340 unsigned int irq = data->irq;
2343 if (!config_enabled(CONFIG_SMP))
2346 if (!cpumask_intersects(mask, cpu_online_mask))
2349 err = assign_irq_vector(irq, cfg, mask);
2353 err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
2355 if (assign_irq_vector(irq, cfg, data->affinity))
2356 pr_err("Failed to recover vector for irq %d\n", irq);
2360 cpumask_copy(data->affinity, mask);
2366 int native_ioapic_set_affinity(struct irq_data *data,
2367 const struct cpumask *mask,
2370 unsigned int dest, irq = data->irq;
2371 unsigned long flags;
2374 if (!config_enabled(CONFIG_SMP))
2377 raw_spin_lock_irqsave(&ioapic_lock, flags);
2378 ret = __ioapic_set_affinity(data, mask, &dest);
2380 /* Only the high 8 bits are valid. */
2381 dest = SET_APIC_LOGICAL_ID(dest);
2382 __target_IO_APIC_irq(irq, dest, data->chip_data);
2383 ret = IRQ_SET_MASK_OK_NOCOPY;
2385 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2389 static void ack_apic_edge(struct irq_data *data)
2391 irq_complete_move(data->chip_data);
2396 atomic_t irq_mis_count;
2398 #ifdef CONFIG_GENERIC_PENDING_IRQ
2399 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2401 struct irq_pin_list *entry;
2402 unsigned long flags;
2404 raw_spin_lock_irqsave(&ioapic_lock, flags);
2405 for_each_irq_pin(entry, cfg->irq_2_pin) {
2410 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2411 /* Is the remote IRR bit set? */
2412 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2413 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2417 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2422 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2424 /* If we are moving the irq we need to mask it */
2425 if (unlikely(irqd_is_setaffinity_pending(data))) {
2432 static inline void ioapic_irqd_unmask(struct irq_data *data,
2433 struct irq_cfg *cfg, bool masked)
2435 if (unlikely(masked)) {
2436 /* Only migrate the irq if the ack has been received.
2438 * On rare occasions the broadcast level triggered ack gets
2439 * delayed going to ioapics, and if we reprogram the
2440 * vector while Remote IRR is still set the irq will never
2443 * To prevent this scenario we read the Remote IRR bit
2444 * of the ioapic. This has two effects.
2445 * - On any sane system the read of the ioapic will
2446 * flush writes (and acks) going to the ioapic from
2448 * - We get to see if the ACK has actually been delivered.
2450 * Based on failed experiments of reprogramming the
2451 * ioapic entry from outside of irq context starting
2452 * with masking the ioapic entry and then polling until
2453 * Remote IRR was clear before reprogramming the
2454 * ioapic I don't trust the Remote IRR bit to be
2455 * completey accurate.
2457 * However there appears to be no other way to plug
2458 * this race, so if the Remote IRR bit is not
2459 * accurate and is causing problems then it is a hardware bug
2460 * and you can go talk to the chipset vendor about it.
2462 if (!io_apic_level_ack_pending(cfg))
2463 irq_move_masked_irq(data);
2468 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2472 static inline void ioapic_irqd_unmask(struct irq_data *data,
2473 struct irq_cfg *cfg, bool masked)
2478 static void ack_apic_level(struct irq_data *data)
2480 struct irq_cfg *cfg = data->chip_data;
2481 int i, irq = data->irq;
2485 irq_complete_move(cfg);
2486 masked = ioapic_irqd_mask(data, cfg);
2489 * It appears there is an erratum which affects at least version 0x11
2490 * of I/O APIC (that's the 82093AA and cores integrated into various
2491 * chipsets). Under certain conditions a level-triggered interrupt is
2492 * erroneously delivered as edge-triggered one but the respective IRR
2493 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2494 * message but it will never arrive and further interrupts are blocked
2495 * from the source. The exact reason is so far unknown, but the
2496 * phenomenon was observed when two consecutive interrupt requests
2497 * from a given source get delivered to the same CPU and the source is
2498 * temporarily disabled in between.
2500 * A workaround is to simulate an EOI message manually. We achieve it
2501 * by setting the trigger mode to edge and then to level when the edge
2502 * trigger mode gets detected in the TMR of a local APIC for a
2503 * level-triggered interrupt. We mask the source for the time of the
2504 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2505 * The idea is from Manfred Spraul. --macro
2507 * Also in the case when cpu goes offline, fixup_irqs() will forward
2508 * any unhandled interrupt on the offlined cpu to the new cpu
2509 * destination that is handling the corresponding interrupt. This
2510 * interrupt forwarding is done via IPI's. Hence, in this case also
2511 * level-triggered io-apic interrupt will be seen as an edge
2512 * interrupt in the IRR. And we can't rely on the cpu's EOI
2513 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2514 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2515 * supporting EOI register, we do an explicit EOI to clear the
2516 * remote IRR and on IO-APIC's which don't have an EOI register,
2517 * we use the above logic (mask+edge followed by unmask+level) from
2518 * Manfred Spraul to clear the remote IRR.
2521 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2524 * We must acknowledge the irq before we move it or the acknowledge will
2525 * not propagate properly.
2530 * Tail end of clearing remote IRR bit (either by delivering the EOI
2531 * message via io-apic EOI register write or simulating it using
2532 * mask+edge followed by unnask+level logic) manually when the
2533 * level triggered interrupt is seen as the edge triggered interrupt
2536 if (!(v & (1 << (i & 0x1f)))) {
2537 atomic_inc(&irq_mis_count);
2539 eoi_ioapic_irq(irq, cfg);
2542 ioapic_irqd_unmask(data, cfg, masked);
2545 #ifdef CONFIG_IRQ_REMAP
2546 static void ir_ack_apic_edge(struct irq_data *data)
2551 static void ir_ack_apic_level(struct irq_data *data)
2554 eoi_ioapic_irq(data->irq, data->chip_data);
2557 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2559 seq_printf(p, " IR-%s", data->chip->name);
2562 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2564 chip->irq_print_chip = ir_print_prefix;
2565 chip->irq_ack = ir_ack_apic_edge;
2566 chip->irq_eoi = ir_ack_apic_level;
2567 chip->irq_set_affinity = x86_io_apic_ops.set_affinity;
2569 #endif /* CONFIG_IRQ_REMAP */
2571 static struct irq_chip ioapic_chip __read_mostly = {
2573 .irq_startup = startup_ioapic_irq,
2574 .irq_mask = mask_ioapic_irq,
2575 .irq_unmask = unmask_ioapic_irq,
2576 .irq_ack = ack_apic_edge,
2577 .irq_eoi = ack_apic_level,
2578 .irq_set_affinity = native_ioapic_set_affinity,
2579 .irq_retrigger = ioapic_retrigger_irq,
2582 static inline void init_IO_APIC_traps(void)
2584 struct irq_cfg *cfg;
2588 * NOTE! The local APIC isn't very good at handling
2589 * multiple interrupts at the same interrupt level.
2590 * As the interrupt level is determined by taking the
2591 * vector number and shifting that right by 4, we
2592 * want to spread these out a bit so that they don't
2593 * all fall in the same interrupt level.
2595 * Also, we've got to be careful not to trash gate
2596 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2598 for_each_active_irq(irq) {
2599 cfg = irq_get_chip_data(irq);
2600 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2602 * Hmm.. We don't have an entry for this,
2603 * so default to an old-fashioned 8259
2604 * interrupt if we can..
2606 if (irq < legacy_pic->nr_legacy_irqs)
2607 legacy_pic->make_irq(irq);
2609 /* Strange. Oh, well.. */
2610 irq_set_chip(irq, &no_irq_chip);
2616 * The local APIC irq-chip implementation:
2619 static void mask_lapic_irq(struct irq_data *data)
2623 v = apic_read(APIC_LVT0);
2624 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2627 static void unmask_lapic_irq(struct irq_data *data)
2631 v = apic_read(APIC_LVT0);
2632 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2635 static void ack_lapic_irq(struct irq_data *data)
2640 static struct irq_chip lapic_chip __read_mostly = {
2641 .name = "local-APIC",
2642 .irq_mask = mask_lapic_irq,
2643 .irq_unmask = unmask_lapic_irq,
2644 .irq_ack = ack_lapic_irq,
2647 static void lapic_register_intr(int irq)
2649 irq_clear_status_flags(irq, IRQ_LEVEL);
2650 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2655 * This looks a bit hackish but it's about the only one way of sending
2656 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2657 * not support the ExtINT mode, unfortunately. We need to send these
2658 * cycles as some i82489DX-based boards have glue logic that keeps the
2659 * 8259A interrupt line asserted until INTA. --macro
2661 static inline void __init unlock_ExtINT_logic(void)
2664 struct IO_APIC_route_entry entry0, entry1;
2665 unsigned char save_control, save_freq_select;
2667 pin = find_isa_irq_pin(8, mp_INT);
2672 apic = find_isa_irq_apic(8, mp_INT);
2678 entry0 = ioapic_read_entry(apic, pin);
2679 clear_IO_APIC_pin(apic, pin);
2681 memset(&entry1, 0, sizeof(entry1));
2683 entry1.dest_mode = 0; /* physical delivery */
2684 entry1.mask = 0; /* unmask IRQ now */
2685 entry1.dest = hard_smp_processor_id();
2686 entry1.delivery_mode = dest_ExtINT;
2687 entry1.polarity = entry0.polarity;
2691 ioapic_write_entry(apic, pin, entry1);
2693 save_control = CMOS_READ(RTC_CONTROL);
2694 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2695 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2697 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2702 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2706 CMOS_WRITE(save_control, RTC_CONTROL);
2707 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2708 clear_IO_APIC_pin(apic, pin);
2710 ioapic_write_entry(apic, pin, entry0);
2713 static int disable_timer_pin_1 __initdata;
2714 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2715 static int __init disable_timer_pin_setup(char *arg)
2717 disable_timer_pin_1 = 1;
2720 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2722 int timer_through_8259 __initdata;
2725 * This code may look a bit paranoid, but it's supposed to cooperate with
2726 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2727 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2728 * fanatically on his truly buggy board.
2730 * FIXME: really need to revamp this for all platforms.
2732 static inline void __init check_timer(void)
2734 struct irq_cfg *cfg = irq_get_chip_data(0);
2735 int node = cpu_to_node(0);
2736 int apic1, pin1, apic2, pin2;
2737 unsigned long flags;
2740 local_irq_save(flags);
2743 * get/set the timer IRQ vector:
2745 legacy_pic->mask(0);
2746 assign_irq_vector(0, cfg, apic->target_cpus());
2749 * As IRQ0 is to be enabled in the 8259A, the virtual
2750 * wire has to be disabled in the local APIC. Also
2751 * timer interrupts need to be acknowledged manually in
2752 * the 8259A for the i82489DX when using the NMI
2753 * watchdog as that APIC treats NMIs as level-triggered.
2754 * The AEOI mode will finish them in the 8259A
2757 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2758 legacy_pic->init(1);
2760 pin1 = find_isa_irq_pin(0, mp_INT);
2761 apic1 = find_isa_irq_apic(0, mp_INT);
2762 pin2 = ioapic_i8259.pin;
2763 apic2 = ioapic_i8259.apic;
2765 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2766 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2767 cfg->vector, apic1, pin1, apic2, pin2);
2770 * Some BIOS writers are clueless and report the ExtINTA
2771 * I/O APIC input from the cascaded 8259A as the timer
2772 * interrupt input. So just in case, if only one pin
2773 * was found above, try it both directly and through the
2777 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2781 } else if (pin2 == -1) {
2788 * Ok, does IRQ0 through the IOAPIC work?
2791 add_pin_to_irq_node(cfg, node, apic1, pin1);
2792 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2794 /* for edge trigger, setup_ioapic_irq already
2795 * leave it unmasked.
2796 * so only need to unmask if it is level-trigger
2797 * do we really have level trigger timer?
2800 idx = find_irq_entry(apic1, pin1, mp_INT);
2801 if (idx != -1 && irq_trigger(idx))
2804 if (timer_irq_works()) {
2805 if (disable_timer_pin_1 > 0)
2806 clear_IO_APIC_pin(0, pin1);
2809 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2810 local_irq_disable();
2811 clear_IO_APIC_pin(apic1, pin1);
2813 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2814 "8254 timer not connected to IO-APIC\n");
2816 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2817 "(IRQ0) through the 8259A ...\n");
2818 apic_printk(APIC_QUIET, KERN_INFO
2819 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2821 * legacy devices should be connected to IO APIC #0
2823 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2824 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2825 legacy_pic->unmask(0);
2826 if (timer_irq_works()) {
2827 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2828 timer_through_8259 = 1;
2832 * Cleanup, just in case ...
2834 local_irq_disable();
2835 legacy_pic->mask(0);
2836 clear_IO_APIC_pin(apic2, pin2);
2837 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2840 apic_printk(APIC_QUIET, KERN_INFO
2841 "...trying to set up timer as Virtual Wire IRQ...\n");
2843 lapic_register_intr(0);
2844 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2845 legacy_pic->unmask(0);
2847 if (timer_irq_works()) {
2848 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2851 local_irq_disable();
2852 legacy_pic->mask(0);
2853 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2854 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2856 apic_printk(APIC_QUIET, KERN_INFO
2857 "...trying to set up timer as ExtINT IRQ...\n");
2859 legacy_pic->init(0);
2860 legacy_pic->make_irq(0);
2861 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2863 unlock_ExtINT_logic();
2865 if (timer_irq_works()) {
2866 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2869 local_irq_disable();
2870 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2871 if (x2apic_preenabled)
2872 apic_printk(APIC_QUIET, KERN_INFO
2873 "Perhaps problem with the pre-enabled x2apic mode\n"
2874 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2875 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2876 "report. Then try booting with the 'noapic' option.\n");
2878 local_irq_restore(flags);
2882 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2883 * to devices. However there may be an I/O APIC pin available for
2884 * this interrupt regardless. The pin may be left unconnected, but
2885 * typically it will be reused as an ExtINT cascade interrupt for
2886 * the master 8259A. In the MPS case such a pin will normally be
2887 * reported as an ExtINT interrupt in the MP table. With ACPI
2888 * there is no provision for ExtINT interrupts, and in the absence
2889 * of an override it would be treated as an ordinary ISA I/O APIC
2890 * interrupt, that is edge-triggered and unmasked by default. We
2891 * used to do this, but it caused problems on some systems because
2892 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2893 * the same ExtINT cascade interrupt to drive the local APIC of the
2894 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2895 * the I/O APIC in all cases now. No actual device should request
2896 * it anyway. --macro
2898 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2900 void __init setup_IO_APIC(void)
2904 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2906 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2908 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2910 * Set up IO-APIC IRQ routing.
2912 x86_init.mpparse.setup_ioapic_ids();
2915 setup_IO_APIC_irqs();
2916 init_IO_APIC_traps();
2917 if (legacy_pic->nr_legacy_irqs)
2922 * Called after all the initialization is done. If we didn't find any
2923 * APIC bugs then we can allow the modify fast path
2926 static int __init io_apic_bug_finalize(void)
2928 if (sis_apic_bug == -1)
2933 late_initcall(io_apic_bug_finalize);
2935 static void resume_ioapic_id(int ioapic_idx)
2937 unsigned long flags;
2938 union IO_APIC_reg_00 reg_00;
2940 raw_spin_lock_irqsave(&ioapic_lock, flags);
2941 reg_00.raw = io_apic_read(ioapic_idx, 0);
2942 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2943 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2944 io_apic_write(ioapic_idx, 0, reg_00.raw);
2946 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2949 static void ioapic_resume(void)
2953 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2954 resume_ioapic_id(ioapic_idx);
2956 restore_ioapic_entries();
2959 static struct syscore_ops ioapic_syscore_ops = {
2960 .suspend = save_ioapic_entries,
2961 .resume = ioapic_resume,
2964 static int __init ioapic_init_ops(void)
2966 register_syscore_ops(&ioapic_syscore_ops);
2971 device_initcall(ioapic_init_ops);
2974 * Dynamic irq allocate and deallocation
2976 unsigned int __create_irqs(unsigned int from, unsigned int count, int node)
2978 struct irq_cfg **cfg;
2979 unsigned long flags;
2982 if (from < nr_irqs_gsi)
2985 cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node);
2989 irq = alloc_irqs_from(from, count, node);
2993 for (i = 0; i < count; i++) {
2994 cfg[i] = alloc_irq_cfg(irq + i, node);
2999 raw_spin_lock_irqsave(&vector_lock, flags);
3000 for (i = 0; i < count; i++)
3001 if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus()))
3003 raw_spin_unlock_irqrestore(&vector_lock, flags);
3005 for (i = 0; i < count; i++) {
3006 irq_set_chip_data(irq + i, cfg[i]);
3007 irq_clear_status_flags(irq + i, IRQ_NOREQUEST);
3014 for (i--; i >= 0; i--)
3015 __clear_irq_vector(irq + i, cfg[i]);
3016 raw_spin_unlock_irqrestore(&vector_lock, flags);
3018 for (i = 0; i < count; i++)
3019 free_irq_at(irq + i, cfg[i]);
3025 unsigned int create_irq_nr(unsigned int from, int node)
3027 return __create_irqs(from, 1, node);
3030 int create_irq(void)
3032 int node = cpu_to_node(0);
3033 unsigned int irq_want;
3036 irq_want = nr_irqs_gsi;
3037 irq = create_irq_nr(irq_want, node);
3045 void destroy_irq(unsigned int irq)
3047 struct irq_cfg *cfg = irq_get_chip_data(irq);
3048 unsigned long flags;
3050 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3052 if (irq_remapped(cfg))
3053 free_remapped_irq(irq);
3054 raw_spin_lock_irqsave(&vector_lock, flags);
3055 __clear_irq_vector(irq, cfg);
3056 raw_spin_unlock_irqrestore(&vector_lock, flags);
3057 free_irq_at(irq, cfg);
3060 void destroy_irqs(unsigned int irq, unsigned int count)
3064 for (i = 0; i < count; i++)
3065 destroy_irq(irq + i);
3069 * MSI message composition
3071 #ifdef CONFIG_PCI_MSI
3072 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3073 struct msi_msg *msg, u8 hpet_id)
3075 struct irq_cfg *cfg;
3083 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3087 err = apic->cpu_mask_to_apicid_and(cfg->domain,
3088 apic->target_cpus(), &dest);
3092 if (irq_remapped(cfg)) {
3093 compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
3097 if (x2apic_enabled())
3098 msg->address_hi = MSI_ADDR_BASE_HI |
3099 MSI_ADDR_EXT_DEST_ID(dest);
3101 msg->address_hi = MSI_ADDR_BASE_HI;
3105 ((apic->irq_dest_mode == 0) ?
3106 MSI_ADDR_DEST_MODE_PHYSICAL:
3107 MSI_ADDR_DEST_MODE_LOGICAL) |
3108 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3109 MSI_ADDR_REDIRECTION_CPU:
3110 MSI_ADDR_REDIRECTION_LOWPRI) |
3111 MSI_ADDR_DEST_ID(dest);
3114 MSI_DATA_TRIGGER_EDGE |
3115 MSI_DATA_LEVEL_ASSERT |
3116 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3117 MSI_DATA_DELIVERY_FIXED:
3118 MSI_DATA_DELIVERY_LOWPRI) |
3119 MSI_DATA_VECTOR(cfg->vector);
3125 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3127 struct irq_cfg *cfg = data->chip_data;
3131 if (__ioapic_set_affinity(data, mask, &dest))
3134 __get_cached_msi_msg(data->msi_desc, &msg);
3136 msg.data &= ~MSI_DATA_VECTOR_MASK;
3137 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3138 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3139 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3141 __write_msi_msg(data->msi_desc, &msg);
3143 return IRQ_SET_MASK_OK_NOCOPY;
3147 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3148 * which implement the MSI or MSI-X Capability Structure.
3150 static struct irq_chip msi_chip = {
3152 .irq_unmask = unmask_msi_irq,
3153 .irq_mask = mask_msi_irq,
3154 .irq_ack = ack_apic_edge,
3155 .irq_set_affinity = msi_set_affinity,
3156 .irq_retrigger = ioapic_retrigger_irq,
3159 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
3160 unsigned int irq_base, unsigned int irq_offset)
3162 struct irq_chip *chip = &msi_chip;
3164 unsigned int irq = irq_base + irq_offset;
3167 ret = msi_compose_msg(dev, irq, &msg, -1);
3171 irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
3174 * MSI-X message is written per-IRQ, the offset is always 0.
3175 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3178 write_msi_msg(irq, &msg);
3180 if (irq_remapped(irq_get_chip_data(irq))) {
3181 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3182 irq_remap_modify_chip_defaults(chip);
3185 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3187 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3192 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3194 unsigned int irq, irq_want;
3195 struct msi_desc *msidesc;
3198 /* Multiple MSI vectors only supported with interrupt remapping */
3199 if (type == PCI_CAP_ID_MSI && nvec > 1)
3202 node = dev_to_node(&dev->dev);
3203 irq_want = nr_irqs_gsi;
3204 list_for_each_entry(msidesc, &dev->msi_list, list) {
3205 irq = create_irq_nr(irq_want, node);
3211 ret = setup_msi_irq(dev, msidesc, irq, 0);
3222 void native_teardown_msi_irq(unsigned int irq)
3227 #ifdef CONFIG_DMAR_TABLE
3229 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3232 struct irq_cfg *cfg = data->chip_data;
3233 unsigned int dest, irq = data->irq;
3236 if (__ioapic_set_affinity(data, mask, &dest))
3239 dmar_msi_read(irq, &msg);
3241 msg.data &= ~MSI_DATA_VECTOR_MASK;
3242 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3243 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3244 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3245 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3247 dmar_msi_write(irq, &msg);
3249 return IRQ_SET_MASK_OK_NOCOPY;
3252 static struct irq_chip dmar_msi_type = {
3254 .irq_unmask = dmar_msi_unmask,
3255 .irq_mask = dmar_msi_mask,
3256 .irq_ack = ack_apic_edge,
3257 .irq_set_affinity = dmar_msi_set_affinity,
3258 .irq_retrigger = ioapic_retrigger_irq,
3261 int arch_setup_dmar_msi(unsigned int irq)
3266 ret = msi_compose_msg(NULL, irq, &msg, -1);
3269 dmar_msi_write(irq, &msg);
3270 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3276 #ifdef CONFIG_HPET_TIMER
3278 static int hpet_msi_set_affinity(struct irq_data *data,
3279 const struct cpumask *mask, bool force)
3281 struct irq_cfg *cfg = data->chip_data;
3285 if (__ioapic_set_affinity(data, mask, &dest))
3288 hpet_msi_read(data->handler_data, &msg);
3290 msg.data &= ~MSI_DATA_VECTOR_MASK;
3291 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3292 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3293 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3295 hpet_msi_write(data->handler_data, &msg);
3297 return IRQ_SET_MASK_OK_NOCOPY;
3300 static struct irq_chip hpet_msi_type = {
3302 .irq_unmask = hpet_msi_unmask,
3303 .irq_mask = hpet_msi_mask,
3304 .irq_ack = ack_apic_edge,
3305 .irq_set_affinity = hpet_msi_set_affinity,
3306 .irq_retrigger = ioapic_retrigger_irq,
3309 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
3311 struct irq_chip *chip = &hpet_msi_type;
3315 ret = msi_compose_msg(NULL, irq, &msg, id);
3319 hpet_msi_write(irq_get_handler_data(irq), &msg);
3320 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3321 if (irq_remapped(irq_get_chip_data(irq)))
3322 irq_remap_modify_chip_defaults(chip);
3324 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3329 #endif /* CONFIG_PCI_MSI */
3331 * Hypertransport interrupt support
3333 #ifdef CONFIG_HT_IRQ
3335 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3337 struct ht_irq_msg msg;
3338 fetch_ht_irq_msg(irq, &msg);
3340 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3341 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3343 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3344 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3346 write_ht_irq_msg(irq, &msg);
3350 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3352 struct irq_cfg *cfg = data->chip_data;
3355 if (__ioapic_set_affinity(data, mask, &dest))
3358 target_ht_irq(data->irq, dest, cfg->vector);
3359 return IRQ_SET_MASK_OK_NOCOPY;
3362 static struct irq_chip ht_irq_chip = {
3364 .irq_mask = mask_ht_irq,
3365 .irq_unmask = unmask_ht_irq,
3366 .irq_ack = ack_apic_edge,
3367 .irq_set_affinity = ht_set_affinity,
3368 .irq_retrigger = ioapic_retrigger_irq,
3371 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3373 struct irq_cfg *cfg;
3374 struct ht_irq_msg msg;
3382 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3386 err = apic->cpu_mask_to_apicid_and(cfg->domain,
3387 apic->target_cpus(), &dest);
3391 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3395 HT_IRQ_LOW_DEST_ID(dest) |
3396 HT_IRQ_LOW_VECTOR(cfg->vector) |
3397 ((apic->irq_dest_mode == 0) ?
3398 HT_IRQ_LOW_DM_PHYSICAL :
3399 HT_IRQ_LOW_DM_LOGICAL) |
3400 HT_IRQ_LOW_RQEOI_EDGE |
3401 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3402 HT_IRQ_LOW_MT_FIXED :
3403 HT_IRQ_LOW_MT_ARBITRATED) |
3404 HT_IRQ_LOW_IRQ_MASKED;
3406 write_ht_irq_msg(irq, &msg);
3408 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3409 handle_edge_irq, "edge");
3411 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3415 #endif /* CONFIG_HT_IRQ */
3418 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3420 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3425 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3427 setup_ioapic_irq(irq, cfg, attr);
3431 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3432 struct io_apic_irq_attr *attr)
3434 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3437 /* Avoid redundant programming */
3438 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3439 pr_debug("Pin %d-%d already programmed\n",
3440 mpc_ioapic_id(ioapic_idx), pin);
3443 ret = io_apic_setup_irq_pin(irq, node, attr);
3445 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3449 static int __init io_apic_get_redir_entries(int ioapic)
3451 union IO_APIC_reg_01 reg_01;
3452 unsigned long flags;
3454 raw_spin_lock_irqsave(&ioapic_lock, flags);
3455 reg_01.raw = io_apic_read(ioapic, 1);
3456 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3458 /* The register returns the maximum index redir index
3459 * supported, which is one less than the total number of redir
3462 return reg_01.bits.entries + 1;
3465 static void __init probe_nr_irqs_gsi(void)
3469 nr = gsi_top + NR_IRQS_LEGACY;
3470 if (nr > nr_irqs_gsi)
3473 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3476 int get_nr_irqs_gsi(void)
3481 int __init arch_probe_nr_irqs(void)
3485 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3486 nr_irqs = NR_VECTORS * nr_cpu_ids;
3488 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3489 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3491 * for MSI and HT dyn irq
3493 nr += nr_irqs_gsi * 16;
3498 return NR_IRQS_LEGACY;
3501 int io_apic_set_pci_routing(struct device *dev, int irq,
3502 struct io_apic_irq_attr *irq_attr)
3506 if (!IO_APIC_IRQ(irq)) {
3507 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3512 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3514 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3517 #ifdef CONFIG_X86_32
3518 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3520 union IO_APIC_reg_00 reg_00;
3521 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3523 unsigned long flags;
3527 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3528 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3529 * supports up to 16 on one shared APIC bus.
3531 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3532 * advantage of new APIC bus architecture.
3535 if (physids_empty(apic_id_map))
3536 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3538 raw_spin_lock_irqsave(&ioapic_lock, flags);
3539 reg_00.raw = io_apic_read(ioapic, 0);
3540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3542 if (apic_id >= get_physical_broadcast()) {
3543 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3544 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3545 apic_id = reg_00.bits.ID;
3549 * Every APIC in a system must have a unique ID or we get lots of nice
3550 * 'stuck on smp_invalidate_needed IPI wait' messages.
3552 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3554 for (i = 0; i < get_physical_broadcast(); i++) {
3555 if (!apic->check_apicid_used(&apic_id_map, i))
3559 if (i == get_physical_broadcast())
3560 panic("Max apic_id exceeded!\n");
3562 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3563 "trying %d\n", ioapic, apic_id, i);
3568 apic->apicid_to_cpu_present(apic_id, &tmp);
3569 physids_or(apic_id_map, apic_id_map, tmp);
3571 if (reg_00.bits.ID != apic_id) {
3572 reg_00.bits.ID = apic_id;
3574 raw_spin_lock_irqsave(&ioapic_lock, flags);
3575 io_apic_write(ioapic, 0, reg_00.raw);
3576 reg_00.raw = io_apic_read(ioapic, 0);
3577 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3580 if (reg_00.bits.ID != apic_id) {
3581 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3587 apic_printk(APIC_VERBOSE, KERN_INFO
3588 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3593 static u8 __init io_apic_unique_id(u8 id)
3595 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3596 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3597 return io_apic_get_unique_id(nr_ioapics, id);
3602 static u8 __init io_apic_unique_id(u8 id)
3605 DECLARE_BITMAP(used, 256);
3607 bitmap_zero(used, 256);
3608 for (i = 0; i < nr_ioapics; i++) {
3609 __set_bit(mpc_ioapic_id(i), used);
3611 if (!test_bit(id, used))
3613 return find_first_zero_bit(used, 256);
3617 static int __init io_apic_get_version(int ioapic)
3619 union IO_APIC_reg_01 reg_01;
3620 unsigned long flags;
3622 raw_spin_lock_irqsave(&ioapic_lock, flags);
3623 reg_01.raw = io_apic_read(ioapic, 1);
3624 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3626 return reg_01.bits.version;
3629 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3631 int ioapic, pin, idx;
3633 if (skip_ioapic_setup)
3636 ioapic = mp_find_ioapic(gsi);
3640 pin = mp_find_ioapic_pin(ioapic, gsi);
3644 idx = find_irq_entry(ioapic, pin, mp_INT);
3648 *trigger = irq_trigger(idx);
3649 *polarity = irq_polarity(idx);
3654 * This function currently is only a helper for the i386 smp boot process where
3655 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3656 * so mask in all cases should simply be apic->target_cpus()
3659 void __init setup_ioapic_dest(void)
3661 int pin, ioapic, irq, irq_entry;
3662 const struct cpumask *mask;
3663 struct irq_data *idata;
3665 if (skip_ioapic_setup == 1)
3668 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3669 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3670 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3671 if (irq_entry == -1)
3673 irq = pin_2_irq(irq_entry, ioapic, pin);
3675 if ((ioapic > 0) && (irq > 16))
3678 idata = irq_get_irq_data(irq);
3681 * Honour affinities which have been set in early boot
3683 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3684 mask = idata->affinity;
3686 mask = apic->target_cpus();
3688 x86_io_apic_ops.set_affinity(idata, mask, false);
3694 #define IOAPIC_RESOURCE_NAME_SIZE 11
3696 static struct resource *ioapic_resources;
3698 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3701 struct resource *res;
3705 if (nr_ioapics <= 0)
3708 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3711 mem = alloc_bootmem(n);
3714 mem += sizeof(struct resource) * nr_ioapics;
3716 for (i = 0; i < nr_ioapics; i++) {
3718 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3719 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3720 mem += IOAPIC_RESOURCE_NAME_SIZE;
3723 ioapic_resources = res;
3728 void __init native_io_apic_init_mappings(void)
3730 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3731 struct resource *ioapic_res;
3734 ioapic_res = ioapic_setup_resources(nr_ioapics);
3735 for (i = 0; i < nr_ioapics; i++) {
3736 if (smp_found_config) {
3737 ioapic_phys = mpc_ioapic_addr(i);
3738 #ifdef CONFIG_X86_32
3741 "WARNING: bogus zero IO-APIC "
3742 "address found in MPTABLE, "
3743 "disabling IO/APIC support!\n");
3744 smp_found_config = 0;
3745 skip_ioapic_setup = 1;
3746 goto fake_ioapic_page;
3750 #ifdef CONFIG_X86_32
3753 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3754 ioapic_phys = __pa(ioapic_phys);
3756 set_fixmap_nocache(idx, ioapic_phys);
3757 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3758 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3762 ioapic_res->start = ioapic_phys;
3763 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3767 probe_nr_irqs_gsi();
3770 void __init ioapic_insert_resources(void)
3773 struct resource *r = ioapic_resources;
3778 "IO APIC resources couldn't be allocated.\n");
3782 for (i = 0; i < nr_ioapics; i++) {
3783 insert_resource(&iomem_resource, r);
3788 int mp_find_ioapic(u32 gsi)
3792 if (nr_ioapics == 0)
3795 /* Find the IOAPIC that manages this GSI. */
3796 for (i = 0; i < nr_ioapics; i++) {
3797 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3798 if ((gsi >= gsi_cfg->gsi_base)
3799 && (gsi <= gsi_cfg->gsi_end))
3803 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3807 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3809 struct mp_ioapic_gsi *gsi_cfg;
3811 if (WARN_ON(ioapic == -1))
3814 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3815 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3818 return gsi - gsi_cfg->gsi_base;
3821 static __init int bad_ioapic(unsigned long address)
3823 if (nr_ioapics >= MAX_IO_APICS) {
3824 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3825 MAX_IO_APICS, nr_ioapics);
3829 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3835 static __init int bad_ioapic_register(int idx)
3837 union IO_APIC_reg_00 reg_00;
3838 union IO_APIC_reg_01 reg_01;
3839 union IO_APIC_reg_02 reg_02;
3841 reg_00.raw = io_apic_read(idx, 0);
3842 reg_01.raw = io_apic_read(idx, 1);
3843 reg_02.raw = io_apic_read(idx, 2);
3845 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3846 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3847 mpc_ioapic_addr(idx));
3854 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3858 struct mp_ioapic_gsi *gsi_cfg;
3860 if (bad_ioapic(address))
3865 ioapics[idx].mp_config.type = MP_IOAPIC;
3866 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3867 ioapics[idx].mp_config.apicaddr = address;
3869 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3871 if (bad_ioapic_register(idx)) {
3872 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3876 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3877 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3880 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3881 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3883 entries = io_apic_get_redir_entries(idx);
3884 gsi_cfg = mp_ioapic_gsi_routing(idx);
3885 gsi_cfg->gsi_base = gsi_base;
3886 gsi_cfg->gsi_end = gsi_base + entries - 1;
3889 * The number of IO-APIC IRQ registers (== #pins):
3891 ioapics[idx].nr_registers = entries;
3893 if (gsi_cfg->gsi_end >= gsi_top)
3894 gsi_top = gsi_cfg->gsi_end + 1;
3896 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3897 idx, mpc_ioapic_id(idx),
3898 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3899 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3904 /* Enable IOAPIC early just for system timer */
3905 void __init pre_init_apic_IRQ0(void)
3907 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3909 printk(KERN_INFO "Early APIC setup for system timer0\n");
3911 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3912 &phys_cpu_present_map);
3916 io_apic_setup_irq_pin(0, 0, &attr);
3917 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,