2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/pci-ats.h>
22 #include <linux/bitmap.h>
23 #include <linux/slab.h>
24 #include <linux/debugfs.h>
25 #include <linux/scatterlist.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/iommu-helper.h>
28 #include <linux/iommu.h>
29 #include <linux/delay.h>
30 #include <asm/proto.h>
31 #include <asm/iommu.h>
33 #include <asm/amd_iommu_proto.h>
34 #include <asm/amd_iommu_types.h>
35 #include <asm/amd_iommu.h>
37 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
39 #define LOOP_TIMEOUT 100000
41 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
43 /* A list of preallocated protection domains */
44 static LIST_HEAD(iommu_pd_list);
45 static DEFINE_SPINLOCK(iommu_pd_list_lock);
48 * Domain for untranslated devices - only allocated
49 * if iommu=pt passed on kernel cmd line.
51 static struct protection_domain *pt_domain;
53 static struct iommu_ops amd_iommu_ops;
56 * general struct to manage commands send to an IOMMU
62 static void update_domain(struct protection_domain *domain);
64 /****************************************************************************
68 ****************************************************************************/
70 static inline u16 get_device_id(struct device *dev)
72 struct pci_dev *pdev = to_pci_dev(dev);
74 return calc_devid(pdev->bus->number, pdev->devfn);
77 static struct iommu_dev_data *get_dev_data(struct device *dev)
79 return dev->archdata.iommu;
83 * In this function the list of preallocated protection domains is traversed to
84 * find the domain for a specific device
86 static struct dma_ops_domain *find_protection_domain(u16 devid)
88 struct dma_ops_domain *entry, *ret = NULL;
90 u16 alias = amd_iommu_alias_table[devid];
92 if (list_empty(&iommu_pd_list))
95 spin_lock_irqsave(&iommu_pd_list_lock, flags);
97 list_for_each_entry(entry, &iommu_pd_list, list) {
98 if (entry->target_dev == devid ||
99 entry->target_dev == alias) {
105 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
111 * This function checks if the driver got a valid device from the caller to
112 * avoid dereferencing invalid pointers.
114 static bool check_device(struct device *dev)
118 if (!dev || !dev->dma_mask)
121 /* No device or no PCI device */
122 if (dev->bus != &pci_bus_type)
125 devid = get_device_id(dev);
127 /* Out of our scope? */
128 if (devid > amd_iommu_last_bdf)
131 if (amd_iommu_rlookup_table[devid] == NULL)
137 static int iommu_init_device(struct device *dev)
139 struct iommu_dev_data *dev_data;
140 struct pci_dev *pdev;
143 if (dev->archdata.iommu)
146 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
152 devid = get_device_id(dev);
153 alias = amd_iommu_alias_table[devid];
154 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
156 dev_data->alias = &pdev->dev;
158 atomic_set(&dev_data->bind, 0);
160 dev->archdata.iommu = dev_data;
166 static void iommu_uninit_device(struct device *dev)
168 kfree(dev->archdata.iommu);
171 void __init amd_iommu_uninit_devices(void)
173 struct pci_dev *pdev = NULL;
175 for_each_pci_dev(pdev) {
177 if (!check_device(&pdev->dev))
180 iommu_uninit_device(&pdev->dev);
184 int __init amd_iommu_init_devices(void)
186 struct pci_dev *pdev = NULL;
189 for_each_pci_dev(pdev) {
191 if (!check_device(&pdev->dev))
194 ret = iommu_init_device(&pdev->dev);
203 amd_iommu_uninit_devices();
207 #ifdef CONFIG_AMD_IOMMU_STATS
210 * Initialization code for statistics collection
213 DECLARE_STATS_COUNTER(compl_wait);
214 DECLARE_STATS_COUNTER(cnt_map_single);
215 DECLARE_STATS_COUNTER(cnt_unmap_single);
216 DECLARE_STATS_COUNTER(cnt_map_sg);
217 DECLARE_STATS_COUNTER(cnt_unmap_sg);
218 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
219 DECLARE_STATS_COUNTER(cnt_free_coherent);
220 DECLARE_STATS_COUNTER(cross_page);
221 DECLARE_STATS_COUNTER(domain_flush_single);
222 DECLARE_STATS_COUNTER(domain_flush_all);
223 DECLARE_STATS_COUNTER(alloced_io_mem);
224 DECLARE_STATS_COUNTER(total_map_requests);
226 static struct dentry *stats_dir;
227 static struct dentry *de_fflush;
229 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
231 if (stats_dir == NULL)
234 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
238 static void amd_iommu_stats_init(void)
240 stats_dir = debugfs_create_dir("amd-iommu", NULL);
241 if (stats_dir == NULL)
244 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
245 (u32 *)&amd_iommu_unmap_flush);
247 amd_iommu_stats_add(&compl_wait);
248 amd_iommu_stats_add(&cnt_map_single);
249 amd_iommu_stats_add(&cnt_unmap_single);
250 amd_iommu_stats_add(&cnt_map_sg);
251 amd_iommu_stats_add(&cnt_unmap_sg);
252 amd_iommu_stats_add(&cnt_alloc_coherent);
253 amd_iommu_stats_add(&cnt_free_coherent);
254 amd_iommu_stats_add(&cross_page);
255 amd_iommu_stats_add(&domain_flush_single);
256 amd_iommu_stats_add(&domain_flush_all);
257 amd_iommu_stats_add(&alloced_io_mem);
258 amd_iommu_stats_add(&total_map_requests);
263 /****************************************************************************
265 * Interrupt handling functions
267 ****************************************************************************/
269 static void dump_dte_entry(u16 devid)
273 for (i = 0; i < 8; ++i)
274 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
275 amd_iommu_dev_table[devid].data[i]);
278 static void dump_command(unsigned long phys_addr)
280 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
283 for (i = 0; i < 4; ++i)
284 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
287 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
290 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
291 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
292 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
293 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
294 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
296 printk(KERN_ERR "AMD-Vi: Event logged [");
299 case EVENT_TYPE_ILL_DEV:
300 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
301 "address=0x%016llx flags=0x%04x]\n",
302 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
304 dump_dte_entry(devid);
306 case EVENT_TYPE_IO_FAULT:
307 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
308 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
309 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
310 domid, address, flags);
312 case EVENT_TYPE_DEV_TAB_ERR:
313 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
314 "address=0x%016llx flags=0x%04x]\n",
315 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
318 case EVENT_TYPE_PAGE_TAB_ERR:
319 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
320 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
321 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
322 domid, address, flags);
324 case EVENT_TYPE_ILL_CMD:
325 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
326 dump_command(address);
328 case EVENT_TYPE_CMD_HARD_ERR:
329 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
330 "flags=0x%04x]\n", address, flags);
332 case EVENT_TYPE_IOTLB_INV_TO:
333 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
334 "address=0x%016llx]\n",
335 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
338 case EVENT_TYPE_INV_DEV_REQ:
339 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
340 "address=0x%016llx flags=0x%04x]\n",
341 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
345 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
349 static void iommu_poll_events(struct amd_iommu *iommu)
354 spin_lock_irqsave(&iommu->lock, flags);
356 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
357 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
359 while (head != tail) {
360 iommu_print_event(iommu, iommu->evt_buf + head);
361 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
364 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
366 spin_unlock_irqrestore(&iommu->lock, flags);
369 irqreturn_t amd_iommu_int_thread(int irq, void *data)
371 struct amd_iommu *iommu;
373 for_each_iommu(iommu)
374 iommu_poll_events(iommu);
379 irqreturn_t amd_iommu_int_handler(int irq, void *data)
381 return IRQ_WAKE_THREAD;
384 /****************************************************************************
386 * IOMMU command queuing functions
388 ****************************************************************************/
390 static int wait_on_sem(volatile u64 *sem)
394 while (*sem == 0 && i < LOOP_TIMEOUT) {
399 if (i == LOOP_TIMEOUT) {
400 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
407 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
408 struct iommu_cmd *cmd,
413 target = iommu->cmd_buf + tail;
414 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
416 /* Copy command to buffer */
417 memcpy(target, cmd, sizeof(*cmd));
419 /* Tell the IOMMU about it */
420 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
423 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
425 WARN_ON(address & 0x7ULL);
427 memset(cmd, 0, sizeof(*cmd));
428 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
429 cmd->data[1] = upper_32_bits(__pa(address));
431 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
434 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
436 memset(cmd, 0, sizeof(*cmd));
437 cmd->data[0] = devid;
438 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
441 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
442 size_t size, u16 domid, int pde)
447 pages = iommu_num_pages(address, size, PAGE_SIZE);
452 * If we have to flush more than one page, flush all
453 * TLB entries for this domain
455 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
459 address &= PAGE_MASK;
461 memset(cmd, 0, sizeof(*cmd));
462 cmd->data[1] |= domid;
463 cmd->data[2] = lower_32_bits(address);
464 cmd->data[3] = upper_32_bits(address);
465 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
466 if (s) /* size bit - we flush more than one 4kb page */
467 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
468 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
469 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
472 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
473 u64 address, size_t size)
478 pages = iommu_num_pages(address, size, PAGE_SIZE);
483 * If we have to flush more than one page, flush all
484 * TLB entries for this domain
486 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
490 address &= PAGE_MASK;
492 memset(cmd, 0, sizeof(*cmd));
493 cmd->data[0] = devid;
494 cmd->data[0] |= (qdep & 0xff) << 24;
495 cmd->data[1] = devid;
496 cmd->data[2] = lower_32_bits(address);
497 cmd->data[3] = upper_32_bits(address);
498 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
500 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
503 static void build_inv_all(struct iommu_cmd *cmd)
505 memset(cmd, 0, sizeof(*cmd));
506 CMD_SET_TYPE(cmd, CMD_INV_ALL);
510 * Writes the command to the IOMMUs command buffer and informs the
511 * hardware about the new command.
513 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
515 u32 left, tail, head, next_tail;
518 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
521 spin_lock_irqsave(&iommu->lock, flags);
523 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
524 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
525 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
526 left = (head - next_tail) % iommu->cmd_buf_size;
529 struct iommu_cmd sync_cmd;
530 volatile u64 sem = 0;
533 build_completion_wait(&sync_cmd, (u64)&sem);
534 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
536 spin_unlock_irqrestore(&iommu->lock, flags);
538 if ((ret = wait_on_sem(&sem)) != 0)
544 copy_cmd_to_buffer(iommu, cmd, tail);
546 /* We need to sync now to make sure all commands are processed */
547 iommu->need_sync = true;
549 spin_unlock_irqrestore(&iommu->lock, flags);
555 * This function queues a completion wait command into the command
558 static int iommu_completion_wait(struct amd_iommu *iommu)
560 struct iommu_cmd cmd;
561 volatile u64 sem = 0;
564 if (!iommu->need_sync)
567 build_completion_wait(&cmd, (u64)&sem);
569 ret = iommu_queue_command(iommu, &cmd);
573 return wait_on_sem(&sem);
576 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
578 struct iommu_cmd cmd;
580 build_inv_dte(&cmd, devid);
582 return iommu_queue_command(iommu, &cmd);
585 static void iommu_flush_dte_all(struct amd_iommu *iommu)
589 for (devid = 0; devid <= 0xffff; ++devid)
590 iommu_flush_dte(iommu, devid);
592 iommu_completion_wait(iommu);
596 * This function uses heavy locking and may disable irqs for some time. But
597 * this is no issue because it is only called during resume.
599 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
603 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
604 struct iommu_cmd cmd;
605 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
607 iommu_queue_command(iommu, &cmd);
610 iommu_completion_wait(iommu);
613 static void iommu_flush_all(struct amd_iommu *iommu)
615 struct iommu_cmd cmd;
619 iommu_queue_command(iommu, &cmd);
620 iommu_completion_wait(iommu);
623 void iommu_flush_all_caches(struct amd_iommu *iommu)
625 if (iommu_feature(iommu, FEATURE_IA)) {
626 iommu_flush_all(iommu);
628 iommu_flush_dte_all(iommu);
629 iommu_flush_tlb_all(iommu);
634 * Command send function for flushing on-device TLB
636 static int device_flush_iotlb(struct device *dev, u64 address, size_t size)
638 struct pci_dev *pdev = to_pci_dev(dev);
639 struct amd_iommu *iommu;
640 struct iommu_cmd cmd;
644 qdep = pci_ats_queue_depth(pdev);
645 devid = get_device_id(dev);
646 iommu = amd_iommu_rlookup_table[devid];
648 build_inv_iotlb_pages(&cmd, devid, qdep, address, size);
650 return iommu_queue_command(iommu, &cmd);
654 * Command send function for invalidating a device table entry
656 static int device_flush_dte(struct device *dev)
658 struct amd_iommu *iommu;
659 struct pci_dev *pdev;
663 pdev = to_pci_dev(dev);
664 devid = get_device_id(dev);
665 iommu = amd_iommu_rlookup_table[devid];
667 ret = iommu_flush_dte(iommu, devid);
671 if (pci_ats_enabled(pdev))
672 ret = device_flush_iotlb(dev, 0, ~0UL);
678 * TLB invalidation function which is called from the mapping functions.
679 * It invalidates a single PTE if the range to flush is within a single
680 * page. Otherwise it flushes the whole TLB of the IOMMU.
682 static void __domain_flush_pages(struct protection_domain *domain,
683 u64 address, size_t size, int pde)
685 struct iommu_dev_data *dev_data;
686 struct iommu_cmd cmd;
689 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
691 for (i = 0; i < amd_iommus_present; ++i) {
692 if (!domain->dev_iommu[i])
696 * Devices of this domain are behind this IOMMU
697 * We need a TLB flush
699 ret |= iommu_queue_command(amd_iommus[i], &cmd);
702 list_for_each_entry(dev_data, &domain->dev_list, list) {
703 struct pci_dev *pdev = to_pci_dev(dev_data->dev);
705 if (!pci_ats_enabled(pdev))
708 ret |= device_flush_iotlb(dev_data->dev, address, size);
714 static void domain_flush_pages(struct protection_domain *domain,
715 u64 address, size_t size)
717 __domain_flush_pages(domain, address, size, 0);
720 /* Flush the whole IO/TLB for a given protection domain */
721 static void domain_flush_tlb(struct protection_domain *domain)
723 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
726 /* Flush the whole IO/TLB for a given protection domain - including PDE */
727 static void domain_flush_tlb_pde(struct protection_domain *domain)
729 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
732 static void domain_flush_complete(struct protection_domain *domain)
736 for (i = 0; i < amd_iommus_present; ++i) {
737 if (!domain->dev_iommu[i])
741 * Devices of this domain are behind this IOMMU
742 * We need to wait for completion of all commands.
744 iommu_completion_wait(amd_iommus[i]);
750 * This function flushes the DTEs for all devices in domain
752 static void domain_flush_devices(struct protection_domain *domain)
754 struct iommu_dev_data *dev_data;
757 spin_lock_irqsave(&domain->lock, flags);
759 list_for_each_entry(dev_data, &domain->dev_list, list)
760 device_flush_dte(dev_data->dev);
762 spin_unlock_irqrestore(&domain->lock, flags);
765 /****************************************************************************
767 * The functions below are used the create the page table mappings for
768 * unity mapped regions.
770 ****************************************************************************/
773 * This function is used to add another level to an IO page table. Adding
774 * another level increases the size of the address space by 9 bits to a size up
777 static bool increase_address_space(struct protection_domain *domain,
782 if (domain->mode == PAGE_MODE_6_LEVEL)
783 /* address space already 64 bit large */
786 pte = (void *)get_zeroed_page(gfp);
790 *pte = PM_LEVEL_PDE(domain->mode,
791 virt_to_phys(domain->pt_root));
792 domain->pt_root = pte;
794 domain->updated = true;
799 static u64 *alloc_pte(struct protection_domain *domain,
800 unsigned long address,
801 unsigned long page_size,
808 BUG_ON(!is_power_of_2(page_size));
810 while (address > PM_LEVEL_SIZE(domain->mode))
811 increase_address_space(domain, gfp);
813 level = domain->mode - 1;
814 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
815 address = PAGE_SIZE_ALIGN(address, page_size);
816 end_lvl = PAGE_SIZE_LEVEL(page_size);
818 while (level > end_lvl) {
819 if (!IOMMU_PTE_PRESENT(*pte)) {
820 page = (u64 *)get_zeroed_page(gfp);
823 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
826 /* No level skipping support yet */
827 if (PM_PTE_LEVEL(*pte) != level)
832 pte = IOMMU_PTE_PAGE(*pte);
834 if (pte_page && level == end_lvl)
837 pte = &pte[PM_LEVEL_INDEX(level, address)];
844 * This function checks if there is a PTE for a given dma address. If
845 * there is one, it returns the pointer to it.
847 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
852 if (address > PM_LEVEL_SIZE(domain->mode))
855 level = domain->mode - 1;
856 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
861 if (!IOMMU_PTE_PRESENT(*pte))
865 if (PM_PTE_LEVEL(*pte) == 0x07) {
866 unsigned long pte_mask, __pte;
869 * If we have a series of large PTEs, make
870 * sure to return a pointer to the first one.
872 pte_mask = PTE_PAGE_SIZE(*pte);
873 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
874 __pte = ((unsigned long)pte) & pte_mask;
879 /* No level skipping support yet */
880 if (PM_PTE_LEVEL(*pte) != level)
885 /* Walk to the next level */
886 pte = IOMMU_PTE_PAGE(*pte);
887 pte = &pte[PM_LEVEL_INDEX(level, address)];
894 * Generic mapping functions. It maps a physical address into a DMA
895 * address space. It allocates the page table pages if necessary.
896 * In the future it can be extended to a generic mapping function
897 * supporting all features of AMD IOMMU page tables like level skipping
898 * and full 64 bit address spaces.
900 static int iommu_map_page(struct protection_domain *dom,
901 unsigned long bus_addr,
902 unsigned long phys_addr,
904 unsigned long page_size)
909 if (!(prot & IOMMU_PROT_MASK))
912 bus_addr = PAGE_ALIGN(bus_addr);
913 phys_addr = PAGE_ALIGN(phys_addr);
914 count = PAGE_SIZE_PTE_COUNT(page_size);
915 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
917 for (i = 0; i < count; ++i)
918 if (IOMMU_PTE_PRESENT(pte[i]))
921 if (page_size > PAGE_SIZE) {
922 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
923 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
925 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
927 if (prot & IOMMU_PROT_IR)
928 __pte |= IOMMU_PTE_IR;
929 if (prot & IOMMU_PROT_IW)
930 __pte |= IOMMU_PTE_IW;
932 for (i = 0; i < count; ++i)
940 static unsigned long iommu_unmap_page(struct protection_domain *dom,
941 unsigned long bus_addr,
942 unsigned long page_size)
944 unsigned long long unmap_size, unmapped;
947 BUG_ON(!is_power_of_2(page_size));
951 while (unmapped < page_size) {
953 pte = fetch_pte(dom, bus_addr);
957 * No PTE for this address
958 * move forward in 4kb steps
960 unmap_size = PAGE_SIZE;
961 } else if (PM_PTE_LEVEL(*pte) == 0) {
962 /* 4kb PTE found for this address */
963 unmap_size = PAGE_SIZE;
968 /* Large PTE found which maps this address */
969 unmap_size = PTE_PAGE_SIZE(*pte);
970 count = PAGE_SIZE_PTE_COUNT(unmap_size);
971 for (i = 0; i < count; i++)
975 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
976 unmapped += unmap_size;
979 BUG_ON(!is_power_of_2(unmapped));
985 * This function checks if a specific unity mapping entry is needed for
986 * this specific IOMMU.
988 static int iommu_for_unity_map(struct amd_iommu *iommu,
989 struct unity_map_entry *entry)
993 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
994 bdf = amd_iommu_alias_table[i];
995 if (amd_iommu_rlookup_table[bdf] == iommu)
1003 * This function actually applies the mapping to the page table of the
1006 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1007 struct unity_map_entry *e)
1012 for (addr = e->address_start; addr < e->address_end;
1013 addr += PAGE_SIZE) {
1014 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1019 * if unity mapping is in aperture range mark the page
1020 * as allocated in the aperture
1022 if (addr < dma_dom->aperture_size)
1023 __set_bit(addr >> PAGE_SHIFT,
1024 dma_dom->aperture[0]->bitmap);
1031 * Init the unity mappings for a specific IOMMU in the system
1033 * Basically iterates over all unity mapping entries and applies them to
1034 * the default domain DMA of that IOMMU if necessary.
1036 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1038 struct unity_map_entry *entry;
1041 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1042 if (!iommu_for_unity_map(iommu, entry))
1044 ret = dma_ops_unity_map(iommu->default_dom, entry);
1053 * Inits the unity mappings required for a specific device
1055 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1058 struct unity_map_entry *e;
1061 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1062 if (!(devid >= e->devid_start && devid <= e->devid_end))
1064 ret = dma_ops_unity_map(dma_dom, e);
1072 /****************************************************************************
1074 * The next functions belong to the address allocator for the dma_ops
1075 * interface functions. They work like the allocators in the other IOMMU
1076 * drivers. Its basically a bitmap which marks the allocated pages in
1077 * the aperture. Maybe it could be enhanced in the future to a more
1078 * efficient allocator.
1080 ****************************************************************************/
1083 * The address allocator core functions.
1085 * called with domain->lock held
1089 * Used to reserve address ranges in the aperture (e.g. for exclusion
1092 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1093 unsigned long start_page,
1096 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1098 if (start_page + pages > last_page)
1099 pages = last_page - start_page;
1101 for (i = start_page; i < start_page + pages; ++i) {
1102 int index = i / APERTURE_RANGE_PAGES;
1103 int page = i % APERTURE_RANGE_PAGES;
1104 __set_bit(page, dom->aperture[index]->bitmap);
1109 * This function is used to add a new aperture range to an existing
1110 * aperture in case of dma_ops domain allocation or address allocation
1113 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1114 bool populate, gfp_t gfp)
1116 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1117 struct amd_iommu *iommu;
1120 #ifdef CONFIG_IOMMU_STRESS
1124 if (index >= APERTURE_MAX_RANGES)
1127 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1128 if (!dma_dom->aperture[index])
1131 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1132 if (!dma_dom->aperture[index]->bitmap)
1135 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1138 unsigned long address = dma_dom->aperture_size;
1139 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1140 u64 *pte, *pte_page;
1142 for (i = 0; i < num_ptes; ++i) {
1143 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1148 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1150 address += APERTURE_RANGE_SIZE / 64;
1154 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1156 /* Initialize the exclusion range if necessary */
1157 for_each_iommu(iommu) {
1158 if (iommu->exclusion_start &&
1159 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1160 && iommu->exclusion_start < dma_dom->aperture_size) {
1161 unsigned long startpage;
1162 int pages = iommu_num_pages(iommu->exclusion_start,
1163 iommu->exclusion_length,
1165 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1166 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1171 * Check for areas already mapped as present in the new aperture
1172 * range and mark those pages as reserved in the allocator. Such
1173 * mappings may already exist as a result of requested unity
1174 * mappings for devices.
1176 for (i = dma_dom->aperture[index]->offset;
1177 i < dma_dom->aperture_size;
1179 u64 *pte = fetch_pte(&dma_dom->domain, i);
1180 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1183 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1186 update_domain(&dma_dom->domain);
1191 update_domain(&dma_dom->domain);
1193 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1195 kfree(dma_dom->aperture[index]);
1196 dma_dom->aperture[index] = NULL;
1201 static unsigned long dma_ops_area_alloc(struct device *dev,
1202 struct dma_ops_domain *dom,
1204 unsigned long align_mask,
1206 unsigned long start)
1208 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1209 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1210 int i = start >> APERTURE_RANGE_SHIFT;
1211 unsigned long boundary_size;
1212 unsigned long address = -1;
1213 unsigned long limit;
1215 next_bit >>= PAGE_SHIFT;
1217 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1218 PAGE_SIZE) >> PAGE_SHIFT;
1220 for (;i < max_index; ++i) {
1221 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1223 if (dom->aperture[i]->offset >= dma_mask)
1226 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1227 dma_mask >> PAGE_SHIFT);
1229 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1230 limit, next_bit, pages, 0,
1231 boundary_size, align_mask);
1232 if (address != -1) {
1233 address = dom->aperture[i]->offset +
1234 (address << PAGE_SHIFT);
1235 dom->next_address = address + (pages << PAGE_SHIFT);
1245 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1246 struct dma_ops_domain *dom,
1248 unsigned long align_mask,
1251 unsigned long address;
1253 #ifdef CONFIG_IOMMU_STRESS
1254 dom->next_address = 0;
1255 dom->need_flush = true;
1258 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1259 dma_mask, dom->next_address);
1261 if (address == -1) {
1262 dom->next_address = 0;
1263 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1265 dom->need_flush = true;
1268 if (unlikely(address == -1))
1269 address = DMA_ERROR_CODE;
1271 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1277 * The address free function.
1279 * called with domain->lock held
1281 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1282 unsigned long address,
1285 unsigned i = address >> APERTURE_RANGE_SHIFT;
1286 struct aperture_range *range = dom->aperture[i];
1288 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1290 #ifdef CONFIG_IOMMU_STRESS
1295 if (address >= dom->next_address)
1296 dom->need_flush = true;
1298 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1300 bitmap_clear(range->bitmap, address, pages);
1304 /****************************************************************************
1306 * The next functions belong to the domain allocation. A domain is
1307 * allocated for every IOMMU as the default domain. If device isolation
1308 * is enabled, every device get its own domain. The most important thing
1309 * about domains is the page table mapping the DMA address space they
1312 ****************************************************************************/
1315 * This function adds a protection domain to the global protection domain list
1317 static void add_domain_to_list(struct protection_domain *domain)
1319 unsigned long flags;
1321 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1322 list_add(&domain->list, &amd_iommu_pd_list);
1323 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1327 * This function removes a protection domain to the global
1328 * protection domain list
1330 static void del_domain_from_list(struct protection_domain *domain)
1332 unsigned long flags;
1334 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1335 list_del(&domain->list);
1336 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1339 static u16 domain_id_alloc(void)
1341 unsigned long flags;
1344 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1345 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1347 if (id > 0 && id < MAX_DOMAIN_ID)
1348 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1351 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1356 static void domain_id_free(int id)
1358 unsigned long flags;
1360 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1361 if (id > 0 && id < MAX_DOMAIN_ID)
1362 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1363 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1366 static void free_pagetable(struct protection_domain *domain)
1371 p1 = domain->pt_root;
1376 for (i = 0; i < 512; ++i) {
1377 if (!IOMMU_PTE_PRESENT(p1[i]))
1380 p2 = IOMMU_PTE_PAGE(p1[i]);
1381 for (j = 0; j < 512; ++j) {
1382 if (!IOMMU_PTE_PRESENT(p2[j]))
1384 p3 = IOMMU_PTE_PAGE(p2[j]);
1385 free_page((unsigned long)p3);
1388 free_page((unsigned long)p2);
1391 free_page((unsigned long)p1);
1393 domain->pt_root = NULL;
1397 * Free a domain, only used if something went wrong in the
1398 * allocation path and we need to free an already allocated page table
1400 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1407 del_domain_from_list(&dom->domain);
1409 free_pagetable(&dom->domain);
1411 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1412 if (!dom->aperture[i])
1414 free_page((unsigned long)dom->aperture[i]->bitmap);
1415 kfree(dom->aperture[i]);
1422 * Allocates a new protection domain usable for the dma_ops functions.
1423 * It also initializes the page table and the address allocator data
1424 * structures required for the dma_ops interface
1426 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1428 struct dma_ops_domain *dma_dom;
1430 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1434 spin_lock_init(&dma_dom->domain.lock);
1436 dma_dom->domain.id = domain_id_alloc();
1437 if (dma_dom->domain.id == 0)
1439 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1440 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1441 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1442 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1443 dma_dom->domain.priv = dma_dom;
1444 if (!dma_dom->domain.pt_root)
1447 dma_dom->need_flush = false;
1448 dma_dom->target_dev = 0xffff;
1450 add_domain_to_list(&dma_dom->domain);
1452 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1456 * mark the first page as allocated so we never return 0 as
1457 * a valid dma-address. So we can use 0 as error value
1459 dma_dom->aperture[0]->bitmap[0] = 1;
1460 dma_dom->next_address = 0;
1466 dma_ops_domain_free(dma_dom);
1472 * little helper function to check whether a given protection domain is a
1475 static bool dma_ops_domain(struct protection_domain *domain)
1477 return domain->flags & PD_DMA_OPS_MASK;
1480 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1482 u64 pte_root = virt_to_phys(domain->pt_root);
1485 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1486 << DEV_ENTRY_MODE_SHIFT;
1487 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1490 flags |= DTE_FLAG_IOTLB;
1492 amd_iommu_dev_table[devid].data[3] |= flags;
1493 amd_iommu_dev_table[devid].data[2] = domain->id;
1494 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1495 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1498 static void clear_dte_entry(u16 devid)
1500 /* remove entry from the device table seen by the hardware */
1501 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1502 amd_iommu_dev_table[devid].data[1] = 0;
1503 amd_iommu_dev_table[devid].data[2] = 0;
1505 amd_iommu_apply_erratum_63(devid);
1508 static void do_attach(struct device *dev, struct protection_domain *domain)
1510 struct iommu_dev_data *dev_data;
1511 struct amd_iommu *iommu;
1512 struct pci_dev *pdev;
1516 devid = get_device_id(dev);
1517 iommu = amd_iommu_rlookup_table[devid];
1518 dev_data = get_dev_data(dev);
1519 pdev = to_pci_dev(dev);
1521 if (amd_iommu_iotlb_sup)
1522 ats = pci_ats_enabled(pdev);
1524 /* Update data structures */
1525 dev_data->domain = domain;
1526 list_add(&dev_data->list, &domain->dev_list);
1527 set_dte_entry(devid, domain, ats);
1529 /* Do reference counting */
1530 domain->dev_iommu[iommu->index] += 1;
1531 domain->dev_cnt += 1;
1533 /* Flush the DTE entry */
1534 device_flush_dte(dev);
1537 static void do_detach(struct device *dev)
1539 struct iommu_dev_data *dev_data;
1540 struct amd_iommu *iommu;
1543 devid = get_device_id(dev);
1544 iommu = amd_iommu_rlookup_table[devid];
1545 dev_data = get_dev_data(dev);
1547 /* decrease reference counters */
1548 dev_data->domain->dev_iommu[iommu->index] -= 1;
1549 dev_data->domain->dev_cnt -= 1;
1551 /* Update data structures */
1552 dev_data->domain = NULL;
1553 list_del(&dev_data->list);
1554 clear_dte_entry(devid);
1556 /* Flush the DTE entry */
1557 device_flush_dte(dev);
1561 * If a device is not yet associated with a domain, this function does
1562 * assigns it visible for the hardware
1564 static int __attach_device(struct device *dev,
1565 struct protection_domain *domain)
1567 struct iommu_dev_data *dev_data, *alias_data;
1570 dev_data = get_dev_data(dev);
1571 alias_data = get_dev_data(dev_data->alias);
1577 spin_lock(&domain->lock);
1579 /* Some sanity checks */
1581 if (alias_data->domain != NULL &&
1582 alias_data->domain != domain)
1585 if (dev_data->domain != NULL &&
1586 dev_data->domain != domain)
1589 /* Do real assignment */
1590 if (dev_data->alias != dev) {
1591 alias_data = get_dev_data(dev_data->alias);
1592 if (alias_data->domain == NULL)
1593 do_attach(dev_data->alias, domain);
1595 atomic_inc(&alias_data->bind);
1598 if (dev_data->domain == NULL)
1599 do_attach(dev, domain);
1601 atomic_inc(&dev_data->bind);
1608 spin_unlock(&domain->lock);
1614 * If a device is not yet associated with a domain, this function does
1615 * assigns it visible for the hardware
1617 static int attach_device(struct device *dev,
1618 struct protection_domain *domain)
1620 struct pci_dev *pdev = to_pci_dev(dev);
1621 unsigned long flags;
1624 if (amd_iommu_iotlb_sup)
1625 pci_enable_ats(pdev, PAGE_SHIFT);
1627 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1628 ret = __attach_device(dev, domain);
1629 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1632 * We might boot into a crash-kernel here. The crashed kernel
1633 * left the caches in the IOMMU dirty. So we have to flush
1634 * here to evict all dirty stuff.
1636 domain_flush_tlb_pde(domain);
1642 * Removes a device from a protection domain (unlocked)
1644 static void __detach_device(struct device *dev)
1646 struct iommu_dev_data *dev_data = get_dev_data(dev);
1647 struct iommu_dev_data *alias_data;
1648 struct protection_domain *domain;
1649 unsigned long flags;
1651 BUG_ON(!dev_data->domain);
1653 domain = dev_data->domain;
1655 spin_lock_irqsave(&domain->lock, flags);
1657 if (dev_data->alias != dev) {
1658 alias_data = get_dev_data(dev_data->alias);
1659 if (atomic_dec_and_test(&alias_data->bind))
1660 do_detach(dev_data->alias);
1663 if (atomic_dec_and_test(&dev_data->bind))
1666 spin_unlock_irqrestore(&domain->lock, flags);
1669 * If we run in passthrough mode the device must be assigned to the
1670 * passthrough domain if it is detached from any other domain.
1671 * Make sure we can deassign from the pt_domain itself.
1673 if (iommu_pass_through &&
1674 (dev_data->domain == NULL && domain != pt_domain))
1675 __attach_device(dev, pt_domain);
1679 * Removes a device from a protection domain (with devtable_lock held)
1681 static void detach_device(struct device *dev)
1683 struct pci_dev *pdev = to_pci_dev(dev);
1684 unsigned long flags;
1686 /* lock device table */
1687 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1688 __detach_device(dev);
1689 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1691 if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev))
1692 pci_disable_ats(pdev);
1696 * Find out the protection domain structure for a given PCI device. This
1697 * will give us the pointer to the page table root for example.
1699 static struct protection_domain *domain_for_device(struct device *dev)
1701 struct protection_domain *dom;
1702 struct iommu_dev_data *dev_data, *alias_data;
1703 unsigned long flags;
1706 devid = get_device_id(dev);
1707 dev_data = get_dev_data(dev);
1708 alias_data = get_dev_data(dev_data->alias);
1712 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1713 dom = dev_data->domain;
1715 alias_data->domain != NULL) {
1716 __attach_device(dev, alias_data->domain);
1717 dom = alias_data->domain;
1720 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1725 static int device_change_notifier(struct notifier_block *nb,
1726 unsigned long action, void *data)
1728 struct device *dev = data;
1730 struct protection_domain *domain;
1731 struct dma_ops_domain *dma_domain;
1732 struct amd_iommu *iommu;
1733 unsigned long flags;
1735 if (!check_device(dev))
1738 devid = get_device_id(dev);
1739 iommu = amd_iommu_rlookup_table[devid];
1742 case BUS_NOTIFY_UNBOUND_DRIVER:
1744 domain = domain_for_device(dev);
1748 if (iommu_pass_through)
1752 case BUS_NOTIFY_ADD_DEVICE:
1754 iommu_init_device(dev);
1756 domain = domain_for_device(dev);
1758 /* allocate a protection domain if a device is added */
1759 dma_domain = find_protection_domain(devid);
1762 dma_domain = dma_ops_domain_alloc();
1765 dma_domain->target_dev = devid;
1767 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1768 list_add_tail(&dma_domain->list, &iommu_pd_list);
1769 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1772 case BUS_NOTIFY_DEL_DEVICE:
1774 iommu_uninit_device(dev);
1780 device_flush_dte(dev);
1781 iommu_completion_wait(iommu);
1787 static struct notifier_block device_nb = {
1788 .notifier_call = device_change_notifier,
1791 void amd_iommu_init_notifier(void)
1793 bus_register_notifier(&pci_bus_type, &device_nb);
1796 /*****************************************************************************
1798 * The next functions belong to the dma_ops mapping/unmapping code.
1800 *****************************************************************************/
1803 * In the dma_ops path we only have the struct device. This function
1804 * finds the corresponding IOMMU, the protection domain and the
1805 * requestor id for a given device.
1806 * If the device is not yet associated with a domain this is also done
1809 static struct protection_domain *get_domain(struct device *dev)
1811 struct protection_domain *domain;
1812 struct dma_ops_domain *dma_dom;
1813 u16 devid = get_device_id(dev);
1815 if (!check_device(dev))
1816 return ERR_PTR(-EINVAL);
1818 domain = domain_for_device(dev);
1819 if (domain != NULL && !dma_ops_domain(domain))
1820 return ERR_PTR(-EBUSY);
1825 /* Device not bount yet - bind it */
1826 dma_dom = find_protection_domain(devid);
1828 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1829 attach_device(dev, &dma_dom->domain);
1830 DUMP_printk("Using protection domain %d for device %s\n",
1831 dma_dom->domain.id, dev_name(dev));
1833 return &dma_dom->domain;
1836 static void update_device_table(struct protection_domain *domain)
1838 struct iommu_dev_data *dev_data;
1840 list_for_each_entry(dev_data, &domain->dev_list, list) {
1841 struct pci_dev *pdev = to_pci_dev(dev_data->dev);
1842 u16 devid = get_device_id(dev_data->dev);
1843 set_dte_entry(devid, domain, pci_ats_enabled(pdev));
1847 static void update_domain(struct protection_domain *domain)
1849 if (!domain->updated)
1852 update_device_table(domain);
1854 domain_flush_devices(domain);
1855 domain_flush_tlb_pde(domain);
1857 domain->updated = false;
1861 * This function fetches the PTE for a given address in the aperture
1863 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1864 unsigned long address)
1866 struct aperture_range *aperture;
1867 u64 *pte, *pte_page;
1869 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1873 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1875 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1877 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1879 pte += PM_LEVEL_INDEX(0, address);
1881 update_domain(&dom->domain);
1887 * This is the generic map function. It maps one 4kb page at paddr to
1888 * the given address in the DMA address space for the domain.
1890 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1891 unsigned long address,
1897 WARN_ON(address > dom->aperture_size);
1901 pte = dma_ops_get_pte(dom, address);
1903 return DMA_ERROR_CODE;
1905 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1907 if (direction == DMA_TO_DEVICE)
1908 __pte |= IOMMU_PTE_IR;
1909 else if (direction == DMA_FROM_DEVICE)
1910 __pte |= IOMMU_PTE_IW;
1911 else if (direction == DMA_BIDIRECTIONAL)
1912 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1918 return (dma_addr_t)address;
1922 * The generic unmapping function for on page in the DMA address space.
1924 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1925 unsigned long address)
1927 struct aperture_range *aperture;
1930 if (address >= dom->aperture_size)
1933 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1937 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1941 pte += PM_LEVEL_INDEX(0, address);
1949 * This function contains common code for mapping of a physically
1950 * contiguous memory region into DMA address space. It is used by all
1951 * mapping functions provided with this IOMMU driver.
1952 * Must be called with the domain lock held.
1954 static dma_addr_t __map_single(struct device *dev,
1955 struct dma_ops_domain *dma_dom,
1962 dma_addr_t offset = paddr & ~PAGE_MASK;
1963 dma_addr_t address, start, ret;
1965 unsigned long align_mask = 0;
1968 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1971 INC_STATS_COUNTER(total_map_requests);
1974 INC_STATS_COUNTER(cross_page);
1977 align_mask = (1UL << get_order(size)) - 1;
1980 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1982 if (unlikely(address == DMA_ERROR_CODE)) {
1984 * setting next_address here will let the address
1985 * allocator only scan the new allocated range in the
1986 * first run. This is a small optimization.
1988 dma_dom->next_address = dma_dom->aperture_size;
1990 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1994 * aperture was successfully enlarged by 128 MB, try
2001 for (i = 0; i < pages; ++i) {
2002 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2003 if (ret == DMA_ERROR_CODE)
2011 ADD_STATS_COUNTER(alloced_io_mem, size);
2013 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2014 domain_flush_tlb(&dma_dom->domain);
2015 dma_dom->need_flush = false;
2016 } else if (unlikely(amd_iommu_np_cache))
2017 domain_flush_pages(&dma_dom->domain, address, size);
2024 for (--i; i >= 0; --i) {
2026 dma_ops_domain_unmap(dma_dom, start);
2029 dma_ops_free_addresses(dma_dom, address, pages);
2031 return DMA_ERROR_CODE;
2035 * Does the reverse of the __map_single function. Must be called with
2036 * the domain lock held too
2038 static void __unmap_single(struct dma_ops_domain *dma_dom,
2039 dma_addr_t dma_addr,
2043 dma_addr_t flush_addr;
2044 dma_addr_t i, start;
2047 if ((dma_addr == DMA_ERROR_CODE) ||
2048 (dma_addr + size > dma_dom->aperture_size))
2051 flush_addr = dma_addr;
2052 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2053 dma_addr &= PAGE_MASK;
2056 for (i = 0; i < pages; ++i) {
2057 dma_ops_domain_unmap(dma_dom, start);
2061 SUB_STATS_COUNTER(alloced_io_mem, size);
2063 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2065 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2066 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2067 dma_dom->need_flush = false;
2072 * The exported map_single function for dma_ops.
2074 static dma_addr_t map_page(struct device *dev, struct page *page,
2075 unsigned long offset, size_t size,
2076 enum dma_data_direction dir,
2077 struct dma_attrs *attrs)
2079 unsigned long flags;
2080 struct protection_domain *domain;
2083 phys_addr_t paddr = page_to_phys(page) + offset;
2085 INC_STATS_COUNTER(cnt_map_single);
2087 domain = get_domain(dev);
2088 if (PTR_ERR(domain) == -EINVAL)
2089 return (dma_addr_t)paddr;
2090 else if (IS_ERR(domain))
2091 return DMA_ERROR_CODE;
2093 dma_mask = *dev->dma_mask;
2095 spin_lock_irqsave(&domain->lock, flags);
2097 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2099 if (addr == DMA_ERROR_CODE)
2102 domain_flush_complete(domain);
2105 spin_unlock_irqrestore(&domain->lock, flags);
2111 * The exported unmap_single function for dma_ops.
2113 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2114 enum dma_data_direction dir, struct dma_attrs *attrs)
2116 unsigned long flags;
2117 struct protection_domain *domain;
2119 INC_STATS_COUNTER(cnt_unmap_single);
2121 domain = get_domain(dev);
2125 spin_lock_irqsave(&domain->lock, flags);
2127 __unmap_single(domain->priv, dma_addr, size, dir);
2129 domain_flush_complete(domain);
2131 spin_unlock_irqrestore(&domain->lock, flags);
2135 * This is a special map_sg function which is used if we should map a
2136 * device which is not handled by an AMD IOMMU in the system.
2138 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2139 int nelems, int dir)
2141 struct scatterlist *s;
2144 for_each_sg(sglist, s, nelems, i) {
2145 s->dma_address = (dma_addr_t)sg_phys(s);
2146 s->dma_length = s->length;
2153 * The exported map_sg function for dma_ops (handles scatter-gather
2156 static int map_sg(struct device *dev, struct scatterlist *sglist,
2157 int nelems, enum dma_data_direction dir,
2158 struct dma_attrs *attrs)
2160 unsigned long flags;
2161 struct protection_domain *domain;
2163 struct scatterlist *s;
2165 int mapped_elems = 0;
2168 INC_STATS_COUNTER(cnt_map_sg);
2170 domain = get_domain(dev);
2171 if (PTR_ERR(domain) == -EINVAL)
2172 return map_sg_no_iommu(dev, sglist, nelems, dir);
2173 else if (IS_ERR(domain))
2176 dma_mask = *dev->dma_mask;
2178 spin_lock_irqsave(&domain->lock, flags);
2180 for_each_sg(sglist, s, nelems, i) {
2183 s->dma_address = __map_single(dev, domain->priv,
2184 paddr, s->length, dir, false,
2187 if (s->dma_address) {
2188 s->dma_length = s->length;
2194 domain_flush_complete(domain);
2197 spin_unlock_irqrestore(&domain->lock, flags);
2199 return mapped_elems;
2201 for_each_sg(sglist, s, mapped_elems, i) {
2203 __unmap_single(domain->priv, s->dma_address,
2204 s->dma_length, dir);
2205 s->dma_address = s->dma_length = 0;
2214 * The exported map_sg function for dma_ops (handles scatter-gather
2217 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2218 int nelems, enum dma_data_direction dir,
2219 struct dma_attrs *attrs)
2221 unsigned long flags;
2222 struct protection_domain *domain;
2223 struct scatterlist *s;
2226 INC_STATS_COUNTER(cnt_unmap_sg);
2228 domain = get_domain(dev);
2232 spin_lock_irqsave(&domain->lock, flags);
2234 for_each_sg(sglist, s, nelems, i) {
2235 __unmap_single(domain->priv, s->dma_address,
2236 s->dma_length, dir);
2237 s->dma_address = s->dma_length = 0;
2240 domain_flush_complete(domain);
2242 spin_unlock_irqrestore(&domain->lock, flags);
2246 * The exported alloc_coherent function for dma_ops.
2248 static void *alloc_coherent(struct device *dev, size_t size,
2249 dma_addr_t *dma_addr, gfp_t flag)
2251 unsigned long flags;
2253 struct protection_domain *domain;
2255 u64 dma_mask = dev->coherent_dma_mask;
2257 INC_STATS_COUNTER(cnt_alloc_coherent);
2259 domain = get_domain(dev);
2260 if (PTR_ERR(domain) == -EINVAL) {
2261 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2262 *dma_addr = __pa(virt_addr);
2264 } else if (IS_ERR(domain))
2267 dma_mask = dev->coherent_dma_mask;
2268 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2271 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2275 paddr = virt_to_phys(virt_addr);
2278 dma_mask = *dev->dma_mask;
2280 spin_lock_irqsave(&domain->lock, flags);
2282 *dma_addr = __map_single(dev, domain->priv, paddr,
2283 size, DMA_BIDIRECTIONAL, true, dma_mask);
2285 if (*dma_addr == DMA_ERROR_CODE) {
2286 spin_unlock_irqrestore(&domain->lock, flags);
2290 domain_flush_complete(domain);
2292 spin_unlock_irqrestore(&domain->lock, flags);
2298 free_pages((unsigned long)virt_addr, get_order(size));
2304 * The exported free_coherent function for dma_ops.
2306 static void free_coherent(struct device *dev, size_t size,
2307 void *virt_addr, dma_addr_t dma_addr)
2309 unsigned long flags;
2310 struct protection_domain *domain;
2312 INC_STATS_COUNTER(cnt_free_coherent);
2314 domain = get_domain(dev);
2318 spin_lock_irqsave(&domain->lock, flags);
2320 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2322 domain_flush_complete(domain);
2324 spin_unlock_irqrestore(&domain->lock, flags);
2327 free_pages((unsigned long)virt_addr, get_order(size));
2331 * This function is called by the DMA layer to find out if we can handle a
2332 * particular device. It is part of the dma_ops.
2334 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2336 return check_device(dev);
2340 * The function for pre-allocating protection domains.
2342 * If the driver core informs the DMA layer if a driver grabs a device
2343 * we don't need to preallocate the protection domains anymore.
2344 * For now we have to.
2346 static void prealloc_protection_domains(void)
2348 struct pci_dev *dev = NULL;
2349 struct dma_ops_domain *dma_dom;
2352 for_each_pci_dev(dev) {
2354 /* Do we handle this device? */
2355 if (!check_device(&dev->dev))
2358 /* Is there already any domain for it? */
2359 if (domain_for_device(&dev->dev))
2362 devid = get_device_id(&dev->dev);
2364 dma_dom = dma_ops_domain_alloc();
2367 init_unity_mappings_for_device(dma_dom, devid);
2368 dma_dom->target_dev = devid;
2370 attach_device(&dev->dev, &dma_dom->domain);
2372 list_add_tail(&dma_dom->list, &iommu_pd_list);
2376 static struct dma_map_ops amd_iommu_dma_ops = {
2377 .alloc_coherent = alloc_coherent,
2378 .free_coherent = free_coherent,
2379 .map_page = map_page,
2380 .unmap_page = unmap_page,
2382 .unmap_sg = unmap_sg,
2383 .dma_supported = amd_iommu_dma_supported,
2387 * The function which clues the AMD IOMMU driver into dma_ops.
2390 void __init amd_iommu_init_api(void)
2392 register_iommu(&amd_iommu_ops);
2395 int __init amd_iommu_init_dma_ops(void)
2397 struct amd_iommu *iommu;
2401 * first allocate a default protection domain for every IOMMU we
2402 * found in the system. Devices not assigned to any other
2403 * protection domain will be assigned to the default one.
2405 for_each_iommu(iommu) {
2406 iommu->default_dom = dma_ops_domain_alloc();
2407 if (iommu->default_dom == NULL)
2409 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2410 ret = iommu_init_unity_mappings(iommu);
2416 * Pre-allocate the protection domains for each device.
2418 prealloc_protection_domains();
2423 /* Make the driver finally visible to the drivers */
2424 dma_ops = &amd_iommu_dma_ops;
2426 amd_iommu_stats_init();
2432 for_each_iommu(iommu) {
2433 if (iommu->default_dom)
2434 dma_ops_domain_free(iommu->default_dom);
2440 /*****************************************************************************
2442 * The following functions belong to the exported interface of AMD IOMMU
2444 * This interface allows access to lower level functions of the IOMMU
2445 * like protection domain handling and assignement of devices to domains
2446 * which is not possible with the dma_ops interface.
2448 *****************************************************************************/
2450 static void cleanup_domain(struct protection_domain *domain)
2452 struct iommu_dev_data *dev_data, *next;
2453 unsigned long flags;
2455 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2457 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2458 struct device *dev = dev_data->dev;
2460 __detach_device(dev);
2461 atomic_set(&dev_data->bind, 0);
2464 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2467 static void protection_domain_free(struct protection_domain *domain)
2472 del_domain_from_list(domain);
2475 domain_id_free(domain->id);
2480 static struct protection_domain *protection_domain_alloc(void)
2482 struct protection_domain *domain;
2484 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2488 spin_lock_init(&domain->lock);
2489 mutex_init(&domain->api_lock);
2490 domain->id = domain_id_alloc();
2493 INIT_LIST_HEAD(&domain->dev_list);
2495 add_domain_to_list(domain);
2505 static int amd_iommu_domain_init(struct iommu_domain *dom)
2507 struct protection_domain *domain;
2509 domain = protection_domain_alloc();
2513 domain->mode = PAGE_MODE_3_LEVEL;
2514 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2515 if (!domain->pt_root)
2523 protection_domain_free(domain);
2528 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2530 struct protection_domain *domain = dom->priv;
2535 if (domain->dev_cnt > 0)
2536 cleanup_domain(domain);
2538 BUG_ON(domain->dev_cnt != 0);
2540 free_pagetable(domain);
2542 protection_domain_free(domain);
2547 static void amd_iommu_detach_device(struct iommu_domain *dom,
2550 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2551 struct amd_iommu *iommu;
2554 if (!check_device(dev))
2557 devid = get_device_id(dev);
2559 if (dev_data->domain != NULL)
2562 iommu = amd_iommu_rlookup_table[devid];
2566 device_flush_dte(dev);
2567 iommu_completion_wait(iommu);
2570 static int amd_iommu_attach_device(struct iommu_domain *dom,
2573 struct protection_domain *domain = dom->priv;
2574 struct iommu_dev_data *dev_data;
2575 struct amd_iommu *iommu;
2579 if (!check_device(dev))
2582 dev_data = dev->archdata.iommu;
2584 devid = get_device_id(dev);
2586 iommu = amd_iommu_rlookup_table[devid];
2590 if (dev_data->domain)
2593 ret = attach_device(dev, domain);
2595 iommu_completion_wait(iommu);
2600 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2601 phys_addr_t paddr, int gfp_order, int iommu_prot)
2603 unsigned long page_size = 0x1000UL << gfp_order;
2604 struct protection_domain *domain = dom->priv;
2608 if (iommu_prot & IOMMU_READ)
2609 prot |= IOMMU_PROT_IR;
2610 if (iommu_prot & IOMMU_WRITE)
2611 prot |= IOMMU_PROT_IW;
2613 mutex_lock(&domain->api_lock);
2614 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2615 mutex_unlock(&domain->api_lock);
2620 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2623 struct protection_domain *domain = dom->priv;
2624 unsigned long page_size, unmap_size;
2626 page_size = 0x1000UL << gfp_order;
2628 mutex_lock(&domain->api_lock);
2629 unmap_size = iommu_unmap_page(domain, iova, page_size);
2630 mutex_unlock(&domain->api_lock);
2632 domain_flush_tlb_pde(domain);
2634 return get_order(unmap_size);
2637 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2640 struct protection_domain *domain = dom->priv;
2641 unsigned long offset_mask;
2645 pte = fetch_pte(domain, iova);
2647 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2650 if (PM_PTE_LEVEL(*pte) == 0)
2651 offset_mask = PAGE_SIZE - 1;
2653 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2655 __pte = *pte & PM_ADDR_MASK;
2656 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2661 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2665 case IOMMU_CAP_CACHE_COHERENCY:
2672 static struct iommu_ops amd_iommu_ops = {
2673 .domain_init = amd_iommu_domain_init,
2674 .domain_destroy = amd_iommu_domain_destroy,
2675 .attach_dev = amd_iommu_attach_device,
2676 .detach_dev = amd_iommu_detach_device,
2677 .map = amd_iommu_map,
2678 .unmap = amd_iommu_unmap,
2679 .iova_to_phys = amd_iommu_iova_to_phys,
2680 .domain_has_cap = amd_iommu_domain_has_cap,
2683 /*****************************************************************************
2685 * The next functions do a basic initialization of IOMMU for pass through
2688 * In passthrough mode the IOMMU is initialized and enabled but not used for
2689 * DMA-API translation.
2691 *****************************************************************************/
2693 int __init amd_iommu_init_passthrough(void)
2695 struct amd_iommu *iommu;
2696 struct pci_dev *dev = NULL;
2699 /* allocate passthrough domain */
2700 pt_domain = protection_domain_alloc();
2704 pt_domain->mode |= PAGE_MODE_NONE;
2706 for_each_pci_dev(dev) {
2707 if (!check_device(&dev->dev))
2710 devid = get_device_id(&dev->dev);
2712 iommu = amd_iommu_rlookup_table[devid];
2716 attach_device(&dev->dev, pt_domain);
2719 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");