Merge tag 'kvm-3.9-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[firefly-linux-kernel-4.4.55.git] / arch / x86 / include / asm / vmx.h
1 /*
2  * vmx.h: VMX Architecture related definitions
3  * Copyright (c) 2004, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16  * Place - Suite 330, Boston, MA 02111-1307 USA.
17  *
18  * A few random additions are:
19  * Copyright (C) 2006 Qumranet
20  *    Avi Kivity <avi@qumranet.com>
21  *    Yaniv Kamay <yaniv@qumranet.com>
22  *
23  */
24 #ifndef VMX_H
25 #define VMX_H
26
27
28 #include <linux/types.h>
29 #include <uapi/asm/vmx.h>
30
31 /*
32  * Definitions of Primary Processor-Based VM-Execution Controls.
33  */
34 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
35 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
36 #define CPU_BASED_HLT_EXITING                   0x00000080
37 #define CPU_BASED_INVLPG_EXITING                0x00000200
38 #define CPU_BASED_MWAIT_EXITING                 0x00000400
39 #define CPU_BASED_RDPMC_EXITING                 0x00000800
40 #define CPU_BASED_RDTSC_EXITING                 0x00001000
41 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
42 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
43 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
44 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
45 #define CPU_BASED_TPR_SHADOW                    0x00200000
46 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
47 #define CPU_BASED_MOV_DR_EXITING                0x00800000
48 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
49 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
50 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
51 #define CPU_BASED_MONITOR_EXITING               0x20000000
52 #define CPU_BASED_PAUSE_EXITING                 0x40000000
53 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
54 /*
55  * Definitions of Secondary Processor-Based VM-Execution Controls.
56  */
57 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
58 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
59 #define SECONDARY_EXEC_RDTSCP                   0x00000008
60 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
61 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
62 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
63 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
64 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
65 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
66 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
67 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
68
69
70 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
71 #define PIN_BASED_NMI_EXITING                   0x00000008
72 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
73
74 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000002
75 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
76 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
77 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
78 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
79 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
80 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
81 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
82 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
83
84 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000002
85 #define VM_ENTRY_IA32E_MODE                     0x00000200
86 #define VM_ENTRY_SMM                            0x00000400
87 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
88 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
89 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
90 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
91
92 /* VMCS Encodings */
93 enum vmcs_field {
94         VIRTUAL_PROCESSOR_ID            = 0x00000000,
95         GUEST_ES_SELECTOR               = 0x00000800,
96         GUEST_CS_SELECTOR               = 0x00000802,
97         GUEST_SS_SELECTOR               = 0x00000804,
98         GUEST_DS_SELECTOR               = 0x00000806,
99         GUEST_FS_SELECTOR               = 0x00000808,
100         GUEST_GS_SELECTOR               = 0x0000080a,
101         GUEST_LDTR_SELECTOR             = 0x0000080c,
102         GUEST_TR_SELECTOR               = 0x0000080e,
103         GUEST_INTR_STATUS               = 0x00000810,
104         HOST_ES_SELECTOR                = 0x00000c00,
105         HOST_CS_SELECTOR                = 0x00000c02,
106         HOST_SS_SELECTOR                = 0x00000c04,
107         HOST_DS_SELECTOR                = 0x00000c06,
108         HOST_FS_SELECTOR                = 0x00000c08,
109         HOST_GS_SELECTOR                = 0x00000c0a,
110         HOST_TR_SELECTOR                = 0x00000c0c,
111         IO_BITMAP_A                     = 0x00002000,
112         IO_BITMAP_A_HIGH                = 0x00002001,
113         IO_BITMAP_B                     = 0x00002002,
114         IO_BITMAP_B_HIGH                = 0x00002003,
115         MSR_BITMAP                      = 0x00002004,
116         MSR_BITMAP_HIGH                 = 0x00002005,
117         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
118         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
119         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
120         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
121         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
122         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
123         TSC_OFFSET                      = 0x00002010,
124         TSC_OFFSET_HIGH                 = 0x00002011,
125         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
126         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
127         APIC_ACCESS_ADDR                = 0x00002014,
128         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
129         EPT_POINTER                     = 0x0000201a,
130         EPT_POINTER_HIGH                = 0x0000201b,
131         EOI_EXIT_BITMAP0                = 0x0000201c,
132         EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
133         EOI_EXIT_BITMAP1                = 0x0000201e,
134         EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
135         EOI_EXIT_BITMAP2                = 0x00002020,
136         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
137         EOI_EXIT_BITMAP3                = 0x00002022,
138         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
139         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
140         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
141         VMCS_LINK_POINTER               = 0x00002800,
142         VMCS_LINK_POINTER_HIGH          = 0x00002801,
143         GUEST_IA32_DEBUGCTL             = 0x00002802,
144         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
145         GUEST_IA32_PAT                  = 0x00002804,
146         GUEST_IA32_PAT_HIGH             = 0x00002805,
147         GUEST_IA32_EFER                 = 0x00002806,
148         GUEST_IA32_EFER_HIGH            = 0x00002807,
149         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
150         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
151         GUEST_PDPTR0                    = 0x0000280a,
152         GUEST_PDPTR0_HIGH               = 0x0000280b,
153         GUEST_PDPTR1                    = 0x0000280c,
154         GUEST_PDPTR1_HIGH               = 0x0000280d,
155         GUEST_PDPTR2                    = 0x0000280e,
156         GUEST_PDPTR2_HIGH               = 0x0000280f,
157         GUEST_PDPTR3                    = 0x00002810,
158         GUEST_PDPTR3_HIGH               = 0x00002811,
159         HOST_IA32_PAT                   = 0x00002c00,
160         HOST_IA32_PAT_HIGH              = 0x00002c01,
161         HOST_IA32_EFER                  = 0x00002c02,
162         HOST_IA32_EFER_HIGH             = 0x00002c03,
163         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
164         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
165         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
166         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
167         EXCEPTION_BITMAP                = 0x00004004,
168         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
169         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
170         CR3_TARGET_COUNT                = 0x0000400a,
171         VM_EXIT_CONTROLS                = 0x0000400c,
172         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
173         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
174         VM_ENTRY_CONTROLS               = 0x00004012,
175         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
176         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
177         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
178         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
179         TPR_THRESHOLD                   = 0x0000401c,
180         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
181         PLE_GAP                         = 0x00004020,
182         PLE_WINDOW                      = 0x00004022,
183         VM_INSTRUCTION_ERROR            = 0x00004400,
184         VM_EXIT_REASON                  = 0x00004402,
185         VM_EXIT_INTR_INFO               = 0x00004404,
186         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
187         IDT_VECTORING_INFO_FIELD        = 0x00004408,
188         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
189         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
190         VMX_INSTRUCTION_INFO            = 0x0000440e,
191         GUEST_ES_LIMIT                  = 0x00004800,
192         GUEST_CS_LIMIT                  = 0x00004802,
193         GUEST_SS_LIMIT                  = 0x00004804,
194         GUEST_DS_LIMIT                  = 0x00004806,
195         GUEST_FS_LIMIT                  = 0x00004808,
196         GUEST_GS_LIMIT                  = 0x0000480a,
197         GUEST_LDTR_LIMIT                = 0x0000480c,
198         GUEST_TR_LIMIT                  = 0x0000480e,
199         GUEST_GDTR_LIMIT                = 0x00004810,
200         GUEST_IDTR_LIMIT                = 0x00004812,
201         GUEST_ES_AR_BYTES               = 0x00004814,
202         GUEST_CS_AR_BYTES               = 0x00004816,
203         GUEST_SS_AR_BYTES               = 0x00004818,
204         GUEST_DS_AR_BYTES               = 0x0000481a,
205         GUEST_FS_AR_BYTES               = 0x0000481c,
206         GUEST_GS_AR_BYTES               = 0x0000481e,
207         GUEST_LDTR_AR_BYTES             = 0x00004820,
208         GUEST_TR_AR_BYTES               = 0x00004822,
209         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
210         GUEST_ACTIVITY_STATE            = 0X00004826,
211         GUEST_SYSENTER_CS               = 0x0000482A,
212         HOST_IA32_SYSENTER_CS           = 0x00004c00,
213         CR0_GUEST_HOST_MASK             = 0x00006000,
214         CR4_GUEST_HOST_MASK             = 0x00006002,
215         CR0_READ_SHADOW                 = 0x00006004,
216         CR4_READ_SHADOW                 = 0x00006006,
217         CR3_TARGET_VALUE0               = 0x00006008,
218         CR3_TARGET_VALUE1               = 0x0000600a,
219         CR3_TARGET_VALUE2               = 0x0000600c,
220         CR3_TARGET_VALUE3               = 0x0000600e,
221         EXIT_QUALIFICATION              = 0x00006400,
222         GUEST_LINEAR_ADDRESS            = 0x0000640a,
223         GUEST_CR0                       = 0x00006800,
224         GUEST_CR3                       = 0x00006802,
225         GUEST_CR4                       = 0x00006804,
226         GUEST_ES_BASE                   = 0x00006806,
227         GUEST_CS_BASE                   = 0x00006808,
228         GUEST_SS_BASE                   = 0x0000680a,
229         GUEST_DS_BASE                   = 0x0000680c,
230         GUEST_FS_BASE                   = 0x0000680e,
231         GUEST_GS_BASE                   = 0x00006810,
232         GUEST_LDTR_BASE                 = 0x00006812,
233         GUEST_TR_BASE                   = 0x00006814,
234         GUEST_GDTR_BASE                 = 0x00006816,
235         GUEST_IDTR_BASE                 = 0x00006818,
236         GUEST_DR7                       = 0x0000681a,
237         GUEST_RSP                       = 0x0000681c,
238         GUEST_RIP                       = 0x0000681e,
239         GUEST_RFLAGS                    = 0x00006820,
240         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
241         GUEST_SYSENTER_ESP              = 0x00006824,
242         GUEST_SYSENTER_EIP              = 0x00006826,
243         HOST_CR0                        = 0x00006c00,
244         HOST_CR3                        = 0x00006c02,
245         HOST_CR4                        = 0x00006c04,
246         HOST_FS_BASE                    = 0x00006c06,
247         HOST_GS_BASE                    = 0x00006c08,
248         HOST_TR_BASE                    = 0x00006c0a,
249         HOST_GDTR_BASE                  = 0x00006c0c,
250         HOST_IDTR_BASE                  = 0x00006c0e,
251         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
252         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
253         HOST_RSP                        = 0x00006c14,
254         HOST_RIP                        = 0x00006c16,
255 };
256
257 /*
258  * Interruption-information format
259  */
260 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
261 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
262 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
263 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
264 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
265 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
266
267 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
268 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
269 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
270 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
271
272 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
273 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
274 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
275 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
276 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
277
278 /* GUEST_INTERRUPTIBILITY_INFO flags. */
279 #define GUEST_INTR_STATE_STI            0x00000001
280 #define GUEST_INTR_STATE_MOV_SS         0x00000002
281 #define GUEST_INTR_STATE_SMI            0x00000004
282 #define GUEST_INTR_STATE_NMI            0x00000008
283
284 /* GUEST_ACTIVITY_STATE flags */
285 #define GUEST_ACTIVITY_ACTIVE           0
286 #define GUEST_ACTIVITY_HLT              1
287 #define GUEST_ACTIVITY_SHUTDOWN         2
288 #define GUEST_ACTIVITY_WAIT_SIPI        3
289
290 /*
291  * Exit Qualifications for MOV for Control Register Access
292  */
293 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
294 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
295 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
296 #define LMSW_SOURCE_DATA_SHIFT 16
297 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
298 #define REG_EAX                         (0 << 8)
299 #define REG_ECX                         (1 << 8)
300 #define REG_EDX                         (2 << 8)
301 #define REG_EBX                         (3 << 8)
302 #define REG_ESP                         (4 << 8)
303 #define REG_EBP                         (5 << 8)
304 #define REG_ESI                         (6 << 8)
305 #define REG_EDI                         (7 << 8)
306 #define REG_R8                         (8 << 8)
307 #define REG_R9                         (9 << 8)
308 #define REG_R10                        (10 << 8)
309 #define REG_R11                        (11 << 8)
310 #define REG_R12                        (12 << 8)
311 #define REG_R13                        (13 << 8)
312 #define REG_R14                        (14 << 8)
313 #define REG_R15                        (15 << 8)
314
315 /*
316  * Exit Qualifications for MOV for Debug Register Access
317  */
318 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
319 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
320 #define TYPE_MOV_TO_DR                  (0 << 4)
321 #define TYPE_MOV_FROM_DR                (1 << 4)
322 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
323
324
325 /*
326  * Exit Qualifications for APIC-Access
327  */
328 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
329 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
330 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
331 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
332 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
333 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
334 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
335 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
336
337 /* segment AR */
338 #define SEGMENT_AR_L_MASK (1 << 13)
339
340 #define AR_TYPE_ACCESSES_MASK 1
341 #define AR_TYPE_READABLE_MASK (1 << 1)
342 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
343 #define AR_TYPE_CODE_MASK (1 << 3)
344 #define AR_TYPE_MASK 0x0f
345 #define AR_TYPE_BUSY_64_TSS 11
346 #define AR_TYPE_BUSY_32_TSS 11
347 #define AR_TYPE_BUSY_16_TSS 3
348 #define AR_TYPE_LDT 2
349
350 #define AR_UNUSABLE_MASK (1 << 16)
351 #define AR_S_MASK (1 << 4)
352 #define AR_P_MASK (1 << 7)
353 #define AR_L_MASK (1 << 13)
354 #define AR_DB_MASK (1 << 14)
355 #define AR_G_MASK (1 << 15)
356 #define AR_DPL_SHIFT 5
357 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
358
359 #define AR_RESERVD_MASK 0xfffe0f00
360
361 #define TSS_PRIVATE_MEMSLOT                     (KVM_USER_MEM_SLOTS + 0)
362 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_USER_MEM_SLOTS + 1)
363 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_USER_MEM_SLOTS + 2)
364
365 #define VMX_NR_VPIDS                            (1 << 16)
366 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
367 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
368
369 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
370 #define VMX_EPT_EXTENT_CONTEXT                  1
371 #define VMX_EPT_EXTENT_GLOBAL                   2
372
373 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
374 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
375 #define VMX_EPTP_UC_BIT                         (1ull << 8)
376 #define VMX_EPTP_WB_BIT                         (1ull << 14)
377 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
378 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
379 #define VMX_EPT_AD_BIT                              (1ull << 21)
380 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
381 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
382
383 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
384 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
385
386 #define VMX_EPT_DEFAULT_GAW                     3
387 #define VMX_EPT_MAX_GAW                         0x4
388 #define VMX_EPT_MT_EPTE_SHIFT                   3
389 #define VMX_EPT_GAW_EPTP_SHIFT                  3
390 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
391 #define VMX_EPT_DEFAULT_MT                      0x6ull
392 #define VMX_EPT_READABLE_MASK                   0x1ull
393 #define VMX_EPT_WRITABLE_MASK                   0x2ull
394 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
395 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
396 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
397 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
398
399 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
400
401
402 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
403 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
404 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
405 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
406 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
407 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
408 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
409 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
410 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
411 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
412 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
413
414 struct vmx_msr_entry {
415         u32 index;
416         u32 reserved;
417         u64 value;
418 } __aligned(16);
419
420 /*
421  * Exit Qualifications for entry failure during or after loading guest state
422  */
423 #define ENTRY_FAIL_DEFAULT              0
424 #define ENTRY_FAIL_PDPTE                2
425 #define ENTRY_FAIL_NMI                  3
426 #define ENTRY_FAIL_VMCS_LINK_PTR        4
427
428 /*
429  * VM-instruction error numbers
430  */
431 enum vm_instruction_error_number {
432         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
433         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
434         VMXERR_VMCLEAR_VMXON_POINTER = 3,
435         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
436         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
437         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
438         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
439         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
440         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
441         VMXERR_VMPTRLD_VMXON_POINTER = 10,
442         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
443         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
444         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
445         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
446         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
447         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
448         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
449         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
450         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
451         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
452         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
453         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
454         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
455         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
456         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
457 };
458
459 #endif