1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
89 char wp_works_ok; /* It doesn't on 386's */
91 /* Problems on some 486Dx4's and old 386's: */
100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
105 /* CPUID returned core id bits: */
106 __u8 x86_coreid_bits;
107 /* Max extended CPUID function supported: */
108 __u32 extended_cpuid_level;
109 /* Maximum supported CPUID level, -1=no CPUID: */
111 __u32 x86_capability[NCAPINTS];
112 char x86_vendor_id[16];
113 char x86_model_id[64];
114 /* in KB - valid for CPUS which support this call: */
116 int x86_cache_alignment; /* In bytes */
118 unsigned long loops_per_jiffy;
119 /* cpuid returned max cores value: */
123 u16 x86_clflush_size;
124 /* number of cores as seen by the OS: */
126 /* Physical processor id: */
130 /* Compute unit id */
132 /* Index into per_cpu list: */
135 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
137 #define X86_VENDOR_INTEL 0
138 #define X86_VENDOR_CYRIX 1
139 #define X86_VENDOR_AMD 2
140 #define X86_VENDOR_UMC 3
141 #define X86_VENDOR_CENTAUR 5
142 #define X86_VENDOR_TRANSMETA 7
143 #define X86_VENDOR_NSC 8
144 #define X86_VENDOR_NUM 9
146 #define X86_VENDOR_UNKNOWN 0xff
149 * capabilities of CPUs
151 extern struct cpuinfo_x86 boot_cpu_data;
152 extern struct cpuinfo_x86 new_cpu_data;
154 extern struct tss_struct doublefault_tss;
155 extern __u32 cpu_caps_cleared[NCAPINTS];
156 extern __u32 cpu_caps_set[NCAPINTS];
159 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
160 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
162 #define cpu_info boot_cpu_data
163 #define cpu_data(cpu) boot_cpu_data
166 extern const struct seq_operations cpuinfo_op;
168 static inline int hlt_works(int cpu)
171 return cpu_data(cpu).hlt_works_ok;
177 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
179 extern void cpu_detect(struct cpuinfo_x86 *c);
181 extern struct pt_regs *idle_regs(struct pt_regs *);
183 extern void early_cpu_init(void);
184 extern void identify_boot_cpu(void);
185 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
186 extern void print_cpu_info(struct cpuinfo_x86 *);
187 void print_cpu_msr(struct cpuinfo_x86 *);
188 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
189 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
190 extern unsigned short num_cache_leaves;
192 extern void detect_extended_topology(struct cpuinfo_x86 *c);
193 extern void detect_ht(struct cpuinfo_x86 *c);
195 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
196 unsigned int *ecx, unsigned int *edx)
198 /* ecx is often an input as well as an output. */
204 : "0" (*eax), "2" (*ecx)
208 static inline void load_cr3(pgd_t *pgdir)
210 write_cr3(__pa(pgdir));
214 /* This is the TSS defined by the hardware. */
216 unsigned short back_link, __blh;
218 unsigned short ss0, __ss0h;
220 /* ss1 caches MSR_IA32_SYSENTER_CS: */
221 unsigned short ss1, __ss1h;
223 unsigned short ss2, __ss2h;
235 unsigned short es, __esh;
236 unsigned short cs, __csh;
237 unsigned short ss, __ssh;
238 unsigned short ds, __dsh;
239 unsigned short fs, __fsh;
240 unsigned short gs, __gsh;
241 unsigned short ldt, __ldth;
242 unsigned short trace;
243 unsigned short io_bitmap_base;
245 } __attribute__((packed));
259 } __attribute__((packed)) ____cacheline_aligned;
265 #define IO_BITMAP_BITS 65536
266 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
267 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
268 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
269 #define INVALID_IO_BITMAP_OFFSET 0x8000
273 * The hardware state:
275 struct x86_hw_tss x86_tss;
278 * The extra 1 is there because the CPU will access an
279 * additional byte beyond the end of the IO permission
280 * bitmap. The extra byte must be all 1 bits, and must
281 * be within the limit.
283 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
286 * .. and then another 0x100 bytes for the emergency kernel stack:
288 unsigned long stack[64];
290 } ____cacheline_aligned;
292 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
295 * Save the original ist values for checking stack pointers during debugging
298 unsigned long ist[7];
301 #define MXCSR_DEFAULT 0x1f80
303 struct i387_fsave_struct {
304 u32 cwd; /* FPU Control Word */
305 u32 swd; /* FPU Status Word */
306 u32 twd; /* FPU Tag Word */
307 u32 fip; /* FPU IP Offset */
308 u32 fcs; /* FPU IP Selector */
309 u32 foo; /* FPU Operand Pointer Offset */
310 u32 fos; /* FPU Operand Pointer Selector */
312 /* 8*10 bytes for each FP-reg = 80 bytes: */
315 /* Software status information [not touched by FSAVE ]: */
319 struct i387_fxsave_struct {
320 u16 cwd; /* Control Word */
321 u16 swd; /* Status Word */
322 u16 twd; /* Tag Word */
323 u16 fop; /* Last Instruction Opcode */
326 u64 rip; /* Instruction Pointer */
327 u64 rdp; /* Data Pointer */
330 u32 fip; /* FPU IP Offset */
331 u32 fcs; /* FPU IP Selector */
332 u32 foo; /* FPU Operand Offset */
333 u32 fos; /* FPU Operand Selector */
336 u32 mxcsr; /* MXCSR Register State */
337 u32 mxcsr_mask; /* MXCSR Mask */
339 /* 8*16 bytes for each FP-reg = 128 bytes: */
342 /* 16*16 bytes for each XMM-reg = 256 bytes: */
352 } __attribute__((aligned(16)));
354 struct i387_soft_struct {
362 /* 8*10 bytes for each FP-reg = 80 bytes: */
370 struct math_emu_info *info;
375 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
379 struct xsave_hdr_struct {
383 } __attribute__((packed));
385 struct xsave_struct {
386 struct i387_fxsave_struct i387;
387 struct xsave_hdr_struct xsave_hdr;
388 struct ymmh_struct ymmh;
389 /* new processor state extensions will go here */
390 } __attribute__ ((packed, aligned (64)));
392 union thread_xstate {
393 struct i387_fsave_struct fsave;
394 struct i387_fxsave_struct fxsave;
395 struct i387_soft_struct soft;
396 struct xsave_struct xsave;
400 unsigned int last_cpu;
401 unsigned int has_fpu;
402 union thread_xstate *state;
406 DECLARE_PER_CPU(struct orig_ist, orig_ist);
408 union irq_stack_union {
409 char irq_stack[IRQ_STACK_SIZE];
411 * GCC hardcodes the stack canary as %gs:40. Since the
412 * irq_stack is the object at %gs:0, we reserve the bottom
413 * 48 bytes of the irq stack for the canary.
417 unsigned long stack_canary;
421 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
422 DECLARE_INIT_PER_CPU(irq_stack_union);
424 DECLARE_PER_CPU(char *, irq_stack_ptr);
425 DECLARE_PER_CPU(unsigned int, irq_count);
426 extern asmlinkage void ignore_sysret(void);
428 #ifdef CONFIG_CC_STACKPROTECTOR
430 * Make sure stack canary segment base is cached-aligned:
431 * "For Intel Atom processors, avoid non zero segment base address
432 * that is not aligned to cache line boundary at all cost."
433 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
435 struct stack_canary {
436 char __pad[20]; /* canary at %gs:20 */
437 unsigned long canary;
439 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
443 extern unsigned int xstate_size;
444 extern void free_thread_xstate(struct task_struct *);
445 extern struct kmem_cache *task_xstate_cachep;
449 struct thread_struct {
450 /* Cached TLS descriptors: */
451 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
455 unsigned long sysenter_cs;
457 unsigned long usersp; /* Copy from PDA */
460 unsigned short fsindex;
461 unsigned short gsindex;
470 /* Save middle states of ptrace breakpoints */
471 struct perf_event *ptrace_bps[HBP_NUM];
472 /* Debug status used for traps, single steps, etc... */
473 unsigned long debugreg6;
474 /* Keep track of the exact dr7 value set by the user */
475 unsigned long ptrace_dr7;
478 unsigned long trap_nr;
479 unsigned long error_code;
480 /* floating point and extended processor state */
483 /* Virtual 86 mode info */
484 struct vm86_struct __user *vm86_info;
485 unsigned long screen_bitmap;
486 unsigned long v86flags;
487 unsigned long v86mask;
488 unsigned long saved_sp0;
489 unsigned int saved_fs;
490 unsigned int saved_gs;
492 /* IO permissions: */
493 unsigned long *io_bitmap_ptr;
495 /* Max allowed port in the bitmap, in bytes: */
496 unsigned io_bitmap_max;
500 * Set IOPL bits in EFLAGS from given mask
502 static inline void native_set_iopl_mask(unsigned mask)
507 asm volatile ("pushfl;"
514 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
519 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
521 tss->x86_tss.sp0 = thread->sp0;
523 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
524 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
525 tss->x86_tss.ss1 = thread->sysenter_cs;
526 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
531 static inline void native_swapgs(void)
534 asm volatile("swapgs" ::: "memory");
538 #ifdef CONFIG_PARAVIRT
539 #include <asm/paravirt.h>
541 #define __cpuid native_cpuid
542 #define paravirt_enabled() 0
544 static inline void load_sp0(struct tss_struct *tss,
545 struct thread_struct *thread)
547 native_load_sp0(tss, thread);
550 #define set_iopl_mask native_set_iopl_mask
551 #endif /* CONFIG_PARAVIRT */
554 * Save the cr4 feature set we're using (ie
555 * Pentium 4MB enable and PPro Global page
556 * enable), so that any CPU's that boot up
557 * after us can get the correct flags.
559 extern unsigned long mmu_cr4_features;
560 extern u32 *trampoline_cr4_features;
562 static inline void set_in_cr4(unsigned long mask)
566 mmu_cr4_features |= mask;
567 if (trampoline_cr4_features)
568 *trampoline_cr4_features = mmu_cr4_features;
574 static inline void clear_in_cr4(unsigned long mask)
578 mmu_cr4_features &= ~mask;
579 if (trampoline_cr4_features)
580 *trampoline_cr4_features = mmu_cr4_features;
591 /* Free all resources held by a thread. */
592 extern void release_thread(struct task_struct *);
594 unsigned long get_wchan(struct task_struct *p);
597 * Generic CPUID function
598 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
599 * resulting in stale register contents being returned.
601 static inline void cpuid(unsigned int op,
602 unsigned int *eax, unsigned int *ebx,
603 unsigned int *ecx, unsigned int *edx)
607 __cpuid(eax, ebx, ecx, edx);
610 /* Some CPUID calls want 'count' to be placed in ecx */
611 static inline void cpuid_count(unsigned int op, int count,
612 unsigned int *eax, unsigned int *ebx,
613 unsigned int *ecx, unsigned int *edx)
617 __cpuid(eax, ebx, ecx, edx);
621 * CPUID functions returning a single datum
623 static inline unsigned int cpuid_eax(unsigned int op)
625 unsigned int eax, ebx, ecx, edx;
627 cpuid(op, &eax, &ebx, &ecx, &edx);
632 static inline unsigned int cpuid_ebx(unsigned int op)
634 unsigned int eax, ebx, ecx, edx;
636 cpuid(op, &eax, &ebx, &ecx, &edx);
641 static inline unsigned int cpuid_ecx(unsigned int op)
643 unsigned int eax, ebx, ecx, edx;
645 cpuid(op, &eax, &ebx, &ecx, &edx);
650 static inline unsigned int cpuid_edx(unsigned int op)
652 unsigned int eax, ebx, ecx, edx;
654 cpuid(op, &eax, &ebx, &ecx, &edx);
659 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
660 static inline void rep_nop(void)
662 asm volatile("rep; nop" ::: "memory");
665 static inline void cpu_relax(void)
670 /* Stop speculative execution and prefetching of modified code. */
671 static inline void sync_core(void)
675 #if defined(CONFIG_M386) || defined(CONFIG_M486)
676 if (boot_cpu_data.x86 < 5)
677 /* There is no speculative execution.
678 * jmp is a barrier to prefetching. */
679 asm volatile("jmp 1f\n1:\n" ::: "memory");
682 /* cpuid is a barrier to speculative execution.
683 * Prefetched instructions are automatically
684 * invalidated when modified. */
685 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
686 : "ebx", "ecx", "edx", "memory");
689 static inline void __monitor(const void *eax, unsigned long ecx,
692 /* "monitor %eax, %ecx, %edx;" */
693 asm volatile(".byte 0x0f, 0x01, 0xc8;"
694 :: "a" (eax), "c" (ecx), "d"(edx));
697 static inline void __mwait(unsigned long eax, unsigned long ecx)
699 /* "mwait %eax, %ecx;" */
700 asm volatile(".byte 0x0f, 0x01, 0xc9;"
701 :: "a" (eax), "c" (ecx));
704 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
707 /* "mwait %eax, %ecx;" */
708 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
709 :: "a" (eax), "c" (ecx));
712 extern void select_idle_routine(const struct cpuinfo_x86 *c);
713 extern void init_amd_e400_c1e_mask(void);
715 extern unsigned long boot_option_idle_override;
716 extern bool amd_e400_c1e_detected;
718 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
719 IDLE_POLL, IDLE_FORCE_MWAIT};
721 extern void enable_sep_cpu(void);
722 extern int sysenter_setup(void);
724 extern void early_trap_init(void);
726 /* Defined in head.S */
727 extern struct desc_ptr early_gdt_descr;
729 extern void cpu_set_gdt(int);
730 extern void switch_to_new_gdt(int);
731 extern void load_percpu_segment(int);
732 extern void cpu_init(void);
734 static inline unsigned long get_debugctlmsr(void)
736 unsigned long debugctlmsr = 0;
738 #ifndef CONFIG_X86_DEBUGCTLMSR
739 if (boot_cpu_data.x86 < 6)
742 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
747 static inline void update_debugctlmsr(unsigned long debugctlmsr)
749 #ifndef CONFIG_X86_DEBUGCTLMSR
750 if (boot_cpu_data.x86 < 6)
753 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
756 extern void set_task_blockstep(struct task_struct *task, bool on);
759 * from system description table in BIOS. Mostly for MCA use, but
760 * others may find it useful:
762 extern unsigned int machine_id;
763 extern unsigned int machine_submodel_id;
764 extern unsigned int BIOS_revision;
766 /* Boot loader type from the setup header: */
767 extern int bootloader_type;
768 extern int bootloader_version;
770 extern char ignore_fpu_irq;
772 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
773 #define ARCH_HAS_PREFETCHW
774 #define ARCH_HAS_SPINLOCK_PREFETCH
777 # define BASE_PREFETCH ASM_NOP4
778 # define ARCH_HAS_PREFETCH
780 # define BASE_PREFETCH "prefetcht0 (%1)"
784 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
786 * It's not worth to care about 3dnow prefetches for the K6
787 * because they are microcoded there and very slow.
789 static inline void prefetch(const void *x)
791 alternative_input(BASE_PREFETCH,
798 * 3dnow prefetch to get an exclusive cache line.
799 * Useful for spinlocks to avoid one state transition in the
800 * cache coherency protocol:
802 static inline void prefetchw(const void *x)
804 alternative_input(BASE_PREFETCH,
810 static inline void spin_lock_prefetch(const void *x)
817 * User space process size: 3GB (default).
819 #define TASK_SIZE PAGE_OFFSET
820 #define TASK_SIZE_MAX TASK_SIZE
821 #define STACK_TOP TASK_SIZE
822 #define STACK_TOP_MAX STACK_TOP
824 #define INIT_THREAD { \
825 .sp0 = sizeof(init_stack) + (long)&init_stack, \
827 .sysenter_cs = __KERNEL_CS, \
828 .io_bitmap_ptr = NULL, \
832 * Note that the .io_bitmap member must be extra-big. This is because
833 * the CPU will access an additional byte beyond the end of the IO
834 * permission bitmap. The extra byte must be all 1 bits, and must
835 * be within the limit.
839 .sp0 = sizeof(init_stack) + (long)&init_stack, \
840 .ss0 = __KERNEL_DS, \
841 .ss1 = __KERNEL_CS, \
842 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
844 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
847 extern unsigned long thread_saved_pc(struct task_struct *tsk);
849 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
850 #define KSTK_TOP(info) \
852 unsigned long *__ptr = (unsigned long *)(info); \
853 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
857 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
858 * This is necessary to guarantee that the entire "struct pt_regs"
859 * is accessible even if the CPU haven't stored the SS/ESP registers
860 * on the stack (interrupt gate does not save these registers
861 * when switching to the same priv ring).
862 * Therefore beware: accessing the ss/esp fields of the
863 * "struct pt_regs" is possible, but they may contain the
864 * completely wrong values.
866 #define task_pt_regs(task) \
868 struct pt_regs *__regs__; \
869 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
873 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
877 * User space process size. 47bits minus one guard page.
879 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
881 /* This decides where the kernel will search for a free chunk of vm
882 * space during mmap's.
884 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
885 0xc0000000 : 0xFFFFe000)
887 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
888 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
889 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
890 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
892 #define STACK_TOP TASK_SIZE
893 #define STACK_TOP_MAX TASK_SIZE_MAX
895 #define INIT_THREAD { \
896 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
900 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
904 * Return saved PC of a blocked thread.
905 * What is this good for? it will be always the scheduler or ret_from_fork.
907 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
909 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
910 extern unsigned long KSTK_ESP(struct task_struct *task);
913 * User space RSP while inside the SYSCALL fast path
915 DECLARE_PER_CPU(unsigned long, old_rsp);
917 #endif /* CONFIG_X86_64 */
919 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
920 unsigned long new_sp);
923 * This decides where the kernel will search for a free chunk of vm
924 * space during mmap's.
926 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
928 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
930 /* Get/set a process' ability to use the timestamp counter instruction */
931 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
932 #define SET_TSC_CTL(val) set_tsc_mode((val))
934 extern int get_tsc_mode(unsigned long adr);
935 extern int set_tsc_mode(unsigned int val);
937 extern int amd_get_nb_id(int cpu);
943 static inline void get_aperfmperf(struct aperfmperf *am)
945 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
947 rdmsrl(MSR_IA32_APERF, am->aperf);
948 rdmsrl(MSR_IA32_MPERF, am->mperf);
951 #define APERFMPERF_SHIFT 10
954 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
955 struct aperfmperf *new)
957 u64 aperf = new->aperf - old->aperf;
958 u64 mperf = new->mperf - old->mperf;
959 unsigned long ratio = aperf;
961 mperf >>= APERFMPERF_SHIFT;
963 ratio = div64_u64(aperf, mperf);
969 * AMD errata checking
971 #ifdef CONFIG_CPU_SUP_AMD
972 extern const int amd_erratum_383[];
973 extern const int amd_erratum_400[];
974 extern bool cpu_has_amd_erratum(const int *);
976 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
977 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
978 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
979 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
980 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
981 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
982 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
985 #define cpu_has_amd_erratum(x) (false)
986 #endif /* CONFIG_CPU_SUP_AMD */
988 extern unsigned long arch_align_stack(unsigned long sp);
989 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
991 void default_idle(void);
992 bool set_pm_idle_to_default(void);
994 void stop_this_cpu(void *dummy);
996 #endif /* _ASM_X86_PROCESSOR_H */