1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
14 #include <asm/system.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
27 * Define the default level of output to be very little
28 * This can be turned up by using apic=verbose for more
29 * information and apic=debug for _lots_ of information.
30 * apic_verbosity is defined in apic.c
32 #define apic_printk(v, s, a...) do { \
33 if ((v) <= apic_verbosity) \
38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
39 extern void generic_apic_probe(void);
41 static inline void generic_apic_probe(void)
46 #ifdef CONFIG_X86_LOCAL_APIC
48 extern unsigned int apic_verbosity;
49 extern int local_apic_timer_c2_ok;
51 extern int disable_apic;
52 extern unsigned int lapic_timer_frequency;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
76 static inline bool apic_from_smp_config(void)
78 return smp_found_config && !disable_apic;
82 * Basic functions accessing APICs.
84 #ifdef CONFIG_PARAVIRT
85 #include <asm/paravirt.h>
89 extern int is_vsmp_box(void);
91 static inline int is_vsmp_box(void)
96 extern void xapic_wait_icr_idle(void);
97 extern u32 safe_xapic_wait_icr_idle(void);
98 extern void xapic_icr_write(u32, u32);
99 extern int setup_profiling_timer(unsigned int);
101 static inline void native_apic_mem_write(u32 reg, u32 v)
103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
106 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
107 ASM_OUTPUT2("0" (v), "m" (*addr)));
110 static inline u32 native_apic_mem_read(u32 reg)
112 return *((volatile u32 *)(APIC_BASE + reg));
115 extern void native_apic_wait_icr_idle(void);
116 extern u32 native_safe_apic_wait_icr_idle(void);
117 extern void native_apic_icr_write(u32 low, u32 id);
118 extern u64 native_apic_icr_read(void);
120 extern int x2apic_mode;
122 #ifdef CONFIG_X86_X2APIC
124 * Make previous memory operations globally visible before
125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
128 static inline void x2apic_wrmsr_fence(void)
130 asm volatile("mfence" : : : "memory");
133 static inline void native_apic_msr_write(u32 reg, u32 v)
135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
142 static inline u32 native_apic_msr_read(u32 reg)
149 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
153 static inline void native_x2apic_wait_icr_idle(void)
155 /* no need to wait for icr idle in x2apic */
159 static inline u32 native_safe_x2apic_wait_icr_idle(void)
161 /* no need to wait for icr idle in x2apic */
165 static inline void native_x2apic_icr_write(u32 low, u32 id)
167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
170 static inline u64 native_x2apic_icr_read(void)
174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
178 extern int x2apic_phys;
179 extern int x2apic_preenabled;
180 extern void check_x2apic(void);
181 extern void enable_x2apic(void);
182 extern void x2apic_icr_write(u32 low, u32 id);
183 static inline int x2apic_enabled(void)
190 rdmsrl(MSR_IA32_APICBASE, msr);
191 if (msr & X2APIC_ENABLE)
196 #define x2apic_supported() (cpu_has_x2apic)
197 static inline void x2apic_force_phys(void)
202 static inline void disable_x2apic(void)
205 static inline void check_x2apic(void)
208 static inline void enable_x2apic(void)
211 static inline int x2apic_enabled(void)
215 static inline void x2apic_force_phys(void)
220 #define x2apic_preenabled 0
221 #define x2apic_supported() 0
224 extern void enable_IR_x2apic(void);
226 extern int get_physical_broadcast(void);
228 extern int lapic_get_maxlvt(void);
229 extern void clear_local_APIC(void);
230 extern void connect_bsp_APIC(void);
231 extern void disconnect_bsp_APIC(int virt_wire_setup);
232 extern void disable_local_APIC(void);
233 extern void lapic_shutdown(void);
234 extern int verify_local_APIC(void);
235 extern void sync_Arb_IDs(void);
236 extern void init_bsp_APIC(void);
237 extern void setup_local_APIC(void);
238 extern void end_local_APIC_setup(void);
239 extern void bsp_end_local_APIC_setup(void);
240 extern void init_apic_mappings(void);
241 void register_lapic_address(unsigned long address);
242 extern void setup_boot_APIC_clock(void);
243 extern void setup_secondary_APIC_clock(void);
244 extern int APIC_init_uniprocessor(void);
245 extern int apic_force_enable(unsigned long addr);
248 * On 32bit this is mach-xxx local
251 extern int apic_is_clustered_box(void);
253 static inline int apic_is_clustered_box(void)
259 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
261 #else /* !CONFIG_X86_LOCAL_APIC */
262 static inline void lapic_shutdown(void) { }
263 #define local_apic_timer_c2_ok 1
264 static inline void init_apic_mappings(void) { }
265 static inline void disable_local_APIC(void) { }
266 # define setup_boot_APIC_clock x86_init_noop
267 # define setup_secondary_APIC_clock x86_init_noop
268 #endif /* !CONFIG_X86_LOCAL_APIC */
271 #define SET_APIC_ID(x) (apic->set_apic_id(x))
277 * Copyright 2004 James Cleverdon, IBM.
278 * Subject to the GNU Public License, v.2
280 * Generic APIC sub-arch data struct.
282 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
283 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
290 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
291 int (*apic_id_valid)(int apicid);
292 int (*apic_id_registered)(void);
294 u32 irq_delivery_mode;
297 const struct cpumask *(*target_cpus)(void);
302 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
303 unsigned long (*check_apicid_present)(int apicid);
305 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
306 void (*init_apic_ldr)(void);
308 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
310 void (*setup_apic_routing)(void);
311 int (*multi_timer_check)(int apic, int irq);
312 int (*cpu_present_to_apicid)(int mps_cpu);
313 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
314 void (*setup_portio_remap)(void);
315 int (*check_phys_apicid_present)(int phys_apicid);
316 void (*enable_apic_mode)(void);
317 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
320 * When one of the next two hooks returns 1 the apic
321 * is switched to this. Essentially they are additional
324 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
326 unsigned int (*get_apic_id)(unsigned long x);
327 unsigned long (*set_apic_id)(unsigned int id);
328 unsigned long apic_id_mask;
330 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
331 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
332 const struct cpumask *andmask);
335 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
336 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
338 void (*send_IPI_allbutself)(int vector);
339 void (*send_IPI_all)(int vector);
340 void (*send_IPI_self)(int vector);
342 /* wakeup_secondary_cpu */
343 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
345 int trampoline_phys_low;
346 int trampoline_phys_high;
348 void (*wait_for_init_deassert)(atomic_t *deassert);
349 void (*smp_callin_clear_local_apic)(void);
350 void (*inquire_remote_apic)(int apicid);
353 u32 (*read)(u32 reg);
354 void (*write)(u32 reg, u32 v);
355 u64 (*icr_read)(void);
356 void (*icr_write)(u32 low, u32 high);
357 void (*wait_icr_idle)(void);
358 u32 (*safe_wait_icr_idle)(void);
362 * Called very early during boot from get_smp_config(). It should
363 * return the logical apicid. x86_[bios]_cpu_to_apicid is
364 * initialized before this function is called.
366 * If logical apicid can't be determined that early, the function
367 * may return BAD_APICID. Logical apicid will be configured after
368 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
369 * won't be applied properly during early boot in this case.
371 int (*x86_32_early_logical_apicid)(int cpu);
374 * Optional method called from setup_local_APIC() after logical
375 * apicid is guaranteed to be known to initialize apicid -> node
376 * mapping if NUMA initialization hasn't done so already. Don't
379 int (*x86_32_numa_cpu_node)(int cpu);
384 * Pointer to the local APIC driver in use on this system (there's
385 * always just one such driver in use - the kernel decides via an
386 * early probing process which one it picks - and then sticks to it):
388 extern struct apic *apic;
391 * APIC drivers are probed based on how they are listed in the .apicdrivers
392 * section. So the order is important and enforced by the ordering
393 * of different apic driver files in the Makefile.
395 * For the files having two apic drivers, we use apic_drivers()
396 * to enforce the order with in them.
398 #define apic_driver(sym) \
399 static struct apic *__apicdrivers_##sym __used \
400 __aligned(sizeof(struct apic *)) \
401 __section(.apicdrivers) = { &sym }
403 #define apic_drivers(sym1, sym2) \
404 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
405 __aligned(sizeof(struct apic *)) \
406 __section(.apicdrivers) = { &sym1, &sym2 }
408 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
411 * APIC functionality to boot other CPUs - only used on SMP:
414 extern atomic_t init_deasserted;
415 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
418 #ifdef CONFIG_X86_LOCAL_APIC
420 static inline u32 apic_read(u32 reg)
422 return apic->read(reg);
425 static inline void apic_write(u32 reg, u32 val)
427 apic->write(reg, val);
430 static inline u64 apic_icr_read(void)
432 return apic->icr_read();
435 static inline void apic_icr_write(u32 low, u32 high)
437 apic->icr_write(low, high);
440 static inline void apic_wait_icr_idle(void)
442 apic->wait_icr_idle();
445 static inline u32 safe_apic_wait_icr_idle(void)
447 return apic->safe_wait_icr_idle();
450 #else /* CONFIG_X86_LOCAL_APIC */
452 static inline u32 apic_read(u32 reg) { return 0; }
453 static inline void apic_write(u32 reg, u32 val) { }
454 static inline u64 apic_icr_read(void) { return 0; }
455 static inline void apic_icr_write(u32 low, u32 high) { }
456 static inline void apic_wait_icr_idle(void) { }
457 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
459 #endif /* CONFIG_X86_LOCAL_APIC */
461 static inline void ack_APIC_irq(void)
464 * ack_APIC_irq() actually gets compiled as a single instruction
468 /* Docs say use 0 for future compatibility */
469 apic_write(APIC_EOI, 0);
472 static inline unsigned default_get_apic_id(unsigned long x)
474 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
476 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
477 return (x >> 24) & 0xFF;
479 return (x >> 24) & 0x0F;
483 * Warm reset vector default position:
485 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
486 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
489 extern int default_acpi_madt_oem_check(char *, char *);
491 extern void apic_send_IPI_self(int vector);
493 DECLARE_PER_CPU(int, x2apic_extra_bits);
495 extern int default_cpu_present_to_apicid(int mps_cpu);
496 extern int default_check_phys_apicid_present(int phys_apicid);
499 static inline void default_wait_for_init_deassert(atomic_t *deassert)
501 while (!atomic_read(deassert))
506 extern void generic_bigsmp_probe(void);
509 #ifdef CONFIG_X86_LOCAL_APIC
513 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
515 static inline const struct cpumask *default_target_cpus(void)
518 return cpu_online_mask;
520 return cpumask_of(0);
524 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
527 static inline unsigned int read_apic_id(void)
531 reg = apic_read(APIC_ID);
533 return apic->get_apic_id(reg);
536 static inline int default_apic_id_valid(int apicid)
538 return x2apic_mode || (apicid < 255);
541 extern void default_setup_apic_routing(void);
543 extern struct apic apic_noop;
547 static inline int noop_x86_32_early_logical_apicid(int cpu)
553 * Set up the logical destination ID.
555 * Intel recommends to set DFR, LDR and TPR before enabling
556 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
557 * document number 292116). So here it goes...
559 extern void default_init_apic_ldr(void);
561 static inline int default_apic_id_registered(void)
563 return physid_isset(read_apic_id(), phys_cpu_present_map);
566 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
568 return cpuid_apic >> index_msb;
573 static inline unsigned int
574 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
576 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
579 static inline unsigned int
580 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
581 const struct cpumask *andmask)
583 unsigned long mask1 = cpumask_bits(cpumask)[0];
584 unsigned long mask2 = cpumask_bits(andmask)[0];
585 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
587 return (unsigned int)(mask1 & mask2 & mask3);
590 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
592 return physid_isset(apicid, *map);
595 static inline unsigned long default_check_apicid_present(int bit)
597 return physid_isset(bit, phys_cpu_present_map);
600 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
605 static inline int __default_cpu_present_to_apicid(int mps_cpu)
607 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
608 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
614 __default_check_phys_apicid_present(int phys_apicid)
616 return physid_isset(phys_apicid, phys_cpu_present_map);
620 static inline int default_cpu_present_to_apicid(int mps_cpu)
622 return __default_cpu_present_to_apicid(mps_cpu);
626 default_check_phys_apicid_present(int phys_apicid)
628 return __default_check_phys_apicid_present(phys_apicid);
631 extern int default_cpu_present_to_apicid(int mps_cpu);
632 extern int default_check_phys_apicid_present(int phys_apicid);
635 #endif /* CONFIG_X86_LOCAL_APIC */
637 #endif /* _ASM_X86_APIC_H */