1 /* Define to include "bfd.h" and get actual BFD relocations below. */
2 /* #define WANT_BFD_RELOCS */
6 #define MAYBE_BFD_RELOC(X) (X)
8 #define MAYBE_BFD_RELOC(X) -1
11 /* Special registers. */
16 /* FIXME: Rename this. */
17 #include <asm/opcode-tile.h>
20 const struct tile_opcode tile_opcodes[394] =
22 { "bpt", TILE_OPC_BPT, 0x2 /* pipes */, 0 /* num_operands */,
23 TREG_ZERO, /* implicitly_written_register */
36 0xfbffffff80000000ULL,
42 /* fixed_bit_values */
44 0x400b3cae00000000ULL,
50 { "info", TILE_OPC_INFO, 0xf /* pipes */, 1 /* num_operands */,
51 TREG_ZERO, /* implicitly_written_register */
63 0x800000007ff00fffULL,
64 0xfff807ff80000000ULL,
65 0x8000000078000fffULL,
66 0xf80007ff80000000ULL,
70 /* fixed_bit_values */
71 0x0000000050100fffULL,
72 0x302007ff80000000ULL,
73 0x8000000050000fffULL,
74 0xc00007ff80000000ULL,
78 { "infol", TILE_OPC_INFOL, 0x3 /* pipes */, 1 /* num_operands */,
79 TREG_ZERO, /* implicitly_written_register */
91 0x8000000070000fffULL,
92 0xf80007ff80000000ULL,
98 /* fixed_bit_values */
99 0x0000000030000fffULL,
100 0x200007ff80000000ULL,
106 { "j", TILE_OPC_J, 0x2 /* pipes */, 1 /* num_operands */,
107 TREG_ZERO, /* implicitly_written_register */
118 /* fixed_bit_masks */
120 0xf000000000000000ULL,
126 /* fixed_bit_values */
128 0x5000000000000000ULL,
134 { "jal", TILE_OPC_JAL, 0x2 /* pipes */, 1 /* num_operands */,
135 TREG_LR, /* implicitly_written_register */
146 /* fixed_bit_masks */
148 0xf000000000000000ULL,
154 /* fixed_bit_values */
156 0x6000000000000000ULL,
162 { "move", TILE_OPC_MOVE, 0xf /* pipes */, 2 /* num_operands */,
163 TREG_ZERO, /* implicitly_written_register */
174 /* fixed_bit_masks */
175 0x800000007ffff000ULL,
176 0xfffff80000000000ULL,
177 0x80000000780ff000ULL,
178 0xf807f80000000000ULL,
182 /* fixed_bit_values */
183 0x0000000000cff000ULL,
184 0x0833f80000000000ULL,
185 0x80000000180bf000ULL,
186 0x9805f80000000000ULL,
190 { "move.sn", TILE_OPC_MOVE_SN, 0x3 /* pipes */, 2 /* num_operands */,
191 TREG_SN, /* implicitly_written_register */
202 /* fixed_bit_masks */
203 0x800000007ffff000ULL,
204 0xfffff80000000000ULL,
210 /* fixed_bit_values */
211 0x0000000008cff000ULL,
212 0x0c33f80000000000ULL,
218 { "movei", TILE_OPC_MOVEI, 0xf /* pipes */, 2 /* num_operands */,
219 TREG_ZERO, /* implicitly_written_register */
230 /* fixed_bit_masks */
231 0x800000007ff00fc0ULL,
232 0xfff807e000000000ULL,
233 0x8000000078000fc0ULL,
234 0xf80007e000000000ULL,
238 /* fixed_bit_values */
239 0x0000000040800fc0ULL,
240 0x305807e000000000ULL,
241 0x8000000058000fc0ULL,
242 0xc80007e000000000ULL,
246 { "movei.sn", TILE_OPC_MOVEI_SN, 0x3 /* pipes */, 2 /* num_operands */,
247 TREG_SN, /* implicitly_written_register */
258 /* fixed_bit_masks */
259 0x800000007ff00fc0ULL,
260 0xfff807e000000000ULL,
266 /* fixed_bit_values */
267 0x0000000048800fc0ULL,
268 0x345807e000000000ULL,
274 { "moveli", TILE_OPC_MOVELI, 0x3 /* pipes */, 2 /* num_operands */,
275 TREG_ZERO, /* implicitly_written_register */
286 /* fixed_bit_masks */
287 0x8000000070000fc0ULL,
288 0xf80007e000000000ULL,
294 /* fixed_bit_values */
295 0x0000000020000fc0ULL,
296 0x180007e000000000ULL,
302 { "moveli.sn", TILE_OPC_MOVELI_SN, 0x3 /* pipes */, 2 /* num_operands */,
303 TREG_SN, /* implicitly_written_register */
314 /* fixed_bit_masks */
315 0x8000000070000fc0ULL,
316 0xf80007e000000000ULL,
322 /* fixed_bit_values */
323 0x0000000010000fc0ULL,
324 0x100007e000000000ULL,
330 { "movelis", TILE_OPC_MOVELIS, 0x3 /* pipes */, 2 /* num_operands */,
331 TREG_SN, /* implicitly_written_register */
342 /* fixed_bit_masks */
343 0x8000000070000fc0ULL,
344 0xf80007e000000000ULL,
350 /* fixed_bit_values */
351 0x0000000010000fc0ULL,
352 0x100007e000000000ULL,
358 { "prefetch", TILE_OPC_PREFETCH, 0x12 /* pipes */, 1 /* num_operands */,
359 TREG_ZERO, /* implicitly_written_register */
370 /* fixed_bit_masks */
372 0xfffff81f80000000ULL,
375 0x8700000003f00000ULL
378 /* fixed_bit_values */
380 0x400b501f80000000ULL,
383 0x8000000003f00000ULL
386 { "add", TILE_OPC_ADD, 0xf /* pipes */, 3 /* num_operands */,
387 TREG_ZERO, /* implicitly_written_register */
398 /* fixed_bit_masks */
399 0x800000007ffc0000ULL,
400 0xfffe000000000000ULL,
401 0x80000000780c0000ULL,
402 0xf806000000000000ULL,
406 /* fixed_bit_values */
407 0x00000000000c0000ULL,
408 0x0806000000000000ULL,
409 0x8000000008000000ULL,
410 0x8800000000000000ULL,
414 { "add.sn", TILE_OPC_ADD_SN, 0x3 /* pipes */, 3 /* num_operands */,
415 TREG_SN, /* implicitly_written_register */
426 /* fixed_bit_masks */
427 0x800000007ffc0000ULL,
428 0xfffe000000000000ULL,
434 /* fixed_bit_values */
435 0x00000000080c0000ULL,
436 0x0c06000000000000ULL,
442 { "addb", TILE_OPC_ADDB, 0x3 /* pipes */, 3 /* num_operands */,
443 TREG_ZERO, /* implicitly_written_register */
454 /* fixed_bit_masks */
455 0x800000007ffc0000ULL,
456 0xfffe000000000000ULL,
462 /* fixed_bit_values */
463 0x0000000000040000ULL,
464 0x0802000000000000ULL,
470 { "addb.sn", TILE_OPC_ADDB_SN, 0x3 /* pipes */, 3 /* num_operands */,
471 TREG_SN, /* implicitly_written_register */
482 /* fixed_bit_masks */
483 0x800000007ffc0000ULL,
484 0xfffe000000000000ULL,
490 /* fixed_bit_values */
491 0x0000000008040000ULL,
492 0x0c02000000000000ULL,
498 { "addbs_u", TILE_OPC_ADDBS_U, 0x3 /* pipes */, 3 /* num_operands */,
499 TREG_ZERO, /* implicitly_written_register */
510 /* fixed_bit_masks */
511 0x800000007ffc0000ULL,
512 0xfffe000000000000ULL,
518 /* fixed_bit_values */
519 0x0000000001880000ULL,
520 0x0888000000000000ULL,
526 { "addbs_u.sn", TILE_OPC_ADDBS_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
527 TREG_SN, /* implicitly_written_register */
538 /* fixed_bit_masks */
539 0x800000007ffc0000ULL,
540 0xfffe000000000000ULL,
546 /* fixed_bit_values */
547 0x0000000009880000ULL,
548 0x0c88000000000000ULL,
554 { "addh", TILE_OPC_ADDH, 0x3 /* pipes */, 3 /* num_operands */,
555 TREG_ZERO, /* implicitly_written_register */
566 /* fixed_bit_masks */
567 0x800000007ffc0000ULL,
568 0xfffe000000000000ULL,
574 /* fixed_bit_values */
575 0x0000000000080000ULL,
576 0x0804000000000000ULL,
582 { "addh.sn", TILE_OPC_ADDH_SN, 0x3 /* pipes */, 3 /* num_operands */,
583 TREG_SN, /* implicitly_written_register */
594 /* fixed_bit_masks */
595 0x800000007ffc0000ULL,
596 0xfffe000000000000ULL,
602 /* fixed_bit_values */
603 0x0000000008080000ULL,
604 0x0c04000000000000ULL,
610 { "addhs", TILE_OPC_ADDHS, 0x3 /* pipes */, 3 /* num_operands */,
611 TREG_ZERO, /* implicitly_written_register */
622 /* fixed_bit_masks */
623 0x800000007ffc0000ULL,
624 0xfffe000000000000ULL,
630 /* fixed_bit_values */
631 0x00000000018c0000ULL,
632 0x088a000000000000ULL,
638 { "addhs.sn", TILE_OPC_ADDHS_SN, 0x3 /* pipes */, 3 /* num_operands */,
639 TREG_SN, /* implicitly_written_register */
650 /* fixed_bit_masks */
651 0x800000007ffc0000ULL,
652 0xfffe000000000000ULL,
658 /* fixed_bit_values */
659 0x00000000098c0000ULL,
660 0x0c8a000000000000ULL,
666 { "addi", TILE_OPC_ADDI, 0xf /* pipes */, 3 /* num_operands */,
667 TREG_ZERO, /* implicitly_written_register */
678 /* fixed_bit_masks */
679 0x800000007ff00000ULL,
680 0xfff8000000000000ULL,
681 0x8000000078000000ULL,
682 0xf800000000000000ULL,
686 /* fixed_bit_values */
687 0x0000000040300000ULL,
688 0x3018000000000000ULL,
689 0x8000000048000000ULL,
690 0xb800000000000000ULL,
694 { "addi.sn", TILE_OPC_ADDI_SN, 0x3 /* pipes */, 3 /* num_operands */,
695 TREG_SN, /* implicitly_written_register */
706 /* fixed_bit_masks */
707 0x800000007ff00000ULL,
708 0xfff8000000000000ULL,
714 /* fixed_bit_values */
715 0x0000000048300000ULL,
716 0x3418000000000000ULL,
722 { "addib", TILE_OPC_ADDIB, 0x3 /* pipes */, 3 /* num_operands */,
723 TREG_ZERO, /* implicitly_written_register */
734 /* fixed_bit_masks */
735 0x800000007ff00000ULL,
736 0xfff8000000000000ULL,
742 /* fixed_bit_values */
743 0x0000000040100000ULL,
744 0x3008000000000000ULL,
750 { "addib.sn", TILE_OPC_ADDIB_SN, 0x3 /* pipes */, 3 /* num_operands */,
751 TREG_SN, /* implicitly_written_register */
762 /* fixed_bit_masks */
763 0x800000007ff00000ULL,
764 0xfff8000000000000ULL,
770 /* fixed_bit_values */
771 0x0000000048100000ULL,
772 0x3408000000000000ULL,
778 { "addih", TILE_OPC_ADDIH, 0x3 /* pipes */, 3 /* num_operands */,
779 TREG_ZERO, /* implicitly_written_register */
790 /* fixed_bit_masks */
791 0x800000007ff00000ULL,
792 0xfff8000000000000ULL,
798 /* fixed_bit_values */
799 0x0000000040200000ULL,
800 0x3010000000000000ULL,
806 { "addih.sn", TILE_OPC_ADDIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
807 TREG_SN, /* implicitly_written_register */
818 /* fixed_bit_masks */
819 0x800000007ff00000ULL,
820 0xfff8000000000000ULL,
826 /* fixed_bit_values */
827 0x0000000048200000ULL,
828 0x3410000000000000ULL,
834 { "addli", TILE_OPC_ADDLI, 0x3 /* pipes */, 3 /* num_operands */,
835 TREG_ZERO, /* implicitly_written_register */
846 /* fixed_bit_masks */
847 0x8000000070000000ULL,
848 0xf800000000000000ULL,
854 /* fixed_bit_values */
855 0x0000000020000000ULL,
856 0x1800000000000000ULL,
862 { "addli.sn", TILE_OPC_ADDLI_SN, 0x3 /* pipes */, 3 /* num_operands */,
863 TREG_SN, /* implicitly_written_register */
874 /* fixed_bit_masks */
875 0x8000000070000000ULL,
876 0xf800000000000000ULL,
882 /* fixed_bit_values */
883 0x0000000010000000ULL,
884 0x1000000000000000ULL,
890 { "addlis", TILE_OPC_ADDLIS, 0x3 /* pipes */, 3 /* num_operands */,
891 TREG_SN, /* implicitly_written_register */
902 /* fixed_bit_masks */
903 0x8000000070000000ULL,
904 0xf800000000000000ULL,
910 /* fixed_bit_values */
911 0x0000000010000000ULL,
912 0x1000000000000000ULL,
918 { "adds", TILE_OPC_ADDS, 0x3 /* pipes */, 3 /* num_operands */,
919 TREG_ZERO, /* implicitly_written_register */
930 /* fixed_bit_masks */
931 0x800000007ffc0000ULL,
932 0xfffe000000000000ULL,
938 /* fixed_bit_values */
939 0x0000000001800000ULL,
940 0x0884000000000000ULL,
946 { "adds.sn", TILE_OPC_ADDS_SN, 0x3 /* pipes */, 3 /* num_operands */,
947 TREG_SN, /* implicitly_written_register */
958 /* fixed_bit_masks */
959 0x800000007ffc0000ULL,
960 0xfffe000000000000ULL,
966 /* fixed_bit_values */
967 0x0000000009800000ULL,
968 0x0c84000000000000ULL,
974 { "adiffb_u", TILE_OPC_ADIFFB_U, 0x1 /* pipes */, 3 /* num_operands */,
975 TREG_ZERO, /* implicitly_written_register */
986 /* fixed_bit_masks */
987 0x800000007ffc0000ULL,
994 /* fixed_bit_values */
995 0x0000000000100000ULL,
1002 { "adiffb_u.sn", TILE_OPC_ADIFFB_U_SN, 0x1 /* pipes */, 3 /* num_operands */,
1003 TREG_SN, /* implicitly_written_register */
1014 /* fixed_bit_masks */
1015 0x800000007ffc0000ULL,
1022 /* fixed_bit_values */
1023 0x0000000008100000ULL,
1030 { "adiffh", TILE_OPC_ADIFFH, 0x1 /* pipes */, 3 /* num_operands */,
1031 TREG_ZERO, /* implicitly_written_register */
1042 /* fixed_bit_masks */
1043 0x800000007ffc0000ULL,
1050 /* fixed_bit_values */
1051 0x0000000000140000ULL,
1058 { "adiffh.sn", TILE_OPC_ADIFFH_SN, 0x1 /* pipes */, 3 /* num_operands */,
1059 TREG_SN, /* implicitly_written_register */
1070 /* fixed_bit_masks */
1071 0x800000007ffc0000ULL,
1078 /* fixed_bit_values */
1079 0x0000000008140000ULL,
1086 { "and", TILE_OPC_AND, 0xf /* pipes */, 3 /* num_operands */,
1087 TREG_ZERO, /* implicitly_written_register */
1098 /* fixed_bit_masks */
1099 0x800000007ffc0000ULL,
1100 0xfffe000000000000ULL,
1101 0x80000000780c0000ULL,
1102 0xf806000000000000ULL,
1106 /* fixed_bit_values */
1107 0x0000000000180000ULL,
1108 0x0808000000000000ULL,
1109 0x8000000018000000ULL,
1110 0x9800000000000000ULL,
1114 { "and.sn", TILE_OPC_AND_SN, 0x3 /* pipes */, 3 /* num_operands */,
1115 TREG_SN, /* implicitly_written_register */
1126 /* fixed_bit_masks */
1127 0x800000007ffc0000ULL,
1128 0xfffe000000000000ULL,
1134 /* fixed_bit_values */
1135 0x0000000008180000ULL,
1136 0x0c08000000000000ULL,
1142 { "andi", TILE_OPC_ANDI, 0xf /* pipes */, 3 /* num_operands */,
1143 TREG_ZERO, /* implicitly_written_register */
1154 /* fixed_bit_masks */
1155 0x800000007ff00000ULL,
1156 0xfff8000000000000ULL,
1157 0x8000000078000000ULL,
1158 0xf800000000000000ULL,
1162 /* fixed_bit_values */
1163 0x0000000050100000ULL,
1164 0x3020000000000000ULL,
1165 0x8000000050000000ULL,
1166 0xc000000000000000ULL,
1170 { "andi.sn", TILE_OPC_ANDI_SN, 0x3 /* pipes */, 3 /* num_operands */,
1171 TREG_SN, /* implicitly_written_register */
1182 /* fixed_bit_masks */
1183 0x800000007ff00000ULL,
1184 0xfff8000000000000ULL,
1190 /* fixed_bit_values */
1191 0x0000000058100000ULL,
1192 0x3420000000000000ULL,
1198 { "auli", TILE_OPC_AULI, 0x3 /* pipes */, 3 /* num_operands */,
1199 TREG_ZERO, /* implicitly_written_register */
1210 /* fixed_bit_masks */
1211 0x8000000070000000ULL,
1212 0xf800000000000000ULL,
1218 /* fixed_bit_values */
1219 0x0000000030000000ULL,
1220 0x2000000000000000ULL,
1226 { "avgb_u", TILE_OPC_AVGB_U, 0x1 /* pipes */, 3 /* num_operands */,
1227 TREG_ZERO, /* implicitly_written_register */
1238 /* fixed_bit_masks */
1239 0x800000007ffc0000ULL,
1246 /* fixed_bit_values */
1247 0x00000000001c0000ULL,
1254 { "avgb_u.sn", TILE_OPC_AVGB_U_SN, 0x1 /* pipes */, 3 /* num_operands */,
1255 TREG_SN, /* implicitly_written_register */
1266 /* fixed_bit_masks */
1267 0x800000007ffc0000ULL,
1274 /* fixed_bit_values */
1275 0x00000000081c0000ULL,
1282 { "avgh", TILE_OPC_AVGH, 0x1 /* pipes */, 3 /* num_operands */,
1283 TREG_ZERO, /* implicitly_written_register */
1294 /* fixed_bit_masks */
1295 0x800000007ffc0000ULL,
1302 /* fixed_bit_values */
1303 0x0000000000200000ULL,
1310 { "avgh.sn", TILE_OPC_AVGH_SN, 0x1 /* pipes */, 3 /* num_operands */,
1311 TREG_SN, /* implicitly_written_register */
1322 /* fixed_bit_masks */
1323 0x800000007ffc0000ULL,
1330 /* fixed_bit_values */
1331 0x0000000008200000ULL,
1338 { "bbns", TILE_OPC_BBNS, 0x2 /* pipes */, 2 /* num_operands */,
1339 TREG_ZERO, /* implicitly_written_register */
1350 /* fixed_bit_masks */
1352 0xfc00000780000000ULL,
1358 /* fixed_bit_values */
1360 0x2800000700000000ULL,
1366 { "bbns.sn", TILE_OPC_BBNS_SN, 0x2 /* pipes */, 2 /* num_operands */,
1367 TREG_SN, /* implicitly_written_register */
1378 /* fixed_bit_masks */
1380 0xfc00000780000000ULL,
1386 /* fixed_bit_values */
1388 0x2c00000700000000ULL,
1394 { "bbnst", TILE_OPC_BBNST, 0x2 /* pipes */, 2 /* num_operands */,
1395 TREG_ZERO, /* implicitly_written_register */
1406 /* fixed_bit_masks */
1408 0xfc00000780000000ULL,
1414 /* fixed_bit_values */
1416 0x2800000780000000ULL,
1422 { "bbnst.sn", TILE_OPC_BBNST_SN, 0x2 /* pipes */, 2 /* num_operands */,
1423 TREG_SN, /* implicitly_written_register */
1434 /* fixed_bit_masks */
1436 0xfc00000780000000ULL,
1442 /* fixed_bit_values */
1444 0x2c00000780000000ULL,
1450 { "bbs", TILE_OPC_BBS, 0x2 /* pipes */, 2 /* num_operands */,
1451 TREG_ZERO, /* implicitly_written_register */
1462 /* fixed_bit_masks */
1464 0xfc00000780000000ULL,
1470 /* fixed_bit_values */
1472 0x2800000600000000ULL,
1478 { "bbs.sn", TILE_OPC_BBS_SN, 0x2 /* pipes */, 2 /* num_operands */,
1479 TREG_SN, /* implicitly_written_register */
1490 /* fixed_bit_masks */
1492 0xfc00000780000000ULL,
1498 /* fixed_bit_values */
1500 0x2c00000600000000ULL,
1506 { "bbst", TILE_OPC_BBST, 0x2 /* pipes */, 2 /* num_operands */,
1507 TREG_ZERO, /* implicitly_written_register */
1518 /* fixed_bit_masks */
1520 0xfc00000780000000ULL,
1526 /* fixed_bit_values */
1528 0x2800000680000000ULL,
1534 { "bbst.sn", TILE_OPC_BBST_SN, 0x2 /* pipes */, 2 /* num_operands */,
1535 TREG_SN, /* implicitly_written_register */
1546 /* fixed_bit_masks */
1548 0xfc00000780000000ULL,
1554 /* fixed_bit_values */
1556 0x2c00000680000000ULL,
1562 { "bgez", TILE_OPC_BGEZ, 0x2 /* pipes */, 2 /* num_operands */,
1563 TREG_ZERO, /* implicitly_written_register */
1574 /* fixed_bit_masks */
1576 0xfc00000780000000ULL,
1582 /* fixed_bit_values */
1584 0x2800000300000000ULL,
1590 { "bgez.sn", TILE_OPC_BGEZ_SN, 0x2 /* pipes */, 2 /* num_operands */,
1591 TREG_SN, /* implicitly_written_register */
1602 /* fixed_bit_masks */
1604 0xfc00000780000000ULL,
1610 /* fixed_bit_values */
1612 0x2c00000300000000ULL,
1618 { "bgezt", TILE_OPC_BGEZT, 0x2 /* pipes */, 2 /* num_operands */,
1619 TREG_ZERO, /* implicitly_written_register */
1630 /* fixed_bit_masks */
1632 0xfc00000780000000ULL,
1638 /* fixed_bit_values */
1640 0x2800000380000000ULL,
1646 { "bgezt.sn", TILE_OPC_BGEZT_SN, 0x2 /* pipes */, 2 /* num_operands */,
1647 TREG_SN, /* implicitly_written_register */
1658 /* fixed_bit_masks */
1660 0xfc00000780000000ULL,
1666 /* fixed_bit_values */
1668 0x2c00000380000000ULL,
1674 { "bgz", TILE_OPC_BGZ, 0x2 /* pipes */, 2 /* num_operands */,
1675 TREG_ZERO, /* implicitly_written_register */
1686 /* fixed_bit_masks */
1688 0xfc00000780000000ULL,
1694 /* fixed_bit_values */
1696 0x2800000200000000ULL,
1702 { "bgz.sn", TILE_OPC_BGZ_SN, 0x2 /* pipes */, 2 /* num_operands */,
1703 TREG_SN, /* implicitly_written_register */
1714 /* fixed_bit_masks */
1716 0xfc00000780000000ULL,
1722 /* fixed_bit_values */
1724 0x2c00000200000000ULL,
1730 { "bgzt", TILE_OPC_BGZT, 0x2 /* pipes */, 2 /* num_operands */,
1731 TREG_ZERO, /* implicitly_written_register */
1742 /* fixed_bit_masks */
1744 0xfc00000780000000ULL,
1750 /* fixed_bit_values */
1752 0x2800000280000000ULL,
1758 { "bgzt.sn", TILE_OPC_BGZT_SN, 0x2 /* pipes */, 2 /* num_operands */,
1759 TREG_SN, /* implicitly_written_register */
1770 /* fixed_bit_masks */
1772 0xfc00000780000000ULL,
1778 /* fixed_bit_values */
1780 0x2c00000280000000ULL,
1786 { "bitx", TILE_OPC_BITX, 0x5 /* pipes */, 2 /* num_operands */,
1787 TREG_ZERO, /* implicitly_written_register */
1798 /* fixed_bit_masks */
1799 0x800000007ffff000ULL,
1801 0x80000000780ff000ULL,
1806 /* fixed_bit_values */
1807 0x0000000070161000ULL,
1809 0x80000000680a1000ULL,
1814 { "bitx.sn", TILE_OPC_BITX_SN, 0x1 /* pipes */, 2 /* num_operands */,
1815 TREG_SN, /* implicitly_written_register */
1826 /* fixed_bit_masks */
1827 0x800000007ffff000ULL,
1834 /* fixed_bit_values */
1835 0x0000000078161000ULL,
1842 { "blez", TILE_OPC_BLEZ, 0x2 /* pipes */, 2 /* num_operands */,
1843 TREG_ZERO, /* implicitly_written_register */
1854 /* fixed_bit_masks */
1856 0xfc00000780000000ULL,
1862 /* fixed_bit_values */
1864 0x2800000500000000ULL,
1870 { "blez.sn", TILE_OPC_BLEZ_SN, 0x2 /* pipes */, 2 /* num_operands */,
1871 TREG_SN, /* implicitly_written_register */
1882 /* fixed_bit_masks */
1884 0xfc00000780000000ULL,
1890 /* fixed_bit_values */
1892 0x2c00000500000000ULL,
1898 { "blezt", TILE_OPC_BLEZT, 0x2 /* pipes */, 2 /* num_operands */,
1899 TREG_ZERO, /* implicitly_written_register */
1910 /* fixed_bit_masks */
1912 0xfc00000780000000ULL,
1918 /* fixed_bit_values */
1920 0x2800000580000000ULL,
1926 { "blezt.sn", TILE_OPC_BLEZT_SN, 0x2 /* pipes */, 2 /* num_operands */,
1927 TREG_SN, /* implicitly_written_register */
1938 /* fixed_bit_masks */
1940 0xfc00000780000000ULL,
1946 /* fixed_bit_values */
1948 0x2c00000580000000ULL,
1954 { "blz", TILE_OPC_BLZ, 0x2 /* pipes */, 2 /* num_operands */,
1955 TREG_ZERO, /* implicitly_written_register */
1966 /* fixed_bit_masks */
1968 0xfc00000780000000ULL,
1974 /* fixed_bit_values */
1976 0x2800000400000000ULL,
1982 { "blz.sn", TILE_OPC_BLZ_SN, 0x2 /* pipes */, 2 /* num_operands */,
1983 TREG_SN, /* implicitly_written_register */
1994 /* fixed_bit_masks */
1996 0xfc00000780000000ULL,
2002 /* fixed_bit_values */
2004 0x2c00000400000000ULL,
2010 { "blzt", TILE_OPC_BLZT, 0x2 /* pipes */, 2 /* num_operands */,
2011 TREG_ZERO, /* implicitly_written_register */
2022 /* fixed_bit_masks */
2024 0xfc00000780000000ULL,
2030 /* fixed_bit_values */
2032 0x2800000480000000ULL,
2038 { "blzt.sn", TILE_OPC_BLZT_SN, 0x2 /* pipes */, 2 /* num_operands */,
2039 TREG_SN, /* implicitly_written_register */
2050 /* fixed_bit_masks */
2052 0xfc00000780000000ULL,
2058 /* fixed_bit_values */
2060 0x2c00000480000000ULL,
2066 { "bnz", TILE_OPC_BNZ, 0x2 /* pipes */, 2 /* num_operands */,
2067 TREG_ZERO, /* implicitly_written_register */
2078 /* fixed_bit_masks */
2080 0xfc00000780000000ULL,
2086 /* fixed_bit_values */
2088 0x2800000100000000ULL,
2094 { "bnz.sn", TILE_OPC_BNZ_SN, 0x2 /* pipes */, 2 /* num_operands */,
2095 TREG_SN, /* implicitly_written_register */
2106 /* fixed_bit_masks */
2108 0xfc00000780000000ULL,
2114 /* fixed_bit_values */
2116 0x2c00000100000000ULL,
2122 { "bnzt", TILE_OPC_BNZT, 0x2 /* pipes */, 2 /* num_operands */,
2123 TREG_ZERO, /* implicitly_written_register */
2134 /* fixed_bit_masks */
2136 0xfc00000780000000ULL,
2142 /* fixed_bit_values */
2144 0x2800000180000000ULL,
2150 { "bnzt.sn", TILE_OPC_BNZT_SN, 0x2 /* pipes */, 2 /* num_operands */,
2151 TREG_SN, /* implicitly_written_register */
2162 /* fixed_bit_masks */
2164 0xfc00000780000000ULL,
2170 /* fixed_bit_values */
2172 0x2c00000180000000ULL,
2178 { "bytex", TILE_OPC_BYTEX, 0x5 /* pipes */, 2 /* num_operands */,
2179 TREG_ZERO, /* implicitly_written_register */
2190 /* fixed_bit_masks */
2191 0x800000007ffff000ULL,
2193 0x80000000780ff000ULL,
2198 /* fixed_bit_values */
2199 0x0000000070162000ULL,
2201 0x80000000680a2000ULL,
2206 { "bytex.sn", TILE_OPC_BYTEX_SN, 0x1 /* pipes */, 2 /* num_operands */,
2207 TREG_SN, /* implicitly_written_register */
2218 /* fixed_bit_masks */
2219 0x800000007ffff000ULL,
2226 /* fixed_bit_values */
2227 0x0000000078162000ULL,
2234 { "bz", TILE_OPC_BZ, 0x2 /* pipes */, 2 /* num_operands */,
2235 TREG_ZERO, /* implicitly_written_register */
2246 /* fixed_bit_masks */
2248 0xfc00000780000000ULL,
2254 /* fixed_bit_values */
2256 0x2800000000000000ULL,
2262 { "bz.sn", TILE_OPC_BZ_SN, 0x2 /* pipes */, 2 /* num_operands */,
2263 TREG_SN, /* implicitly_written_register */
2274 /* fixed_bit_masks */
2276 0xfc00000780000000ULL,
2282 /* fixed_bit_values */
2284 0x2c00000000000000ULL,
2290 { "bzt", TILE_OPC_BZT, 0x2 /* pipes */, 2 /* num_operands */,
2291 TREG_ZERO, /* implicitly_written_register */
2302 /* fixed_bit_masks */
2304 0xfc00000780000000ULL,
2310 /* fixed_bit_values */
2312 0x2800000080000000ULL,
2318 { "bzt.sn", TILE_OPC_BZT_SN, 0x2 /* pipes */, 2 /* num_operands */,
2319 TREG_SN, /* implicitly_written_register */
2330 /* fixed_bit_masks */
2332 0xfc00000780000000ULL,
2338 /* fixed_bit_values */
2340 0x2c00000080000000ULL,
2346 { "clz", TILE_OPC_CLZ, 0x5 /* pipes */, 2 /* num_operands */,
2347 TREG_ZERO, /* implicitly_written_register */
2358 /* fixed_bit_masks */
2359 0x800000007ffff000ULL,
2361 0x80000000780ff000ULL,
2366 /* fixed_bit_values */
2367 0x0000000070163000ULL,
2369 0x80000000680a3000ULL,
2374 { "clz.sn", TILE_OPC_CLZ_SN, 0x1 /* pipes */, 2 /* num_operands */,
2375 TREG_SN, /* implicitly_written_register */
2386 /* fixed_bit_masks */
2387 0x800000007ffff000ULL,
2394 /* fixed_bit_values */
2395 0x0000000078163000ULL,
2402 { "crc32_32", TILE_OPC_CRC32_32, 0x1 /* pipes */, 3 /* num_operands */,
2403 TREG_ZERO, /* implicitly_written_register */
2414 /* fixed_bit_masks */
2415 0x800000007ffc0000ULL,
2422 /* fixed_bit_values */
2423 0x0000000000240000ULL,
2430 { "crc32_32.sn", TILE_OPC_CRC32_32_SN, 0x1 /* pipes */, 3 /* num_operands */,
2431 TREG_SN, /* implicitly_written_register */
2442 /* fixed_bit_masks */
2443 0x800000007ffc0000ULL,
2450 /* fixed_bit_values */
2451 0x0000000008240000ULL,
2458 { "crc32_8", TILE_OPC_CRC32_8, 0x1 /* pipes */, 3 /* num_operands */,
2459 TREG_ZERO, /* implicitly_written_register */
2470 /* fixed_bit_masks */
2471 0x800000007ffc0000ULL,
2478 /* fixed_bit_values */
2479 0x0000000000280000ULL,
2486 { "crc32_8.sn", TILE_OPC_CRC32_8_SN, 0x1 /* pipes */, 3 /* num_operands */,
2487 TREG_SN, /* implicitly_written_register */
2498 /* fixed_bit_masks */
2499 0x800000007ffc0000ULL,
2506 /* fixed_bit_values */
2507 0x0000000008280000ULL,
2514 { "ctz", TILE_OPC_CTZ, 0x5 /* pipes */, 2 /* num_operands */,
2515 TREG_ZERO, /* implicitly_written_register */
2526 /* fixed_bit_masks */
2527 0x800000007ffff000ULL,
2529 0x80000000780ff000ULL,
2534 /* fixed_bit_values */
2535 0x0000000070164000ULL,
2537 0x80000000680a4000ULL,
2542 { "ctz.sn", TILE_OPC_CTZ_SN, 0x1 /* pipes */, 2 /* num_operands */,
2543 TREG_SN, /* implicitly_written_register */
2554 /* fixed_bit_masks */
2555 0x800000007ffff000ULL,
2562 /* fixed_bit_values */
2563 0x0000000078164000ULL,
2570 { "drain", TILE_OPC_DRAIN, 0x2 /* pipes */, 0 /* num_operands */,
2571 TREG_ZERO, /* implicitly_written_register */
2582 /* fixed_bit_masks */
2584 0xfbfff80000000000ULL,
2590 /* fixed_bit_values */
2592 0x400b080000000000ULL,
2598 { "dtlbpr", TILE_OPC_DTLBPR, 0x2 /* pipes */, 1 /* num_operands */,
2599 TREG_ZERO, /* implicitly_written_register */
2610 /* fixed_bit_masks */
2612 0xfbfff80000000000ULL,
2618 /* fixed_bit_values */
2620 0x400b100000000000ULL,
2626 { "dword_align", TILE_OPC_DWORD_ALIGN, 0x1 /* pipes */, 3 /* num_operands */,
2627 TREG_ZERO, /* implicitly_written_register */
2638 /* fixed_bit_masks */
2639 0x800000007ffc0000ULL,
2646 /* fixed_bit_values */
2647 0x00000000017c0000ULL,
2654 { "dword_align.sn", TILE_OPC_DWORD_ALIGN_SN, 0x1 /* pipes */, 3 /* num_operands */,
2655 TREG_SN, /* implicitly_written_register */
2666 /* fixed_bit_masks */
2667 0x800000007ffc0000ULL,
2674 /* fixed_bit_values */
2675 0x00000000097c0000ULL,
2682 { "finv", TILE_OPC_FINV, 0x2 /* pipes */, 1 /* num_operands */,
2683 TREG_ZERO, /* implicitly_written_register */
2694 /* fixed_bit_masks */
2696 0xfbfff80000000000ULL,
2702 /* fixed_bit_values */
2704 0x400b180000000000ULL,
2710 { "flush", TILE_OPC_FLUSH, 0x2 /* pipes */, 1 /* num_operands */,
2711 TREG_ZERO, /* implicitly_written_register */
2722 /* fixed_bit_masks */
2724 0xfbfff80000000000ULL,
2730 /* fixed_bit_values */
2732 0x400b200000000000ULL,
2738 { "fnop", TILE_OPC_FNOP, 0xf /* pipes */, 0 /* num_operands */,
2739 TREG_ZERO, /* implicitly_written_register */
2750 /* fixed_bit_masks */
2751 0x8000000077fff000ULL,
2752 0xfbfff80000000000ULL,
2753 0x80000000780ff000ULL,
2754 0xf807f80000000000ULL,
2758 /* fixed_bit_values */
2759 0x0000000070165000ULL,
2760 0x400b280000000000ULL,
2761 0x80000000680a5000ULL,
2762 0xd805080000000000ULL,
2766 { "icoh", TILE_OPC_ICOH, 0x2 /* pipes */, 1 /* num_operands */,
2767 TREG_ZERO, /* implicitly_written_register */
2778 /* fixed_bit_masks */
2780 0xfbfff80000000000ULL,
2786 /* fixed_bit_values */
2788 0x400b300000000000ULL,
2794 { "ill", TILE_OPC_ILL, 0xa /* pipes */, 0 /* num_operands */,
2795 TREG_ZERO, /* implicitly_written_register */
2806 /* fixed_bit_masks */
2808 0xfbfff80000000000ULL,
2810 0xf807f80000000000ULL,
2814 /* fixed_bit_values */
2816 0x400b380000000000ULL,
2818 0xd805100000000000ULL,
2822 { "inthb", TILE_OPC_INTHB, 0x3 /* pipes */, 3 /* num_operands */,
2823 TREG_ZERO, /* implicitly_written_register */
2834 /* fixed_bit_masks */
2835 0x800000007ffc0000ULL,
2836 0xfffe000000000000ULL,
2842 /* fixed_bit_values */
2843 0x00000000002c0000ULL,
2844 0x080a000000000000ULL,
2850 { "inthb.sn", TILE_OPC_INTHB_SN, 0x3 /* pipes */, 3 /* num_operands */,
2851 TREG_SN, /* implicitly_written_register */
2862 /* fixed_bit_masks */
2863 0x800000007ffc0000ULL,
2864 0xfffe000000000000ULL,
2870 /* fixed_bit_values */
2871 0x00000000082c0000ULL,
2872 0x0c0a000000000000ULL,
2878 { "inthh", TILE_OPC_INTHH, 0x3 /* pipes */, 3 /* num_operands */,
2879 TREG_ZERO, /* implicitly_written_register */
2890 /* fixed_bit_masks */
2891 0x800000007ffc0000ULL,
2892 0xfffe000000000000ULL,
2898 /* fixed_bit_values */
2899 0x0000000000300000ULL,
2900 0x080c000000000000ULL,
2906 { "inthh.sn", TILE_OPC_INTHH_SN, 0x3 /* pipes */, 3 /* num_operands */,
2907 TREG_SN, /* implicitly_written_register */
2918 /* fixed_bit_masks */
2919 0x800000007ffc0000ULL,
2920 0xfffe000000000000ULL,
2926 /* fixed_bit_values */
2927 0x0000000008300000ULL,
2928 0x0c0c000000000000ULL,
2934 { "intlb", TILE_OPC_INTLB, 0x3 /* pipes */, 3 /* num_operands */,
2935 TREG_ZERO, /* implicitly_written_register */
2946 /* fixed_bit_masks */
2947 0x800000007ffc0000ULL,
2948 0xfffe000000000000ULL,
2954 /* fixed_bit_values */
2955 0x0000000000340000ULL,
2956 0x080e000000000000ULL,
2962 { "intlb.sn", TILE_OPC_INTLB_SN, 0x3 /* pipes */, 3 /* num_operands */,
2963 TREG_SN, /* implicitly_written_register */
2974 /* fixed_bit_masks */
2975 0x800000007ffc0000ULL,
2976 0xfffe000000000000ULL,
2982 /* fixed_bit_values */
2983 0x0000000008340000ULL,
2984 0x0c0e000000000000ULL,
2990 { "intlh", TILE_OPC_INTLH, 0x3 /* pipes */, 3 /* num_operands */,
2991 TREG_ZERO, /* implicitly_written_register */
3002 /* fixed_bit_masks */
3003 0x800000007ffc0000ULL,
3004 0xfffe000000000000ULL,
3010 /* fixed_bit_values */
3011 0x0000000000380000ULL,
3012 0x0810000000000000ULL,
3018 { "intlh.sn", TILE_OPC_INTLH_SN, 0x3 /* pipes */, 3 /* num_operands */,
3019 TREG_SN, /* implicitly_written_register */
3030 /* fixed_bit_masks */
3031 0x800000007ffc0000ULL,
3032 0xfffe000000000000ULL,
3038 /* fixed_bit_values */
3039 0x0000000008380000ULL,
3040 0x0c10000000000000ULL,
3046 { "inv", TILE_OPC_INV, 0x2 /* pipes */, 1 /* num_operands */,
3047 TREG_ZERO, /* implicitly_written_register */
3058 /* fixed_bit_masks */
3060 0xfbfff80000000000ULL,
3066 /* fixed_bit_values */
3068 0x400b400000000000ULL,
3074 { "iret", TILE_OPC_IRET, 0x2 /* pipes */, 0 /* num_operands */,
3075 TREG_ZERO, /* implicitly_written_register */
3086 /* fixed_bit_masks */
3088 0xfbfff80000000000ULL,
3094 /* fixed_bit_values */
3096 0x400b480000000000ULL,
3102 { "jalb", TILE_OPC_JALB, 0x2 /* pipes */, 1 /* num_operands */,
3103 TREG_LR, /* implicitly_written_register */
3114 /* fixed_bit_masks */
3116 0xf800000000000000ULL,
3122 /* fixed_bit_values */
3124 0x6800000000000000ULL,
3130 { "jalf", TILE_OPC_JALF, 0x2 /* pipes */, 1 /* num_operands */,
3131 TREG_LR, /* implicitly_written_register */
3142 /* fixed_bit_masks */
3144 0xf800000000000000ULL,
3150 /* fixed_bit_values */
3152 0x6000000000000000ULL,
3158 { "jalr", TILE_OPC_JALR, 0x2 /* pipes */, 1 /* num_operands */,
3159 TREG_LR, /* implicitly_written_register */
3170 /* fixed_bit_masks */
3172 0xfbfe000000000000ULL,
3178 /* fixed_bit_values */
3180 0x0814000000000000ULL,
3186 { "jalrp", TILE_OPC_JALRP, 0x2 /* pipes */, 1 /* num_operands */,
3187 TREG_LR, /* implicitly_written_register */
3198 /* fixed_bit_masks */
3200 0xfbfe000000000000ULL,
3206 /* fixed_bit_values */
3208 0x0812000000000000ULL,
3214 { "jb", TILE_OPC_JB, 0x2 /* pipes */, 1 /* num_operands */,
3215 TREG_ZERO, /* implicitly_written_register */
3226 /* fixed_bit_masks */
3228 0xf800000000000000ULL,
3234 /* fixed_bit_values */
3236 0x5800000000000000ULL,
3242 { "jf", TILE_OPC_JF, 0x2 /* pipes */, 1 /* num_operands */,
3243 TREG_ZERO, /* implicitly_written_register */
3254 /* fixed_bit_masks */
3256 0xf800000000000000ULL,
3262 /* fixed_bit_values */
3264 0x5000000000000000ULL,
3270 { "jr", TILE_OPC_JR, 0x2 /* pipes */, 1 /* num_operands */,
3271 TREG_ZERO, /* implicitly_written_register */
3282 /* fixed_bit_masks */
3284 0xfbfe000000000000ULL,
3290 /* fixed_bit_values */
3292 0x0818000000000000ULL,
3298 { "jrp", TILE_OPC_JRP, 0x2 /* pipes */, 1 /* num_operands */,
3299 TREG_ZERO, /* implicitly_written_register */
3310 /* fixed_bit_masks */
3312 0xfbfe000000000000ULL,
3318 /* fixed_bit_values */
3320 0x0816000000000000ULL,
3326 { "lb", TILE_OPC_LB, 0x12 /* pipes */, 2 /* num_operands */,
3327 TREG_ZERO, /* implicitly_written_register */
3338 /* fixed_bit_masks */
3340 0xfffff80000000000ULL,
3343 0x8700000000000000ULL
3346 /* fixed_bit_values */
3348 0x400b500000000000ULL,
3351 0x8000000000000000ULL
3354 { "lb.sn", TILE_OPC_LB_SN, 0x2 /* pipes */, 2 /* num_operands */,
3355 TREG_SN, /* implicitly_written_register */
3366 /* fixed_bit_masks */
3368 0xfffff80000000000ULL,
3374 /* fixed_bit_values */
3376 0x440b500000000000ULL,
3382 { "lb_u", TILE_OPC_LB_U, 0x12 /* pipes */, 2 /* num_operands */,
3383 TREG_ZERO, /* implicitly_written_register */
3394 /* fixed_bit_masks */
3396 0xfffff80000000000ULL,
3399 0x8700000000000000ULL
3402 /* fixed_bit_values */
3404 0x400b580000000000ULL,
3407 0x8100000000000000ULL
3410 { "lb_u.sn", TILE_OPC_LB_U_SN, 0x2 /* pipes */, 2 /* num_operands */,
3411 TREG_SN, /* implicitly_written_register */
3422 /* fixed_bit_masks */
3424 0xfffff80000000000ULL,
3430 /* fixed_bit_values */
3432 0x440b580000000000ULL,
3438 { "lbadd", TILE_OPC_LBADD, 0x2 /* pipes */, 3 /* num_operands */,
3439 TREG_ZERO, /* implicitly_written_register */
3450 /* fixed_bit_masks */
3452 0xfff8000000000000ULL,
3458 /* fixed_bit_values */
3460 0x30b0000000000000ULL,
3466 { "lbadd.sn", TILE_OPC_LBADD_SN, 0x2 /* pipes */, 3 /* num_operands */,
3467 TREG_SN, /* implicitly_written_register */
3478 /* fixed_bit_masks */
3480 0xfff8000000000000ULL,
3486 /* fixed_bit_values */
3488 0x34b0000000000000ULL,
3494 { "lbadd_u", TILE_OPC_LBADD_U, 0x2 /* pipes */, 3 /* num_operands */,
3495 TREG_ZERO, /* implicitly_written_register */
3506 /* fixed_bit_masks */
3508 0xfff8000000000000ULL,
3514 /* fixed_bit_values */
3516 0x30b8000000000000ULL,
3522 { "lbadd_u.sn", TILE_OPC_LBADD_U_SN, 0x2 /* pipes */, 3 /* num_operands */,
3523 TREG_SN, /* implicitly_written_register */
3534 /* fixed_bit_masks */
3536 0xfff8000000000000ULL,
3542 /* fixed_bit_values */
3544 0x34b8000000000000ULL,
3550 { "lh", TILE_OPC_LH, 0x12 /* pipes */, 2 /* num_operands */,
3551 TREG_ZERO, /* implicitly_written_register */
3562 /* fixed_bit_masks */
3564 0xfffff80000000000ULL,
3567 0x8700000000000000ULL
3570 /* fixed_bit_values */
3572 0x400b600000000000ULL,
3575 0x8200000000000000ULL
3578 { "lh.sn", TILE_OPC_LH_SN, 0x2 /* pipes */, 2 /* num_operands */,
3579 TREG_SN, /* implicitly_written_register */
3590 /* fixed_bit_masks */
3592 0xfffff80000000000ULL,
3598 /* fixed_bit_values */
3600 0x440b600000000000ULL,
3606 { "lh_u", TILE_OPC_LH_U, 0x12 /* pipes */, 2 /* num_operands */,
3607 TREG_ZERO, /* implicitly_written_register */
3618 /* fixed_bit_masks */
3620 0xfffff80000000000ULL,
3623 0x8700000000000000ULL
3626 /* fixed_bit_values */
3628 0x400b680000000000ULL,
3631 0x8300000000000000ULL
3634 { "lh_u.sn", TILE_OPC_LH_U_SN, 0x2 /* pipes */, 2 /* num_operands */,
3635 TREG_SN, /* implicitly_written_register */
3646 /* fixed_bit_masks */
3648 0xfffff80000000000ULL,
3654 /* fixed_bit_values */
3656 0x440b680000000000ULL,
3662 { "lhadd", TILE_OPC_LHADD, 0x2 /* pipes */, 3 /* num_operands */,
3663 TREG_ZERO, /* implicitly_written_register */
3674 /* fixed_bit_masks */
3676 0xfff8000000000000ULL,
3682 /* fixed_bit_values */
3684 0x30c0000000000000ULL,
3690 { "lhadd.sn", TILE_OPC_LHADD_SN, 0x2 /* pipes */, 3 /* num_operands */,
3691 TREG_SN, /* implicitly_written_register */
3702 /* fixed_bit_masks */
3704 0xfff8000000000000ULL,
3710 /* fixed_bit_values */
3712 0x34c0000000000000ULL,
3718 { "lhadd_u", TILE_OPC_LHADD_U, 0x2 /* pipes */, 3 /* num_operands */,
3719 TREG_ZERO, /* implicitly_written_register */
3730 /* fixed_bit_masks */
3732 0xfff8000000000000ULL,
3738 /* fixed_bit_values */
3740 0x30c8000000000000ULL,
3746 { "lhadd_u.sn", TILE_OPC_LHADD_U_SN, 0x2 /* pipes */, 3 /* num_operands */,
3747 TREG_SN, /* implicitly_written_register */
3758 /* fixed_bit_masks */
3760 0xfff8000000000000ULL,
3766 /* fixed_bit_values */
3768 0x34c8000000000000ULL,
3774 { "lnk", TILE_OPC_LNK, 0x2 /* pipes */, 1 /* num_operands */,
3775 TREG_ZERO, /* implicitly_written_register */
3786 /* fixed_bit_masks */
3788 0xfffe000000000000ULL,
3794 /* fixed_bit_values */
3796 0x081a000000000000ULL,
3802 { "lnk.sn", TILE_OPC_LNK_SN, 0x2 /* pipes */, 1 /* num_operands */,
3803 TREG_SN, /* implicitly_written_register */
3814 /* fixed_bit_masks */
3816 0xfffe000000000000ULL,
3822 /* fixed_bit_values */
3824 0x0c1a000000000000ULL,
3830 { "lw", TILE_OPC_LW, 0x12 /* pipes */, 2 /* num_operands */,
3831 TREG_ZERO, /* implicitly_written_register */
3842 /* fixed_bit_masks */
3844 0xfffff80000000000ULL,
3847 0x8700000000000000ULL
3850 /* fixed_bit_values */
3852 0x400b700000000000ULL,
3855 0x8400000000000000ULL
3858 { "lw.sn", TILE_OPC_LW_SN, 0x2 /* pipes */, 2 /* num_operands */,
3859 TREG_SN, /* implicitly_written_register */
3870 /* fixed_bit_masks */
3872 0xfffff80000000000ULL,
3878 /* fixed_bit_values */
3880 0x440b700000000000ULL,
3886 { "lw_na", TILE_OPC_LW_NA, 0x2 /* pipes */, 2 /* num_operands */,
3887 TREG_ZERO, /* implicitly_written_register */
3898 /* fixed_bit_masks */
3900 0xfffff80000000000ULL,
3906 /* fixed_bit_values */
3908 0x400bc00000000000ULL,
3914 { "lw_na.sn", TILE_OPC_LW_NA_SN, 0x2 /* pipes */, 2 /* num_operands */,
3915 TREG_SN, /* implicitly_written_register */
3926 /* fixed_bit_masks */
3928 0xfffff80000000000ULL,
3934 /* fixed_bit_values */
3936 0x440bc00000000000ULL,
3942 { "lwadd", TILE_OPC_LWADD, 0x2 /* pipes */, 3 /* num_operands */,
3943 TREG_ZERO, /* implicitly_written_register */
3954 /* fixed_bit_masks */
3956 0xfff8000000000000ULL,
3962 /* fixed_bit_values */
3964 0x30d0000000000000ULL,
3970 { "lwadd.sn", TILE_OPC_LWADD_SN, 0x2 /* pipes */, 3 /* num_operands */,
3971 TREG_SN, /* implicitly_written_register */
3982 /* fixed_bit_masks */
3984 0xfff8000000000000ULL,
3990 /* fixed_bit_values */
3992 0x34d0000000000000ULL,
3998 { "lwadd_na", TILE_OPC_LWADD_NA, 0x2 /* pipes */, 3 /* num_operands */,
3999 TREG_ZERO, /* implicitly_written_register */
4010 /* fixed_bit_masks */
4012 0xfff8000000000000ULL,
4018 /* fixed_bit_values */
4020 0x30d8000000000000ULL,
4026 { "lwadd_na.sn", TILE_OPC_LWADD_NA_SN, 0x2 /* pipes */, 3 /* num_operands */,
4027 TREG_SN, /* implicitly_written_register */
4038 /* fixed_bit_masks */
4040 0xfff8000000000000ULL,
4046 /* fixed_bit_values */
4048 0x34d8000000000000ULL,
4054 { "maxb_u", TILE_OPC_MAXB_U, 0x3 /* pipes */, 3 /* num_operands */,
4055 TREG_ZERO, /* implicitly_written_register */
4066 /* fixed_bit_masks */
4067 0x800000007ffc0000ULL,
4068 0xfffe000000000000ULL,
4074 /* fixed_bit_values */
4075 0x00000000003c0000ULL,
4076 0x081c000000000000ULL,
4082 { "maxb_u.sn", TILE_OPC_MAXB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
4083 TREG_SN, /* implicitly_written_register */
4094 /* fixed_bit_masks */
4095 0x800000007ffc0000ULL,
4096 0xfffe000000000000ULL,
4102 /* fixed_bit_values */
4103 0x00000000083c0000ULL,
4104 0x0c1c000000000000ULL,
4110 { "maxh", TILE_OPC_MAXH, 0x3 /* pipes */, 3 /* num_operands */,
4111 TREG_ZERO, /* implicitly_written_register */
4122 /* fixed_bit_masks */
4123 0x800000007ffc0000ULL,
4124 0xfffe000000000000ULL,
4130 /* fixed_bit_values */
4131 0x0000000000400000ULL,
4132 0x081e000000000000ULL,
4138 { "maxh.sn", TILE_OPC_MAXH_SN, 0x3 /* pipes */, 3 /* num_operands */,
4139 TREG_SN, /* implicitly_written_register */
4150 /* fixed_bit_masks */
4151 0x800000007ffc0000ULL,
4152 0xfffe000000000000ULL,
4158 /* fixed_bit_values */
4159 0x0000000008400000ULL,
4160 0x0c1e000000000000ULL,
4166 { "maxib_u", TILE_OPC_MAXIB_U, 0x3 /* pipes */, 3 /* num_operands */,
4167 TREG_ZERO, /* implicitly_written_register */
4178 /* fixed_bit_masks */
4179 0x800000007ff00000ULL,
4180 0xfff8000000000000ULL,
4186 /* fixed_bit_values */
4187 0x0000000040400000ULL,
4188 0x3028000000000000ULL,
4194 { "maxib_u.sn", TILE_OPC_MAXIB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
4195 TREG_SN, /* implicitly_written_register */
4206 /* fixed_bit_masks */
4207 0x800000007ff00000ULL,
4208 0xfff8000000000000ULL,
4214 /* fixed_bit_values */
4215 0x0000000048400000ULL,
4216 0x3428000000000000ULL,
4222 { "maxih", TILE_OPC_MAXIH, 0x3 /* pipes */, 3 /* num_operands */,
4223 TREG_ZERO, /* implicitly_written_register */
4234 /* fixed_bit_masks */
4235 0x800000007ff00000ULL,
4236 0xfff8000000000000ULL,
4242 /* fixed_bit_values */
4243 0x0000000040500000ULL,
4244 0x3030000000000000ULL,
4250 { "maxih.sn", TILE_OPC_MAXIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
4251 TREG_SN, /* implicitly_written_register */
4262 /* fixed_bit_masks */
4263 0x800000007ff00000ULL,
4264 0xfff8000000000000ULL,
4270 /* fixed_bit_values */
4271 0x0000000048500000ULL,
4272 0x3430000000000000ULL,
4278 { "mf", TILE_OPC_MF, 0x2 /* pipes */, 0 /* num_operands */,
4279 TREG_ZERO, /* implicitly_written_register */
4290 /* fixed_bit_masks */
4292 0xfbfff80000000000ULL,
4298 /* fixed_bit_values */
4300 0x400b780000000000ULL,
4306 { "mfspr", TILE_OPC_MFSPR, 0x2 /* pipes */, 2 /* num_operands */,
4307 TREG_ZERO, /* implicitly_written_register */
4318 /* fixed_bit_masks */
4320 0xfbf8000000000000ULL,
4326 /* fixed_bit_values */
4328 0x3038000000000000ULL,
4334 { "minb_u", TILE_OPC_MINB_U, 0x3 /* pipes */, 3 /* num_operands */,
4335 TREG_ZERO, /* implicitly_written_register */
4346 /* fixed_bit_masks */
4347 0x800000007ffc0000ULL,
4348 0xfffe000000000000ULL,
4354 /* fixed_bit_values */
4355 0x0000000000440000ULL,
4356 0x0820000000000000ULL,
4362 { "minb_u.sn", TILE_OPC_MINB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
4363 TREG_SN, /* implicitly_written_register */
4374 /* fixed_bit_masks */
4375 0x800000007ffc0000ULL,
4376 0xfffe000000000000ULL,
4382 /* fixed_bit_values */
4383 0x0000000008440000ULL,
4384 0x0c20000000000000ULL,
4390 { "minh", TILE_OPC_MINH, 0x3 /* pipes */, 3 /* num_operands */,
4391 TREG_ZERO, /* implicitly_written_register */
4402 /* fixed_bit_masks */
4403 0x800000007ffc0000ULL,
4404 0xfffe000000000000ULL,
4410 /* fixed_bit_values */
4411 0x0000000000480000ULL,
4412 0x0822000000000000ULL,
4418 { "minh.sn", TILE_OPC_MINH_SN, 0x3 /* pipes */, 3 /* num_operands */,
4419 TREG_SN, /* implicitly_written_register */
4430 /* fixed_bit_masks */
4431 0x800000007ffc0000ULL,
4432 0xfffe000000000000ULL,
4438 /* fixed_bit_values */
4439 0x0000000008480000ULL,
4440 0x0c22000000000000ULL,
4446 { "minib_u", TILE_OPC_MINIB_U, 0x3 /* pipes */, 3 /* num_operands */,
4447 TREG_ZERO, /* implicitly_written_register */
4458 /* fixed_bit_masks */
4459 0x800000007ff00000ULL,
4460 0xfff8000000000000ULL,
4466 /* fixed_bit_values */
4467 0x0000000040600000ULL,
4468 0x3040000000000000ULL,
4474 { "minib_u.sn", TILE_OPC_MINIB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
4475 TREG_SN, /* implicitly_written_register */
4486 /* fixed_bit_masks */
4487 0x800000007ff00000ULL,
4488 0xfff8000000000000ULL,
4494 /* fixed_bit_values */
4495 0x0000000048600000ULL,
4496 0x3440000000000000ULL,
4502 { "minih", TILE_OPC_MINIH, 0x3 /* pipes */, 3 /* num_operands */,
4503 TREG_ZERO, /* implicitly_written_register */
4514 /* fixed_bit_masks */
4515 0x800000007ff00000ULL,
4516 0xfff8000000000000ULL,
4522 /* fixed_bit_values */
4523 0x0000000040700000ULL,
4524 0x3048000000000000ULL,
4530 { "minih.sn", TILE_OPC_MINIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
4531 TREG_SN, /* implicitly_written_register */
4542 /* fixed_bit_masks */
4543 0x800000007ff00000ULL,
4544 0xfff8000000000000ULL,
4550 /* fixed_bit_values */
4551 0x0000000048700000ULL,
4552 0x3448000000000000ULL,
4558 { "mm", TILE_OPC_MM, 0x3 /* pipes */, 5 /* num_operands */,
4559 TREG_ZERO, /* implicitly_written_register */
4563 { 7, 8, 16, 26, 27 },
4564 { 9, 10, 17, 28, 29 },
4570 /* fixed_bit_masks */
4571 0x8000000070000000ULL,
4572 0xf800000000000000ULL,
4578 /* fixed_bit_values */
4579 0x0000000060000000ULL,
4580 0x3800000000000000ULL,
4586 { "mnz", TILE_OPC_MNZ, 0xf /* pipes */, 3 /* num_operands */,
4587 TREG_ZERO, /* implicitly_written_register */
4598 /* fixed_bit_masks */
4599 0x800000007ffc0000ULL,
4600 0xfffe000000000000ULL,
4601 0x80000000780c0000ULL,
4602 0xf806000000000000ULL,
4606 /* fixed_bit_values */
4607 0x0000000000540000ULL,
4608 0x0828000000000000ULL,
4609 0x8000000010000000ULL,
4610 0x9002000000000000ULL,
4614 { "mnz.sn", TILE_OPC_MNZ_SN, 0x3 /* pipes */, 3 /* num_operands */,
4615 TREG_SN, /* implicitly_written_register */
4626 /* fixed_bit_masks */
4627 0x800000007ffc0000ULL,
4628 0xfffe000000000000ULL,
4634 /* fixed_bit_values */
4635 0x0000000008540000ULL,
4636 0x0c28000000000000ULL,
4642 { "mnzb", TILE_OPC_MNZB, 0x3 /* pipes */, 3 /* num_operands */,
4643 TREG_ZERO, /* implicitly_written_register */
4654 /* fixed_bit_masks */
4655 0x800000007ffc0000ULL,
4656 0xfffe000000000000ULL,
4662 /* fixed_bit_values */
4663 0x00000000004c0000ULL,
4664 0x0824000000000000ULL,
4670 { "mnzb.sn", TILE_OPC_MNZB_SN, 0x3 /* pipes */, 3 /* num_operands */,
4671 TREG_SN, /* implicitly_written_register */
4682 /* fixed_bit_masks */
4683 0x800000007ffc0000ULL,
4684 0xfffe000000000000ULL,
4690 /* fixed_bit_values */
4691 0x00000000084c0000ULL,
4692 0x0c24000000000000ULL,
4698 { "mnzh", TILE_OPC_MNZH, 0x3 /* pipes */, 3 /* num_operands */,
4699 TREG_ZERO, /* implicitly_written_register */
4710 /* fixed_bit_masks */
4711 0x800000007ffc0000ULL,
4712 0xfffe000000000000ULL,
4718 /* fixed_bit_values */
4719 0x0000000000500000ULL,
4720 0x0826000000000000ULL,
4726 { "mnzh.sn", TILE_OPC_MNZH_SN, 0x3 /* pipes */, 3 /* num_operands */,
4727 TREG_SN, /* implicitly_written_register */
4738 /* fixed_bit_masks */
4739 0x800000007ffc0000ULL,
4740 0xfffe000000000000ULL,
4746 /* fixed_bit_values */
4747 0x0000000008500000ULL,
4748 0x0c26000000000000ULL,
4754 { "mtspr", TILE_OPC_MTSPR, 0x2 /* pipes */, 2 /* num_operands */,
4755 TREG_ZERO, /* implicitly_written_register */
4766 /* fixed_bit_masks */
4768 0xfbf8000000000000ULL,
4774 /* fixed_bit_values */
4776 0x3050000000000000ULL,
4782 { "mulhh_ss", TILE_OPC_MULHH_SS, 0x5 /* pipes */, 3 /* num_operands */,
4783 TREG_ZERO, /* implicitly_written_register */
4794 /* fixed_bit_masks */
4795 0x800000007ffc0000ULL,
4797 0x80000000780c0000ULL,
4802 /* fixed_bit_values */
4803 0x0000000000680000ULL,
4805 0x8000000038000000ULL,
4810 { "mulhh_ss.sn", TILE_OPC_MULHH_SS_SN, 0x1 /* pipes */, 3 /* num_operands */,
4811 TREG_SN, /* implicitly_written_register */
4822 /* fixed_bit_masks */
4823 0x800000007ffc0000ULL,
4830 /* fixed_bit_values */
4831 0x0000000008680000ULL,
4838 { "mulhh_su", TILE_OPC_MULHH_SU, 0x1 /* pipes */, 3 /* num_operands */,
4839 TREG_ZERO, /* implicitly_written_register */
4850 /* fixed_bit_masks */
4851 0x800000007ffc0000ULL,
4858 /* fixed_bit_values */
4859 0x00000000006c0000ULL,
4866 { "mulhh_su.sn", TILE_OPC_MULHH_SU_SN, 0x1 /* pipes */, 3 /* num_operands */,
4867 TREG_SN, /* implicitly_written_register */
4878 /* fixed_bit_masks */
4879 0x800000007ffc0000ULL,
4886 /* fixed_bit_values */
4887 0x00000000086c0000ULL,
4894 { "mulhh_uu", TILE_OPC_MULHH_UU, 0x5 /* pipes */, 3 /* num_operands */,
4895 TREG_ZERO, /* implicitly_written_register */
4906 /* fixed_bit_masks */
4907 0x800000007ffc0000ULL,
4909 0x80000000780c0000ULL,
4914 /* fixed_bit_values */
4915 0x0000000000700000ULL,
4917 0x8000000038040000ULL,
4922 { "mulhh_uu.sn", TILE_OPC_MULHH_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
4923 TREG_SN, /* implicitly_written_register */
4934 /* fixed_bit_masks */
4935 0x800000007ffc0000ULL,
4942 /* fixed_bit_values */
4943 0x0000000008700000ULL,
4950 { "mulhha_ss", TILE_OPC_MULHHA_SS, 0x5 /* pipes */, 3 /* num_operands */,
4951 TREG_ZERO, /* implicitly_written_register */
4962 /* fixed_bit_masks */
4963 0x800000007ffc0000ULL,
4965 0x80000000780c0000ULL,
4970 /* fixed_bit_values */
4971 0x0000000000580000ULL,
4973 0x8000000040000000ULL,
4978 { "mulhha_ss.sn", TILE_OPC_MULHHA_SS_SN, 0x1 /* pipes */, 3 /* num_operands */,
4979 TREG_SN, /* implicitly_written_register */
4990 /* fixed_bit_masks */
4991 0x800000007ffc0000ULL,
4998 /* fixed_bit_values */
4999 0x0000000008580000ULL,
5006 { "mulhha_su", TILE_OPC_MULHHA_SU, 0x1 /* pipes */, 3 /* num_operands */,
5007 TREG_ZERO, /* implicitly_written_register */
5018 /* fixed_bit_masks */
5019 0x800000007ffc0000ULL,
5026 /* fixed_bit_values */
5027 0x00000000005c0000ULL,
5034 { "mulhha_su.sn", TILE_OPC_MULHHA_SU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5035 TREG_SN, /* implicitly_written_register */
5046 /* fixed_bit_masks */
5047 0x800000007ffc0000ULL,
5054 /* fixed_bit_values */
5055 0x00000000085c0000ULL,
5062 { "mulhha_uu", TILE_OPC_MULHHA_UU, 0x5 /* pipes */, 3 /* num_operands */,
5063 TREG_ZERO, /* implicitly_written_register */
5074 /* fixed_bit_masks */
5075 0x800000007ffc0000ULL,
5077 0x80000000780c0000ULL,
5082 /* fixed_bit_values */
5083 0x0000000000600000ULL,
5085 0x8000000040040000ULL,
5090 { "mulhha_uu.sn", TILE_OPC_MULHHA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5091 TREG_SN, /* implicitly_written_register */
5102 /* fixed_bit_masks */
5103 0x800000007ffc0000ULL,
5110 /* fixed_bit_values */
5111 0x0000000008600000ULL,
5118 { "mulhhsa_uu", TILE_OPC_MULHHSA_UU, 0x1 /* pipes */, 3 /* num_operands */,
5119 TREG_ZERO, /* implicitly_written_register */
5130 /* fixed_bit_masks */
5131 0x800000007ffc0000ULL,
5138 /* fixed_bit_values */
5139 0x0000000000640000ULL,
5146 { "mulhhsa_uu.sn", TILE_OPC_MULHHSA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5147 TREG_SN, /* implicitly_written_register */
5158 /* fixed_bit_masks */
5159 0x800000007ffc0000ULL,
5166 /* fixed_bit_values */
5167 0x0000000008640000ULL,
5174 { "mulhl_ss", TILE_OPC_MULHL_SS, 0x1 /* pipes */, 3 /* num_operands */,
5175 TREG_ZERO, /* implicitly_written_register */
5186 /* fixed_bit_masks */
5187 0x800000007ffc0000ULL,
5194 /* fixed_bit_values */
5195 0x0000000000880000ULL,
5202 { "mulhl_ss.sn", TILE_OPC_MULHL_SS_SN, 0x1 /* pipes */, 3 /* num_operands */,
5203 TREG_SN, /* implicitly_written_register */
5214 /* fixed_bit_masks */
5215 0x800000007ffc0000ULL,
5222 /* fixed_bit_values */
5223 0x0000000008880000ULL,
5230 { "mulhl_su", TILE_OPC_MULHL_SU, 0x1 /* pipes */, 3 /* num_operands */,
5231 TREG_ZERO, /* implicitly_written_register */
5242 /* fixed_bit_masks */
5243 0x800000007ffc0000ULL,
5250 /* fixed_bit_values */
5251 0x00000000008c0000ULL,
5258 { "mulhl_su.sn", TILE_OPC_MULHL_SU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5259 TREG_SN, /* implicitly_written_register */
5270 /* fixed_bit_masks */
5271 0x800000007ffc0000ULL,
5278 /* fixed_bit_values */
5279 0x00000000088c0000ULL,
5286 { "mulhl_us", TILE_OPC_MULHL_US, 0x1 /* pipes */, 3 /* num_operands */,
5287 TREG_ZERO, /* implicitly_written_register */
5298 /* fixed_bit_masks */
5299 0x800000007ffc0000ULL,
5306 /* fixed_bit_values */
5307 0x0000000000900000ULL,
5314 { "mulhl_us.sn", TILE_OPC_MULHL_US_SN, 0x1 /* pipes */, 3 /* num_operands */,
5315 TREG_SN, /* implicitly_written_register */
5326 /* fixed_bit_masks */
5327 0x800000007ffc0000ULL,
5334 /* fixed_bit_values */
5335 0x0000000008900000ULL,
5342 { "mulhl_uu", TILE_OPC_MULHL_UU, 0x1 /* pipes */, 3 /* num_operands */,
5343 TREG_ZERO, /* implicitly_written_register */
5354 /* fixed_bit_masks */
5355 0x800000007ffc0000ULL,
5362 /* fixed_bit_values */
5363 0x0000000000940000ULL,
5370 { "mulhl_uu.sn", TILE_OPC_MULHL_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5371 TREG_SN, /* implicitly_written_register */
5382 /* fixed_bit_masks */
5383 0x800000007ffc0000ULL,
5390 /* fixed_bit_values */
5391 0x0000000008940000ULL,
5398 { "mulhla_ss", TILE_OPC_MULHLA_SS, 0x1 /* pipes */, 3 /* num_operands */,
5399 TREG_ZERO, /* implicitly_written_register */
5410 /* fixed_bit_masks */
5411 0x800000007ffc0000ULL,
5418 /* fixed_bit_values */
5419 0x0000000000740000ULL,
5426 { "mulhla_ss.sn", TILE_OPC_MULHLA_SS_SN, 0x1 /* pipes */, 3 /* num_operands */,
5427 TREG_SN, /* implicitly_written_register */
5438 /* fixed_bit_masks */
5439 0x800000007ffc0000ULL,
5446 /* fixed_bit_values */
5447 0x0000000008740000ULL,
5454 { "mulhla_su", TILE_OPC_MULHLA_SU, 0x1 /* pipes */, 3 /* num_operands */,
5455 TREG_ZERO, /* implicitly_written_register */
5466 /* fixed_bit_masks */
5467 0x800000007ffc0000ULL,
5474 /* fixed_bit_values */
5475 0x0000000000780000ULL,
5482 { "mulhla_su.sn", TILE_OPC_MULHLA_SU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5483 TREG_SN, /* implicitly_written_register */
5494 /* fixed_bit_masks */
5495 0x800000007ffc0000ULL,
5502 /* fixed_bit_values */
5503 0x0000000008780000ULL,
5510 { "mulhla_us", TILE_OPC_MULHLA_US, 0x1 /* pipes */, 3 /* num_operands */,
5511 TREG_ZERO, /* implicitly_written_register */
5522 /* fixed_bit_masks */
5523 0x800000007ffc0000ULL,
5530 /* fixed_bit_values */
5531 0x00000000007c0000ULL,
5538 { "mulhla_us.sn", TILE_OPC_MULHLA_US_SN, 0x1 /* pipes */, 3 /* num_operands */,
5539 TREG_SN, /* implicitly_written_register */
5550 /* fixed_bit_masks */
5551 0x800000007ffc0000ULL,
5558 /* fixed_bit_values */
5559 0x00000000087c0000ULL,
5566 { "mulhla_uu", TILE_OPC_MULHLA_UU, 0x1 /* pipes */, 3 /* num_operands */,
5567 TREG_ZERO, /* implicitly_written_register */
5578 /* fixed_bit_masks */
5579 0x800000007ffc0000ULL,
5586 /* fixed_bit_values */
5587 0x0000000000800000ULL,
5594 { "mulhla_uu.sn", TILE_OPC_MULHLA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5595 TREG_SN, /* implicitly_written_register */
5606 /* fixed_bit_masks */
5607 0x800000007ffc0000ULL,
5614 /* fixed_bit_values */
5615 0x0000000008800000ULL,
5622 { "mulhlsa_uu", TILE_OPC_MULHLSA_UU, 0x5 /* pipes */, 3 /* num_operands */,
5623 TREG_ZERO, /* implicitly_written_register */
5634 /* fixed_bit_masks */
5635 0x800000007ffc0000ULL,
5637 0x80000000780c0000ULL,
5642 /* fixed_bit_values */
5643 0x0000000000840000ULL,
5645 0x8000000030000000ULL,
5650 { "mulhlsa_uu.sn", TILE_OPC_MULHLSA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5651 TREG_SN, /* implicitly_written_register */
5662 /* fixed_bit_masks */
5663 0x800000007ffc0000ULL,
5670 /* fixed_bit_values */
5671 0x0000000008840000ULL,
5678 { "mulll_ss", TILE_OPC_MULLL_SS, 0x5 /* pipes */, 3 /* num_operands */,
5679 TREG_ZERO, /* implicitly_written_register */
5690 /* fixed_bit_masks */
5691 0x800000007ffc0000ULL,
5693 0x80000000780c0000ULL,
5698 /* fixed_bit_values */
5699 0x0000000000a80000ULL,
5701 0x8000000038080000ULL,
5706 { "mulll_ss.sn", TILE_OPC_MULLL_SS_SN, 0x1 /* pipes */, 3 /* num_operands */,
5707 TREG_SN, /* implicitly_written_register */
5718 /* fixed_bit_masks */
5719 0x800000007ffc0000ULL,
5726 /* fixed_bit_values */
5727 0x0000000008a80000ULL,
5734 { "mulll_su", TILE_OPC_MULLL_SU, 0x1 /* pipes */, 3 /* num_operands */,
5735 TREG_ZERO, /* implicitly_written_register */
5746 /* fixed_bit_masks */
5747 0x800000007ffc0000ULL,
5754 /* fixed_bit_values */
5755 0x0000000000ac0000ULL,
5762 { "mulll_su.sn", TILE_OPC_MULLL_SU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5763 TREG_SN, /* implicitly_written_register */
5774 /* fixed_bit_masks */
5775 0x800000007ffc0000ULL,
5782 /* fixed_bit_values */
5783 0x0000000008ac0000ULL,
5790 { "mulll_uu", TILE_OPC_MULLL_UU, 0x5 /* pipes */, 3 /* num_operands */,
5791 TREG_ZERO, /* implicitly_written_register */
5802 /* fixed_bit_masks */
5803 0x800000007ffc0000ULL,
5805 0x80000000780c0000ULL,
5810 /* fixed_bit_values */
5811 0x0000000000b00000ULL,
5813 0x80000000380c0000ULL,
5818 { "mulll_uu.sn", TILE_OPC_MULLL_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5819 TREG_SN, /* implicitly_written_register */
5830 /* fixed_bit_masks */
5831 0x800000007ffc0000ULL,
5838 /* fixed_bit_values */
5839 0x0000000008b00000ULL,
5846 { "mullla_ss", TILE_OPC_MULLLA_SS, 0x5 /* pipes */, 3 /* num_operands */,
5847 TREG_ZERO, /* implicitly_written_register */
5858 /* fixed_bit_masks */
5859 0x800000007ffc0000ULL,
5861 0x80000000780c0000ULL,
5866 /* fixed_bit_values */
5867 0x0000000000980000ULL,
5869 0x8000000040080000ULL,
5874 { "mullla_ss.sn", TILE_OPC_MULLLA_SS_SN, 0x1 /* pipes */, 3 /* num_operands */,
5875 TREG_SN, /* implicitly_written_register */
5886 /* fixed_bit_masks */
5887 0x800000007ffc0000ULL,
5894 /* fixed_bit_values */
5895 0x0000000008980000ULL,
5902 { "mullla_su", TILE_OPC_MULLLA_SU, 0x1 /* pipes */, 3 /* num_operands */,
5903 TREG_ZERO, /* implicitly_written_register */
5914 /* fixed_bit_masks */
5915 0x800000007ffc0000ULL,
5922 /* fixed_bit_values */
5923 0x00000000009c0000ULL,
5930 { "mullla_su.sn", TILE_OPC_MULLLA_SU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5931 TREG_SN, /* implicitly_written_register */
5942 /* fixed_bit_masks */
5943 0x800000007ffc0000ULL,
5950 /* fixed_bit_values */
5951 0x00000000089c0000ULL,
5958 { "mullla_uu", TILE_OPC_MULLLA_UU, 0x5 /* pipes */, 3 /* num_operands */,
5959 TREG_ZERO, /* implicitly_written_register */
5970 /* fixed_bit_masks */
5971 0x800000007ffc0000ULL,
5973 0x80000000780c0000ULL,
5978 /* fixed_bit_values */
5979 0x0000000000a00000ULL,
5981 0x80000000400c0000ULL,
5986 { "mullla_uu.sn", TILE_OPC_MULLLA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
5987 TREG_SN, /* implicitly_written_register */
5998 /* fixed_bit_masks */
5999 0x800000007ffc0000ULL,
6006 /* fixed_bit_values */
6007 0x0000000008a00000ULL,
6014 { "mulllsa_uu", TILE_OPC_MULLLSA_UU, 0x1 /* pipes */, 3 /* num_operands */,
6015 TREG_ZERO, /* implicitly_written_register */
6026 /* fixed_bit_masks */
6027 0x800000007ffc0000ULL,
6034 /* fixed_bit_values */
6035 0x0000000000a40000ULL,
6042 { "mulllsa_uu.sn", TILE_OPC_MULLLSA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */,
6043 TREG_SN, /* implicitly_written_register */
6054 /* fixed_bit_masks */
6055 0x800000007ffc0000ULL,
6062 /* fixed_bit_values */
6063 0x0000000008a40000ULL,
6070 { "mvnz", TILE_OPC_MVNZ, 0x5 /* pipes */, 3 /* num_operands */,
6071 TREG_ZERO, /* implicitly_written_register */
6082 /* fixed_bit_masks */
6083 0x800000007ffc0000ULL,
6085 0x80000000780c0000ULL,
6090 /* fixed_bit_values */
6091 0x0000000000b40000ULL,
6093 0x8000000010040000ULL,
6098 { "mvnz.sn", TILE_OPC_MVNZ_SN, 0x1 /* pipes */, 3 /* num_operands */,
6099 TREG_SN, /* implicitly_written_register */
6110 /* fixed_bit_masks */
6111 0x800000007ffc0000ULL,
6118 /* fixed_bit_values */
6119 0x0000000008b40000ULL,
6126 { "mvz", TILE_OPC_MVZ, 0x5 /* pipes */, 3 /* num_operands */,
6127 TREG_ZERO, /* implicitly_written_register */
6138 /* fixed_bit_masks */
6139 0x800000007ffc0000ULL,
6141 0x80000000780c0000ULL,
6146 /* fixed_bit_values */
6147 0x0000000000b80000ULL,
6149 0x8000000010080000ULL,
6154 { "mvz.sn", TILE_OPC_MVZ_SN, 0x1 /* pipes */, 3 /* num_operands */,
6155 TREG_SN, /* implicitly_written_register */
6166 /* fixed_bit_masks */
6167 0x800000007ffc0000ULL,
6174 /* fixed_bit_values */
6175 0x0000000008b80000ULL,
6182 { "mz", TILE_OPC_MZ, 0xf /* pipes */, 3 /* num_operands */,
6183 TREG_ZERO, /* implicitly_written_register */
6194 /* fixed_bit_masks */
6195 0x800000007ffc0000ULL,
6196 0xfffe000000000000ULL,
6197 0x80000000780c0000ULL,
6198 0xf806000000000000ULL,
6202 /* fixed_bit_values */
6203 0x0000000000c40000ULL,
6204 0x082e000000000000ULL,
6205 0x80000000100c0000ULL,
6206 0x9004000000000000ULL,
6210 { "mz.sn", TILE_OPC_MZ_SN, 0x3 /* pipes */, 3 /* num_operands */,
6211 TREG_SN, /* implicitly_written_register */
6222 /* fixed_bit_masks */
6223 0x800000007ffc0000ULL,
6224 0xfffe000000000000ULL,
6230 /* fixed_bit_values */
6231 0x0000000008c40000ULL,
6232 0x0c2e000000000000ULL,
6238 { "mzb", TILE_OPC_MZB, 0x3 /* pipes */, 3 /* num_operands */,
6239 TREG_ZERO, /* implicitly_written_register */
6250 /* fixed_bit_masks */
6251 0x800000007ffc0000ULL,
6252 0xfffe000000000000ULL,
6258 /* fixed_bit_values */
6259 0x0000000000bc0000ULL,
6260 0x082a000000000000ULL,
6266 { "mzb.sn", TILE_OPC_MZB_SN, 0x3 /* pipes */, 3 /* num_operands */,
6267 TREG_SN, /* implicitly_written_register */
6278 /* fixed_bit_masks */
6279 0x800000007ffc0000ULL,
6280 0xfffe000000000000ULL,
6286 /* fixed_bit_values */
6287 0x0000000008bc0000ULL,
6288 0x0c2a000000000000ULL,
6294 { "mzh", TILE_OPC_MZH, 0x3 /* pipes */, 3 /* num_operands */,
6295 TREG_ZERO, /* implicitly_written_register */
6306 /* fixed_bit_masks */
6307 0x800000007ffc0000ULL,
6308 0xfffe000000000000ULL,
6314 /* fixed_bit_values */
6315 0x0000000000c00000ULL,
6316 0x082c000000000000ULL,
6322 { "mzh.sn", TILE_OPC_MZH_SN, 0x3 /* pipes */, 3 /* num_operands */,
6323 TREG_SN, /* implicitly_written_register */
6334 /* fixed_bit_masks */
6335 0x800000007ffc0000ULL,
6336 0xfffe000000000000ULL,
6342 /* fixed_bit_values */
6343 0x0000000008c00000ULL,
6344 0x0c2c000000000000ULL,
6350 { "nap", TILE_OPC_NAP, 0x2 /* pipes */, 0 /* num_operands */,
6351 TREG_ZERO, /* implicitly_written_register */
6362 /* fixed_bit_masks */
6364 0xfbfff80000000000ULL,
6370 /* fixed_bit_values */
6372 0x400b800000000000ULL,
6378 { "nop", TILE_OPC_NOP, 0xf /* pipes */, 0 /* num_operands */,
6379 TREG_ZERO, /* implicitly_written_register */
6390 /* fixed_bit_masks */
6391 0x8000000077fff000ULL,
6392 0xfbfff80000000000ULL,
6393 0x80000000780ff000ULL,
6394 0xf807f80000000000ULL,
6398 /* fixed_bit_values */
6399 0x0000000070166000ULL,
6400 0x400b880000000000ULL,
6401 0x80000000680a6000ULL,
6402 0xd805180000000000ULL,
6406 { "nor", TILE_OPC_NOR, 0xf /* pipes */, 3 /* num_operands */,
6407 TREG_ZERO, /* implicitly_written_register */
6418 /* fixed_bit_masks */
6419 0x800000007ffc0000ULL,
6420 0xfffe000000000000ULL,
6421 0x80000000780c0000ULL,
6422 0xf806000000000000ULL,
6426 /* fixed_bit_values */
6427 0x0000000000c80000ULL,
6428 0x0830000000000000ULL,
6429 0x8000000018040000ULL,
6430 0x9802000000000000ULL,
6434 { "nor.sn", TILE_OPC_NOR_SN, 0x3 /* pipes */, 3 /* num_operands */,
6435 TREG_SN, /* implicitly_written_register */
6446 /* fixed_bit_masks */
6447 0x800000007ffc0000ULL,
6448 0xfffe000000000000ULL,
6454 /* fixed_bit_values */
6455 0x0000000008c80000ULL,
6456 0x0c30000000000000ULL,
6462 { "or", TILE_OPC_OR, 0xf /* pipes */, 3 /* num_operands */,
6463 TREG_ZERO, /* implicitly_written_register */
6474 /* fixed_bit_masks */
6475 0x800000007ffc0000ULL,
6476 0xfffe000000000000ULL,
6477 0x80000000780c0000ULL,
6478 0xf806000000000000ULL,
6482 /* fixed_bit_values */
6483 0x0000000000cc0000ULL,
6484 0x0832000000000000ULL,
6485 0x8000000018080000ULL,
6486 0x9804000000000000ULL,
6490 { "or.sn", TILE_OPC_OR_SN, 0x3 /* pipes */, 3 /* num_operands */,
6491 TREG_SN, /* implicitly_written_register */
6502 /* fixed_bit_masks */
6503 0x800000007ffc0000ULL,
6504 0xfffe000000000000ULL,
6510 /* fixed_bit_values */
6511 0x0000000008cc0000ULL,
6512 0x0c32000000000000ULL,
6518 { "ori", TILE_OPC_ORI, 0xf /* pipes */, 3 /* num_operands */,
6519 TREG_ZERO, /* implicitly_written_register */
6530 /* fixed_bit_masks */
6531 0x800000007ff00000ULL,
6532 0xfff8000000000000ULL,
6533 0x8000000078000000ULL,
6534 0xf800000000000000ULL,
6538 /* fixed_bit_values */
6539 0x0000000040800000ULL,
6540 0x3058000000000000ULL,
6541 0x8000000058000000ULL,
6542 0xc800000000000000ULL,
6546 { "ori.sn", TILE_OPC_ORI_SN, 0x3 /* pipes */, 3 /* num_operands */,
6547 TREG_SN, /* implicitly_written_register */
6558 /* fixed_bit_masks */
6559 0x800000007ff00000ULL,
6560 0xfff8000000000000ULL,
6566 /* fixed_bit_values */
6567 0x0000000048800000ULL,
6568 0x3458000000000000ULL,
6574 { "packbs_u", TILE_OPC_PACKBS_U, 0x3 /* pipes */, 3 /* num_operands */,
6575 TREG_ZERO, /* implicitly_written_register */
6586 /* fixed_bit_masks */
6587 0x800000007ffc0000ULL,
6588 0xfffe000000000000ULL,
6594 /* fixed_bit_values */
6595 0x00000000019c0000ULL,
6596 0x0892000000000000ULL,
6602 { "packbs_u.sn", TILE_OPC_PACKBS_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
6603 TREG_SN, /* implicitly_written_register */
6614 /* fixed_bit_masks */
6615 0x800000007ffc0000ULL,
6616 0xfffe000000000000ULL,
6622 /* fixed_bit_values */
6623 0x00000000099c0000ULL,
6624 0x0c92000000000000ULL,
6630 { "packhb", TILE_OPC_PACKHB, 0x3 /* pipes */, 3 /* num_operands */,
6631 TREG_ZERO, /* implicitly_written_register */
6642 /* fixed_bit_masks */
6643 0x800000007ffc0000ULL,
6644 0xfffe000000000000ULL,
6650 /* fixed_bit_values */
6651 0x0000000000d00000ULL,
6652 0x0834000000000000ULL,
6658 { "packhb.sn", TILE_OPC_PACKHB_SN, 0x3 /* pipes */, 3 /* num_operands */,
6659 TREG_SN, /* implicitly_written_register */
6670 /* fixed_bit_masks */
6671 0x800000007ffc0000ULL,
6672 0xfffe000000000000ULL,
6678 /* fixed_bit_values */
6679 0x0000000008d00000ULL,
6680 0x0c34000000000000ULL,
6686 { "packhs", TILE_OPC_PACKHS, 0x3 /* pipes */, 3 /* num_operands */,
6687 TREG_ZERO, /* implicitly_written_register */
6698 /* fixed_bit_masks */
6699 0x800000007ffc0000ULL,
6700 0xfffe000000000000ULL,
6706 /* fixed_bit_values */
6707 0x0000000001980000ULL,
6708 0x0890000000000000ULL,
6714 { "packhs.sn", TILE_OPC_PACKHS_SN, 0x3 /* pipes */, 3 /* num_operands */,
6715 TREG_SN, /* implicitly_written_register */
6726 /* fixed_bit_masks */
6727 0x800000007ffc0000ULL,
6728 0xfffe000000000000ULL,
6734 /* fixed_bit_values */
6735 0x0000000009980000ULL,
6736 0x0c90000000000000ULL,
6742 { "packlb", TILE_OPC_PACKLB, 0x3 /* pipes */, 3 /* num_operands */,
6743 TREG_ZERO, /* implicitly_written_register */
6754 /* fixed_bit_masks */
6755 0x800000007ffc0000ULL,
6756 0xfffe000000000000ULL,
6762 /* fixed_bit_values */
6763 0x0000000000d40000ULL,
6764 0x0836000000000000ULL,
6770 { "packlb.sn", TILE_OPC_PACKLB_SN, 0x3 /* pipes */, 3 /* num_operands */,
6771 TREG_SN, /* implicitly_written_register */
6782 /* fixed_bit_masks */
6783 0x800000007ffc0000ULL,
6784 0xfffe000000000000ULL,
6790 /* fixed_bit_values */
6791 0x0000000008d40000ULL,
6792 0x0c36000000000000ULL,
6798 { "pcnt", TILE_OPC_PCNT, 0x5 /* pipes */, 2 /* num_operands */,
6799 TREG_ZERO, /* implicitly_written_register */
6810 /* fixed_bit_masks */
6811 0x800000007ffff000ULL,
6813 0x80000000780ff000ULL,
6818 /* fixed_bit_values */
6819 0x0000000070167000ULL,
6821 0x80000000680a7000ULL,
6826 { "pcnt.sn", TILE_OPC_PCNT_SN, 0x1 /* pipes */, 2 /* num_operands */,
6827 TREG_SN, /* implicitly_written_register */
6838 /* fixed_bit_masks */
6839 0x800000007ffff000ULL,
6846 /* fixed_bit_values */
6847 0x0000000078167000ULL,
6854 { "rl", TILE_OPC_RL, 0xf /* pipes */, 3 /* num_operands */,
6855 TREG_ZERO, /* implicitly_written_register */
6866 /* fixed_bit_masks */
6867 0x800000007ffc0000ULL,
6868 0xfffe000000000000ULL,
6869 0x80000000780c0000ULL,
6870 0xf806000000000000ULL,
6874 /* fixed_bit_values */
6875 0x0000000000d80000ULL,
6876 0x0838000000000000ULL,
6877 0x8000000020000000ULL,
6878 0xa000000000000000ULL,
6882 { "rl.sn", TILE_OPC_RL_SN, 0x3 /* pipes */, 3 /* num_operands */,
6883 TREG_SN, /* implicitly_written_register */
6894 /* fixed_bit_masks */
6895 0x800000007ffc0000ULL,
6896 0xfffe000000000000ULL,
6902 /* fixed_bit_values */
6903 0x0000000008d80000ULL,
6904 0x0c38000000000000ULL,
6910 { "rli", TILE_OPC_RLI, 0xf /* pipes */, 3 /* num_operands */,
6911 TREG_ZERO, /* implicitly_written_register */
6922 /* fixed_bit_masks */
6923 0x800000007ffe0000ULL,
6924 0xffff000000000000ULL,
6925 0x80000000780e0000ULL,
6926 0xf807000000000000ULL,
6930 /* fixed_bit_values */
6931 0x0000000070020000ULL,
6932 0x4001000000000000ULL,
6933 0x8000000068020000ULL,
6934 0xd801000000000000ULL,
6938 { "rli.sn", TILE_OPC_RLI_SN, 0x3 /* pipes */, 3 /* num_operands */,
6939 TREG_SN, /* implicitly_written_register */
6950 /* fixed_bit_masks */
6951 0x800000007ffe0000ULL,
6952 0xffff000000000000ULL,
6958 /* fixed_bit_values */
6959 0x0000000078020000ULL,
6960 0x4401000000000000ULL,
6966 { "s1a", TILE_OPC_S1A, 0xf /* pipes */, 3 /* num_operands */,
6967 TREG_ZERO, /* implicitly_written_register */
6978 /* fixed_bit_masks */
6979 0x800000007ffc0000ULL,
6980 0xfffe000000000000ULL,
6981 0x80000000780c0000ULL,
6982 0xf806000000000000ULL,
6986 /* fixed_bit_values */
6987 0x0000000000dc0000ULL,
6988 0x083a000000000000ULL,
6989 0x8000000008040000ULL,
6990 0x8802000000000000ULL,
6994 { "s1a.sn", TILE_OPC_S1A_SN, 0x3 /* pipes */, 3 /* num_operands */,
6995 TREG_SN, /* implicitly_written_register */
7006 /* fixed_bit_masks */
7007 0x800000007ffc0000ULL,
7008 0xfffe000000000000ULL,
7014 /* fixed_bit_values */
7015 0x0000000008dc0000ULL,
7016 0x0c3a000000000000ULL,
7022 { "s2a", TILE_OPC_S2A, 0xf /* pipes */, 3 /* num_operands */,
7023 TREG_ZERO, /* implicitly_written_register */
7034 /* fixed_bit_masks */
7035 0x800000007ffc0000ULL,
7036 0xfffe000000000000ULL,
7037 0x80000000780c0000ULL,
7038 0xf806000000000000ULL,
7042 /* fixed_bit_values */
7043 0x0000000000e00000ULL,
7044 0x083c000000000000ULL,
7045 0x8000000008080000ULL,
7046 0x8804000000000000ULL,
7050 { "s2a.sn", TILE_OPC_S2A_SN, 0x3 /* pipes */, 3 /* num_operands */,
7051 TREG_SN, /* implicitly_written_register */
7062 /* fixed_bit_masks */
7063 0x800000007ffc0000ULL,
7064 0xfffe000000000000ULL,
7070 /* fixed_bit_values */
7071 0x0000000008e00000ULL,
7072 0x0c3c000000000000ULL,
7078 { "s3a", TILE_OPC_S3A, 0xf /* pipes */, 3 /* num_operands */,
7079 TREG_ZERO, /* implicitly_written_register */
7090 /* fixed_bit_masks */
7091 0x800000007ffc0000ULL,
7092 0xfffe000000000000ULL,
7093 0x80000000780c0000ULL,
7094 0xf806000000000000ULL,
7098 /* fixed_bit_values */
7099 0x0000000000e40000ULL,
7100 0x083e000000000000ULL,
7101 0x8000000030040000ULL,
7102 0xb002000000000000ULL,
7106 { "s3a.sn", TILE_OPC_S3A_SN, 0x3 /* pipes */, 3 /* num_operands */,
7107 TREG_SN, /* implicitly_written_register */
7118 /* fixed_bit_masks */
7119 0x800000007ffc0000ULL,
7120 0xfffe000000000000ULL,
7126 /* fixed_bit_values */
7127 0x0000000008e40000ULL,
7128 0x0c3e000000000000ULL,
7134 { "sadab_u", TILE_OPC_SADAB_U, 0x1 /* pipes */, 3 /* num_operands */,
7135 TREG_ZERO, /* implicitly_written_register */
7146 /* fixed_bit_masks */
7147 0x800000007ffc0000ULL,
7154 /* fixed_bit_values */
7155 0x0000000000e80000ULL,
7162 { "sadab_u.sn", TILE_OPC_SADAB_U_SN, 0x1 /* pipes */, 3 /* num_operands */,
7163 TREG_SN, /* implicitly_written_register */
7174 /* fixed_bit_masks */
7175 0x800000007ffc0000ULL,
7182 /* fixed_bit_values */
7183 0x0000000008e80000ULL,
7190 { "sadah", TILE_OPC_SADAH, 0x1 /* pipes */, 3 /* num_operands */,
7191 TREG_ZERO, /* implicitly_written_register */
7202 /* fixed_bit_masks */
7203 0x800000007ffc0000ULL,
7210 /* fixed_bit_values */
7211 0x0000000000ec0000ULL,
7218 { "sadah.sn", TILE_OPC_SADAH_SN, 0x1 /* pipes */, 3 /* num_operands */,
7219 TREG_SN, /* implicitly_written_register */
7230 /* fixed_bit_masks */
7231 0x800000007ffc0000ULL,
7238 /* fixed_bit_values */
7239 0x0000000008ec0000ULL,
7246 { "sadah_u", TILE_OPC_SADAH_U, 0x1 /* pipes */, 3 /* num_operands */,
7247 TREG_ZERO, /* implicitly_written_register */
7258 /* fixed_bit_masks */
7259 0x800000007ffc0000ULL,
7266 /* fixed_bit_values */
7267 0x0000000000f00000ULL,
7274 { "sadah_u.sn", TILE_OPC_SADAH_U_SN, 0x1 /* pipes */, 3 /* num_operands */,
7275 TREG_SN, /* implicitly_written_register */
7286 /* fixed_bit_masks */
7287 0x800000007ffc0000ULL,
7294 /* fixed_bit_values */
7295 0x0000000008f00000ULL,
7302 { "sadb_u", TILE_OPC_SADB_U, 0x1 /* pipes */, 3 /* num_operands */,
7303 TREG_ZERO, /* implicitly_written_register */
7314 /* fixed_bit_masks */
7315 0x800000007ffc0000ULL,
7322 /* fixed_bit_values */
7323 0x0000000000f40000ULL,
7330 { "sadb_u.sn", TILE_OPC_SADB_U_SN, 0x1 /* pipes */, 3 /* num_operands */,
7331 TREG_SN, /* implicitly_written_register */
7342 /* fixed_bit_masks */
7343 0x800000007ffc0000ULL,
7350 /* fixed_bit_values */
7351 0x0000000008f40000ULL,
7358 { "sadh", TILE_OPC_SADH, 0x1 /* pipes */, 3 /* num_operands */,
7359 TREG_ZERO, /* implicitly_written_register */
7370 /* fixed_bit_masks */
7371 0x800000007ffc0000ULL,
7378 /* fixed_bit_values */
7379 0x0000000000f80000ULL,
7386 { "sadh.sn", TILE_OPC_SADH_SN, 0x1 /* pipes */, 3 /* num_operands */,
7387 TREG_SN, /* implicitly_written_register */
7398 /* fixed_bit_masks */
7399 0x800000007ffc0000ULL,
7406 /* fixed_bit_values */
7407 0x0000000008f80000ULL,
7414 { "sadh_u", TILE_OPC_SADH_U, 0x1 /* pipes */, 3 /* num_operands */,
7415 TREG_ZERO, /* implicitly_written_register */
7426 /* fixed_bit_masks */
7427 0x800000007ffc0000ULL,
7434 /* fixed_bit_values */
7435 0x0000000000fc0000ULL,
7442 { "sadh_u.sn", TILE_OPC_SADH_U_SN, 0x1 /* pipes */, 3 /* num_operands */,
7443 TREG_SN, /* implicitly_written_register */
7454 /* fixed_bit_masks */
7455 0x800000007ffc0000ULL,
7462 /* fixed_bit_values */
7463 0x0000000008fc0000ULL,
7470 { "sb", TILE_OPC_SB, 0x12 /* pipes */, 2 /* num_operands */,
7471 TREG_ZERO, /* implicitly_written_register */
7482 /* fixed_bit_masks */
7484 0xfbfe000000000000ULL,
7487 0x8700000000000000ULL
7490 /* fixed_bit_values */
7492 0x0840000000000000ULL,
7495 0x8500000000000000ULL
7498 { "sbadd", TILE_OPC_SBADD, 0x2 /* pipes */, 3 /* num_operands */,
7499 TREG_ZERO, /* implicitly_written_register */
7510 /* fixed_bit_masks */
7512 0xfbf8000000000000ULL,
7518 /* fixed_bit_values */
7520 0x30e0000000000000ULL,
7526 { "seq", TILE_OPC_SEQ, 0xf /* pipes */, 3 /* num_operands */,
7527 TREG_ZERO, /* implicitly_written_register */
7538 /* fixed_bit_masks */
7539 0x800000007ffc0000ULL,
7540 0xfffe000000000000ULL,
7541 0x80000000780c0000ULL,
7542 0xf806000000000000ULL,
7546 /* fixed_bit_values */
7547 0x0000000001080000ULL,
7548 0x0846000000000000ULL,
7549 0x8000000030080000ULL,
7550 0xb004000000000000ULL,
7554 { "seq.sn", TILE_OPC_SEQ_SN, 0x3 /* pipes */, 3 /* num_operands */,
7555 TREG_SN, /* implicitly_written_register */
7566 /* fixed_bit_masks */
7567 0x800000007ffc0000ULL,
7568 0xfffe000000000000ULL,
7574 /* fixed_bit_values */
7575 0x0000000009080000ULL,
7576 0x0c46000000000000ULL,
7582 { "seqb", TILE_OPC_SEQB, 0x3 /* pipes */, 3 /* num_operands */,
7583 TREG_ZERO, /* implicitly_written_register */
7594 /* fixed_bit_masks */
7595 0x800000007ffc0000ULL,
7596 0xfffe000000000000ULL,
7602 /* fixed_bit_values */
7603 0x0000000001000000ULL,
7604 0x0842000000000000ULL,
7610 { "seqb.sn", TILE_OPC_SEQB_SN, 0x3 /* pipes */, 3 /* num_operands */,
7611 TREG_SN, /* implicitly_written_register */
7622 /* fixed_bit_masks */
7623 0x800000007ffc0000ULL,
7624 0xfffe000000000000ULL,
7630 /* fixed_bit_values */
7631 0x0000000009000000ULL,
7632 0x0c42000000000000ULL,
7638 { "seqh", TILE_OPC_SEQH, 0x3 /* pipes */, 3 /* num_operands */,
7639 TREG_ZERO, /* implicitly_written_register */
7650 /* fixed_bit_masks */
7651 0x800000007ffc0000ULL,
7652 0xfffe000000000000ULL,
7658 /* fixed_bit_values */
7659 0x0000000001040000ULL,
7660 0x0844000000000000ULL,
7666 { "seqh.sn", TILE_OPC_SEQH_SN, 0x3 /* pipes */, 3 /* num_operands */,
7667 TREG_SN, /* implicitly_written_register */
7678 /* fixed_bit_masks */
7679 0x800000007ffc0000ULL,
7680 0xfffe000000000000ULL,
7686 /* fixed_bit_values */
7687 0x0000000009040000ULL,
7688 0x0c44000000000000ULL,
7694 { "seqi", TILE_OPC_SEQI, 0xf /* pipes */, 3 /* num_operands */,
7695 TREG_ZERO, /* implicitly_written_register */
7706 /* fixed_bit_masks */
7707 0x800000007ff00000ULL,
7708 0xfff8000000000000ULL,
7709 0x8000000078000000ULL,
7710 0xf800000000000000ULL,
7714 /* fixed_bit_values */
7715 0x0000000040b00000ULL,
7716 0x3070000000000000ULL,
7717 0x8000000060000000ULL,
7718 0xd000000000000000ULL,
7722 { "seqi.sn", TILE_OPC_SEQI_SN, 0x3 /* pipes */, 3 /* num_operands */,
7723 TREG_SN, /* implicitly_written_register */
7734 /* fixed_bit_masks */
7735 0x800000007ff00000ULL,
7736 0xfff8000000000000ULL,
7742 /* fixed_bit_values */
7743 0x0000000048b00000ULL,
7744 0x3470000000000000ULL,
7750 { "seqib", TILE_OPC_SEQIB, 0x3 /* pipes */, 3 /* num_operands */,
7751 TREG_ZERO, /* implicitly_written_register */
7762 /* fixed_bit_masks */
7763 0x800000007ff00000ULL,
7764 0xfff8000000000000ULL,
7770 /* fixed_bit_values */
7771 0x0000000040900000ULL,
7772 0x3060000000000000ULL,
7778 { "seqib.sn", TILE_OPC_SEQIB_SN, 0x3 /* pipes */, 3 /* num_operands */,
7779 TREG_SN, /* implicitly_written_register */
7790 /* fixed_bit_masks */
7791 0x800000007ff00000ULL,
7792 0xfff8000000000000ULL,
7798 /* fixed_bit_values */
7799 0x0000000048900000ULL,
7800 0x3460000000000000ULL,
7806 { "seqih", TILE_OPC_SEQIH, 0x3 /* pipes */, 3 /* num_operands */,
7807 TREG_ZERO, /* implicitly_written_register */
7818 /* fixed_bit_masks */
7819 0x800000007ff00000ULL,
7820 0xfff8000000000000ULL,
7826 /* fixed_bit_values */
7827 0x0000000040a00000ULL,
7828 0x3068000000000000ULL,
7834 { "seqih.sn", TILE_OPC_SEQIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
7835 TREG_SN, /* implicitly_written_register */
7846 /* fixed_bit_masks */
7847 0x800000007ff00000ULL,
7848 0xfff8000000000000ULL,
7854 /* fixed_bit_values */
7855 0x0000000048a00000ULL,
7856 0x3468000000000000ULL,
7862 { "sh", TILE_OPC_SH, 0x12 /* pipes */, 2 /* num_operands */,
7863 TREG_ZERO, /* implicitly_written_register */
7874 /* fixed_bit_masks */
7876 0xfbfe000000000000ULL,
7879 0x8700000000000000ULL
7882 /* fixed_bit_values */
7884 0x0854000000000000ULL,
7887 0x8600000000000000ULL
7890 { "shadd", TILE_OPC_SHADD, 0x2 /* pipes */, 3 /* num_operands */,
7891 TREG_ZERO, /* implicitly_written_register */
7902 /* fixed_bit_masks */
7904 0xfbf8000000000000ULL,
7910 /* fixed_bit_values */
7912 0x30e8000000000000ULL,
7918 { "shl", TILE_OPC_SHL, 0xf /* pipes */, 3 /* num_operands */,
7919 TREG_ZERO, /* implicitly_written_register */
7930 /* fixed_bit_masks */
7931 0x800000007ffc0000ULL,
7932 0xfffe000000000000ULL,
7933 0x80000000780c0000ULL,
7934 0xf806000000000000ULL,
7938 /* fixed_bit_values */
7939 0x0000000001140000ULL,
7940 0x084c000000000000ULL,
7941 0x8000000020040000ULL,
7942 0xa002000000000000ULL,
7946 { "shl.sn", TILE_OPC_SHL_SN, 0x3 /* pipes */, 3 /* num_operands */,
7947 TREG_SN, /* implicitly_written_register */
7958 /* fixed_bit_masks */
7959 0x800000007ffc0000ULL,
7960 0xfffe000000000000ULL,
7966 /* fixed_bit_values */
7967 0x0000000009140000ULL,
7968 0x0c4c000000000000ULL,
7974 { "shlb", TILE_OPC_SHLB, 0x3 /* pipes */, 3 /* num_operands */,
7975 TREG_ZERO, /* implicitly_written_register */
7986 /* fixed_bit_masks */
7987 0x800000007ffc0000ULL,
7988 0xfffe000000000000ULL,
7994 /* fixed_bit_values */
7995 0x00000000010c0000ULL,
7996 0x0848000000000000ULL,
8002 { "shlb.sn", TILE_OPC_SHLB_SN, 0x3 /* pipes */, 3 /* num_operands */,
8003 TREG_SN, /* implicitly_written_register */
8014 /* fixed_bit_masks */
8015 0x800000007ffc0000ULL,
8016 0xfffe000000000000ULL,
8022 /* fixed_bit_values */
8023 0x00000000090c0000ULL,
8024 0x0c48000000000000ULL,
8030 { "shlh", TILE_OPC_SHLH, 0x3 /* pipes */, 3 /* num_operands */,
8031 TREG_ZERO, /* implicitly_written_register */
8042 /* fixed_bit_masks */
8043 0x800000007ffc0000ULL,
8044 0xfffe000000000000ULL,
8050 /* fixed_bit_values */
8051 0x0000000001100000ULL,
8052 0x084a000000000000ULL,
8058 { "shlh.sn", TILE_OPC_SHLH_SN, 0x3 /* pipes */, 3 /* num_operands */,
8059 TREG_SN, /* implicitly_written_register */
8070 /* fixed_bit_masks */
8071 0x800000007ffc0000ULL,
8072 0xfffe000000000000ULL,
8078 /* fixed_bit_values */
8079 0x0000000009100000ULL,
8080 0x0c4a000000000000ULL,
8086 { "shli", TILE_OPC_SHLI, 0xf /* pipes */, 3 /* num_operands */,
8087 TREG_ZERO, /* implicitly_written_register */
8098 /* fixed_bit_masks */
8099 0x800000007ffe0000ULL,
8100 0xffff000000000000ULL,
8101 0x80000000780e0000ULL,
8102 0xf807000000000000ULL,
8106 /* fixed_bit_values */
8107 0x0000000070080000ULL,
8108 0x4004000000000000ULL,
8109 0x8000000068040000ULL,
8110 0xd802000000000000ULL,
8114 { "shli.sn", TILE_OPC_SHLI_SN, 0x3 /* pipes */, 3 /* num_operands */,
8115 TREG_SN, /* implicitly_written_register */
8126 /* fixed_bit_masks */
8127 0x800000007ffe0000ULL,
8128 0xffff000000000000ULL,
8134 /* fixed_bit_values */
8135 0x0000000078080000ULL,
8136 0x4404000000000000ULL,
8142 { "shlib", TILE_OPC_SHLIB, 0x3 /* pipes */, 3 /* num_operands */,
8143 TREG_ZERO, /* implicitly_written_register */
8154 /* fixed_bit_masks */
8155 0x800000007ffe0000ULL,
8156 0xffff000000000000ULL,
8162 /* fixed_bit_values */
8163 0x0000000070040000ULL,
8164 0x4002000000000000ULL,
8170 { "shlib.sn", TILE_OPC_SHLIB_SN, 0x3 /* pipes */, 3 /* num_operands */,
8171 TREG_SN, /* implicitly_written_register */
8182 /* fixed_bit_masks */
8183 0x800000007ffe0000ULL,
8184 0xffff000000000000ULL,
8190 /* fixed_bit_values */
8191 0x0000000078040000ULL,
8192 0x4402000000000000ULL,
8198 { "shlih", TILE_OPC_SHLIH, 0x3 /* pipes */, 3 /* num_operands */,
8199 TREG_ZERO, /* implicitly_written_register */
8210 /* fixed_bit_masks */
8211 0x800000007ffe0000ULL,
8212 0xffff000000000000ULL,
8218 /* fixed_bit_values */
8219 0x0000000070060000ULL,
8220 0x4003000000000000ULL,
8226 { "shlih.sn", TILE_OPC_SHLIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
8227 TREG_SN, /* implicitly_written_register */
8238 /* fixed_bit_masks */
8239 0x800000007ffe0000ULL,
8240 0xffff000000000000ULL,
8246 /* fixed_bit_values */
8247 0x0000000078060000ULL,
8248 0x4403000000000000ULL,
8254 { "shr", TILE_OPC_SHR, 0xf /* pipes */, 3 /* num_operands */,
8255 TREG_ZERO, /* implicitly_written_register */
8266 /* fixed_bit_masks */
8267 0x800000007ffc0000ULL,
8268 0xfffe000000000000ULL,
8269 0x80000000780c0000ULL,
8270 0xf806000000000000ULL,
8274 /* fixed_bit_values */
8275 0x0000000001200000ULL,
8276 0x0852000000000000ULL,
8277 0x8000000020080000ULL,
8278 0xa004000000000000ULL,
8282 { "shr.sn", TILE_OPC_SHR_SN, 0x3 /* pipes */, 3 /* num_operands */,
8283 TREG_SN, /* implicitly_written_register */
8294 /* fixed_bit_masks */
8295 0x800000007ffc0000ULL,
8296 0xfffe000000000000ULL,
8302 /* fixed_bit_values */
8303 0x0000000009200000ULL,
8304 0x0c52000000000000ULL,
8310 { "shrb", TILE_OPC_SHRB, 0x3 /* pipes */, 3 /* num_operands */,
8311 TREG_ZERO, /* implicitly_written_register */
8322 /* fixed_bit_masks */
8323 0x800000007ffc0000ULL,
8324 0xfffe000000000000ULL,
8330 /* fixed_bit_values */
8331 0x0000000001180000ULL,
8332 0x084e000000000000ULL,
8338 { "shrb.sn", TILE_OPC_SHRB_SN, 0x3 /* pipes */, 3 /* num_operands */,
8339 TREG_SN, /* implicitly_written_register */
8350 /* fixed_bit_masks */
8351 0x800000007ffc0000ULL,
8352 0xfffe000000000000ULL,
8358 /* fixed_bit_values */
8359 0x0000000009180000ULL,
8360 0x0c4e000000000000ULL,
8366 { "shrh", TILE_OPC_SHRH, 0x3 /* pipes */, 3 /* num_operands */,
8367 TREG_ZERO, /* implicitly_written_register */
8378 /* fixed_bit_masks */
8379 0x800000007ffc0000ULL,
8380 0xfffe000000000000ULL,
8386 /* fixed_bit_values */
8387 0x00000000011c0000ULL,
8388 0x0850000000000000ULL,
8394 { "shrh.sn", TILE_OPC_SHRH_SN, 0x3 /* pipes */, 3 /* num_operands */,
8395 TREG_SN, /* implicitly_written_register */
8406 /* fixed_bit_masks */
8407 0x800000007ffc0000ULL,
8408 0xfffe000000000000ULL,
8414 /* fixed_bit_values */
8415 0x00000000091c0000ULL,
8416 0x0c50000000000000ULL,
8422 { "shri", TILE_OPC_SHRI, 0xf /* pipes */, 3 /* num_operands */,
8423 TREG_ZERO, /* implicitly_written_register */
8434 /* fixed_bit_masks */
8435 0x800000007ffe0000ULL,
8436 0xffff000000000000ULL,
8437 0x80000000780e0000ULL,
8438 0xf807000000000000ULL,
8442 /* fixed_bit_values */
8443 0x00000000700e0000ULL,
8444 0x4007000000000000ULL,
8445 0x8000000068060000ULL,
8446 0xd803000000000000ULL,
8450 { "shri.sn", TILE_OPC_SHRI_SN, 0x3 /* pipes */, 3 /* num_operands */,
8451 TREG_SN, /* implicitly_written_register */
8462 /* fixed_bit_masks */
8463 0x800000007ffe0000ULL,
8464 0xffff000000000000ULL,
8470 /* fixed_bit_values */
8471 0x00000000780e0000ULL,
8472 0x4407000000000000ULL,
8478 { "shrib", TILE_OPC_SHRIB, 0x3 /* pipes */, 3 /* num_operands */,
8479 TREG_ZERO, /* implicitly_written_register */
8490 /* fixed_bit_masks */
8491 0x800000007ffe0000ULL,
8492 0xffff000000000000ULL,
8498 /* fixed_bit_values */
8499 0x00000000700a0000ULL,
8500 0x4005000000000000ULL,
8506 { "shrib.sn", TILE_OPC_SHRIB_SN, 0x3 /* pipes */, 3 /* num_operands */,
8507 TREG_SN, /* implicitly_written_register */
8518 /* fixed_bit_masks */
8519 0x800000007ffe0000ULL,
8520 0xffff000000000000ULL,
8526 /* fixed_bit_values */
8527 0x00000000780a0000ULL,
8528 0x4405000000000000ULL,
8534 { "shrih", TILE_OPC_SHRIH, 0x3 /* pipes */, 3 /* num_operands */,
8535 TREG_ZERO, /* implicitly_written_register */
8546 /* fixed_bit_masks */
8547 0x800000007ffe0000ULL,
8548 0xffff000000000000ULL,
8554 /* fixed_bit_values */
8555 0x00000000700c0000ULL,
8556 0x4006000000000000ULL,
8562 { "shrih.sn", TILE_OPC_SHRIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
8563 TREG_SN, /* implicitly_written_register */
8574 /* fixed_bit_masks */
8575 0x800000007ffe0000ULL,
8576 0xffff000000000000ULL,
8582 /* fixed_bit_values */
8583 0x00000000780c0000ULL,
8584 0x4406000000000000ULL,
8590 { "slt", TILE_OPC_SLT, 0xf /* pipes */, 3 /* num_operands */,
8591 TREG_ZERO, /* implicitly_written_register */
8602 /* fixed_bit_masks */
8603 0x800000007ffc0000ULL,
8604 0xfffe000000000000ULL,
8605 0x80000000780c0000ULL,
8606 0xf806000000000000ULL,
8610 /* fixed_bit_values */
8611 0x00000000014c0000ULL,
8612 0x086a000000000000ULL,
8613 0x8000000028080000ULL,
8614 0xa804000000000000ULL,
8618 { "slt.sn", TILE_OPC_SLT_SN, 0x3 /* pipes */, 3 /* num_operands */,
8619 TREG_SN, /* implicitly_written_register */
8630 /* fixed_bit_masks */
8631 0x800000007ffc0000ULL,
8632 0xfffe000000000000ULL,
8638 /* fixed_bit_values */
8639 0x00000000094c0000ULL,
8640 0x0c6a000000000000ULL,
8646 { "slt_u", TILE_OPC_SLT_U, 0xf /* pipes */, 3 /* num_operands */,
8647 TREG_ZERO, /* implicitly_written_register */
8658 /* fixed_bit_masks */
8659 0x800000007ffc0000ULL,
8660 0xfffe000000000000ULL,
8661 0x80000000780c0000ULL,
8662 0xf806000000000000ULL,
8666 /* fixed_bit_values */
8667 0x0000000001500000ULL,
8668 0x086c000000000000ULL,
8669 0x80000000280c0000ULL,
8670 0xa806000000000000ULL,
8674 { "slt_u.sn", TILE_OPC_SLT_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
8675 TREG_SN, /* implicitly_written_register */
8686 /* fixed_bit_masks */
8687 0x800000007ffc0000ULL,
8688 0xfffe000000000000ULL,
8694 /* fixed_bit_values */
8695 0x0000000009500000ULL,
8696 0x0c6c000000000000ULL,
8702 { "sltb", TILE_OPC_SLTB, 0x3 /* pipes */, 3 /* num_operands */,
8703 TREG_ZERO, /* implicitly_written_register */
8714 /* fixed_bit_masks */
8715 0x800000007ffc0000ULL,
8716 0xfffe000000000000ULL,
8722 /* fixed_bit_values */
8723 0x0000000001240000ULL,
8724 0x0856000000000000ULL,
8730 { "sltb.sn", TILE_OPC_SLTB_SN, 0x3 /* pipes */, 3 /* num_operands */,
8731 TREG_SN, /* implicitly_written_register */
8742 /* fixed_bit_masks */
8743 0x800000007ffc0000ULL,
8744 0xfffe000000000000ULL,
8750 /* fixed_bit_values */
8751 0x0000000009240000ULL,
8752 0x0c56000000000000ULL,
8758 { "sltb_u", TILE_OPC_SLTB_U, 0x3 /* pipes */, 3 /* num_operands */,
8759 TREG_ZERO, /* implicitly_written_register */
8770 /* fixed_bit_masks */
8771 0x800000007ffc0000ULL,
8772 0xfffe000000000000ULL,
8778 /* fixed_bit_values */
8779 0x0000000001280000ULL,
8780 0x0858000000000000ULL,
8786 { "sltb_u.sn", TILE_OPC_SLTB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
8787 TREG_SN, /* implicitly_written_register */
8798 /* fixed_bit_masks */
8799 0x800000007ffc0000ULL,
8800 0xfffe000000000000ULL,
8806 /* fixed_bit_values */
8807 0x0000000009280000ULL,
8808 0x0c58000000000000ULL,
8814 { "slte", TILE_OPC_SLTE, 0xf /* pipes */, 3 /* num_operands */,
8815 TREG_ZERO, /* implicitly_written_register */
8826 /* fixed_bit_masks */
8827 0x800000007ffc0000ULL,
8828 0xfffe000000000000ULL,
8829 0x80000000780c0000ULL,
8830 0xf806000000000000ULL,
8834 /* fixed_bit_values */
8835 0x00000000013c0000ULL,
8836 0x0862000000000000ULL,
8837 0x8000000028000000ULL,
8838 0xa800000000000000ULL,
8842 { "slte.sn", TILE_OPC_SLTE_SN, 0x3 /* pipes */, 3 /* num_operands */,
8843 TREG_SN, /* implicitly_written_register */
8854 /* fixed_bit_masks */
8855 0x800000007ffc0000ULL,
8856 0xfffe000000000000ULL,
8862 /* fixed_bit_values */
8863 0x00000000093c0000ULL,
8864 0x0c62000000000000ULL,
8870 { "slte_u", TILE_OPC_SLTE_U, 0xf /* pipes */, 3 /* num_operands */,
8871 TREG_ZERO, /* implicitly_written_register */
8882 /* fixed_bit_masks */
8883 0x800000007ffc0000ULL,
8884 0xfffe000000000000ULL,
8885 0x80000000780c0000ULL,
8886 0xf806000000000000ULL,
8890 /* fixed_bit_values */
8891 0x0000000001400000ULL,
8892 0x0864000000000000ULL,
8893 0x8000000028040000ULL,
8894 0xa802000000000000ULL,
8898 { "slte_u.sn", TILE_OPC_SLTE_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
8899 TREG_SN, /* implicitly_written_register */
8910 /* fixed_bit_masks */
8911 0x800000007ffc0000ULL,
8912 0xfffe000000000000ULL,
8918 /* fixed_bit_values */
8919 0x0000000009400000ULL,
8920 0x0c64000000000000ULL,
8926 { "slteb", TILE_OPC_SLTEB, 0x3 /* pipes */, 3 /* num_operands */,
8927 TREG_ZERO, /* implicitly_written_register */
8938 /* fixed_bit_masks */
8939 0x800000007ffc0000ULL,
8940 0xfffe000000000000ULL,
8946 /* fixed_bit_values */
8947 0x00000000012c0000ULL,
8948 0x085a000000000000ULL,
8954 { "slteb.sn", TILE_OPC_SLTEB_SN, 0x3 /* pipes */, 3 /* num_operands */,
8955 TREG_SN, /* implicitly_written_register */
8966 /* fixed_bit_masks */
8967 0x800000007ffc0000ULL,
8968 0xfffe000000000000ULL,
8974 /* fixed_bit_values */
8975 0x00000000092c0000ULL,
8976 0x0c5a000000000000ULL,
8982 { "slteb_u", TILE_OPC_SLTEB_U, 0x3 /* pipes */, 3 /* num_operands */,
8983 TREG_ZERO, /* implicitly_written_register */
8994 /* fixed_bit_masks */
8995 0x800000007ffc0000ULL,
8996 0xfffe000000000000ULL,
9002 /* fixed_bit_values */
9003 0x0000000001300000ULL,
9004 0x085c000000000000ULL,
9010 { "slteb_u.sn", TILE_OPC_SLTEB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
9011 TREG_SN, /* implicitly_written_register */
9022 /* fixed_bit_masks */
9023 0x800000007ffc0000ULL,
9024 0xfffe000000000000ULL,
9030 /* fixed_bit_values */
9031 0x0000000009300000ULL,
9032 0x0c5c000000000000ULL,
9038 { "slteh", TILE_OPC_SLTEH, 0x3 /* pipes */, 3 /* num_operands */,
9039 TREG_ZERO, /* implicitly_written_register */
9050 /* fixed_bit_masks */
9051 0x800000007ffc0000ULL,
9052 0xfffe000000000000ULL,
9058 /* fixed_bit_values */
9059 0x0000000001340000ULL,
9060 0x085e000000000000ULL,
9066 { "slteh.sn", TILE_OPC_SLTEH_SN, 0x3 /* pipes */, 3 /* num_operands */,
9067 TREG_SN, /* implicitly_written_register */
9078 /* fixed_bit_masks */
9079 0x800000007ffc0000ULL,
9080 0xfffe000000000000ULL,
9086 /* fixed_bit_values */
9087 0x0000000009340000ULL,
9088 0x0c5e000000000000ULL,
9094 { "slteh_u", TILE_OPC_SLTEH_U, 0x3 /* pipes */, 3 /* num_operands */,
9095 TREG_ZERO, /* implicitly_written_register */
9106 /* fixed_bit_masks */
9107 0x800000007ffc0000ULL,
9108 0xfffe000000000000ULL,
9114 /* fixed_bit_values */
9115 0x0000000001380000ULL,
9116 0x0860000000000000ULL,
9122 { "slteh_u.sn", TILE_OPC_SLTEH_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
9123 TREG_SN, /* implicitly_written_register */
9134 /* fixed_bit_masks */
9135 0x800000007ffc0000ULL,
9136 0xfffe000000000000ULL,
9142 /* fixed_bit_values */
9143 0x0000000009380000ULL,
9144 0x0c60000000000000ULL,
9150 { "slth", TILE_OPC_SLTH, 0x3 /* pipes */, 3 /* num_operands */,
9151 TREG_ZERO, /* implicitly_written_register */
9162 /* fixed_bit_masks */
9163 0x800000007ffc0000ULL,
9164 0xfffe000000000000ULL,
9170 /* fixed_bit_values */
9171 0x0000000001440000ULL,
9172 0x0866000000000000ULL,
9178 { "slth.sn", TILE_OPC_SLTH_SN, 0x3 /* pipes */, 3 /* num_operands */,
9179 TREG_SN, /* implicitly_written_register */
9190 /* fixed_bit_masks */
9191 0x800000007ffc0000ULL,
9192 0xfffe000000000000ULL,
9198 /* fixed_bit_values */
9199 0x0000000009440000ULL,
9200 0x0c66000000000000ULL,
9206 { "slth_u", TILE_OPC_SLTH_U, 0x3 /* pipes */, 3 /* num_operands */,
9207 TREG_ZERO, /* implicitly_written_register */
9218 /* fixed_bit_masks */
9219 0x800000007ffc0000ULL,
9220 0xfffe000000000000ULL,
9226 /* fixed_bit_values */
9227 0x0000000001480000ULL,
9228 0x0868000000000000ULL,
9234 { "slth_u.sn", TILE_OPC_SLTH_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
9235 TREG_SN, /* implicitly_written_register */
9246 /* fixed_bit_masks */
9247 0x800000007ffc0000ULL,
9248 0xfffe000000000000ULL,
9254 /* fixed_bit_values */
9255 0x0000000009480000ULL,
9256 0x0c68000000000000ULL,
9262 { "slti", TILE_OPC_SLTI, 0xf /* pipes */, 3 /* num_operands */,
9263 TREG_ZERO, /* implicitly_written_register */
9274 /* fixed_bit_masks */
9275 0x800000007ff00000ULL,
9276 0xfff8000000000000ULL,
9277 0x8000000078000000ULL,
9278 0xf800000000000000ULL,
9282 /* fixed_bit_values */
9283 0x0000000041000000ULL,
9284 0x3098000000000000ULL,
9285 0x8000000070000000ULL,
9286 0xe000000000000000ULL,
9290 { "slti.sn", TILE_OPC_SLTI_SN, 0x3 /* pipes */, 3 /* num_operands */,
9291 TREG_SN, /* implicitly_written_register */
9302 /* fixed_bit_masks */
9303 0x800000007ff00000ULL,
9304 0xfff8000000000000ULL,
9310 /* fixed_bit_values */
9311 0x0000000049000000ULL,
9312 0x3498000000000000ULL,
9318 { "slti_u", TILE_OPC_SLTI_U, 0xf /* pipes */, 3 /* num_operands */,
9319 TREG_ZERO, /* implicitly_written_register */
9330 /* fixed_bit_masks */
9331 0x800000007ff00000ULL,
9332 0xfff8000000000000ULL,
9333 0x8000000078000000ULL,
9334 0xf800000000000000ULL,
9338 /* fixed_bit_values */
9339 0x0000000041100000ULL,
9340 0x30a0000000000000ULL,
9341 0x8000000078000000ULL,
9342 0xe800000000000000ULL,
9346 { "slti_u.sn", TILE_OPC_SLTI_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
9347 TREG_SN, /* implicitly_written_register */
9358 /* fixed_bit_masks */
9359 0x800000007ff00000ULL,
9360 0xfff8000000000000ULL,
9366 /* fixed_bit_values */
9367 0x0000000049100000ULL,
9368 0x34a0000000000000ULL,
9374 { "sltib", TILE_OPC_SLTIB, 0x3 /* pipes */, 3 /* num_operands */,
9375 TREG_ZERO, /* implicitly_written_register */
9386 /* fixed_bit_masks */
9387 0x800000007ff00000ULL,
9388 0xfff8000000000000ULL,
9394 /* fixed_bit_values */
9395 0x0000000040c00000ULL,
9396 0x3078000000000000ULL,
9402 { "sltib.sn", TILE_OPC_SLTIB_SN, 0x3 /* pipes */, 3 /* num_operands */,
9403 TREG_SN, /* implicitly_written_register */
9414 /* fixed_bit_masks */
9415 0x800000007ff00000ULL,
9416 0xfff8000000000000ULL,
9422 /* fixed_bit_values */
9423 0x0000000048c00000ULL,
9424 0x3478000000000000ULL,
9430 { "sltib_u", TILE_OPC_SLTIB_U, 0x3 /* pipes */, 3 /* num_operands */,
9431 TREG_ZERO, /* implicitly_written_register */
9442 /* fixed_bit_masks */
9443 0x800000007ff00000ULL,
9444 0xfff8000000000000ULL,
9450 /* fixed_bit_values */
9451 0x0000000040d00000ULL,
9452 0x3080000000000000ULL,
9458 { "sltib_u.sn", TILE_OPC_SLTIB_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
9459 TREG_SN, /* implicitly_written_register */
9470 /* fixed_bit_masks */
9471 0x800000007ff00000ULL,
9472 0xfff8000000000000ULL,
9478 /* fixed_bit_values */
9479 0x0000000048d00000ULL,
9480 0x3480000000000000ULL,
9486 { "sltih", TILE_OPC_SLTIH, 0x3 /* pipes */, 3 /* num_operands */,
9487 TREG_ZERO, /* implicitly_written_register */
9498 /* fixed_bit_masks */
9499 0x800000007ff00000ULL,
9500 0xfff8000000000000ULL,
9506 /* fixed_bit_values */
9507 0x0000000040e00000ULL,
9508 0x3088000000000000ULL,
9514 { "sltih.sn", TILE_OPC_SLTIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
9515 TREG_SN, /* implicitly_written_register */
9526 /* fixed_bit_masks */
9527 0x800000007ff00000ULL,
9528 0xfff8000000000000ULL,
9534 /* fixed_bit_values */
9535 0x0000000048e00000ULL,
9536 0x3488000000000000ULL,
9542 { "sltih_u", TILE_OPC_SLTIH_U, 0x3 /* pipes */, 3 /* num_operands */,
9543 TREG_ZERO, /* implicitly_written_register */
9554 /* fixed_bit_masks */
9555 0x800000007ff00000ULL,
9556 0xfff8000000000000ULL,
9562 /* fixed_bit_values */
9563 0x0000000040f00000ULL,
9564 0x3090000000000000ULL,
9570 { "sltih_u.sn", TILE_OPC_SLTIH_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
9571 TREG_SN, /* implicitly_written_register */
9582 /* fixed_bit_masks */
9583 0x800000007ff00000ULL,
9584 0xfff8000000000000ULL,
9590 /* fixed_bit_values */
9591 0x0000000048f00000ULL,
9592 0x3490000000000000ULL,
9598 { "sne", TILE_OPC_SNE, 0xf /* pipes */, 3 /* num_operands */,
9599 TREG_ZERO, /* implicitly_written_register */
9610 /* fixed_bit_masks */
9611 0x800000007ffc0000ULL,
9612 0xfffe000000000000ULL,
9613 0x80000000780c0000ULL,
9614 0xf806000000000000ULL,
9618 /* fixed_bit_values */
9619 0x00000000015c0000ULL,
9620 0x0872000000000000ULL,
9621 0x80000000300c0000ULL,
9622 0xb006000000000000ULL,
9626 { "sne.sn", TILE_OPC_SNE_SN, 0x3 /* pipes */, 3 /* num_operands */,
9627 TREG_SN, /* implicitly_written_register */
9638 /* fixed_bit_masks */
9639 0x800000007ffc0000ULL,
9640 0xfffe000000000000ULL,
9646 /* fixed_bit_values */
9647 0x00000000095c0000ULL,
9648 0x0c72000000000000ULL,
9654 { "sneb", TILE_OPC_SNEB, 0x3 /* pipes */, 3 /* num_operands */,
9655 TREG_ZERO, /* implicitly_written_register */
9666 /* fixed_bit_masks */
9667 0x800000007ffc0000ULL,
9668 0xfffe000000000000ULL,
9674 /* fixed_bit_values */
9675 0x0000000001540000ULL,
9676 0x086e000000000000ULL,
9682 { "sneb.sn", TILE_OPC_SNEB_SN, 0x3 /* pipes */, 3 /* num_operands */,
9683 TREG_SN, /* implicitly_written_register */
9694 /* fixed_bit_masks */
9695 0x800000007ffc0000ULL,
9696 0xfffe000000000000ULL,
9702 /* fixed_bit_values */
9703 0x0000000009540000ULL,
9704 0x0c6e000000000000ULL,
9710 { "sneh", TILE_OPC_SNEH, 0x3 /* pipes */, 3 /* num_operands */,
9711 TREG_ZERO, /* implicitly_written_register */
9722 /* fixed_bit_masks */
9723 0x800000007ffc0000ULL,
9724 0xfffe000000000000ULL,
9730 /* fixed_bit_values */
9731 0x0000000001580000ULL,
9732 0x0870000000000000ULL,
9738 { "sneh.sn", TILE_OPC_SNEH_SN, 0x3 /* pipes */, 3 /* num_operands */,
9739 TREG_SN, /* implicitly_written_register */
9750 /* fixed_bit_masks */
9751 0x800000007ffc0000ULL,
9752 0xfffe000000000000ULL,
9758 /* fixed_bit_values */
9759 0x0000000009580000ULL,
9760 0x0c70000000000000ULL,
9766 { "sra", TILE_OPC_SRA, 0xf /* pipes */, 3 /* num_operands */,
9767 TREG_ZERO, /* implicitly_written_register */
9778 /* fixed_bit_masks */
9779 0x800000007ffc0000ULL,
9780 0xfffe000000000000ULL,
9781 0x80000000780c0000ULL,
9782 0xf806000000000000ULL,
9786 /* fixed_bit_values */
9787 0x0000000001680000ULL,
9788 0x0878000000000000ULL,
9789 0x80000000200c0000ULL,
9790 0xa006000000000000ULL,
9794 { "sra.sn", TILE_OPC_SRA_SN, 0x3 /* pipes */, 3 /* num_operands */,
9795 TREG_SN, /* implicitly_written_register */
9806 /* fixed_bit_masks */
9807 0x800000007ffc0000ULL,
9808 0xfffe000000000000ULL,
9814 /* fixed_bit_values */
9815 0x0000000009680000ULL,
9816 0x0c78000000000000ULL,
9822 { "srab", TILE_OPC_SRAB, 0x3 /* pipes */, 3 /* num_operands */,
9823 TREG_ZERO, /* implicitly_written_register */
9834 /* fixed_bit_masks */
9835 0x800000007ffc0000ULL,
9836 0xfffe000000000000ULL,
9842 /* fixed_bit_values */
9843 0x0000000001600000ULL,
9844 0x0874000000000000ULL,
9850 { "srab.sn", TILE_OPC_SRAB_SN, 0x3 /* pipes */, 3 /* num_operands */,
9851 TREG_SN, /* implicitly_written_register */
9862 /* fixed_bit_masks */
9863 0x800000007ffc0000ULL,
9864 0xfffe000000000000ULL,
9870 /* fixed_bit_values */
9871 0x0000000009600000ULL,
9872 0x0c74000000000000ULL,
9878 { "srah", TILE_OPC_SRAH, 0x3 /* pipes */, 3 /* num_operands */,
9879 TREG_ZERO, /* implicitly_written_register */
9890 /* fixed_bit_masks */
9891 0x800000007ffc0000ULL,
9892 0xfffe000000000000ULL,
9898 /* fixed_bit_values */
9899 0x0000000001640000ULL,
9900 0x0876000000000000ULL,
9906 { "srah.sn", TILE_OPC_SRAH_SN, 0x3 /* pipes */, 3 /* num_operands */,
9907 TREG_SN, /* implicitly_written_register */
9918 /* fixed_bit_masks */
9919 0x800000007ffc0000ULL,
9920 0xfffe000000000000ULL,
9926 /* fixed_bit_values */
9927 0x0000000009640000ULL,
9928 0x0c76000000000000ULL,
9934 { "srai", TILE_OPC_SRAI, 0xf /* pipes */, 3 /* num_operands */,
9935 TREG_ZERO, /* implicitly_written_register */
9946 /* fixed_bit_masks */
9947 0x800000007ffe0000ULL,
9948 0xffff000000000000ULL,
9949 0x80000000780e0000ULL,
9950 0xf807000000000000ULL,
9954 /* fixed_bit_values */
9955 0x0000000070140000ULL,
9956 0x400a000000000000ULL,
9957 0x8000000068080000ULL,
9958 0xd804000000000000ULL,
9962 { "srai.sn", TILE_OPC_SRAI_SN, 0x3 /* pipes */, 3 /* num_operands */,
9963 TREG_SN, /* implicitly_written_register */
9974 /* fixed_bit_masks */
9975 0x800000007ffe0000ULL,
9976 0xffff000000000000ULL,
9982 /* fixed_bit_values */
9983 0x0000000078140000ULL,
9984 0x440a000000000000ULL,
9990 { "sraib", TILE_OPC_SRAIB, 0x3 /* pipes */, 3 /* num_operands */,
9991 TREG_ZERO, /* implicitly_written_register */
10002 /* fixed_bit_masks */
10003 0x800000007ffe0000ULL,
10004 0xffff000000000000ULL,
10010 /* fixed_bit_values */
10011 0x0000000070100000ULL,
10012 0x4008000000000000ULL,
10018 { "sraib.sn", TILE_OPC_SRAIB_SN, 0x3 /* pipes */, 3 /* num_operands */,
10019 TREG_SN, /* implicitly_written_register */
10020 1, /* can_bundle */
10030 /* fixed_bit_masks */
10031 0x800000007ffe0000ULL,
10032 0xffff000000000000ULL,
10038 /* fixed_bit_values */
10039 0x0000000078100000ULL,
10040 0x4408000000000000ULL,
10046 { "sraih", TILE_OPC_SRAIH, 0x3 /* pipes */, 3 /* num_operands */,
10047 TREG_ZERO, /* implicitly_written_register */
10048 1, /* can_bundle */
10058 /* fixed_bit_masks */
10059 0x800000007ffe0000ULL,
10060 0xffff000000000000ULL,
10066 /* fixed_bit_values */
10067 0x0000000070120000ULL,
10068 0x4009000000000000ULL,
10074 { "sraih.sn", TILE_OPC_SRAIH_SN, 0x3 /* pipes */, 3 /* num_operands */,
10075 TREG_SN, /* implicitly_written_register */
10076 1, /* can_bundle */
10086 /* fixed_bit_masks */
10087 0x800000007ffe0000ULL,
10088 0xffff000000000000ULL,
10094 /* fixed_bit_values */
10095 0x0000000078120000ULL,
10096 0x4409000000000000ULL,
10102 { "sub", TILE_OPC_SUB, 0xf /* pipes */, 3 /* num_operands */,
10103 TREG_ZERO, /* implicitly_written_register */
10104 1, /* can_bundle */
10114 /* fixed_bit_masks */
10115 0x800000007ffc0000ULL,
10116 0xfffe000000000000ULL,
10117 0x80000000780c0000ULL,
10118 0xf806000000000000ULL,
10122 /* fixed_bit_values */
10123 0x0000000001740000ULL,
10124 0x087e000000000000ULL,
10125 0x80000000080c0000ULL,
10126 0x8806000000000000ULL,
10130 { "sub.sn", TILE_OPC_SUB_SN, 0x3 /* pipes */, 3 /* num_operands */,
10131 TREG_SN, /* implicitly_written_register */
10132 1, /* can_bundle */
10142 /* fixed_bit_masks */
10143 0x800000007ffc0000ULL,
10144 0xfffe000000000000ULL,
10150 /* fixed_bit_values */
10151 0x0000000009740000ULL,
10152 0x0c7e000000000000ULL,
10158 { "subb", TILE_OPC_SUBB, 0x3 /* pipes */, 3 /* num_operands */,
10159 TREG_ZERO, /* implicitly_written_register */
10160 1, /* can_bundle */
10170 /* fixed_bit_masks */
10171 0x800000007ffc0000ULL,
10172 0xfffe000000000000ULL,
10178 /* fixed_bit_values */
10179 0x00000000016c0000ULL,
10180 0x087a000000000000ULL,
10186 { "subb.sn", TILE_OPC_SUBB_SN, 0x3 /* pipes */, 3 /* num_operands */,
10187 TREG_SN, /* implicitly_written_register */
10188 1, /* can_bundle */
10198 /* fixed_bit_masks */
10199 0x800000007ffc0000ULL,
10200 0xfffe000000000000ULL,
10206 /* fixed_bit_values */
10207 0x00000000096c0000ULL,
10208 0x0c7a000000000000ULL,
10214 { "subbs_u", TILE_OPC_SUBBS_U, 0x3 /* pipes */, 3 /* num_operands */,
10215 TREG_ZERO, /* implicitly_written_register */
10216 1, /* can_bundle */
10226 /* fixed_bit_masks */
10227 0x800000007ffc0000ULL,
10228 0xfffe000000000000ULL,
10234 /* fixed_bit_values */
10235 0x0000000001900000ULL,
10236 0x088c000000000000ULL,
10242 { "subbs_u.sn", TILE_OPC_SUBBS_U_SN, 0x3 /* pipes */, 3 /* num_operands */,
10243 TREG_SN, /* implicitly_written_register */
10244 1, /* can_bundle */
10254 /* fixed_bit_masks */
10255 0x800000007ffc0000ULL,
10256 0xfffe000000000000ULL,
10262 /* fixed_bit_values */
10263 0x0000000009900000ULL,
10264 0x0c8c000000000000ULL,
10270 { "subh", TILE_OPC_SUBH, 0x3 /* pipes */, 3 /* num_operands */,
10271 TREG_ZERO, /* implicitly_written_register */
10272 1, /* can_bundle */
10282 /* fixed_bit_masks */
10283 0x800000007ffc0000ULL,
10284 0xfffe000000000000ULL,
10290 /* fixed_bit_values */
10291 0x0000000001700000ULL,
10292 0x087c000000000000ULL,
10298 { "subh.sn", TILE_OPC_SUBH_SN, 0x3 /* pipes */, 3 /* num_operands */,
10299 TREG_SN, /* implicitly_written_register */
10300 1, /* can_bundle */
10310 /* fixed_bit_masks */
10311 0x800000007ffc0000ULL,
10312 0xfffe000000000000ULL,
10318 /* fixed_bit_values */
10319 0x0000000009700000ULL,
10320 0x0c7c000000000000ULL,
10326 { "subhs", TILE_OPC_SUBHS, 0x3 /* pipes */, 3 /* num_operands */,
10327 TREG_ZERO, /* implicitly_written_register */
10328 1, /* can_bundle */
10338 /* fixed_bit_masks */
10339 0x800000007ffc0000ULL,
10340 0xfffe000000000000ULL,
10346 /* fixed_bit_values */
10347 0x0000000001940000ULL,
10348 0x088e000000000000ULL,
10354 { "subhs.sn", TILE_OPC_SUBHS_SN, 0x3 /* pipes */, 3 /* num_operands */,
10355 TREG_SN, /* implicitly_written_register */
10356 1, /* can_bundle */
10366 /* fixed_bit_masks */
10367 0x800000007ffc0000ULL,
10368 0xfffe000000000000ULL,
10374 /* fixed_bit_values */
10375 0x0000000009940000ULL,
10376 0x0c8e000000000000ULL,
10382 { "subs", TILE_OPC_SUBS, 0x3 /* pipes */, 3 /* num_operands */,
10383 TREG_ZERO, /* implicitly_written_register */
10384 1, /* can_bundle */
10394 /* fixed_bit_masks */
10395 0x800000007ffc0000ULL,
10396 0xfffe000000000000ULL,
10402 /* fixed_bit_values */
10403 0x0000000001840000ULL,
10404 0x0886000000000000ULL,
10410 { "subs.sn", TILE_OPC_SUBS_SN, 0x3 /* pipes */, 3 /* num_operands */,
10411 TREG_SN, /* implicitly_written_register */
10412 1, /* can_bundle */
10422 /* fixed_bit_masks */
10423 0x800000007ffc0000ULL,
10424 0xfffe000000000000ULL,
10430 /* fixed_bit_values */
10431 0x0000000009840000ULL,
10432 0x0c86000000000000ULL,
10438 { "sw", TILE_OPC_SW, 0x12 /* pipes */, 2 /* num_operands */,
10439 TREG_ZERO, /* implicitly_written_register */
10440 1, /* can_bundle */
10450 /* fixed_bit_masks */
10452 0xfbfe000000000000ULL,
10455 0x8700000000000000ULL
10458 /* fixed_bit_values */
10460 0x0880000000000000ULL,
10463 0x8700000000000000ULL
10466 { "swadd", TILE_OPC_SWADD, 0x2 /* pipes */, 3 /* num_operands */,
10467 TREG_ZERO, /* implicitly_written_register */
10468 1, /* can_bundle */
10478 /* fixed_bit_masks */
10480 0xfbf8000000000000ULL,
10486 /* fixed_bit_values */
10488 0x30f0000000000000ULL,
10494 { "swint0", TILE_OPC_SWINT0, 0x2 /* pipes */, 0 /* num_operands */,
10495 TREG_ZERO, /* implicitly_written_register */
10496 0, /* can_bundle */
10506 /* fixed_bit_masks */
10508 0xfbfff80000000000ULL,
10514 /* fixed_bit_values */
10516 0x400b900000000000ULL,
10522 { "swint1", TILE_OPC_SWINT1, 0x2 /* pipes */, 0 /* num_operands */,
10523 TREG_ZERO, /* implicitly_written_register */
10524 0, /* can_bundle */
10534 /* fixed_bit_masks */
10536 0xfbfff80000000000ULL,
10542 /* fixed_bit_values */
10544 0x400b980000000000ULL,
10550 { "swint2", TILE_OPC_SWINT2, 0x2 /* pipes */, 0 /* num_operands */,
10551 TREG_ZERO, /* implicitly_written_register */
10552 0, /* can_bundle */
10562 /* fixed_bit_masks */
10564 0xfbfff80000000000ULL,
10570 /* fixed_bit_values */
10572 0x400ba00000000000ULL,
10578 { "swint3", TILE_OPC_SWINT3, 0x2 /* pipes */, 0 /* num_operands */,
10579 TREG_ZERO, /* implicitly_written_register */
10580 0, /* can_bundle */
10590 /* fixed_bit_masks */
10592 0xfbfff80000000000ULL,
10598 /* fixed_bit_values */
10600 0x400ba80000000000ULL,
10606 { "tblidxb0", TILE_OPC_TBLIDXB0, 0x5 /* pipes */, 2 /* num_operands */,
10607 TREG_ZERO, /* implicitly_written_register */
10608 1, /* can_bundle */
10618 /* fixed_bit_masks */
10619 0x800000007ffff000ULL,
10621 0x80000000780ff000ULL,
10626 /* fixed_bit_values */
10627 0x0000000070168000ULL,
10629 0x80000000680a8000ULL,
10634 { "tblidxb0.sn", TILE_OPC_TBLIDXB0_SN, 0x1 /* pipes */, 2 /* num_operands */,
10635 TREG_SN, /* implicitly_written_register */
10636 1, /* can_bundle */
10646 /* fixed_bit_masks */
10647 0x800000007ffff000ULL,
10654 /* fixed_bit_values */
10655 0x0000000078168000ULL,
10662 { "tblidxb1", TILE_OPC_TBLIDXB1, 0x5 /* pipes */, 2 /* num_operands */,
10663 TREG_ZERO, /* implicitly_written_register */
10664 1, /* can_bundle */
10674 /* fixed_bit_masks */
10675 0x800000007ffff000ULL,
10677 0x80000000780ff000ULL,
10682 /* fixed_bit_values */
10683 0x0000000070169000ULL,
10685 0x80000000680a9000ULL,
10690 { "tblidxb1.sn", TILE_OPC_TBLIDXB1_SN, 0x1 /* pipes */, 2 /* num_operands */,
10691 TREG_SN, /* implicitly_written_register */
10692 1, /* can_bundle */
10702 /* fixed_bit_masks */
10703 0x800000007ffff000ULL,
10710 /* fixed_bit_values */
10711 0x0000000078169000ULL,
10718 { "tblidxb2", TILE_OPC_TBLIDXB2, 0x5 /* pipes */, 2 /* num_operands */,
10719 TREG_ZERO, /* implicitly_written_register */
10720 1, /* can_bundle */
10730 /* fixed_bit_masks */
10731 0x800000007ffff000ULL,
10733 0x80000000780ff000ULL,
10738 /* fixed_bit_values */
10739 0x000000007016a000ULL,
10741 0x80000000680aa000ULL,
10746 { "tblidxb2.sn", TILE_OPC_TBLIDXB2_SN, 0x1 /* pipes */, 2 /* num_operands */,
10747 TREG_SN, /* implicitly_written_register */
10748 1, /* can_bundle */
10758 /* fixed_bit_masks */
10759 0x800000007ffff000ULL,
10766 /* fixed_bit_values */
10767 0x000000007816a000ULL,
10774 { "tblidxb3", TILE_OPC_TBLIDXB3, 0x5 /* pipes */, 2 /* num_operands */,
10775 TREG_ZERO, /* implicitly_written_register */
10776 1, /* can_bundle */
10786 /* fixed_bit_masks */
10787 0x800000007ffff000ULL,
10789 0x80000000780ff000ULL,
10794 /* fixed_bit_values */
10795 0x000000007016b000ULL,
10797 0x80000000680ab000ULL,
10802 { "tblidxb3.sn", TILE_OPC_TBLIDXB3_SN, 0x1 /* pipes */, 2 /* num_operands */,
10803 TREG_SN, /* implicitly_written_register */
10804 1, /* can_bundle */
10814 /* fixed_bit_masks */
10815 0x800000007ffff000ULL,
10822 /* fixed_bit_values */
10823 0x000000007816b000ULL,
10830 { "tns", TILE_OPC_TNS, 0x2 /* pipes */, 2 /* num_operands */,
10831 TREG_ZERO, /* implicitly_written_register */
10832 1, /* can_bundle */
10842 /* fixed_bit_masks */
10844 0xfffff80000000000ULL,
10850 /* fixed_bit_values */
10852 0x400bb00000000000ULL,
10858 { "tns.sn", TILE_OPC_TNS_SN, 0x2 /* pipes */, 2 /* num_operands */,
10859 TREG_SN, /* implicitly_written_register */
10860 1, /* can_bundle */
10870 /* fixed_bit_masks */
10872 0xfffff80000000000ULL,
10878 /* fixed_bit_values */
10880 0x440bb00000000000ULL,
10886 { "wh64", TILE_OPC_WH64, 0x2 /* pipes */, 1 /* num_operands */,
10887 TREG_ZERO, /* implicitly_written_register */
10888 1, /* can_bundle */
10898 /* fixed_bit_masks */
10900 0xfbfff80000000000ULL,
10906 /* fixed_bit_values */
10908 0x400bb80000000000ULL,
10914 { "xor", TILE_OPC_XOR, 0xf /* pipes */, 3 /* num_operands */,
10915 TREG_ZERO, /* implicitly_written_register */
10916 1, /* can_bundle */
10926 /* fixed_bit_masks */
10927 0x800000007ffc0000ULL,
10928 0xfffe000000000000ULL,
10929 0x80000000780c0000ULL,
10930 0xf806000000000000ULL,
10934 /* fixed_bit_values */
10935 0x0000000001780000ULL,
10936 0x0882000000000000ULL,
10937 0x80000000180c0000ULL,
10938 0x9806000000000000ULL,
10942 { "xor.sn", TILE_OPC_XOR_SN, 0x3 /* pipes */, 3 /* num_operands */,
10943 TREG_SN, /* implicitly_written_register */
10944 1, /* can_bundle */
10954 /* fixed_bit_masks */
10955 0x800000007ffc0000ULL,
10956 0xfffe000000000000ULL,
10962 /* fixed_bit_values */
10963 0x0000000009780000ULL,
10964 0x0c82000000000000ULL,
10970 { "xori", TILE_OPC_XORI, 0x3 /* pipes */, 3 /* num_operands */,
10971 TREG_ZERO, /* implicitly_written_register */
10972 1, /* can_bundle */
10982 /* fixed_bit_masks */
10983 0x800000007ff00000ULL,
10984 0xfff8000000000000ULL,
10990 /* fixed_bit_values */
10991 0x0000000050200000ULL,
10992 0x30a8000000000000ULL,
10998 { "xori.sn", TILE_OPC_XORI_SN, 0x3 /* pipes */, 3 /* num_operands */,
10999 TREG_SN, /* implicitly_written_register */
11000 1, /* can_bundle */
11010 /* fixed_bit_masks */
11011 0x800000007ff00000ULL,
11012 0xfff8000000000000ULL,
11018 /* fixed_bit_values */
11019 0x0000000058200000ULL,
11020 0x34a8000000000000ULL,
11026 { 0, TILE_OPC_NONE, 0, 0, 0, TREG_ZERO, { { 0, } }, { 0, }, { 0, }
11029 #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
11030 #define CHILD(array_index) (TILE_OPC_NONE + (array_index))
11032 static const unsigned short decode_X0_fsm[1153] =
11034 BITFIELD(22, 9) /* index 0 */,
11035 CHILD(513), CHILD(530), CHILD(547), CHILD(564), CHILD(596), CHILD(613),
11036 CHILD(630), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11037 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11038 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11039 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11040 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11041 TILE_OPC_NONE, CHILD(663), CHILD(680), CHILD(697), CHILD(714), CHILD(746),
11042 CHILD(763), CHILD(780), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11043 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11044 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11045 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11046 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11047 TILE_OPC_NONE, TILE_OPC_NONE, CHILD(813), CHILD(813), CHILD(813),
11048 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11049 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11050 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11051 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11052 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11053 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11054 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11055 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11056 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11057 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
11058 CHILD(813), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11059 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11060 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11061 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11062 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11063 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11064 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11065 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11066 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11067 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
11068 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(843),
11069 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11070 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11071 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11072 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11073 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11074 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11075 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11076 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11077 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11078 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11079 CHILD(843), CHILD(843), CHILD(843), CHILD(873), CHILD(878), CHILD(883),
11080 CHILD(903), CHILD(908), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11081 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11082 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11083 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11084 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11085 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(913),
11086 CHILD(918), CHILD(923), CHILD(943), CHILD(948), TILE_OPC_NONE,
11087 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11088 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11089 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11090 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11091 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11092 TILE_OPC_NONE, CHILD(953), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11093 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11094 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11095 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11096 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11097 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11098 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(988), TILE_OPC_NONE,
11099 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11100 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11101 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11102 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11103 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11104 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11105 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11106 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11107 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11108 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11109 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11110 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11111 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11112 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11113 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11114 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11115 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11116 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11117 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, CHILD(993),
11118 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11119 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11120 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11121 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11122 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11123 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11124 TILE_OPC_NONE, CHILD(1076), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11125 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11126 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11127 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11128 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11129 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11130 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11131 BITFIELD(18, 4) /* index 513 */,
11132 TILE_OPC_NONE, TILE_OPC_ADDB, TILE_OPC_ADDH, TILE_OPC_ADD,
11133 TILE_OPC_ADIFFB_U, TILE_OPC_ADIFFH, TILE_OPC_AND, TILE_OPC_AVGB_U,
11134 TILE_OPC_AVGH, TILE_OPC_CRC32_32, TILE_OPC_CRC32_8, TILE_OPC_INTHB,
11135 TILE_OPC_INTHH, TILE_OPC_INTLB, TILE_OPC_INTLH, TILE_OPC_MAXB_U,
11136 BITFIELD(18, 4) /* index 530 */,
11137 TILE_OPC_MAXH, TILE_OPC_MINB_U, TILE_OPC_MINH, TILE_OPC_MNZB, TILE_OPC_MNZH,
11138 TILE_OPC_MNZ, TILE_OPC_MULHHA_SS, TILE_OPC_MULHHA_SU, TILE_OPC_MULHHA_UU,
11139 TILE_OPC_MULHHSA_UU, TILE_OPC_MULHH_SS, TILE_OPC_MULHH_SU,
11140 TILE_OPC_MULHH_UU, TILE_OPC_MULHLA_SS, TILE_OPC_MULHLA_SU,
11141 TILE_OPC_MULHLA_US,
11142 BITFIELD(18, 4) /* index 547 */,
11143 TILE_OPC_MULHLA_UU, TILE_OPC_MULHLSA_UU, TILE_OPC_MULHL_SS,
11144 TILE_OPC_MULHL_SU, TILE_OPC_MULHL_US, TILE_OPC_MULHL_UU, TILE_OPC_MULLLA_SS,
11145 TILE_OPC_MULLLA_SU, TILE_OPC_MULLLA_UU, TILE_OPC_MULLLSA_UU,
11146 TILE_OPC_MULLL_SS, TILE_OPC_MULLL_SU, TILE_OPC_MULLL_UU, TILE_OPC_MVNZ,
11147 TILE_OPC_MVZ, TILE_OPC_MZB,
11148 BITFIELD(18, 4) /* index 564 */,
11149 TILE_OPC_MZH, TILE_OPC_MZ, TILE_OPC_NOR, CHILD(581), TILE_OPC_PACKHB,
11150 TILE_OPC_PACKLB, TILE_OPC_RL, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_S3A,
11151 TILE_OPC_SADAB_U, TILE_OPC_SADAH, TILE_OPC_SADAH_U, TILE_OPC_SADB_U,
11152 TILE_OPC_SADH, TILE_OPC_SADH_U,
11153 BITFIELD(12, 2) /* index 581 */,
11154 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(586),
11155 BITFIELD(14, 2) /* index 586 */,
11156 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(591),
11157 BITFIELD(16, 2) /* index 591 */,
11158 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE,
11159 BITFIELD(18, 4) /* index 596 */,
11160 TILE_OPC_SEQB, TILE_OPC_SEQH, TILE_OPC_SEQ, TILE_OPC_SHLB, TILE_OPC_SHLH,
11161 TILE_OPC_SHL, TILE_OPC_SHRB, TILE_OPC_SHRH, TILE_OPC_SHR, TILE_OPC_SLTB,
11162 TILE_OPC_SLTB_U, TILE_OPC_SLTEB, TILE_OPC_SLTEB_U, TILE_OPC_SLTEH,
11163 TILE_OPC_SLTEH_U, TILE_OPC_SLTE,
11164 BITFIELD(18, 4) /* index 613 */,
11165 TILE_OPC_SLTE_U, TILE_OPC_SLTH, TILE_OPC_SLTH_U, TILE_OPC_SLT,
11166 TILE_OPC_SLT_U, TILE_OPC_SNEB, TILE_OPC_SNEH, TILE_OPC_SNE, TILE_OPC_SRAB,
11167 TILE_OPC_SRAH, TILE_OPC_SRA, TILE_OPC_SUBB, TILE_OPC_SUBH, TILE_OPC_SUB,
11168 TILE_OPC_XOR, TILE_OPC_DWORD_ALIGN,
11169 BITFIELD(18, 3) /* index 630 */,
11170 CHILD(639), CHILD(642), CHILD(645), CHILD(648), CHILD(651), CHILD(654),
11171 CHILD(657), CHILD(660),
11172 BITFIELD(21, 1) /* index 639 */,
11173 TILE_OPC_ADDS, TILE_OPC_NONE,
11174 BITFIELD(21, 1) /* index 642 */,
11175 TILE_OPC_SUBS, TILE_OPC_NONE,
11176 BITFIELD(21, 1) /* index 645 */,
11177 TILE_OPC_ADDBS_U, TILE_OPC_NONE,
11178 BITFIELD(21, 1) /* index 648 */,
11179 TILE_OPC_ADDHS, TILE_OPC_NONE,
11180 BITFIELD(21, 1) /* index 651 */,
11181 TILE_OPC_SUBBS_U, TILE_OPC_NONE,
11182 BITFIELD(21, 1) /* index 654 */,
11183 TILE_OPC_SUBHS, TILE_OPC_NONE,
11184 BITFIELD(21, 1) /* index 657 */,
11185 TILE_OPC_PACKHS, TILE_OPC_NONE,
11186 BITFIELD(21, 1) /* index 660 */,
11187 TILE_OPC_PACKBS_U, TILE_OPC_NONE,
11188 BITFIELD(18, 4) /* index 663 */,
11189 TILE_OPC_NONE, TILE_OPC_ADDB_SN, TILE_OPC_ADDH_SN, TILE_OPC_ADD_SN,
11190 TILE_OPC_ADIFFB_U_SN, TILE_OPC_ADIFFH_SN, TILE_OPC_AND_SN,
11191 TILE_OPC_AVGB_U_SN, TILE_OPC_AVGH_SN, TILE_OPC_CRC32_32_SN,
11192 TILE_OPC_CRC32_8_SN, TILE_OPC_INTHB_SN, TILE_OPC_INTHH_SN,
11193 TILE_OPC_INTLB_SN, TILE_OPC_INTLH_SN, TILE_OPC_MAXB_U_SN,
11194 BITFIELD(18, 4) /* index 680 */,
11195 TILE_OPC_MAXH_SN, TILE_OPC_MINB_U_SN, TILE_OPC_MINH_SN, TILE_OPC_MNZB_SN,
11196 TILE_OPC_MNZH_SN, TILE_OPC_MNZ_SN, TILE_OPC_MULHHA_SS_SN,
11197 TILE_OPC_MULHHA_SU_SN, TILE_OPC_MULHHA_UU_SN, TILE_OPC_MULHHSA_UU_SN,
11198 TILE_OPC_MULHH_SS_SN, TILE_OPC_MULHH_SU_SN, TILE_OPC_MULHH_UU_SN,
11199 TILE_OPC_MULHLA_SS_SN, TILE_OPC_MULHLA_SU_SN, TILE_OPC_MULHLA_US_SN,
11200 BITFIELD(18, 4) /* index 697 */,
11201 TILE_OPC_MULHLA_UU_SN, TILE_OPC_MULHLSA_UU_SN, TILE_OPC_MULHL_SS_SN,
11202 TILE_OPC_MULHL_SU_SN, TILE_OPC_MULHL_US_SN, TILE_OPC_MULHL_UU_SN,
11203 TILE_OPC_MULLLA_SS_SN, TILE_OPC_MULLLA_SU_SN, TILE_OPC_MULLLA_UU_SN,
11204 TILE_OPC_MULLLSA_UU_SN, TILE_OPC_MULLL_SS_SN, TILE_OPC_MULLL_SU_SN,
11205 TILE_OPC_MULLL_UU_SN, TILE_OPC_MVNZ_SN, TILE_OPC_MVZ_SN, TILE_OPC_MZB_SN,
11206 BITFIELD(18, 4) /* index 714 */,
11207 TILE_OPC_MZH_SN, TILE_OPC_MZ_SN, TILE_OPC_NOR_SN, CHILD(731),
11208 TILE_OPC_PACKHB_SN, TILE_OPC_PACKLB_SN, TILE_OPC_RL_SN, TILE_OPC_S1A_SN,
11209 TILE_OPC_S2A_SN, TILE_OPC_S3A_SN, TILE_OPC_SADAB_U_SN, TILE_OPC_SADAH_SN,
11210 TILE_OPC_SADAH_U_SN, TILE_OPC_SADB_U_SN, TILE_OPC_SADH_SN,
11211 TILE_OPC_SADH_U_SN,
11212 BITFIELD(12, 2) /* index 731 */,
11213 TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(736),
11214 BITFIELD(14, 2) /* index 736 */,
11215 TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(741),
11216 BITFIELD(16, 2) /* index 741 */,
11217 TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_MOVE_SN,
11218 BITFIELD(18, 4) /* index 746 */,
11219 TILE_OPC_SEQB_SN, TILE_OPC_SEQH_SN, TILE_OPC_SEQ_SN, TILE_OPC_SHLB_SN,
11220 TILE_OPC_SHLH_SN, TILE_OPC_SHL_SN, TILE_OPC_SHRB_SN, TILE_OPC_SHRH_SN,
11221 TILE_OPC_SHR_SN, TILE_OPC_SLTB_SN, TILE_OPC_SLTB_U_SN, TILE_OPC_SLTEB_SN,
11222 TILE_OPC_SLTEB_U_SN, TILE_OPC_SLTEH_SN, TILE_OPC_SLTEH_U_SN,
11224 BITFIELD(18, 4) /* index 763 */,
11225 TILE_OPC_SLTE_U_SN, TILE_OPC_SLTH_SN, TILE_OPC_SLTH_U_SN, TILE_OPC_SLT_SN,
11226 TILE_OPC_SLT_U_SN, TILE_OPC_SNEB_SN, TILE_OPC_SNEH_SN, TILE_OPC_SNE_SN,
11227 TILE_OPC_SRAB_SN, TILE_OPC_SRAH_SN, TILE_OPC_SRA_SN, TILE_OPC_SUBB_SN,
11228 TILE_OPC_SUBH_SN, TILE_OPC_SUB_SN, TILE_OPC_XOR_SN, TILE_OPC_DWORD_ALIGN_SN,
11229 BITFIELD(18, 3) /* index 780 */,
11230 CHILD(789), CHILD(792), CHILD(795), CHILD(798), CHILD(801), CHILD(804),
11231 CHILD(807), CHILD(810),
11232 BITFIELD(21, 1) /* index 789 */,
11233 TILE_OPC_ADDS_SN, TILE_OPC_NONE,
11234 BITFIELD(21, 1) /* index 792 */,
11235 TILE_OPC_SUBS_SN, TILE_OPC_NONE,
11236 BITFIELD(21, 1) /* index 795 */,
11237 TILE_OPC_ADDBS_U_SN, TILE_OPC_NONE,
11238 BITFIELD(21, 1) /* index 798 */,
11239 TILE_OPC_ADDHS_SN, TILE_OPC_NONE,
11240 BITFIELD(21, 1) /* index 801 */,
11241 TILE_OPC_SUBBS_U_SN, TILE_OPC_NONE,
11242 BITFIELD(21, 1) /* index 804 */,
11243 TILE_OPC_SUBHS_SN, TILE_OPC_NONE,
11244 BITFIELD(21, 1) /* index 807 */,
11245 TILE_OPC_PACKHS_SN, TILE_OPC_NONE,
11246 BITFIELD(21, 1) /* index 810 */,
11247 TILE_OPC_PACKBS_U_SN, TILE_OPC_NONE,
11248 BITFIELD(6, 2) /* index 813 */,
11249 TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(818),
11250 BITFIELD(8, 2) /* index 818 */,
11251 TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(823),
11252 BITFIELD(10, 2) /* index 823 */,
11253 TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_MOVELI_SN,
11254 BITFIELD(6, 2) /* index 828 */,
11255 TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(833),
11256 BITFIELD(8, 2) /* index 833 */,
11257 TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(838),
11258 BITFIELD(10, 2) /* index 838 */,
11259 TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_MOVELI,
11260 BITFIELD(0, 2) /* index 843 */,
11261 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(848),
11262 BITFIELD(2, 2) /* index 848 */,
11263 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(853),
11264 BITFIELD(4, 2) /* index 853 */,
11265 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(858),
11266 BITFIELD(6, 2) /* index 858 */,
11267 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(863),
11268 BITFIELD(8, 2) /* index 863 */,
11269 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(868),
11270 BITFIELD(10, 2) /* index 868 */,
11271 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_INFOL,
11272 BITFIELD(20, 2) /* index 873 */,
11273 TILE_OPC_NONE, TILE_OPC_ADDIB, TILE_OPC_ADDIH, TILE_OPC_ADDI,
11274 BITFIELD(20, 2) /* index 878 */,
11275 TILE_OPC_MAXIB_U, TILE_OPC_MAXIH, TILE_OPC_MINIB_U, TILE_OPC_MINIH,
11276 BITFIELD(20, 2) /* index 883 */,
11277 CHILD(888), TILE_OPC_SEQIB, TILE_OPC_SEQIH, TILE_OPC_SEQI,
11278 BITFIELD(6, 2) /* index 888 */,
11279 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(893),
11280 BITFIELD(8, 2) /* index 893 */,
11281 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(898),
11282 BITFIELD(10, 2) /* index 898 */,
11283 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI,
11284 BITFIELD(20, 2) /* index 903 */,
11285 TILE_OPC_SLTIB, TILE_OPC_SLTIB_U, TILE_OPC_SLTIH, TILE_OPC_SLTIH_U,
11286 BITFIELD(20, 2) /* index 908 */,
11287 TILE_OPC_SLTI, TILE_OPC_SLTI_U, TILE_OPC_NONE, TILE_OPC_NONE,
11288 BITFIELD(20, 2) /* index 913 */,
11289 TILE_OPC_NONE, TILE_OPC_ADDIB_SN, TILE_OPC_ADDIH_SN, TILE_OPC_ADDI_SN,
11290 BITFIELD(20, 2) /* index 918 */,
11291 TILE_OPC_MAXIB_U_SN, TILE_OPC_MAXIH_SN, TILE_OPC_MINIB_U_SN,
11293 BITFIELD(20, 2) /* index 923 */,
11294 CHILD(928), TILE_OPC_SEQIB_SN, TILE_OPC_SEQIH_SN, TILE_OPC_SEQI_SN,
11295 BITFIELD(6, 2) /* index 928 */,
11296 TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(933),
11297 BITFIELD(8, 2) /* index 933 */,
11298 TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(938),
11299 BITFIELD(10, 2) /* index 938 */,
11300 TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_MOVEI_SN,
11301 BITFIELD(20, 2) /* index 943 */,
11302 TILE_OPC_SLTIB_SN, TILE_OPC_SLTIB_U_SN, TILE_OPC_SLTIH_SN,
11303 TILE_OPC_SLTIH_U_SN,
11304 BITFIELD(20, 2) /* index 948 */,
11305 TILE_OPC_SLTI_SN, TILE_OPC_SLTI_U_SN, TILE_OPC_NONE, TILE_OPC_NONE,
11306 BITFIELD(20, 2) /* index 953 */,
11307 TILE_OPC_NONE, CHILD(958), TILE_OPC_XORI, TILE_OPC_NONE,
11308 BITFIELD(0, 2) /* index 958 */,
11309 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(963),
11310 BITFIELD(2, 2) /* index 963 */,
11311 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(968),
11312 BITFIELD(4, 2) /* index 968 */,
11313 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(973),
11314 BITFIELD(6, 2) /* index 973 */,
11315 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(978),
11316 BITFIELD(8, 2) /* index 978 */,
11317 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(983),
11318 BITFIELD(10, 2) /* index 983 */,
11319 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO,
11320 BITFIELD(20, 2) /* index 988 */,
11321 TILE_OPC_NONE, TILE_OPC_ANDI_SN, TILE_OPC_XORI_SN, TILE_OPC_NONE,
11322 BITFIELD(17, 5) /* index 993 */,
11323 TILE_OPC_NONE, TILE_OPC_RLI, TILE_OPC_SHLIB, TILE_OPC_SHLIH, TILE_OPC_SHLI,
11324 TILE_OPC_SHRIB, TILE_OPC_SHRIH, TILE_OPC_SHRI, TILE_OPC_SRAIB,
11325 TILE_OPC_SRAIH, TILE_OPC_SRAI, CHILD(1026), TILE_OPC_NONE, TILE_OPC_NONE,
11326 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11327 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11328 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11329 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11330 BITFIELD(12, 4) /* index 1026 */,
11331 TILE_OPC_NONE, CHILD(1043), CHILD(1046), CHILD(1049), CHILD(1052),
11332 CHILD(1055), CHILD(1058), CHILD(1061), CHILD(1064), CHILD(1067),
11333 CHILD(1070), CHILD(1073), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11335 BITFIELD(16, 1) /* index 1043 */,
11336 TILE_OPC_BITX, TILE_OPC_NONE,
11337 BITFIELD(16, 1) /* index 1046 */,
11338 TILE_OPC_BYTEX, TILE_OPC_NONE,
11339 BITFIELD(16, 1) /* index 1049 */,
11340 TILE_OPC_CLZ, TILE_OPC_NONE,
11341 BITFIELD(16, 1) /* index 1052 */,
11342 TILE_OPC_CTZ, TILE_OPC_NONE,
11343 BITFIELD(16, 1) /* index 1055 */,
11344 TILE_OPC_FNOP, TILE_OPC_NONE,
11345 BITFIELD(16, 1) /* index 1058 */,
11346 TILE_OPC_NOP, TILE_OPC_NONE,
11347 BITFIELD(16, 1) /* index 1061 */,
11348 TILE_OPC_PCNT, TILE_OPC_NONE,
11349 BITFIELD(16, 1) /* index 1064 */,
11350 TILE_OPC_TBLIDXB0, TILE_OPC_NONE,
11351 BITFIELD(16, 1) /* index 1067 */,
11352 TILE_OPC_TBLIDXB1, TILE_OPC_NONE,
11353 BITFIELD(16, 1) /* index 1070 */,
11354 TILE_OPC_TBLIDXB2, TILE_OPC_NONE,
11355 BITFIELD(16, 1) /* index 1073 */,
11356 TILE_OPC_TBLIDXB3, TILE_OPC_NONE,
11357 BITFIELD(17, 5) /* index 1076 */,
11358 TILE_OPC_NONE, TILE_OPC_RLI_SN, TILE_OPC_SHLIB_SN, TILE_OPC_SHLIH_SN,
11359 TILE_OPC_SHLI_SN, TILE_OPC_SHRIB_SN, TILE_OPC_SHRIH_SN, TILE_OPC_SHRI_SN,
11360 TILE_OPC_SRAIB_SN, TILE_OPC_SRAIH_SN, TILE_OPC_SRAI_SN, CHILD(1109),
11361 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11362 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11363 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11364 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11365 BITFIELD(12, 4) /* index 1109 */,
11366 TILE_OPC_NONE, CHILD(1126), CHILD(1129), CHILD(1132), CHILD(1135),
11367 CHILD(1055), CHILD(1058), CHILD(1138), CHILD(1141), CHILD(1144),
11368 CHILD(1147), CHILD(1150), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11370 BITFIELD(16, 1) /* index 1126 */,
11371 TILE_OPC_BITX_SN, TILE_OPC_NONE,
11372 BITFIELD(16, 1) /* index 1129 */,
11373 TILE_OPC_BYTEX_SN, TILE_OPC_NONE,
11374 BITFIELD(16, 1) /* index 1132 */,
11375 TILE_OPC_CLZ_SN, TILE_OPC_NONE,
11376 BITFIELD(16, 1) /* index 1135 */,
11377 TILE_OPC_CTZ_SN, TILE_OPC_NONE,
11378 BITFIELD(16, 1) /* index 1138 */,
11379 TILE_OPC_PCNT_SN, TILE_OPC_NONE,
11380 BITFIELD(16, 1) /* index 1141 */,
11381 TILE_OPC_TBLIDXB0_SN, TILE_OPC_NONE,
11382 BITFIELD(16, 1) /* index 1144 */,
11383 TILE_OPC_TBLIDXB1_SN, TILE_OPC_NONE,
11384 BITFIELD(16, 1) /* index 1147 */,
11385 TILE_OPC_TBLIDXB2_SN, TILE_OPC_NONE,
11386 BITFIELD(16, 1) /* index 1150 */,
11387 TILE_OPC_TBLIDXB3_SN, TILE_OPC_NONE,
11390 static const unsigned short decode_X1_fsm[1509] =
11392 BITFIELD(54, 9) /* index 0 */,
11393 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11394 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11395 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11396 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11397 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11398 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11399 TILE_OPC_NONE, TILE_OPC_NONE, CHILD(513), CHILD(561), CHILD(594),
11400 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11401 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11402 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(641), CHILD(689),
11403 CHILD(722), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11404 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11405 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(766),
11406 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
11407 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
11408 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
11409 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
11410 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
11411 CHILD(766), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
11412 CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
11413 CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
11414 CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
11415 CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
11416 CHILD(781), CHILD(781), CHILD(781), CHILD(796), CHILD(796), CHILD(796),
11417 CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
11418 CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
11419 CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
11420 CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
11421 CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(826),
11422 CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826),
11423 CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826),
11424 CHILD(826), CHILD(826), CHILD(826), CHILD(843), CHILD(843), CHILD(843),
11425 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11426 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
11427 CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932), TILE_OPC_NONE,
11428 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11429 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11430 TILE_OPC_NONE, CHILD(941), CHILD(950), CHILD(974), CHILD(983),
11431 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11432 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11433 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11434 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11435 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11436 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11437 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11438 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM,
11439 TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, CHILD(992),
11440 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11441 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11442 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11443 CHILD(1303), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11444 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11445 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11446 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11447 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11448 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11449 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11450 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11451 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11452 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_J, TILE_OPC_J,
11453 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11454 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11455 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11456 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11457 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11458 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11459 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11460 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11461 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11462 TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J,
11463 TILE_OPC_J, TILE_OPC_J, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11464 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11465 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11466 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11467 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11468 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11469 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11470 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11471 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11472 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11473 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11474 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11475 TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL,
11476 TILE_OPC_JAL, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11477 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11478 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11479 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11480 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11481 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11482 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11483 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11484 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11485 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11486 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11487 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11488 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11489 BITFIELD(49, 5) /* index 513 */,
11490 TILE_OPC_NONE, TILE_OPC_ADDB, TILE_OPC_ADDH, TILE_OPC_ADD, TILE_OPC_AND,
11491 TILE_OPC_INTHB, TILE_OPC_INTHH, TILE_OPC_INTLB, TILE_OPC_INTLH,
11492 TILE_OPC_JALRP, TILE_OPC_JALR, TILE_OPC_JRP, TILE_OPC_JR, TILE_OPC_LNK,
11493 TILE_OPC_MAXB_U, TILE_OPC_MAXH, TILE_OPC_MINB_U, TILE_OPC_MINH,
11494 TILE_OPC_MNZB, TILE_OPC_MNZH, TILE_OPC_MNZ, TILE_OPC_MZB, TILE_OPC_MZH,
11495 TILE_OPC_MZ, TILE_OPC_NOR, CHILD(546), TILE_OPC_PACKHB, TILE_OPC_PACKLB,
11496 TILE_OPC_RL, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_S3A,
11497 BITFIELD(43, 2) /* index 546 */,
11498 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(551),
11499 BITFIELD(45, 2) /* index 551 */,
11500 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(556),
11501 BITFIELD(47, 2) /* index 556 */,
11502 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE,
11503 BITFIELD(49, 5) /* index 561 */,
11504 TILE_OPC_SB, TILE_OPC_SEQB, TILE_OPC_SEQH, TILE_OPC_SEQ, TILE_OPC_SHLB,
11505 TILE_OPC_SHLH, TILE_OPC_SHL, TILE_OPC_SHRB, TILE_OPC_SHRH, TILE_OPC_SHR,
11506 TILE_OPC_SH, TILE_OPC_SLTB, TILE_OPC_SLTB_U, TILE_OPC_SLTEB,
11507 TILE_OPC_SLTEB_U, TILE_OPC_SLTEH, TILE_OPC_SLTEH_U, TILE_OPC_SLTE,
11508 TILE_OPC_SLTE_U, TILE_OPC_SLTH, TILE_OPC_SLTH_U, TILE_OPC_SLT,
11509 TILE_OPC_SLT_U, TILE_OPC_SNEB, TILE_OPC_SNEH, TILE_OPC_SNE, TILE_OPC_SRAB,
11510 TILE_OPC_SRAH, TILE_OPC_SRA, TILE_OPC_SUBB, TILE_OPC_SUBH, TILE_OPC_SUB,
11511 BITFIELD(49, 4) /* index 594 */,
11512 CHILD(611), CHILD(614), CHILD(617), CHILD(620), CHILD(623), CHILD(626),
11513 CHILD(629), CHILD(632), CHILD(635), CHILD(638), TILE_OPC_NONE,
11514 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11515 BITFIELD(53, 1) /* index 611 */,
11516 TILE_OPC_SW, TILE_OPC_NONE,
11517 BITFIELD(53, 1) /* index 614 */,
11518 TILE_OPC_XOR, TILE_OPC_NONE,
11519 BITFIELD(53, 1) /* index 617 */,
11520 TILE_OPC_ADDS, TILE_OPC_NONE,
11521 BITFIELD(53, 1) /* index 620 */,
11522 TILE_OPC_SUBS, TILE_OPC_NONE,
11523 BITFIELD(53, 1) /* index 623 */,
11524 TILE_OPC_ADDBS_U, TILE_OPC_NONE,
11525 BITFIELD(53, 1) /* index 626 */,
11526 TILE_OPC_ADDHS, TILE_OPC_NONE,
11527 BITFIELD(53, 1) /* index 629 */,
11528 TILE_OPC_SUBBS_U, TILE_OPC_NONE,
11529 BITFIELD(53, 1) /* index 632 */,
11530 TILE_OPC_SUBHS, TILE_OPC_NONE,
11531 BITFIELD(53, 1) /* index 635 */,
11532 TILE_OPC_PACKHS, TILE_OPC_NONE,
11533 BITFIELD(53, 1) /* index 638 */,
11534 TILE_OPC_PACKBS_U, TILE_OPC_NONE,
11535 BITFIELD(49, 5) /* index 641 */,
11536 TILE_OPC_NONE, TILE_OPC_ADDB_SN, TILE_OPC_ADDH_SN, TILE_OPC_ADD_SN,
11537 TILE_OPC_AND_SN, TILE_OPC_INTHB_SN, TILE_OPC_INTHH_SN, TILE_OPC_INTLB_SN,
11538 TILE_OPC_INTLH_SN, TILE_OPC_JALRP, TILE_OPC_JALR, TILE_OPC_JRP, TILE_OPC_JR,
11539 TILE_OPC_LNK_SN, TILE_OPC_MAXB_U_SN, TILE_OPC_MAXH_SN, TILE_OPC_MINB_U_SN,
11540 TILE_OPC_MINH_SN, TILE_OPC_MNZB_SN, TILE_OPC_MNZH_SN, TILE_OPC_MNZ_SN,
11541 TILE_OPC_MZB_SN, TILE_OPC_MZH_SN, TILE_OPC_MZ_SN, TILE_OPC_NOR_SN,
11542 CHILD(674), TILE_OPC_PACKHB_SN, TILE_OPC_PACKLB_SN, TILE_OPC_RL_SN,
11543 TILE_OPC_S1A_SN, TILE_OPC_S2A_SN, TILE_OPC_S3A_SN,
11544 BITFIELD(43, 2) /* index 674 */,
11545 TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(679),
11546 BITFIELD(45, 2) /* index 679 */,
11547 TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(684),
11548 BITFIELD(47, 2) /* index 684 */,
11549 TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_MOVE_SN,
11550 BITFIELD(49, 5) /* index 689 */,
11551 TILE_OPC_SB, TILE_OPC_SEQB_SN, TILE_OPC_SEQH_SN, TILE_OPC_SEQ_SN,
11552 TILE_OPC_SHLB_SN, TILE_OPC_SHLH_SN, TILE_OPC_SHL_SN, TILE_OPC_SHRB_SN,
11553 TILE_OPC_SHRH_SN, TILE_OPC_SHR_SN, TILE_OPC_SH, TILE_OPC_SLTB_SN,
11554 TILE_OPC_SLTB_U_SN, TILE_OPC_SLTEB_SN, TILE_OPC_SLTEB_U_SN,
11555 TILE_OPC_SLTEH_SN, TILE_OPC_SLTEH_U_SN, TILE_OPC_SLTE_SN,
11556 TILE_OPC_SLTE_U_SN, TILE_OPC_SLTH_SN, TILE_OPC_SLTH_U_SN, TILE_OPC_SLT_SN,
11557 TILE_OPC_SLT_U_SN, TILE_OPC_SNEB_SN, TILE_OPC_SNEH_SN, TILE_OPC_SNE_SN,
11558 TILE_OPC_SRAB_SN, TILE_OPC_SRAH_SN, TILE_OPC_SRA_SN, TILE_OPC_SUBB_SN,
11559 TILE_OPC_SUBH_SN, TILE_OPC_SUB_SN,
11560 BITFIELD(49, 4) /* index 722 */,
11561 CHILD(611), CHILD(739), CHILD(742), CHILD(745), CHILD(748), CHILD(751),
11562 CHILD(754), CHILD(757), CHILD(760), CHILD(763), TILE_OPC_NONE,
11563 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11564 BITFIELD(53, 1) /* index 739 */,
11565 TILE_OPC_XOR_SN, TILE_OPC_NONE,
11566 BITFIELD(53, 1) /* index 742 */,
11567 TILE_OPC_ADDS_SN, TILE_OPC_NONE,
11568 BITFIELD(53, 1) /* index 745 */,
11569 TILE_OPC_SUBS_SN, TILE_OPC_NONE,
11570 BITFIELD(53, 1) /* index 748 */,
11571 TILE_OPC_ADDBS_U_SN, TILE_OPC_NONE,
11572 BITFIELD(53, 1) /* index 751 */,
11573 TILE_OPC_ADDHS_SN, TILE_OPC_NONE,
11574 BITFIELD(53, 1) /* index 754 */,
11575 TILE_OPC_SUBBS_U_SN, TILE_OPC_NONE,
11576 BITFIELD(53, 1) /* index 757 */,
11577 TILE_OPC_SUBHS_SN, TILE_OPC_NONE,
11578 BITFIELD(53, 1) /* index 760 */,
11579 TILE_OPC_PACKHS_SN, TILE_OPC_NONE,
11580 BITFIELD(53, 1) /* index 763 */,
11581 TILE_OPC_PACKBS_U_SN, TILE_OPC_NONE,
11582 BITFIELD(37, 2) /* index 766 */,
11583 TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(771),
11584 BITFIELD(39, 2) /* index 771 */,
11585 TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(776),
11586 BITFIELD(41, 2) /* index 776 */,
11587 TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_MOVELI_SN,
11588 BITFIELD(37, 2) /* index 781 */,
11589 TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(786),
11590 BITFIELD(39, 2) /* index 786 */,
11591 TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(791),
11592 BITFIELD(41, 2) /* index 791 */,
11593 TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_MOVELI,
11594 BITFIELD(31, 2) /* index 796 */,
11595 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(801),
11596 BITFIELD(33, 2) /* index 801 */,
11597 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(806),
11598 BITFIELD(35, 2) /* index 806 */,
11599 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(811),
11600 BITFIELD(37, 2) /* index 811 */,
11601 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(816),
11602 BITFIELD(39, 2) /* index 816 */,
11603 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(821),
11604 BITFIELD(41, 2) /* index 821 */,
11605 TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_INFOL,
11606 BITFIELD(31, 4) /* index 826 */,
11607 TILE_OPC_BZ, TILE_OPC_BZT, TILE_OPC_BNZ, TILE_OPC_BNZT, TILE_OPC_BGZ,
11608 TILE_OPC_BGZT, TILE_OPC_BGEZ, TILE_OPC_BGEZT, TILE_OPC_BLZ, TILE_OPC_BLZT,
11609 TILE_OPC_BLEZ, TILE_OPC_BLEZT, TILE_OPC_BBS, TILE_OPC_BBST, TILE_OPC_BBNS,
11611 BITFIELD(31, 4) /* index 843 */,
11612 TILE_OPC_BZ_SN, TILE_OPC_BZT_SN, TILE_OPC_BNZ_SN, TILE_OPC_BNZT_SN,
11613 TILE_OPC_BGZ_SN, TILE_OPC_BGZT_SN, TILE_OPC_BGEZ_SN, TILE_OPC_BGEZT_SN,
11614 TILE_OPC_BLZ_SN, TILE_OPC_BLZT_SN, TILE_OPC_BLEZ_SN, TILE_OPC_BLEZT_SN,
11615 TILE_OPC_BBS_SN, TILE_OPC_BBST_SN, TILE_OPC_BBNS_SN, TILE_OPC_BBNST_SN,
11616 BITFIELD(51, 3) /* index 860 */,
11617 TILE_OPC_NONE, TILE_OPC_ADDIB, TILE_OPC_ADDIH, TILE_OPC_ADDI, CHILD(869),
11618 TILE_OPC_MAXIB_U, TILE_OPC_MAXIH, TILE_OPC_MFSPR,
11619 BITFIELD(31, 2) /* index 869 */,
11620 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(874),
11621 BITFIELD(33, 2) /* index 874 */,
11622 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(879),
11623 BITFIELD(35, 2) /* index 879 */,
11624 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(884),
11625 BITFIELD(37, 2) /* index 884 */,
11626 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(889),
11627 BITFIELD(39, 2) /* index 889 */,
11628 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(894),
11629 BITFIELD(41, 2) /* index 894 */,
11630 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO,
11631 BITFIELD(51, 3) /* index 899 */,
11632 TILE_OPC_MINIB_U, TILE_OPC_MINIH, TILE_OPC_MTSPR, CHILD(908),
11633 TILE_OPC_SEQIB, TILE_OPC_SEQIH, TILE_OPC_SEQI, TILE_OPC_SLTIB,
11634 BITFIELD(37, 2) /* index 908 */,
11635 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(913),
11636 BITFIELD(39, 2) /* index 913 */,
11637 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(918),
11638 BITFIELD(41, 2) /* index 918 */,
11639 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI,
11640 BITFIELD(51, 3) /* index 923 */,
11641 TILE_OPC_SLTIB_U, TILE_OPC_SLTIH, TILE_OPC_SLTIH_U, TILE_OPC_SLTI,
11642 TILE_OPC_SLTI_U, TILE_OPC_XORI, TILE_OPC_LBADD, TILE_OPC_LBADD_U,
11643 BITFIELD(51, 3) /* index 932 */,
11644 TILE_OPC_LHADD, TILE_OPC_LHADD_U, TILE_OPC_LWADD, TILE_OPC_LWADD_NA,
11645 TILE_OPC_SBADD, TILE_OPC_SHADD, TILE_OPC_SWADD, TILE_OPC_NONE,
11646 BITFIELD(51, 3) /* index 941 */,
11647 TILE_OPC_NONE, TILE_OPC_ADDIB_SN, TILE_OPC_ADDIH_SN, TILE_OPC_ADDI_SN,
11648 TILE_OPC_ANDI_SN, TILE_OPC_MAXIB_U_SN, TILE_OPC_MAXIH_SN, TILE_OPC_MFSPR,
11649 BITFIELD(51, 3) /* index 950 */,
11650 TILE_OPC_MINIB_U_SN, TILE_OPC_MINIH_SN, TILE_OPC_MTSPR, CHILD(959),
11651 TILE_OPC_SEQIB_SN, TILE_OPC_SEQIH_SN, TILE_OPC_SEQI_SN, TILE_OPC_SLTIB_SN,
11652 BITFIELD(37, 2) /* index 959 */,
11653 TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(964),
11654 BITFIELD(39, 2) /* index 964 */,
11655 TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(969),
11656 BITFIELD(41, 2) /* index 969 */,
11657 TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_MOVEI_SN,
11658 BITFIELD(51, 3) /* index 974 */,
11659 TILE_OPC_SLTIB_U_SN, TILE_OPC_SLTIH_SN, TILE_OPC_SLTIH_U_SN,
11660 TILE_OPC_SLTI_SN, TILE_OPC_SLTI_U_SN, TILE_OPC_XORI_SN, TILE_OPC_LBADD_SN,
11661 TILE_OPC_LBADD_U_SN,
11662 BITFIELD(51, 3) /* index 983 */,
11663 TILE_OPC_LHADD_SN, TILE_OPC_LHADD_U_SN, TILE_OPC_LWADD_SN,
11664 TILE_OPC_LWADD_NA_SN, TILE_OPC_SBADD, TILE_OPC_SHADD, TILE_OPC_SWADD,
11666 BITFIELD(46, 7) /* index 992 */,
11667 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1121),
11668 CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124), CHILD(1124),
11669 CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127), CHILD(1127),
11670 CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130), CHILD(1130),
11671 CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1136),
11672 CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139), CHILD(1139),
11673 CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), CHILD(1142),
11674 CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), CHILD(1145),
11675 CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1151),
11676 CHILD(1211), CHILD(1259), CHILD(1292), TILE_OPC_NONE, TILE_OPC_NONE,
11677 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11678 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11679 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11680 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11681 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11682 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11683 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11684 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11685 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11686 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11687 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11688 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11689 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11690 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11691 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11692 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11693 BITFIELD(53, 1) /* index 1121 */,
11694 TILE_OPC_RLI, TILE_OPC_NONE,
11695 BITFIELD(53, 1) /* index 1124 */,
11696 TILE_OPC_SHLIB, TILE_OPC_NONE,
11697 BITFIELD(53, 1) /* index 1127 */,
11698 TILE_OPC_SHLIH, TILE_OPC_NONE,
11699 BITFIELD(53, 1) /* index 1130 */,
11700 TILE_OPC_SHLI, TILE_OPC_NONE,
11701 BITFIELD(53, 1) /* index 1133 */,
11702 TILE_OPC_SHRIB, TILE_OPC_NONE,
11703 BITFIELD(53, 1) /* index 1136 */,
11704 TILE_OPC_SHRIH, TILE_OPC_NONE,
11705 BITFIELD(53, 1) /* index 1139 */,
11706 TILE_OPC_SHRI, TILE_OPC_NONE,
11707 BITFIELD(53, 1) /* index 1142 */,
11708 TILE_OPC_SRAIB, TILE_OPC_NONE,
11709 BITFIELD(53, 1) /* index 1145 */,
11710 TILE_OPC_SRAIH, TILE_OPC_NONE,
11711 BITFIELD(53, 1) /* index 1148 */,
11712 TILE_OPC_SRAI, TILE_OPC_NONE,
11713 BITFIELD(43, 3) /* index 1151 */,
11714 TILE_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169),
11715 CHILD(1172), CHILD(1175), CHILD(1178),
11716 BITFIELD(53, 1) /* index 1160 */,
11717 TILE_OPC_DRAIN, TILE_OPC_NONE,
11718 BITFIELD(53, 1) /* index 1163 */,
11719 TILE_OPC_DTLBPR, TILE_OPC_NONE,
11720 BITFIELD(53, 1) /* index 1166 */,
11721 TILE_OPC_FINV, TILE_OPC_NONE,
11722 BITFIELD(53, 1) /* index 1169 */,
11723 TILE_OPC_FLUSH, TILE_OPC_NONE,
11724 BITFIELD(53, 1) /* index 1172 */,
11725 TILE_OPC_FNOP, TILE_OPC_NONE,
11726 BITFIELD(53, 1) /* index 1175 */,
11727 TILE_OPC_ICOH, TILE_OPC_NONE,
11728 BITFIELD(53, 1) /* index 1178 */,
11729 CHILD(1181), TILE_OPC_NONE,
11730 BITFIELD(31, 2) /* index 1181 */,
11731 CHILD(1186), TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL,
11732 BITFIELD(33, 2) /* index 1186 */,
11733 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1191),
11734 BITFIELD(35, 2) /* index 1191 */,
11735 TILE_OPC_ILL, CHILD(1196), TILE_OPC_ILL, TILE_OPC_ILL,
11736 BITFIELD(37, 2) /* index 1196 */,
11737 TILE_OPC_ILL, CHILD(1201), TILE_OPC_ILL, TILE_OPC_ILL,
11738 BITFIELD(39, 2) /* index 1201 */,
11739 TILE_OPC_ILL, CHILD(1206), TILE_OPC_ILL, TILE_OPC_ILL,
11740 BITFIELD(41, 2) /* index 1206 */,
11741 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_BPT, TILE_OPC_ILL,
11742 BITFIELD(43, 3) /* index 1211 */,
11743 CHILD(1220), CHILD(1223), CHILD(1226), CHILD(1244), CHILD(1247),
11744 CHILD(1250), CHILD(1253), CHILD(1256),
11745 BITFIELD(53, 1) /* index 1220 */,
11746 TILE_OPC_INV, TILE_OPC_NONE,
11747 BITFIELD(53, 1) /* index 1223 */,
11748 TILE_OPC_IRET, TILE_OPC_NONE,
11749 BITFIELD(53, 1) /* index 1226 */,
11750 CHILD(1229), TILE_OPC_NONE,
11751 BITFIELD(31, 2) /* index 1229 */,
11752 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1234),
11753 BITFIELD(33, 2) /* index 1234 */,
11754 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1239),
11755 BITFIELD(35, 2) /* index 1239 */,
11756 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH,
11757 BITFIELD(53, 1) /* index 1244 */,
11758 TILE_OPC_LB_U, TILE_OPC_NONE,
11759 BITFIELD(53, 1) /* index 1247 */,
11760 TILE_OPC_LH, TILE_OPC_NONE,
11761 BITFIELD(53, 1) /* index 1250 */,
11762 TILE_OPC_LH_U, TILE_OPC_NONE,
11763 BITFIELD(53, 1) /* index 1253 */,
11764 TILE_OPC_LW, TILE_OPC_NONE,
11765 BITFIELD(53, 1) /* index 1256 */,
11766 TILE_OPC_MF, TILE_OPC_NONE,
11767 BITFIELD(43, 3) /* index 1259 */,
11768 CHILD(1268), CHILD(1271), CHILD(1274), CHILD(1277), CHILD(1280),
11769 CHILD(1283), CHILD(1286), CHILD(1289),
11770 BITFIELD(53, 1) /* index 1268 */,
11771 TILE_OPC_NAP, TILE_OPC_NONE,
11772 BITFIELD(53, 1) /* index 1271 */,
11773 TILE_OPC_NOP, TILE_OPC_NONE,
11774 BITFIELD(53, 1) /* index 1274 */,
11775 TILE_OPC_SWINT0, TILE_OPC_NONE,
11776 BITFIELD(53, 1) /* index 1277 */,
11777 TILE_OPC_SWINT1, TILE_OPC_NONE,
11778 BITFIELD(53, 1) /* index 1280 */,
11779 TILE_OPC_SWINT2, TILE_OPC_NONE,
11780 BITFIELD(53, 1) /* index 1283 */,
11781 TILE_OPC_SWINT3, TILE_OPC_NONE,
11782 BITFIELD(53, 1) /* index 1286 */,
11783 TILE_OPC_TNS, TILE_OPC_NONE,
11784 BITFIELD(53, 1) /* index 1289 */,
11785 TILE_OPC_WH64, TILE_OPC_NONE,
11786 BITFIELD(43, 2) /* index 1292 */,
11787 CHILD(1297), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11788 BITFIELD(45, 1) /* index 1297 */,
11789 CHILD(1300), TILE_OPC_NONE,
11790 BITFIELD(53, 1) /* index 1300 */,
11791 TILE_OPC_LW_NA, TILE_OPC_NONE,
11792 BITFIELD(46, 7) /* index 1303 */,
11793 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1432),
11794 CHILD(1432), CHILD(1432), CHILD(1432), CHILD(1435), CHILD(1435),
11795 CHILD(1435), CHILD(1435), CHILD(1438), CHILD(1438), CHILD(1438),
11796 CHILD(1438), CHILD(1441), CHILD(1441), CHILD(1441), CHILD(1441),
11797 CHILD(1444), CHILD(1444), CHILD(1444), CHILD(1444), CHILD(1447),
11798 CHILD(1447), CHILD(1447), CHILD(1447), CHILD(1450), CHILD(1450),
11799 CHILD(1450), CHILD(1450), CHILD(1453), CHILD(1453), CHILD(1453),
11800 CHILD(1453), CHILD(1456), CHILD(1456), CHILD(1456), CHILD(1456),
11801 CHILD(1459), CHILD(1459), CHILD(1459), CHILD(1459), CHILD(1151),
11802 CHILD(1462), CHILD(1486), CHILD(1498), TILE_OPC_NONE, TILE_OPC_NONE,
11803 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11804 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11805 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11806 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11807 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11808 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11809 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11810 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11811 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11812 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11813 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11814 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11815 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11816 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11817 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11818 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11819 BITFIELD(53, 1) /* index 1432 */,
11820 TILE_OPC_RLI_SN, TILE_OPC_NONE,
11821 BITFIELD(53, 1) /* index 1435 */,
11822 TILE_OPC_SHLIB_SN, TILE_OPC_NONE,
11823 BITFIELD(53, 1) /* index 1438 */,
11824 TILE_OPC_SHLIH_SN, TILE_OPC_NONE,
11825 BITFIELD(53, 1) /* index 1441 */,
11826 TILE_OPC_SHLI_SN, TILE_OPC_NONE,
11827 BITFIELD(53, 1) /* index 1444 */,
11828 TILE_OPC_SHRIB_SN, TILE_OPC_NONE,
11829 BITFIELD(53, 1) /* index 1447 */,
11830 TILE_OPC_SHRIH_SN, TILE_OPC_NONE,
11831 BITFIELD(53, 1) /* index 1450 */,
11832 TILE_OPC_SHRI_SN, TILE_OPC_NONE,
11833 BITFIELD(53, 1) /* index 1453 */,
11834 TILE_OPC_SRAIB_SN, TILE_OPC_NONE,
11835 BITFIELD(53, 1) /* index 1456 */,
11836 TILE_OPC_SRAIH_SN, TILE_OPC_NONE,
11837 BITFIELD(53, 1) /* index 1459 */,
11838 TILE_OPC_SRAI_SN, TILE_OPC_NONE,
11839 BITFIELD(43, 3) /* index 1462 */,
11840 CHILD(1220), CHILD(1223), CHILD(1471), CHILD(1474), CHILD(1477),
11841 CHILD(1480), CHILD(1483), CHILD(1256),
11842 BITFIELD(53, 1) /* index 1471 */,
11843 TILE_OPC_LB_SN, TILE_OPC_NONE,
11844 BITFIELD(53, 1) /* index 1474 */,
11845 TILE_OPC_LB_U_SN, TILE_OPC_NONE,
11846 BITFIELD(53, 1) /* index 1477 */,
11847 TILE_OPC_LH_SN, TILE_OPC_NONE,
11848 BITFIELD(53, 1) /* index 1480 */,
11849 TILE_OPC_LH_U_SN, TILE_OPC_NONE,
11850 BITFIELD(53, 1) /* index 1483 */,
11851 TILE_OPC_LW_SN, TILE_OPC_NONE,
11852 BITFIELD(43, 3) /* index 1486 */,
11853 CHILD(1268), CHILD(1271), CHILD(1274), CHILD(1277), CHILD(1280),
11854 CHILD(1283), CHILD(1495), CHILD(1289),
11855 BITFIELD(53, 1) /* index 1495 */,
11856 TILE_OPC_TNS_SN, TILE_OPC_NONE,
11857 BITFIELD(43, 2) /* index 1498 */,
11858 CHILD(1503), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11859 BITFIELD(45, 1) /* index 1503 */,
11860 CHILD(1506), TILE_OPC_NONE,
11861 BITFIELD(53, 1) /* index 1506 */,
11862 TILE_OPC_LW_NA_SN, TILE_OPC_NONE,
11865 static const unsigned short decode_Y0_fsm[168] =
11867 BITFIELD(27, 4) /* index 0 */,
11868 TILE_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52),
11869 CHILD(57), CHILD(62), CHILD(67), TILE_OPC_ADDI, CHILD(72), CHILD(102),
11870 TILE_OPC_SEQI, CHILD(117), TILE_OPC_SLTI, TILE_OPC_SLTI_U,
11871 BITFIELD(18, 2) /* index 17 */,
11872 TILE_OPC_ADD, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_SUB,
11873 BITFIELD(18, 2) /* index 22 */,
11874 TILE_OPC_MNZ, TILE_OPC_MVNZ, TILE_OPC_MVZ, TILE_OPC_MZ,
11875 BITFIELD(18, 2) /* index 27 */,
11876 TILE_OPC_AND, TILE_OPC_NOR, CHILD(32), TILE_OPC_XOR,
11877 BITFIELD(12, 2) /* index 32 */,
11878 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(37),
11879 BITFIELD(14, 2) /* index 37 */,
11880 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(42),
11881 BITFIELD(16, 2) /* index 42 */,
11882 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE,
11883 BITFIELD(18, 2) /* index 47 */,
11884 TILE_OPC_RL, TILE_OPC_SHL, TILE_OPC_SHR, TILE_OPC_SRA,
11885 BITFIELD(18, 2) /* index 52 */,
11886 TILE_OPC_SLTE, TILE_OPC_SLTE_U, TILE_OPC_SLT, TILE_OPC_SLT_U,
11887 BITFIELD(18, 2) /* index 57 */,
11888 TILE_OPC_MULHLSA_UU, TILE_OPC_S3A, TILE_OPC_SEQ, TILE_OPC_SNE,
11889 BITFIELD(18, 2) /* index 62 */,
11890 TILE_OPC_MULHH_SS, TILE_OPC_MULHH_UU, TILE_OPC_MULLL_SS, TILE_OPC_MULLL_UU,
11891 BITFIELD(18, 2) /* index 67 */,
11892 TILE_OPC_MULHHA_SS, TILE_OPC_MULHHA_UU, TILE_OPC_MULLLA_SS,
11893 TILE_OPC_MULLLA_UU,
11894 BITFIELD(0, 2) /* index 72 */,
11895 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(77),
11896 BITFIELD(2, 2) /* index 77 */,
11897 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(82),
11898 BITFIELD(4, 2) /* index 82 */,
11899 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(87),
11900 BITFIELD(6, 2) /* index 87 */,
11901 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(92),
11902 BITFIELD(8, 2) /* index 92 */,
11903 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(97),
11904 BITFIELD(10, 2) /* index 97 */,
11905 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO,
11906 BITFIELD(6, 2) /* index 102 */,
11907 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(107),
11908 BITFIELD(8, 2) /* index 107 */,
11909 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(112),
11910 BITFIELD(10, 2) /* index 112 */,
11911 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI,
11912 BITFIELD(15, 5) /* index 117 */,
11913 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_RLI,
11914 TILE_OPC_RLI, TILE_OPC_RLI, TILE_OPC_RLI, TILE_OPC_SHLI, TILE_OPC_SHLI,
11915 TILE_OPC_SHLI, TILE_OPC_SHLI, TILE_OPC_SHRI, TILE_OPC_SHRI, TILE_OPC_SHRI,
11916 TILE_OPC_SHRI, TILE_OPC_SRAI, TILE_OPC_SRAI, TILE_OPC_SRAI, TILE_OPC_SRAI,
11917 CHILD(150), CHILD(159), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11918 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11919 TILE_OPC_NONE, TILE_OPC_NONE,
11920 BITFIELD(12, 3) /* index 150 */,
11921 TILE_OPC_NONE, TILE_OPC_BITX, TILE_OPC_BYTEX, TILE_OPC_CLZ, TILE_OPC_CTZ,
11922 TILE_OPC_FNOP, TILE_OPC_NOP, TILE_OPC_PCNT,
11923 BITFIELD(12, 3) /* index 159 */,
11924 TILE_OPC_TBLIDXB0, TILE_OPC_TBLIDXB1, TILE_OPC_TBLIDXB2, TILE_OPC_TBLIDXB3,
11925 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11928 static const unsigned short decode_Y1_fsm[140] =
11930 BITFIELD(59, 4) /* index 0 */,
11931 TILE_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52),
11932 CHILD(57), TILE_OPC_ADDI, CHILD(62), CHILD(92), TILE_OPC_SEQI, CHILD(107),
11933 TILE_OPC_SLTI, TILE_OPC_SLTI_U, TILE_OPC_NONE, TILE_OPC_NONE,
11934 BITFIELD(49, 2) /* index 17 */,
11935 TILE_OPC_ADD, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_SUB,
11936 BITFIELD(49, 2) /* index 22 */,
11937 TILE_OPC_NONE, TILE_OPC_MNZ, TILE_OPC_MZ, TILE_OPC_NONE,
11938 BITFIELD(49, 2) /* index 27 */,
11939 TILE_OPC_AND, TILE_OPC_NOR, CHILD(32), TILE_OPC_XOR,
11940 BITFIELD(43, 2) /* index 32 */,
11941 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(37),
11942 BITFIELD(45, 2) /* index 37 */,
11943 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(42),
11944 BITFIELD(47, 2) /* index 42 */,
11945 TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE,
11946 BITFIELD(49, 2) /* index 47 */,
11947 TILE_OPC_RL, TILE_OPC_SHL, TILE_OPC_SHR, TILE_OPC_SRA,
11948 BITFIELD(49, 2) /* index 52 */,
11949 TILE_OPC_SLTE, TILE_OPC_SLTE_U, TILE_OPC_SLT, TILE_OPC_SLT_U,
11950 BITFIELD(49, 2) /* index 57 */,
11951 TILE_OPC_NONE, TILE_OPC_S3A, TILE_OPC_SEQ, TILE_OPC_SNE,
11952 BITFIELD(31, 2) /* index 62 */,
11953 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(67),
11954 BITFIELD(33, 2) /* index 67 */,
11955 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(72),
11956 BITFIELD(35, 2) /* index 72 */,
11957 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(77),
11958 BITFIELD(37, 2) /* index 77 */,
11959 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(82),
11960 BITFIELD(39, 2) /* index 82 */,
11961 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(87),
11962 BITFIELD(41, 2) /* index 87 */,
11963 TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO,
11964 BITFIELD(37, 2) /* index 92 */,
11965 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(97),
11966 BITFIELD(39, 2) /* index 97 */,
11967 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(102),
11968 BITFIELD(41, 2) /* index 102 */,
11969 TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI,
11970 BITFIELD(48, 3) /* index 107 */,
11971 TILE_OPC_NONE, TILE_OPC_RLI, TILE_OPC_SHLI, TILE_OPC_SHRI, TILE_OPC_SRAI,
11972 CHILD(116), TILE_OPC_NONE, TILE_OPC_NONE,
11973 BITFIELD(43, 3) /* index 116 */,
11974 TILE_OPC_NONE, CHILD(125), CHILD(130), CHILD(135), TILE_OPC_NONE,
11975 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11976 BITFIELD(46, 2) /* index 125 */,
11977 TILE_OPC_FNOP, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11978 BITFIELD(46, 2) /* index 130 */,
11979 TILE_OPC_ILL, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11980 BITFIELD(46, 2) /* index 135 */,
11981 TILE_OPC_NOP, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11984 static const unsigned short decode_Y2_fsm[24] =
11986 BITFIELD(56, 3) /* index 0 */,
11987 CHILD(9), TILE_OPC_LB_U, TILE_OPC_LH, TILE_OPC_LH_U, TILE_OPC_LW,
11988 TILE_OPC_SB, TILE_OPC_SH, TILE_OPC_SW,
11989 BITFIELD(20, 2) /* index 9 */,
11990 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(14),
11991 BITFIELD(22, 2) /* index 14 */,
11992 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(19),
11993 BITFIELD(24, 2) /* index 19 */,
11994 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH,
11999 const unsigned short * const
12000 tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS] =
12008 const struct tile_sn_opcode tile_sn_opcodes[23] =
12010 { "bz", TILE_SN_OPC_BZ,
12011 1 /* num_operands */,
12014 /* fixed_bit_mask */
12016 /* fixed_bit_value */
12019 { "bnz", TILE_SN_OPC_BNZ,
12020 1 /* num_operands */,
12023 /* fixed_bit_mask */
12025 /* fixed_bit_value */
12028 { "jrr", TILE_SN_OPC_JRR,
12029 1 /* num_operands */,
12032 /* fixed_bit_mask */
12034 /* fixed_bit_value */
12037 { "fnop", TILE_SN_OPC_FNOP,
12038 0 /* num_operands */,
12041 /* fixed_bit_mask */
12043 /* fixed_bit_value */
12046 { "blz", TILE_SN_OPC_BLZ,
12047 1 /* num_operands */,
12050 /* fixed_bit_mask */
12052 /* fixed_bit_value */
12055 { "nop", TILE_SN_OPC_NOP,
12056 0 /* num_operands */,
12059 /* fixed_bit_mask */
12061 /* fixed_bit_value */
12064 { "movei", TILE_SN_OPC_MOVEI,
12065 1 /* num_operands */,
12068 /* fixed_bit_mask */
12070 /* fixed_bit_value */
12073 { "move", TILE_SN_OPC_MOVE,
12074 2 /* num_operands */,
12077 /* fixed_bit_mask */
12079 /* fixed_bit_value */
12082 { "bgez", TILE_SN_OPC_BGEZ,
12083 1 /* num_operands */,
12086 /* fixed_bit_mask */
12088 /* fixed_bit_value */
12091 { "jr", TILE_SN_OPC_JR,
12092 1 /* num_operands */,
12095 /* fixed_bit_mask */
12097 /* fixed_bit_value */
12100 { "blez", TILE_SN_OPC_BLEZ,
12101 1 /* num_operands */,
12104 /* fixed_bit_mask */
12106 /* fixed_bit_value */
12109 { "bbns", TILE_SN_OPC_BBNS,
12110 1 /* num_operands */,
12113 /* fixed_bit_mask */
12115 /* fixed_bit_value */
12118 { "jalrr", TILE_SN_OPC_JALRR,
12119 1 /* num_operands */,
12122 /* fixed_bit_mask */
12124 /* fixed_bit_value */
12127 { "bpt", TILE_SN_OPC_BPT,
12128 0 /* num_operands */,
12131 /* fixed_bit_mask */
12133 /* fixed_bit_value */
12136 { "jalr", TILE_SN_OPC_JALR,
12137 1 /* num_operands */,
12140 /* fixed_bit_mask */
12142 /* fixed_bit_value */
12145 { "shr1", TILE_SN_OPC_SHR1,
12146 2 /* num_operands */,
12149 /* fixed_bit_mask */
12151 /* fixed_bit_value */
12154 { "bgz", TILE_SN_OPC_BGZ,
12155 1 /* num_operands */,
12158 /* fixed_bit_mask */
12160 /* fixed_bit_value */
12163 { "bbs", TILE_SN_OPC_BBS,
12164 1 /* num_operands */,
12167 /* fixed_bit_mask */
12169 /* fixed_bit_value */
12172 { "shl8ii", TILE_SN_OPC_SHL8II,
12173 1 /* num_operands */,
12176 /* fixed_bit_mask */
12178 /* fixed_bit_value */
12181 { "addi", TILE_SN_OPC_ADDI,
12182 1 /* num_operands */,
12185 /* fixed_bit_mask */
12187 /* fixed_bit_value */
12190 { "halt", TILE_SN_OPC_HALT,
12191 0 /* num_operands */,
12194 /* fixed_bit_mask */
12196 /* fixed_bit_value */
12199 { "route", TILE_SN_OPC_ROUTE, 0, { 0, }, 0, 0,
12201 { 0, TILE_SN_OPC_NONE, 0, { 0, }, 0, 0,
12204 const unsigned char tile_sn_route_encode[6 * 6 * 6] =
12424 const signed char tile_sn_route_decode[256][3] =
12684 const char tile_sn_direction_names[6][5] =
12694 const signed char tile_sn_dest_map[6][6] = {
12695 { -1, 3, 4, 5, 1, 2 } /* val -> w */,
12696 { -1, 3, 4, 5, 0, 2 } /* val -> c */,
12697 { -1, 3, 4, 5, 0, 1 } /* val -> acc */,
12698 { -1, 4, 5, 0, 1, 2 } /* val -> n */,
12699 { -1, 3, 5, 0, 1, 2 } /* val -> e */,
12700 { -1, 3, 4, 0, 1, 2 } /* val -> s */
12703 const struct tile_operand tile_operands[43] =
12706 TILE_OP_TYPE_IMMEDIATE, /* type */
12707 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_X0), /* default_reloc */
12710 0, /* is_src_reg */
12711 0, /* is_dest_reg */
12712 0, /* is_pc_relative */
12713 0, /* rightshift */
12714 create_Imm8_X0, /* insert */
12715 get_Imm8_X0 /* extract */
12718 TILE_OP_TYPE_IMMEDIATE, /* type */
12719 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_X1), /* default_reloc */
12722 0, /* is_src_reg */
12723 0, /* is_dest_reg */
12724 0, /* is_pc_relative */
12725 0, /* rightshift */
12726 create_Imm8_X1, /* insert */
12727 get_Imm8_X1 /* extract */
12730 TILE_OP_TYPE_IMMEDIATE, /* type */
12731 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_Y0), /* default_reloc */
12734 0, /* is_src_reg */
12735 0, /* is_dest_reg */
12736 0, /* is_pc_relative */
12737 0, /* rightshift */
12738 create_Imm8_Y0, /* insert */
12739 get_Imm8_Y0 /* extract */
12742 TILE_OP_TYPE_IMMEDIATE, /* type */
12743 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_Y1), /* default_reloc */
12746 0, /* is_src_reg */
12747 0, /* is_dest_reg */
12748 0, /* is_pc_relative */
12749 0, /* rightshift */
12750 create_Imm8_Y1, /* insert */
12751 get_Imm8_Y1 /* extract */
12754 TILE_OP_TYPE_IMMEDIATE, /* type */
12755 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM16_X0), /* default_reloc */
12758 0, /* is_src_reg */
12759 0, /* is_dest_reg */
12760 0, /* is_pc_relative */
12761 0, /* rightshift */
12762 create_Imm16_X0, /* insert */
12763 get_Imm16_X0 /* extract */
12766 TILE_OP_TYPE_IMMEDIATE, /* type */
12767 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM16_X1), /* default_reloc */
12770 0, /* is_src_reg */
12771 0, /* is_dest_reg */
12772 0, /* is_pc_relative */
12773 0, /* rightshift */
12774 create_Imm16_X1, /* insert */
12775 get_Imm16_X1 /* extract */
12778 TILE_OP_TYPE_ADDRESS, /* type */
12779 MAYBE_BFD_RELOC(BFD_RELOC_TILE_JOFFLONG_X1), /* default_reloc */
12782 0, /* is_src_reg */
12783 0, /* is_dest_reg */
12784 1, /* is_pc_relative */
12785 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, /* rightshift */
12786 create_JOffLong_X1, /* insert */
12787 get_JOffLong_X1 /* extract */
12790 TILE_OP_TYPE_REGISTER, /* type */
12791 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12794 0, /* is_src_reg */
12795 1, /* is_dest_reg */
12796 0, /* is_pc_relative */
12797 0, /* rightshift */
12798 create_Dest_X0, /* insert */
12799 get_Dest_X0 /* extract */
12802 TILE_OP_TYPE_REGISTER, /* type */
12803 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12806 1, /* is_src_reg */
12807 0, /* is_dest_reg */
12808 0, /* is_pc_relative */
12809 0, /* rightshift */
12810 create_SrcA_X0, /* insert */
12811 get_SrcA_X0 /* extract */
12814 TILE_OP_TYPE_REGISTER, /* type */
12815 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12818 0, /* is_src_reg */
12819 1, /* is_dest_reg */
12820 0, /* is_pc_relative */
12821 0, /* rightshift */
12822 create_Dest_X1, /* insert */
12823 get_Dest_X1 /* extract */
12826 TILE_OP_TYPE_REGISTER, /* type */
12827 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12830 1, /* is_src_reg */
12831 0, /* is_dest_reg */
12832 0, /* is_pc_relative */
12833 0, /* rightshift */
12834 create_SrcA_X1, /* insert */
12835 get_SrcA_X1 /* extract */
12838 TILE_OP_TYPE_REGISTER, /* type */
12839 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12842 0, /* is_src_reg */
12843 1, /* is_dest_reg */
12844 0, /* is_pc_relative */
12845 0, /* rightshift */
12846 create_Dest_Y0, /* insert */
12847 get_Dest_Y0 /* extract */
12850 TILE_OP_TYPE_REGISTER, /* type */
12851 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12854 1, /* is_src_reg */
12855 0, /* is_dest_reg */
12856 0, /* is_pc_relative */
12857 0, /* rightshift */
12858 create_SrcA_Y0, /* insert */
12859 get_SrcA_Y0 /* extract */
12862 TILE_OP_TYPE_REGISTER, /* type */
12863 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12866 0, /* is_src_reg */
12867 1, /* is_dest_reg */
12868 0, /* is_pc_relative */
12869 0, /* rightshift */
12870 create_Dest_Y1, /* insert */
12871 get_Dest_Y1 /* extract */
12874 TILE_OP_TYPE_REGISTER, /* type */
12875 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12878 1, /* is_src_reg */
12879 0, /* is_dest_reg */
12880 0, /* is_pc_relative */
12881 0, /* rightshift */
12882 create_SrcA_Y1, /* insert */
12883 get_SrcA_Y1 /* extract */
12886 TILE_OP_TYPE_REGISTER, /* type */
12887 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12890 1, /* is_src_reg */
12891 0, /* is_dest_reg */
12892 0, /* is_pc_relative */
12893 0, /* rightshift */
12894 create_SrcA_Y2, /* insert */
12895 get_SrcA_Y2 /* extract */
12898 TILE_OP_TYPE_REGISTER, /* type */
12899 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12902 1, /* is_src_reg */
12903 0, /* is_dest_reg */
12904 0, /* is_pc_relative */
12905 0, /* rightshift */
12906 create_SrcB_X0, /* insert */
12907 get_SrcB_X0 /* extract */
12910 TILE_OP_TYPE_REGISTER, /* type */
12911 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12914 1, /* is_src_reg */
12915 0, /* is_dest_reg */
12916 0, /* is_pc_relative */
12917 0, /* rightshift */
12918 create_SrcB_X1, /* insert */
12919 get_SrcB_X1 /* extract */
12922 TILE_OP_TYPE_REGISTER, /* type */
12923 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12926 1, /* is_src_reg */
12927 0, /* is_dest_reg */
12928 0, /* is_pc_relative */
12929 0, /* rightshift */
12930 create_SrcB_Y0, /* insert */
12931 get_SrcB_Y0 /* extract */
12934 TILE_OP_TYPE_REGISTER, /* type */
12935 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12938 1, /* is_src_reg */
12939 0, /* is_dest_reg */
12940 0, /* is_pc_relative */
12941 0, /* rightshift */
12942 create_SrcB_Y1, /* insert */
12943 get_SrcB_Y1 /* extract */
12946 TILE_OP_TYPE_ADDRESS, /* type */
12947 MAYBE_BFD_RELOC(BFD_RELOC_TILE_BROFF_X1), /* default_reloc */
12950 0, /* is_src_reg */
12951 0, /* is_dest_reg */
12952 1, /* is_pc_relative */
12953 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, /* rightshift */
12954 create_BrOff_X1, /* insert */
12955 get_BrOff_X1 /* extract */
12958 TILE_OP_TYPE_REGISTER, /* type */
12959 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12962 1, /* is_src_reg */
12963 1, /* is_dest_reg */
12964 0, /* is_pc_relative */
12965 0, /* rightshift */
12966 create_Dest_X0, /* insert */
12967 get_Dest_X0 /* extract */
12970 TILE_OP_TYPE_ADDRESS, /* type */
12971 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12974 0, /* is_src_reg */
12975 0, /* is_dest_reg */
12976 1, /* is_pc_relative */
12977 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, /* rightshift */
12978 create_JOff_X1, /* insert */
12979 get_JOff_X1 /* extract */
12982 TILE_OP_TYPE_REGISTER, /* type */
12983 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12986 0, /* is_src_reg */
12987 1, /* is_dest_reg */
12988 0, /* is_pc_relative */
12989 0, /* rightshift */
12990 create_SrcBDest_Y2, /* insert */
12991 get_SrcBDest_Y2 /* extract */
12994 TILE_OP_TYPE_REGISTER, /* type */
12995 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
12998 1, /* is_src_reg */
12999 1, /* is_dest_reg */
13000 0, /* is_pc_relative */
13001 0, /* rightshift */
13002 create_SrcA_X1, /* insert */
13003 get_SrcA_X1 /* extract */
13006 TILE_OP_TYPE_SPR, /* type */
13007 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MF_IMM15_X1), /* default_reloc */
13010 0, /* is_src_reg */
13011 0, /* is_dest_reg */
13012 0, /* is_pc_relative */
13013 0, /* rightshift */
13014 create_MF_Imm15_X1, /* insert */
13015 get_MF_Imm15_X1 /* extract */
13018 TILE_OP_TYPE_IMMEDIATE, /* type */
13019 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMSTART_X0), /* default_reloc */
13022 0, /* is_src_reg */
13023 0, /* is_dest_reg */
13024 0, /* is_pc_relative */
13025 0, /* rightshift */
13026 create_MMStart_X0, /* insert */
13027 get_MMStart_X0 /* extract */
13030 TILE_OP_TYPE_IMMEDIATE, /* type */
13031 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMEND_X0), /* default_reloc */
13034 0, /* is_src_reg */
13035 0, /* is_dest_reg */
13036 0, /* is_pc_relative */
13037 0, /* rightshift */
13038 create_MMEnd_X0, /* insert */
13039 get_MMEnd_X0 /* extract */
13042 TILE_OP_TYPE_IMMEDIATE, /* type */
13043 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMSTART_X1), /* default_reloc */
13046 0, /* is_src_reg */
13047 0, /* is_dest_reg */
13048 0, /* is_pc_relative */
13049 0, /* rightshift */
13050 create_MMStart_X1, /* insert */
13051 get_MMStart_X1 /* extract */
13054 TILE_OP_TYPE_IMMEDIATE, /* type */
13055 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMEND_X1), /* default_reloc */
13058 0, /* is_src_reg */
13059 0, /* is_dest_reg */
13060 0, /* is_pc_relative */
13061 0, /* rightshift */
13062 create_MMEnd_X1, /* insert */
13063 get_MMEnd_X1 /* extract */
13066 TILE_OP_TYPE_SPR, /* type */
13067 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MT_IMM15_X1), /* default_reloc */
13070 0, /* is_src_reg */
13071 0, /* is_dest_reg */
13072 0, /* is_pc_relative */
13073 0, /* rightshift */
13074 create_MT_Imm15_X1, /* insert */
13075 get_MT_Imm15_X1 /* extract */
13078 TILE_OP_TYPE_REGISTER, /* type */
13079 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
13082 1, /* is_src_reg */
13083 1, /* is_dest_reg */
13084 0, /* is_pc_relative */
13085 0, /* rightshift */
13086 create_Dest_Y0, /* insert */
13087 get_Dest_Y0 /* extract */
13090 TILE_OP_TYPE_IMMEDIATE, /* type */
13091 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_X0), /* default_reloc */
13094 0, /* is_src_reg */
13095 0, /* is_dest_reg */
13096 0, /* is_pc_relative */
13097 0, /* rightshift */
13098 create_ShAmt_X0, /* insert */
13099 get_ShAmt_X0 /* extract */
13102 TILE_OP_TYPE_IMMEDIATE, /* type */
13103 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_X1), /* default_reloc */
13106 0, /* is_src_reg */
13107 0, /* is_dest_reg */
13108 0, /* is_pc_relative */
13109 0, /* rightshift */
13110 create_ShAmt_X1, /* insert */
13111 get_ShAmt_X1 /* extract */
13114 TILE_OP_TYPE_IMMEDIATE, /* type */
13115 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_Y0), /* default_reloc */
13118 0, /* is_src_reg */
13119 0, /* is_dest_reg */
13120 0, /* is_pc_relative */
13121 0, /* rightshift */
13122 create_ShAmt_Y0, /* insert */
13123 get_ShAmt_Y0 /* extract */
13126 TILE_OP_TYPE_IMMEDIATE, /* type */
13127 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_Y1), /* default_reloc */
13130 0, /* is_src_reg */
13131 0, /* is_dest_reg */
13132 0, /* is_pc_relative */
13133 0, /* rightshift */
13134 create_ShAmt_Y1, /* insert */
13135 get_ShAmt_Y1 /* extract */
13138 TILE_OP_TYPE_REGISTER, /* type */
13139 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
13142 1, /* is_src_reg */
13143 0, /* is_dest_reg */
13144 0, /* is_pc_relative */
13145 0, /* rightshift */
13146 create_SrcBDest_Y2, /* insert */
13147 get_SrcBDest_Y2 /* extract */
13150 TILE_OP_TYPE_IMMEDIATE, /* type */
13151 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
13154 0, /* is_src_reg */
13155 0, /* is_dest_reg */
13156 0, /* is_pc_relative */
13157 0, /* rightshift */
13158 create_Dest_Imm8_X1, /* insert */
13159 get_Dest_Imm8_X1 /* extract */
13162 TILE_OP_TYPE_ADDRESS, /* type */
13163 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SN_BROFF), /* default_reloc */
13166 0, /* is_src_reg */
13167 0, /* is_dest_reg */
13168 1, /* is_pc_relative */
13169 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES, /* rightshift */
13170 create_BrOff_SN, /* insert */
13171 get_BrOff_SN /* extract */
13174 TILE_OP_TYPE_IMMEDIATE, /* type */
13175 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SN_UIMM8), /* default_reloc */
13178 0, /* is_src_reg */
13179 0, /* is_dest_reg */
13180 0, /* is_pc_relative */
13181 0, /* rightshift */
13182 create_Imm8_SN, /* insert */
13183 get_Imm8_SN /* extract */
13186 TILE_OP_TYPE_IMMEDIATE, /* type */
13187 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SN_IMM8), /* default_reloc */
13190 0, /* is_src_reg */
13191 0, /* is_dest_reg */
13192 0, /* is_pc_relative */
13193 0, /* rightshift */
13194 create_Imm8_SN, /* insert */
13195 get_Imm8_SN /* extract */
13198 TILE_OP_TYPE_REGISTER, /* type */
13199 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
13202 0, /* is_src_reg */
13203 1, /* is_dest_reg */
13204 0, /* is_pc_relative */
13205 0, /* rightshift */
13206 create_Dest_SN, /* insert */
13207 get_Dest_SN /* extract */
13210 TILE_OP_TYPE_REGISTER, /* type */
13211 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */
13214 1, /* is_src_reg */
13215 0, /* is_dest_reg */
13216 0, /* is_pc_relative */
13217 0, /* rightshift */
13218 create_Src_SN, /* insert */
13219 get_Src_SN /* extract */
13223 const struct tile_spr tile_sprs[] = {
13224 { 0, "MPL_ITLB_MISS_SET_0" },
13225 { 1, "MPL_ITLB_MISS_SET_1" },
13226 { 2, "MPL_ITLB_MISS_SET_2" },
13227 { 3, "MPL_ITLB_MISS_SET_3" },
13228 { 4, "MPL_ITLB_MISS" },
13229 { 256, "ITLB_CURRENT_0" },
13230 { 257, "ITLB_CURRENT_1" },
13231 { 258, "ITLB_CURRENT_2" },
13232 { 259, "ITLB_CURRENT_3" },
13233 { 260, "ITLB_INDEX" },
13234 { 261, "ITLB_MATCH_0" },
13235 { 262, "ITLB_PR" },
13236 { 263, "NUMBER_ITLB" },
13237 { 264, "REPLACEMENT_ITLB" },
13238 { 265, "WIRED_ITLB" },
13239 { 266, "ITLB_PERF" },
13240 { 512, "MPL_MEM_ERROR_SET_0" },
13241 { 513, "MPL_MEM_ERROR_SET_1" },
13242 { 514, "MPL_MEM_ERROR_SET_2" },
13243 { 515, "MPL_MEM_ERROR_SET_3" },
13244 { 516, "MPL_MEM_ERROR" },
13245 { 517, "L1_I_ERROR" },
13246 { 518, "MEM_ERROR_CBOX_ADDR" },
13247 { 519, "MEM_ERROR_CBOX_STATUS" },
13248 { 520, "MEM_ERROR_ENABLE" },
13249 { 521, "MEM_ERROR_MBOX_ADDR" },
13250 { 522, "MEM_ERROR_MBOX_STATUS" },
13251 { 523, "SNIC_ERROR_LOG_STATUS" },
13252 { 524, "SNIC_ERROR_LOG_VA" },
13253 { 525, "XDN_DEMUX_ERROR" },
13254 { 1024, "MPL_ILL_SET_0" },
13255 { 1025, "MPL_ILL_SET_1" },
13256 { 1026, "MPL_ILL_SET_2" },
13257 { 1027, "MPL_ILL_SET_3" },
13258 { 1028, "MPL_ILL" },
13259 { 1536, "MPL_GPV_SET_0" },
13260 { 1537, "MPL_GPV_SET_1" },
13261 { 1538, "MPL_GPV_SET_2" },
13262 { 1539, "MPL_GPV_SET_3" },
13263 { 1540, "MPL_GPV" },
13264 { 1541, "GPV_REASON" },
13265 { 2048, "MPL_SN_ACCESS_SET_0" },
13266 { 2049, "MPL_SN_ACCESS_SET_1" },
13267 { 2050, "MPL_SN_ACCESS_SET_2" },
13268 { 2051, "MPL_SN_ACCESS_SET_3" },
13269 { 2052, "MPL_SN_ACCESS" },
13271 { 2054, "SNFIFO_DATA" },
13272 { 2055, "SNFIFO_SEL" },
13273 { 2056, "SNIC_INVADDR" },
13274 { 2057, "SNISTATE" },
13275 { 2058, "SNOSTATE" },
13277 { 2060, "SNSTATIC" },
13278 { 2304, "SN_DATA_AVAIL" },
13279 { 2560, "MPL_IDN_ACCESS_SET_0" },
13280 { 2561, "MPL_IDN_ACCESS_SET_1" },
13281 { 2562, "MPL_IDN_ACCESS_SET_2" },
13282 { 2563, "MPL_IDN_ACCESS_SET_3" },
13283 { 2564, "MPL_IDN_ACCESS" },
13284 { 2565, "IDN_DEMUX_CA_COUNT" },
13285 { 2566, "IDN_DEMUX_COUNT_0" },
13286 { 2567, "IDN_DEMUX_COUNT_1" },
13287 { 2568, "IDN_DEMUX_CTL" },
13288 { 2569, "IDN_DEMUX_CURR_TAG" },
13289 { 2570, "IDN_DEMUX_QUEUE_SEL" },
13290 { 2571, "IDN_DEMUX_STATUS" },
13291 { 2572, "IDN_DEMUX_WRITE_FIFO" },
13292 { 2573, "IDN_DEMUX_WRITE_QUEUE" },
13293 { 2574, "IDN_PENDING" },
13294 { 2575, "IDN_SP_FIFO_DATA" },
13295 { 2576, "IDN_SP_FIFO_SEL" },
13296 { 2577, "IDN_SP_FREEZE" },
13297 { 2578, "IDN_SP_STATE" },
13298 { 2579, "IDN_TAG_0" },
13299 { 2580, "IDN_TAG_1" },
13300 { 2581, "IDN_TAG_VALID" },
13301 { 2582, "IDN_TILE_COORD" },
13302 { 2816, "IDN_CA_DATA" },
13303 { 2817, "IDN_CA_REM" },
13304 { 2818, "IDN_CA_TAG" },
13305 { 2819, "IDN_DATA_AVAIL" },
13306 { 3072, "MPL_UDN_ACCESS_SET_0" },
13307 { 3073, "MPL_UDN_ACCESS_SET_1" },
13308 { 3074, "MPL_UDN_ACCESS_SET_2" },
13309 { 3075, "MPL_UDN_ACCESS_SET_3" },
13310 { 3076, "MPL_UDN_ACCESS" },
13311 { 3077, "UDN_DEMUX_CA_COUNT" },
13312 { 3078, "UDN_DEMUX_COUNT_0" },
13313 { 3079, "UDN_DEMUX_COUNT_1" },
13314 { 3080, "UDN_DEMUX_COUNT_2" },
13315 { 3081, "UDN_DEMUX_COUNT_3" },
13316 { 3082, "UDN_DEMUX_CTL" },
13317 { 3083, "UDN_DEMUX_CURR_TAG" },
13318 { 3084, "UDN_DEMUX_QUEUE_SEL" },
13319 { 3085, "UDN_DEMUX_STATUS" },
13320 { 3086, "UDN_DEMUX_WRITE_FIFO" },
13321 { 3087, "UDN_DEMUX_WRITE_QUEUE" },
13322 { 3088, "UDN_PENDING" },
13323 { 3089, "UDN_SP_FIFO_DATA" },
13324 { 3090, "UDN_SP_FIFO_SEL" },
13325 { 3091, "UDN_SP_FREEZE" },
13326 { 3092, "UDN_SP_STATE" },
13327 { 3093, "UDN_TAG_0" },
13328 { 3094, "UDN_TAG_1" },
13329 { 3095, "UDN_TAG_2" },
13330 { 3096, "UDN_TAG_3" },
13331 { 3097, "UDN_TAG_VALID" },
13332 { 3098, "UDN_TILE_COORD" },
13333 { 3328, "UDN_CA_DATA" },
13334 { 3329, "UDN_CA_REM" },
13335 { 3330, "UDN_CA_TAG" },
13336 { 3331, "UDN_DATA_AVAIL" },
13337 { 3584, "MPL_IDN_REFILL_SET_0" },
13338 { 3585, "MPL_IDN_REFILL_SET_1" },
13339 { 3586, "MPL_IDN_REFILL_SET_2" },
13340 { 3587, "MPL_IDN_REFILL_SET_3" },
13341 { 3588, "MPL_IDN_REFILL" },
13342 { 3589, "IDN_REFILL_EN" },
13343 { 4096, "MPL_UDN_REFILL_SET_0" },
13344 { 4097, "MPL_UDN_REFILL_SET_1" },
13345 { 4098, "MPL_UDN_REFILL_SET_2" },
13346 { 4099, "MPL_UDN_REFILL_SET_3" },
13347 { 4100, "MPL_UDN_REFILL" },
13348 { 4101, "UDN_REFILL_EN" },
13349 { 4608, "MPL_IDN_COMPLETE_SET_0" },
13350 { 4609, "MPL_IDN_COMPLETE_SET_1" },
13351 { 4610, "MPL_IDN_COMPLETE_SET_2" },
13352 { 4611, "MPL_IDN_COMPLETE_SET_3" },
13353 { 4612, "MPL_IDN_COMPLETE" },
13354 { 4613, "IDN_REMAINING" },
13355 { 5120, "MPL_UDN_COMPLETE_SET_0" },
13356 { 5121, "MPL_UDN_COMPLETE_SET_1" },
13357 { 5122, "MPL_UDN_COMPLETE_SET_2" },
13358 { 5123, "MPL_UDN_COMPLETE_SET_3" },
13359 { 5124, "MPL_UDN_COMPLETE" },
13360 { 5125, "UDN_REMAINING" },
13361 { 5632, "MPL_SWINT_3_SET_0" },
13362 { 5633, "MPL_SWINT_3_SET_1" },
13363 { 5634, "MPL_SWINT_3_SET_2" },
13364 { 5635, "MPL_SWINT_3_SET_3" },
13365 { 5636, "MPL_SWINT_3" },
13366 { 6144, "MPL_SWINT_2_SET_0" },
13367 { 6145, "MPL_SWINT_2_SET_1" },
13368 { 6146, "MPL_SWINT_2_SET_2" },
13369 { 6147, "MPL_SWINT_2_SET_3" },
13370 { 6148, "MPL_SWINT_2" },
13371 { 6656, "MPL_SWINT_1_SET_0" },
13372 { 6657, "MPL_SWINT_1_SET_1" },
13373 { 6658, "MPL_SWINT_1_SET_2" },
13374 { 6659, "MPL_SWINT_1_SET_3" },
13375 { 6660, "MPL_SWINT_1" },
13376 { 7168, "MPL_SWINT_0_SET_0" },
13377 { 7169, "MPL_SWINT_0_SET_1" },
13378 { 7170, "MPL_SWINT_0_SET_2" },
13379 { 7171, "MPL_SWINT_0_SET_3" },
13380 { 7172, "MPL_SWINT_0" },
13381 { 7680, "MPL_UNALIGN_DATA_SET_0" },
13382 { 7681, "MPL_UNALIGN_DATA_SET_1" },
13383 { 7682, "MPL_UNALIGN_DATA_SET_2" },
13384 { 7683, "MPL_UNALIGN_DATA_SET_3" },
13385 { 7684, "MPL_UNALIGN_DATA" },
13386 { 8192, "MPL_DTLB_MISS_SET_0" },
13387 { 8193, "MPL_DTLB_MISS_SET_1" },
13388 { 8194, "MPL_DTLB_MISS_SET_2" },
13389 { 8195, "MPL_DTLB_MISS_SET_3" },
13390 { 8196, "MPL_DTLB_MISS" },
13393 { 8450, "DTLB_BAD_ADDR" },
13394 { 8451, "DTLB_BAD_ADDR_REASON" },
13395 { 8452, "DTLB_CURRENT_0" },
13396 { 8453, "DTLB_CURRENT_1" },
13397 { 8454, "DTLB_CURRENT_2" },
13398 { 8455, "DTLB_CURRENT_3" },
13399 { 8456, "DTLB_INDEX" },
13400 { 8457, "DTLB_MATCH_0" },
13401 { 8458, "NUMBER_DTLB" },
13402 { 8459, "PHYSICAL_MEMORY_MODE" },
13403 { 8460, "REPLACEMENT_DTLB" },
13404 { 8461, "WIRED_DTLB" },
13405 { 8462, "CACHE_RED_WAY_OVERRIDDEN" },
13406 { 8463, "DTLB_PERF" },
13407 { 8704, "MPL_DTLB_ACCESS_SET_0" },
13408 { 8705, "MPL_DTLB_ACCESS_SET_1" },
13409 { 8706, "MPL_DTLB_ACCESS_SET_2" },
13410 { 8707, "MPL_DTLB_ACCESS_SET_3" },
13411 { 8708, "MPL_DTLB_ACCESS" },
13412 { 9216, "MPL_DMATLB_MISS_SET_0" },
13413 { 9217, "MPL_DMATLB_MISS_SET_1" },
13414 { 9218, "MPL_DMATLB_MISS_SET_2" },
13415 { 9219, "MPL_DMATLB_MISS_SET_3" },
13416 { 9220, "MPL_DMATLB_MISS" },
13417 { 9472, "DMA_BAD_ADDR" },
13418 { 9473, "DMA_STATUS" },
13419 { 9728, "MPL_DMATLB_ACCESS_SET_0" },
13420 { 9729, "MPL_DMATLB_ACCESS_SET_1" },
13421 { 9730, "MPL_DMATLB_ACCESS_SET_2" },
13422 { 9731, "MPL_DMATLB_ACCESS_SET_3" },
13423 { 9732, "MPL_DMATLB_ACCESS" },
13424 { 10240, "MPL_SNITLB_MISS_SET_0" },
13425 { 10241, "MPL_SNITLB_MISS_SET_1" },
13426 { 10242, "MPL_SNITLB_MISS_SET_2" },
13427 { 10243, "MPL_SNITLB_MISS_SET_3" },
13428 { 10244, "MPL_SNITLB_MISS" },
13429 { 10245, "NUMBER_SNITLB" },
13430 { 10246, "REPLACEMENT_SNITLB" },
13431 { 10247, "SNITLB_CURRENT_0" },
13432 { 10248, "SNITLB_CURRENT_1" },
13433 { 10249, "SNITLB_CURRENT_2" },
13434 { 10250, "SNITLB_CURRENT_3" },
13435 { 10251, "SNITLB_INDEX" },
13436 { 10252, "SNITLB_MATCH_0" },
13437 { 10253, "SNITLB_PR" },
13438 { 10254, "WIRED_SNITLB" },
13439 { 10255, "SNITLB_STATUS" },
13440 { 10752, "MPL_SN_NOTIFY_SET_0" },
13441 { 10753, "MPL_SN_NOTIFY_SET_1" },
13442 { 10754, "MPL_SN_NOTIFY_SET_2" },
13443 { 10755, "MPL_SN_NOTIFY_SET_3" },
13444 { 10756, "MPL_SN_NOTIFY" },
13445 { 10757, "SN_NOTIFY_STATUS" },
13446 { 11264, "MPL_SN_FIREWALL_SET_0" },
13447 { 11265, "MPL_SN_FIREWALL_SET_1" },
13448 { 11266, "MPL_SN_FIREWALL_SET_2" },
13449 { 11267, "MPL_SN_FIREWALL_SET_3" },
13450 { 11268, "MPL_SN_FIREWALL" },
13451 { 11269, "SN_DIRECTION_PROTECT" },
13452 { 11776, "MPL_IDN_FIREWALL_SET_0" },
13453 { 11777, "MPL_IDN_FIREWALL_SET_1" },
13454 { 11778, "MPL_IDN_FIREWALL_SET_2" },
13455 { 11779, "MPL_IDN_FIREWALL_SET_3" },
13456 { 11780, "MPL_IDN_FIREWALL" },
13457 { 11781, "IDN_DIRECTION_PROTECT" },
13458 { 12288, "MPL_UDN_FIREWALL_SET_0" },
13459 { 12289, "MPL_UDN_FIREWALL_SET_1" },
13460 { 12290, "MPL_UDN_FIREWALL_SET_2" },
13461 { 12291, "MPL_UDN_FIREWALL_SET_3" },
13462 { 12292, "MPL_UDN_FIREWALL" },
13463 { 12293, "UDN_DIRECTION_PROTECT" },
13464 { 12800, "MPL_TILE_TIMER_SET_0" },
13465 { 12801, "MPL_TILE_TIMER_SET_1" },
13466 { 12802, "MPL_TILE_TIMER_SET_2" },
13467 { 12803, "MPL_TILE_TIMER_SET_3" },
13468 { 12804, "MPL_TILE_TIMER" },
13469 { 12805, "TILE_TIMER_CONTROL" },
13470 { 13312, "MPL_IDN_TIMER_SET_0" },
13471 { 13313, "MPL_IDN_TIMER_SET_1" },
13472 { 13314, "MPL_IDN_TIMER_SET_2" },
13473 { 13315, "MPL_IDN_TIMER_SET_3" },
13474 { 13316, "MPL_IDN_TIMER" },
13475 { 13317, "IDN_DEADLOCK_COUNT" },
13476 { 13318, "IDN_DEADLOCK_TIMEOUT" },
13477 { 13824, "MPL_UDN_TIMER_SET_0" },
13478 { 13825, "MPL_UDN_TIMER_SET_1" },
13479 { 13826, "MPL_UDN_TIMER_SET_2" },
13480 { 13827, "MPL_UDN_TIMER_SET_3" },
13481 { 13828, "MPL_UDN_TIMER" },
13482 { 13829, "UDN_DEADLOCK_COUNT" },
13483 { 13830, "UDN_DEADLOCK_TIMEOUT" },
13484 { 14336, "MPL_DMA_NOTIFY_SET_0" },
13485 { 14337, "MPL_DMA_NOTIFY_SET_1" },
13486 { 14338, "MPL_DMA_NOTIFY_SET_2" },
13487 { 14339, "MPL_DMA_NOTIFY_SET_3" },
13488 { 14340, "MPL_DMA_NOTIFY" },
13489 { 14592, "DMA_BYTE" },
13490 { 14593, "DMA_CHUNK_SIZE" },
13491 { 14594, "DMA_CTR" },
13492 { 14595, "DMA_DST_ADDR" },
13493 { 14596, "DMA_DST_CHUNK_ADDR" },
13494 { 14597, "DMA_SRC_ADDR" },
13495 { 14598, "DMA_SRC_CHUNK_ADDR" },
13496 { 14599, "DMA_STRIDE" },
13497 { 14600, "DMA_USER_STATUS" },
13498 { 14848, "MPL_IDN_CA_SET_0" },
13499 { 14849, "MPL_IDN_CA_SET_1" },
13500 { 14850, "MPL_IDN_CA_SET_2" },
13501 { 14851, "MPL_IDN_CA_SET_3" },
13502 { 14852, "MPL_IDN_CA" },
13503 { 15360, "MPL_UDN_CA_SET_0" },
13504 { 15361, "MPL_UDN_CA_SET_1" },
13505 { 15362, "MPL_UDN_CA_SET_2" },
13506 { 15363, "MPL_UDN_CA_SET_3" },
13507 { 15364, "MPL_UDN_CA" },
13508 { 15872, "MPL_IDN_AVAIL_SET_0" },
13509 { 15873, "MPL_IDN_AVAIL_SET_1" },
13510 { 15874, "MPL_IDN_AVAIL_SET_2" },
13511 { 15875, "MPL_IDN_AVAIL_SET_3" },
13512 { 15876, "MPL_IDN_AVAIL" },
13513 { 15877, "IDN_AVAIL_EN" },
13514 { 16384, "MPL_UDN_AVAIL_SET_0" },
13515 { 16385, "MPL_UDN_AVAIL_SET_1" },
13516 { 16386, "MPL_UDN_AVAIL_SET_2" },
13517 { 16387, "MPL_UDN_AVAIL_SET_3" },
13518 { 16388, "MPL_UDN_AVAIL" },
13519 { 16389, "UDN_AVAIL_EN" },
13520 { 16896, "MPL_PERF_COUNT_SET_0" },
13521 { 16897, "MPL_PERF_COUNT_SET_1" },
13522 { 16898, "MPL_PERF_COUNT_SET_2" },
13523 { 16899, "MPL_PERF_COUNT_SET_3" },
13524 { 16900, "MPL_PERF_COUNT" },
13525 { 16901, "PERF_COUNT_0" },
13526 { 16902, "PERF_COUNT_1" },
13527 { 16903, "PERF_COUNT_CTL" },
13528 { 16904, "PERF_COUNT_STS" },
13529 { 16905, "WATCH_CTL" },
13530 { 16906, "WATCH_MASK" },
13531 { 16907, "WATCH_VAL" },
13532 { 16912, "PERF_COUNT_DN_CTL" },
13533 { 17408, "MPL_INTCTRL_3_SET_0" },
13534 { 17409, "MPL_INTCTRL_3_SET_1" },
13535 { 17410, "MPL_INTCTRL_3_SET_2" },
13536 { 17411, "MPL_INTCTRL_3_SET_3" },
13537 { 17412, "MPL_INTCTRL_3" },
13538 { 17413, "EX_CONTEXT_3_0" },
13539 { 17414, "EX_CONTEXT_3_1" },
13540 { 17415, "INTERRUPT_MASK_3_0" },
13541 { 17416, "INTERRUPT_MASK_3_1" },
13542 { 17417, "INTERRUPT_MASK_RESET_3_0" },
13543 { 17418, "INTERRUPT_MASK_RESET_3_1" },
13544 { 17419, "INTERRUPT_MASK_SET_3_0" },
13545 { 17420, "INTERRUPT_MASK_SET_3_1" },
13546 { 17432, "INTCTRL_3_STATUS" },
13547 { 17664, "SYSTEM_SAVE_3_0" },
13548 { 17665, "SYSTEM_SAVE_3_1" },
13549 { 17666, "SYSTEM_SAVE_3_2" },
13550 { 17667, "SYSTEM_SAVE_3_3" },
13551 { 17920, "MPL_INTCTRL_2_SET_0" },
13552 { 17921, "MPL_INTCTRL_2_SET_1" },
13553 { 17922, "MPL_INTCTRL_2_SET_2" },
13554 { 17923, "MPL_INTCTRL_2_SET_3" },
13555 { 17924, "MPL_INTCTRL_2" },
13556 { 17925, "EX_CONTEXT_2_0" },
13557 { 17926, "EX_CONTEXT_2_1" },
13558 { 17927, "INTCTRL_2_STATUS" },
13559 { 17928, "INTERRUPT_MASK_2_0" },
13560 { 17929, "INTERRUPT_MASK_2_1" },
13561 { 17930, "INTERRUPT_MASK_RESET_2_0" },
13562 { 17931, "INTERRUPT_MASK_RESET_2_1" },
13563 { 17932, "INTERRUPT_MASK_SET_2_0" },
13564 { 17933, "INTERRUPT_MASK_SET_2_1" },
13565 { 18176, "SYSTEM_SAVE_2_0" },
13566 { 18177, "SYSTEM_SAVE_2_1" },
13567 { 18178, "SYSTEM_SAVE_2_2" },
13568 { 18179, "SYSTEM_SAVE_2_3" },
13569 { 18432, "MPL_INTCTRL_1_SET_0" },
13570 { 18433, "MPL_INTCTRL_1_SET_1" },
13571 { 18434, "MPL_INTCTRL_1_SET_2" },
13572 { 18435, "MPL_INTCTRL_1_SET_3" },
13573 { 18436, "MPL_INTCTRL_1" },
13574 { 18437, "EX_CONTEXT_1_0" },
13575 { 18438, "EX_CONTEXT_1_1" },
13576 { 18439, "INTCTRL_1_STATUS" },
13577 { 18440, "INTCTRL_3_STATUS_REV0" },
13578 { 18441, "INTERRUPT_MASK_1_0" },
13579 { 18442, "INTERRUPT_MASK_1_1" },
13580 { 18443, "INTERRUPT_MASK_RESET_1_0" },
13581 { 18444, "INTERRUPT_MASK_RESET_1_1" },
13582 { 18445, "INTERRUPT_MASK_SET_1_0" },
13583 { 18446, "INTERRUPT_MASK_SET_1_1" },
13584 { 18688, "SYSTEM_SAVE_1_0" },
13585 { 18689, "SYSTEM_SAVE_1_1" },
13586 { 18690, "SYSTEM_SAVE_1_2" },
13587 { 18691, "SYSTEM_SAVE_1_3" },
13588 { 18944, "MPL_INTCTRL_0_SET_0" },
13589 { 18945, "MPL_INTCTRL_0_SET_1" },
13590 { 18946, "MPL_INTCTRL_0_SET_2" },
13591 { 18947, "MPL_INTCTRL_0_SET_3" },
13592 { 18948, "MPL_INTCTRL_0" },
13593 { 18949, "EX_CONTEXT_0_0" },
13594 { 18950, "EX_CONTEXT_0_1" },
13595 { 18951, "INTCTRL_0_STATUS" },
13596 { 18952, "INTERRUPT_MASK_0_0" },
13597 { 18953, "INTERRUPT_MASK_0_1" },
13598 { 18954, "INTERRUPT_MASK_RESET_0_0" },
13599 { 18955, "INTERRUPT_MASK_RESET_0_1" },
13600 { 18956, "INTERRUPT_MASK_SET_0_0" },
13601 { 18957, "INTERRUPT_MASK_SET_0_1" },
13602 { 19200, "SYSTEM_SAVE_0_0" },
13603 { 19201, "SYSTEM_SAVE_0_1" },
13604 { 19202, "SYSTEM_SAVE_0_2" },
13605 { 19203, "SYSTEM_SAVE_0_3" },
13606 { 19456, "MPL_BOOT_ACCESS_SET_0" },
13607 { 19457, "MPL_BOOT_ACCESS_SET_1" },
13608 { 19458, "MPL_BOOT_ACCESS_SET_2" },
13609 { 19459, "MPL_BOOT_ACCESS_SET_3" },
13610 { 19460, "MPL_BOOT_ACCESS" },
13611 { 19461, "CBOX_CACHEASRAM_CONFIG" },
13612 { 19462, "CBOX_CACHE_CONFIG" },
13613 { 19463, "CBOX_MMAP_0" },
13614 { 19464, "CBOX_MMAP_1" },
13615 { 19465, "CBOX_MMAP_2" },
13616 { 19466, "CBOX_MMAP_3" },
13617 { 19467, "CBOX_MSR" },
13618 { 19468, "CBOX_SRC_ID" },
13619 { 19469, "CYCLE_HIGH_MODIFY" },
13620 { 19470, "CYCLE_LOW_MODIFY" },
13621 { 19471, "DIAG_BCST_CTL" },
13622 { 19472, "DIAG_BCST_MASK" },
13623 { 19473, "DIAG_BCST_TRIGGER" },
13624 { 19474, "DIAG_MUX_CTL" },
13625 { 19475, "DIAG_TRACE_CTL" },
13626 { 19476, "DIAG_TRACE_STS" },
13627 { 19477, "IDN_DEMUX_BUF_THRESH" },
13628 { 19478, "SBOX_CONFIG" },
13629 { 19479, "TILE_COORD" },
13630 { 19480, "UDN_DEMUX_BUF_THRESH" },
13631 { 19481, "CBOX_HOME_MAP_ADDR" },
13632 { 19482, "CBOX_HOME_MAP_DATA" },
13633 { 19483, "CBOX_MSR1" },
13634 { 19484, "BIG_ENDIAN_CONFIG" },
13635 { 19485, "MEM_STRIPE_CONFIG" },
13636 { 19486, "DIAG_TRACE_WAY" },
13637 { 19487, "VDN_SNOOP_SHIM_CTL" },
13638 { 19488, "PERF_COUNT_PLS" },
13639 { 19489, "DIAG_TRACE_DATA" },
13640 { 19712, "I_AER_0" },
13641 { 19713, "I_AER_1" },
13642 { 19714, "I_PHYSICAL_MEMORY_MODE" },
13643 { 19968, "MPL_WORLD_ACCESS_SET_0" },
13644 { 19969, "MPL_WORLD_ACCESS_SET_1" },
13645 { 19970, "MPL_WORLD_ACCESS_SET_2" },
13646 { 19971, "MPL_WORLD_ACCESS_SET_3" },
13647 { 19972, "MPL_WORLD_ACCESS" },
13648 { 19973, "SIM_SOCKET" },
13649 { 19974, "CYCLE_HIGH" },
13650 { 19975, "CYCLE_LOW" },
13653 { 19978, "INTERRUPT_CRITICAL_SECTION" },
13655 { 19980, "SIM_CONTROL" },
13656 { 19981, "EVENT_BEGIN" },
13657 { 19982, "EVENT_END" },
13658 { 19983, "TILE_WRITE_PENDING" },
13659 { 19984, "TILE_RTF_HWM" },
13660 { 20224, "PROC_STATUS" },
13661 { 20225, "STATUS_SATURATE" },
13662 { 20480, "MPL_I_ASID_SET_0" },
13663 { 20481, "MPL_I_ASID_SET_1" },
13664 { 20482, "MPL_I_ASID_SET_2" },
13665 { 20483, "MPL_I_ASID_SET_3" },
13666 { 20484, "MPL_I_ASID" },
13667 { 20485, "I_ASID" },
13668 { 20992, "MPL_D_ASID_SET_0" },
13669 { 20993, "MPL_D_ASID_SET_1" },
13670 { 20994, "MPL_D_ASID_SET_2" },
13671 { 20995, "MPL_D_ASID_SET_3" },
13672 { 20996, "MPL_D_ASID" },
13673 { 20997, "D_ASID" },
13674 { 21504, "MPL_DMA_ASID_SET_0" },
13675 { 21505, "MPL_DMA_ASID_SET_1" },
13676 { 21506, "MPL_DMA_ASID_SET_2" },
13677 { 21507, "MPL_DMA_ASID_SET_3" },
13678 { 21508, "MPL_DMA_ASID" },
13679 { 21509, "DMA_ASID" },
13680 { 22016, "MPL_SNI_ASID_SET_0" },
13681 { 22017, "MPL_SNI_ASID_SET_1" },
13682 { 22018, "MPL_SNI_ASID_SET_2" },
13683 { 22019, "MPL_SNI_ASID_SET_3" },
13684 { 22020, "MPL_SNI_ASID" },
13685 { 22021, "SNI_ASID" },
13686 { 22528, "MPL_DMA_CPL_SET_0" },
13687 { 22529, "MPL_DMA_CPL_SET_1" },
13688 { 22530, "MPL_DMA_CPL_SET_2" },
13689 { 22531, "MPL_DMA_CPL_SET_3" },
13690 { 22532, "MPL_DMA_CPL" },
13691 { 23040, "MPL_SN_CPL_SET_0" },
13692 { 23041, "MPL_SN_CPL_SET_1" },
13693 { 23042, "MPL_SN_CPL_SET_2" },
13694 { 23043, "MPL_SN_CPL_SET_3" },
13695 { 23044, "MPL_SN_CPL" },
13696 { 23552, "MPL_DOUBLE_FAULT_SET_0" },
13697 { 23553, "MPL_DOUBLE_FAULT_SET_1" },
13698 { 23554, "MPL_DOUBLE_FAULT_SET_2" },
13699 { 23555, "MPL_DOUBLE_FAULT_SET_3" },
13700 { 23556, "MPL_DOUBLE_FAULT" },
13701 { 23557, "LAST_INTERRUPT_REASON" },
13702 { 24064, "MPL_SN_STATIC_ACCESS_SET_0" },
13703 { 24065, "MPL_SN_STATIC_ACCESS_SET_1" },
13704 { 24066, "MPL_SN_STATIC_ACCESS_SET_2" },
13705 { 24067, "MPL_SN_STATIC_ACCESS_SET_3" },
13706 { 24068, "MPL_SN_STATIC_ACCESS" },
13707 { 24069, "SN_STATIC_CTL" },
13708 { 24070, "SN_STATIC_FIFO_DATA" },
13709 { 24071, "SN_STATIC_FIFO_SEL" },
13710 { 24073, "SN_STATIC_ISTATE" },
13711 { 24074, "SN_STATIC_OSTATE" },
13712 { 24076, "SN_STATIC_STATIC" },
13713 { 24320, "SN_STATIC_DATA_AVAIL" },
13714 { 24576, "MPL_AUX_PERF_COUNT_SET_0" },
13715 { 24577, "MPL_AUX_PERF_COUNT_SET_1" },
13716 { 24578, "MPL_AUX_PERF_COUNT_SET_2" },
13717 { 24579, "MPL_AUX_PERF_COUNT_SET_3" },
13718 { 24580, "MPL_AUX_PERF_COUNT" },
13719 { 24581, "AUX_PERF_COUNT_0" },
13720 { 24582, "AUX_PERF_COUNT_1" },
13721 { 24583, "AUX_PERF_COUNT_CTL" },
13722 { 24584, "AUX_PERF_COUNT_STS" },
13725 const int tile_num_sprs = 499;
13730 /* Canonical name of each register. */
13731 const char *const tile_register_names[] =
13733 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
13734 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
13735 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
13736 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
13737 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
13738 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
13739 "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
13740 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero"
13744 /* Given a set of bundle bits and the lookup FSM for a specific pipe,
13745 * returns which instruction the bundle contains in that pipe.
13747 static const struct tile_opcode *
13748 find_opcode(tile_bundle_bits bits, const unsigned short *table)
13754 unsigned short bitspec = table[index];
13755 unsigned int bitfield =
13756 ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
13758 unsigned short next = table[index + 1 + bitfield];
13759 if (next <= TILE_OPC_NONE)
13760 return &tile_opcodes[next];
13762 index = next - TILE_OPC_NONE;
13768 parse_insn_tile(tile_bundle_bits bits,
13770 struct tile_decoded_instruction
13771 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE])
13773 int num_instructions = 0;
13776 int min_pipe, max_pipe;
13777 if ((bits & TILE_BUNDLE_Y_ENCODING_MASK) == 0)
13779 min_pipe = TILE_PIPELINE_X0;
13780 max_pipe = TILE_PIPELINE_X1;
13784 min_pipe = TILE_PIPELINE_Y0;
13785 max_pipe = TILE_PIPELINE_Y2;
13788 /* For each pipe, find an instruction that fits. */
13789 for (pipe = min_pipe; pipe <= max_pipe; pipe++)
13791 const struct tile_opcode *opc;
13792 struct tile_decoded_instruction *d;
13795 d = &decoded[num_instructions++];
13796 opc = find_opcode (bits, tile_bundle_decoder_fsms[pipe]);
13799 /* Decode each operand, sign extending, etc. as appropriate. */
13800 for (i = 0; i < opc->num_operands; i++)
13802 const struct tile_operand *op =
13803 &tile_operands[opc->operands[pipe][i]];
13804 int opval = op->extract (bits);
13807 /* Sign-extend the operand. */
13808 int shift = (int)((sizeof(int) * 8) - op->num_bits);
13809 opval = (opval << shift) >> shift;
13812 /* Adjust PC-relative scaled branch offsets. */
13813 if (op->type == TILE_OP_TYPE_ADDRESS)
13815 opval *= TILE_BUNDLE_SIZE_IN_BYTES;
13819 /* Record the final value. */
13820 d->operands[i] = op;
13821 d->operand_values[i] = opval;
13825 return num_instructions;