1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
36 #include <asm/timer.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
46 static void distribute_irqs(void);
49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
50 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
51 * delivered. We must translate this into a non-vector IRQ so we can
52 * set the softint on this cpu.
54 * To make processing these packets efficient and race free we use
55 * an array of irq buckets below. The interrupt vector handler in
56 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
57 * The IVEC handler does not need to act atomically, the PIL dispatch
58 * code uses CAS to get an atomic snapshot of the list and clear it
62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
64 /* This has to be in the main kernel image, it cannot be
65 * turned into per-cpu data. The reason is that the main
66 * kernel image is locked into the TLB and this structure
67 * is accessed from the vectored interrupt trap handler. If
68 * access to this structure takes a TLB miss it could cause
69 * the 5-level sparc v9 trap stack to overflow.
71 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
73 static struct irqaction *irq_action[NR_IRQS+1];
75 /* This only synchronizes entities which modify IRQ handler
76 * state and some selected user-level spots that want to
77 * read things in the table. IRQ handler processing orders
78 * its' accesses such that no locking is needed.
80 static DEFINE_SPINLOCK(irq_action_lock);
82 static void register_irq_proc (unsigned int irq);
85 * Upper 2b of irqaction->flags holds the ino.
86 * irqaction->mask holds the smp affinity information.
88 #define put_ino_in_irqaction(action, irq) \
89 action->flags &= 0xffffffffffffUL; \
90 action->flags |= __irq_ino(irq) << 48;
92 #define get_ino_in_irqaction(action) (action->flags >> 48)
94 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
95 #define get_smpaff_in_irqaction(action) ((action)->mask)
97 int show_interrupts(struct seq_file *p, void *v)
100 int i = *(loff_t *) v;
101 struct irqaction *action;
106 spin_lock_irqsave(&irq_action_lock, flags);
108 if (!(action = *(i + irq_action)))
110 seq_printf(p, "%3d: ", i);
112 seq_printf(p, "%10u ", kstat_irqs(i));
114 for_each_online_cpu(j) {
115 seq_printf(p, "%10u ",
116 kstat_cpu(j).irqs[i]);
119 seq_printf(p, " %s:%lx", action->name,
120 get_ino_in_irqaction(action));
121 for (action = action->next; action; action = action->next) {
122 seq_printf(p, ", %s:%lx", action->name,
123 get_ino_in_irqaction(action));
128 spin_unlock_irqrestore(&irq_action_lock, flags);
133 extern unsigned long real_hard_smp_processor_id(void);
135 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
139 if (this_is_starfire) {
140 tid = starfire_translate(imap, cpuid);
141 tid <<= IMAP_TID_SHIFT;
144 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
147 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
148 if ((ver >> 32UL) == __JALAPENO_ID ||
149 (ver >> 32UL) == __SERRANO_ID) {
150 tid = cpuid << IMAP_TID_SHIFT;
151 tid &= IMAP_TID_JBUS;
153 unsigned int a = cpuid & 0x1f;
154 unsigned int n = (cpuid >> 5) & 0x1f;
156 tid = ((a << IMAP_AID_SHIFT) |
157 (n << IMAP_NID_SHIFT));
158 tid &= (IMAP_AID_SAFARI |
162 tid = cpuid << IMAP_TID_SHIFT;
170 /* Now these are always passed a true fully specified sun4u INO. */
171 void enable_irq(unsigned int irq)
173 struct ino_bucket *bucket = __bucket(irq);
174 unsigned long imap, cpuid;
182 /* This gets the physical processor ID, even on uniprocessor,
183 * so we can always program the interrupt target correctly.
185 cpuid = real_hard_smp_processor_id();
187 if (tlb_type == hypervisor) {
188 unsigned int ino = __irq_ino(irq);
191 err = sun4v_intr_settarget(ino, cpuid);
193 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
195 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
197 printk("sun4v_intr_setenabled(%x): err(%d)\n",
200 unsigned int tid = sun4u_compute_tid(imap, cpuid);
202 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
203 * of this SYSIO's preconfigured IGN in the SYSIO Control
204 * Register, the hardware just mirrors that value here.
205 * However for Graphics and UPA Slave devices the full
206 * IMAP_INR field can be set by the programmer here.
208 * Things like FFB can now be handled via the new IRQ
211 upa_writel(tid | IMAP_VALID, imap);
217 /* This now gets passed true ino's as well. */
218 void disable_irq(unsigned int irq)
220 struct ino_bucket *bucket = __bucket(irq);
225 if (tlb_type == hypervisor) {
226 unsigned int ino = __irq_ino(irq);
229 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
231 printk("sun4v_intr_setenabled(%x): "
232 "err(%d)\n", ino, err);
236 /* NOTE: We do not want to futz with the IRQ clear registers
237 * and move the state to IDLE, the SCSI code does call
238 * disable_irq() to assure atomicity in the queue cmd
239 * SCSI adapter driver code. Thus we'd lose interrupts.
241 tmp = upa_readl(imap);
243 upa_writel(tmp, imap);
248 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
249 unsigned long iclr, unsigned long imap,
250 struct ino_bucket *bucket)
252 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
253 "(%d:%d:%016lx:%016lx), halting...\n",
254 ino, bucket->pil, bucket->iclr, bucket->imap,
255 pil, inofixup, iclr, imap);
259 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
261 struct ino_bucket *bucket;
265 BUG_ON(tlb_type == hypervisor);
267 /* RULE: Both must be specified in all other cases. */
268 if (iclr == 0UL || imap == 0UL) {
269 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
270 pil, inofixup, iclr, imap);
274 ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
275 if (ino > NUM_IVECS) {
276 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
277 ino, pil, inofixup, iclr, imap);
281 bucket = &ivector_table[ino];
282 if (bucket->flags & IBF_ACTIVE)
283 build_irq_error("IRQ: Trying to build active INO bucket.\n",
284 ino, pil, inofixup, iclr, imap, bucket);
286 if (bucket->irq_info) {
287 if (bucket->imap != imap || bucket->iclr != iclr)
288 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
289 ino, pil, inofixup, iclr, imap, bucket);
294 bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
295 if (!bucket->irq_info) {
296 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
300 /* Ok, looks good, set it up. Don't touch the irq_chain or
309 return __irq(bucket);
312 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
314 struct ino_bucket *bucket;
315 unsigned long sysino;
317 sysino = sun4v_devino_to_sysino(devhandle, devino);
319 bucket = &ivector_table[sysino];
321 /* Catch accidental accesses to these things. IMAP/ICLR handling
322 * is done by hypervisor calls on sun4v platforms, not by direct
325 * But we need to make them look unique for the disable_irq() logic
328 bucket->imap = ~0UL - sysino;
329 bucket->iclr = ~0UL - sysino;
332 bucket->flags = flags;
334 bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
335 if (!bucket->irq_info) {
336 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
340 return __irq(bucket);
343 static void atomic_bucket_insert(struct ino_bucket *bucket)
345 unsigned long pstate;
348 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
349 __asm__ __volatile__("wrpr %0, %1, %%pstate"
350 : : "r" (pstate), "i" (PSTATE_IE));
351 ent = irq_work(smp_processor_id());
352 bucket->irq_chain = *ent;
353 *ent = __irq(bucket);
354 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
357 static int check_irq_sharing(int pil, unsigned long irqflags)
359 struct irqaction *action, *tmp;
361 action = *(irq_action + pil);
363 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
364 for (tmp = action; tmp->next; tmp = tmp->next)
373 static void append_irq_action(int pil, struct irqaction *action)
375 struct irqaction **pp = irq_action + pil;
382 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
384 struct irq_desc *desc = bucket->irq_info;
388 if (bucket->flags & IBF_PCI)
389 max_irq = MAX_IRQ_DESC_ACTION;
390 for (i = 0; i < max_irq; i++) {
391 struct irqaction *p = &desc->action[i];
394 if (desc->action_active_mask & mask)
397 desc->action_active_mask |= mask;
403 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
404 unsigned long irqflags, const char *name, void *dev_id)
406 struct irqaction *action;
407 struct ino_bucket *bucket = __bucket(irq);
411 if (unlikely(!handler))
414 if (unlikely(!bucket->irq_info))
417 if (irqflags & SA_SAMPLE_RANDOM) {
419 * This function might sleep, we want to call it first,
420 * outside of the atomic block. In SA_STATIC_ALLOC case,
421 * random driver's kmalloc will fail, but it is safe.
422 * If already initialized, random driver will not reinit.
423 * Yes, this might clear the entropy pool if the wrong
424 * driver is attempted to be loaded, without actually
425 * installing a new handler, but is this really a problem,
426 * only the sysadmin is able to do this.
428 rand_initialize_irq(irq);
431 spin_lock_irqsave(&irq_action_lock, flags);
433 if (check_irq_sharing(bucket->pil, irqflags)) {
434 spin_unlock_irqrestore(&irq_action_lock, flags);
438 action = get_action_slot(bucket);
440 spin_unlock_irqrestore(&irq_action_lock, flags);
444 bucket->flags |= IBF_ACTIVE;
445 pending = bucket->pending;
449 action->handler = handler;
450 action->flags = irqflags;
453 action->dev_id = dev_id;
454 put_ino_in_irqaction(action, irq);
455 put_smpaff_in_irqaction(action, CPU_MASK_NONE);
457 append_irq_action(bucket->pil, action);
461 /* We ate the IVEC already, this makes sure it does not get lost. */
463 atomic_bucket_insert(bucket);
464 set_softint(1 << PIL_DEVICE_IRQ);
467 spin_unlock_irqrestore(&irq_action_lock, flags);
469 register_irq_proc(__irq_ino(irq));
477 EXPORT_SYMBOL(request_irq);
479 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
481 struct ino_bucket *bucket = __bucket(irq);
482 struct irqaction *action, **pp;
484 pp = irq_action + bucket->pil;
486 if (unlikely(!action))
489 if (unlikely(!action->handler)) {
490 printk("Freeing free IRQ %d\n", bucket->pil);
494 while (action && action->dev_id != dev_id) {
505 void free_irq(unsigned int irq, void *dev_id)
507 struct irqaction *action;
508 struct ino_bucket *bucket;
509 struct irq_desc *desc;
513 spin_lock_irqsave(&irq_action_lock, flags);
515 action = unlink_irq_action(irq, dev_id);
517 spin_unlock_irqrestore(&irq_action_lock, flags);
519 if (unlikely(!action))
522 synchronize_irq(irq);
524 spin_lock_irqsave(&irq_action_lock, flags);
526 bucket = __bucket(irq);
527 desc = bucket->irq_info;
529 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
530 struct irqaction *p = &desc->action[i];
533 desc->action_active_mask &= ~(1 << i);
538 if (!desc->action_active_mask) {
539 unsigned long imap = bucket->imap;
541 /* This unique interrupt source is now inactive. */
542 bucket->flags &= ~IBF_ACTIVE;
544 /* See if any other buckets share this bucket's IMAP
545 * and are still active.
547 for (ent = 0; ent < NUM_IVECS; ent++) {
548 struct ino_bucket *bp = &ivector_table[ent];
551 (bp->flags & IBF_ACTIVE) != 0)
555 /* Only disable when no other sub-irq levels of
556 * the same IMAP are active.
558 if (ent == NUM_IVECS)
562 spin_unlock_irqrestore(&irq_action_lock, flags);
565 EXPORT_SYMBOL(free_irq);
568 void synchronize_irq(unsigned int irq)
570 struct ino_bucket *bucket = __bucket(irq);
573 /* The following is how I wish I could implement this.
574 * Unfortunately the ICLR registers are read-only, you can
575 * only write ICLR_foo values to them. To get the current
576 * IRQ status you would need to get at the IRQ diag registers
577 * in the PCI/SBUS controller and the layout of those vary
578 * from one controller to the next, sigh... -DaveM
580 unsigned long iclr = bucket->iclr;
583 u32 tmp = upa_readl(iclr);
585 if (tmp == ICLR_TRANSMIT ||
586 tmp == ICLR_PENDING) {
593 /* So we have to do this with a INPROGRESS bit just like x86. */
594 while (bucket->flags & IBF_INPROGRESS)
598 #endif /* CONFIG_SMP */
600 static void process_bucket(struct ino_bucket *bp, struct pt_regs *regs)
602 struct irq_desc *desc = bp->irq_info;
603 unsigned char flags = bp->flags;
607 bp->flags |= IBF_INPROGRESS;
609 if (unlikely(!(flags & IBF_ACTIVE))) {
614 if (desc->pre_handler)
615 desc->pre_handler(bp,
616 desc->pre_handler_arg1,
617 desc->pre_handler_arg2);
619 action_mask = desc->action_active_mask;
621 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
622 struct irqaction *p = &desc->action[i];
625 if (!(action_mask & mask))
628 action_mask &= ~mask;
630 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
637 if (tlb_type == hypervisor) {
638 unsigned int ino = __irq_ino(bp);
641 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
643 printk("sun4v_intr_setstate(%x): "
644 "err(%d)\n", ino, err);
646 upa_writel(ICLR_IDLE, bp->iclr);
649 /* Test and add entropy */
650 if (random & SA_SAMPLE_RANDOM)
651 add_interrupt_randomness(bp->pil);
654 bp->flags &= ~IBF_INPROGRESS;
658 extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
660 void timer_irq(int irq, struct pt_regs *regs)
662 unsigned long clr_mask = 1 << irq;
663 unsigned long tick_mask = tick_ops->softint_mask;
665 if (get_softint() & tick_mask) {
667 clr_mask = tick_mask;
669 clear_softint(clr_mask);
672 kstat_this_cpu.irqs[irq]++;
673 timer_interrupt(irq, NULL, regs);
678 void handler_irq(int irq, struct pt_regs *regs)
680 struct ino_bucket *bp;
681 int cpu = smp_processor_id();
683 /* XXX at this point we should be able to assert that
684 * XXX irq is PIL_DEVICE_IRQ...
686 clear_softint(1 << irq);
691 bp = __bucket(xchg32(irq_work(cpu), 0));
693 struct ino_bucket *nbp = __bucket(bp->irq_chain);
695 kstat_this_cpu.irqs[bp->pil]++;
698 process_bucket(bp, regs);
704 #ifdef CONFIG_BLK_DEV_FD
705 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);
707 /* XXX No easy way to include asm/floppy.h XXX */
708 extern unsigned char *pdma_vaddr;
709 extern unsigned long pdma_size;
710 extern volatile int doing_pdma;
711 extern unsigned long fdc_status;
713 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
715 if (likely(doing_pdma)) {
716 void __iomem *stat = (void __iomem *) fdc_status;
717 unsigned char *vaddr = pdma_vaddr;
718 unsigned long size = pdma_size;
723 if (unlikely(!(val & 0x80))) {
728 if (unlikely(!(val & 0x20))) {
736 *vaddr++ = readb(stat + 1);
738 unsigned char data = *vaddr++;
741 writeb(data, stat + 1);
749 /* Send Terminal Count pulse to floppy controller. */
750 val = readb(auxio_register);
751 val |= AUXIO_AUX1_FTCNT;
752 writeb(val, auxio_register);
753 val &= ~AUXIO_AUX1_FTCNT;
754 writeb(val, auxio_register);
760 return floppy_interrupt(irq, dev_cookie, regs);
762 EXPORT_SYMBOL(sparc_floppy_irq);
765 /* We really don't need these at all on the Sparc. We only have
766 * stubs here because they are exported to modules.
768 unsigned long probe_irq_on(void)
773 EXPORT_SYMBOL(probe_irq_on);
775 int probe_irq_off(unsigned long mask)
780 EXPORT_SYMBOL(probe_irq_off);
783 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
785 struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
787 while (!cpu_online(goal_cpu)) {
788 if (++goal_cpu >= NR_CPUS)
792 if (tlb_type == hypervisor) {
793 unsigned int ino = __irq_ino(bucket);
795 sun4v_intr_settarget(ino, goal_cpu);
796 sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
798 unsigned long imap = bucket->imap;
799 unsigned int tid = sun4u_compute_tid(imap, goal_cpu);
801 upa_writel(tid | IMAP_VALID, imap);
805 if (++goal_cpu >= NR_CPUS)
807 } while (!cpu_online(goal_cpu));
812 /* Called from request_irq. */
813 static void distribute_irqs(void)
818 spin_lock_irqsave(&irq_action_lock, flags);
822 * Skip the timer at [0], and very rare error/power intrs at [15].
823 * Also level [12], it causes problems on Ex000 systems.
825 for (level = 1; level < NR_IRQS; level++) {
826 struct irqaction *p = irq_action[level];
832 cpu = retarget_one_irq(p, cpu);
836 spin_unlock_irqrestore(&irq_action_lock, flags);
847 static struct sun5_timer *prom_timers;
848 static u64 prom_limit0, prom_limit1;
850 static void map_prom_timers(void)
852 unsigned int addr[3];
855 /* PROM timer node hangs out in the top level of device siblings... */
856 tnode = prom_finddevice("/counter-timer");
858 /* Assume if node is not present, PROM uses different tick mechanism
859 * which we should not care about.
861 if (tnode == 0 || tnode == -1) {
862 prom_timers = (struct sun5_timer *) 0;
866 /* If PROM is really using this, it must be mapped by him. */
867 err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
869 prom_printf("PROM does not have timer mapped, trying to continue.\n");
870 prom_timers = (struct sun5_timer *) 0;
873 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
876 static void kill_prom_timer(void)
881 /* Save them away for later. */
882 prom_limit0 = prom_timers->limit0;
883 prom_limit1 = prom_timers->limit1;
885 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
886 * We turn both off here just to be paranoid.
888 prom_timers->limit0 = 0;
889 prom_timers->limit1 = 0;
891 /* Wheee, eat the interrupt packet too... */
892 __asm__ __volatile__(
894 " ldxa [%%g0] %0, %%g1\n"
895 " ldxa [%%g2] %1, %%g1\n"
896 " stxa %%g0, [%%g0] %0\n"
899 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
903 void init_irqwork_curcpu(void)
905 int cpu = hard_smp_processor_id();
907 trap_block[cpu].irq_worklist = 0;
910 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
912 unsigned long num_entries = 128;
913 unsigned long status;
915 status = sun4v_cpu_qconf(type, paddr, num_entries);
916 if (status != HV_EOK) {
917 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
918 "err %lu\n", type, paddr, num_entries, status);
923 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
925 struct trap_per_cpu *tb = &trap_block[this_cpu];
927 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
928 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
929 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
930 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
933 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
938 page = alloc_bootmem_low_pages(PAGE_SIZE);
940 page = (void *) get_zeroed_page(GFP_ATOMIC);
943 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
947 *pa_ptr = __pa(page);
950 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
955 page = alloc_bootmem_low_pages(PAGE_SIZE);
957 page = (void *) get_zeroed_page(GFP_ATOMIC);
960 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
964 *pa_ptr = __pa(page);
967 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
972 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
975 page = alloc_bootmem_low_pages(PAGE_SIZE);
977 page = (void *) get_zeroed_page(GFP_ATOMIC);
980 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
984 tb->cpu_mondo_block_pa = __pa(page);
985 tb->cpu_list_pa = __pa(page + 64);
989 /* Allocate and register the mondo and error queues for this cpu. */
990 void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
992 struct trap_per_cpu *tb = &trap_block[cpu];
995 alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
996 alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
997 alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
998 alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
999 alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
1000 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
1002 init_cpu_send_mondo_info(tb, use_bootmem);
1006 if (cpu != hard_smp_processor_id()) {
1007 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1008 cpu, hard_smp_processor_id());
1011 sun4v_register_mondo_queues(cpu);
1015 /* Only invoked on boot processor. */
1016 void __init init_IRQ(void)
1020 memset(&ivector_table[0], 0, sizeof(ivector_table));
1022 if (tlb_type == hypervisor)
1023 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1025 /* We need to clear any IRQ's pending in the soft interrupt
1026 * registers, a spurious one could be left around from the
1027 * PROM timer which we just disabled.
1029 clear_softint(get_softint());
1031 /* Now that ivector table is initialized, it is safe
1032 * to receive IRQ vector traps. We will normally take
1033 * one or two right now, in case some device PROM used
1034 * to boot us wants to speak to us. We just ignore them.
1036 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
1037 "or %%g1, %0, %%g1\n\t"
1038 "wrpr %%g1, 0x0, %%pstate"
1044 static struct proc_dir_entry * root_irq_dir;
1045 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1049 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1050 int count, int *eof, void *data)
1052 struct ino_bucket *bp = ivector_table + (long)data;
1053 struct irq_desc *desc = bp->irq_info;
1054 struct irqaction *ap = desc->action;
1058 mask = get_smpaff_in_irqaction(ap);
1059 if (cpus_empty(mask))
1060 mask = cpu_online_map;
1062 len = cpumask_scnprintf(page, count, mask);
1063 if (count - len < 2)
1065 len += sprintf(page + len, "\n");
1069 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1071 struct ino_bucket *bp = ivector_table + irq;
1072 struct irq_desc *desc = bp->irq_info;
1073 struct irqaction *ap = desc->action;
1075 /* Users specify affinity in terms of hw cpu ids.
1076 * As soon as we do this, handler_irq() might see and take action.
1078 put_smpaff_in_irqaction(ap, hw_aff);
1080 /* Migration is simply done by the next cpu to service this
1085 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1086 unsigned long count, void *data)
1088 int irq = (long) data, full_count = count, err;
1089 cpumask_t new_value;
1091 err = cpumask_parse(buffer, count, new_value);
1094 * Do not allow disabling IRQs completely - it's a too easy
1095 * way to make the system unusable accidentally :-) At least
1096 * one online CPU still has to be targeted.
1098 cpus_and(new_value, new_value, cpu_online_map);
1099 if (cpus_empty(new_value))
1102 set_intr_affinity(irq, new_value);
1109 #define MAX_NAMELEN 10
1111 static void register_irq_proc (unsigned int irq)
1113 char name [MAX_NAMELEN];
1115 if (!root_irq_dir || irq_dir[irq])
1118 memset(name, 0, MAX_NAMELEN);
1119 sprintf(name, "%x", irq);
1121 /* create /proc/irq/1234 */
1122 irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1125 /* XXX SMP affinity not supported on starfire yet. */
1126 if (this_is_starfire == 0) {
1127 struct proc_dir_entry *entry;
1129 /* create /proc/irq/1234/smp_affinity */
1130 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1134 entry->data = (void *)(long)irq;
1135 entry->read_proc = irq_affinity_read_proc;
1136 entry->write_proc = irq_affinity_write_proc;
1142 void init_irq_proc (void)
1144 /* create /proc/irq */
1145 root_irq_dir = proc_mkdir("irq", NULL);