1 /* pcr.c: Generic sparc64 performance counter infrastructure.
3 * Copyright (C) 2009 David S. Miller (davem@davemloft.net)
5 #include <linux/kernel.h>
6 #include <linux/export.h>
7 #include <linux/init.h>
10 #include <linux/irq_work.h>
11 #include <linux/ftrace.h>
16 #include <asm/spitfire.h>
18 /* This code is shared between various users of the performance
19 * counters. Users will be oprofile, pseudo-NMI watchdog, and the
20 * perf_event support layer.
23 #define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
24 #define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
26 (2 << PCR_N2_SL1_SHIFT) | \
27 (0xff << PCR_N2_MASK1_SHIFT))
30 unsigned int picl_shift;
32 /* Performance counter interrupts run unmasked at PIL level 15.
33 * Therefore we can't do things like wakeups and other work
34 * that expects IRQ disabling to be adhered to in locking etc.
36 * Therefore in such situations we defer the work by signalling
37 * a lower level cpu IRQ.
39 void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
41 struct pt_regs *old_regs;
43 clear_softint(1 << PIL_DEFERRED_PCR_WORK);
45 old_regs = set_irq_regs(regs);
47 #ifdef CONFIG_IRQ_WORK
51 set_irq_regs(old_regs);
54 void arch_irq_work_raise(void)
56 set_softint(1 << PIL_DEFERRED_PCR_WORK);
59 const struct pcr_ops *pcr_ops;
60 EXPORT_SYMBOL_GPL(pcr_ops);
62 static u64 direct_pcr_read(void)
70 static void direct_pcr_write(u64 val)
75 static const struct pcr_ops direct_pcr_ops = {
76 .read = direct_pcr_read,
77 .write = direct_pcr_write,
80 static void n2_pcr_write(u64 val)
84 if (val & PCR_N2_HTRACE) {
85 ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
92 static const struct pcr_ops n2_pcr_ops = {
93 .read = direct_pcr_read,
94 .write = n2_pcr_write,
97 static unsigned long perf_hsvc_group;
98 static unsigned long perf_hsvc_major;
99 static unsigned long perf_hsvc_minor;
101 static int __init register_perf_hsvc(void)
103 if (tlb_type == hypervisor) {
104 switch (sun4v_chip_type) {
105 case SUN4V_CHIP_NIAGARA1:
106 perf_hsvc_group = HV_GRP_NIAG_PERF;
109 case SUN4V_CHIP_NIAGARA2:
110 perf_hsvc_group = HV_GRP_N2_CPU;
113 case SUN4V_CHIP_NIAGARA3:
114 perf_hsvc_group = HV_GRP_KT_CPU;
124 if (sun4v_hvapi_register(perf_hsvc_group,
127 printk("perfmon: Could not register hvapi.\n");
134 static void __init unregister_perf_hsvc(void)
136 if (tlb_type != hypervisor)
138 sun4v_hvapi_unregister(perf_hsvc_group);
141 int __init pcr_arch_init(void)
143 int err = register_perf_hsvc();
150 pcr_ops = &n2_pcr_ops;
151 pcr_enable = PCR_N2_ENABLE;
157 pcr_ops = &direct_pcr_ops;
158 pcr_enable = PCR_SUN4U_ENABLE;
162 /* UltraSPARC-I/II and derivatives lack a profile
163 * counter overflow interrupt so we can't make use of
164 * their hardware currently.
175 unregister_perf_hsvc();