4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_dma.h>
22 #include <linux/sh_timer.h>
23 #include <linux/sh_intc.h>
25 #include <linux/notifier.h>
27 #include <asm/suspend.h>
28 #include <asm/clock.h>
29 #include <asm/mmzone.h>
31 #include <cpu/dma-register.h>
32 #include <cpu/sh7724.h>
35 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
37 .slave_id = SHDMA_SLAVE_SCIF0_TX,
39 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
42 .slave_id = SHDMA_SLAVE_SCIF0_RX,
44 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
47 .slave_id = SHDMA_SLAVE_SCIF1_TX,
49 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
52 .slave_id = SHDMA_SLAVE_SCIF1_RX,
54 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
57 .slave_id = SHDMA_SLAVE_SCIF2_TX,
59 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
62 .slave_id = SHDMA_SLAVE_SCIF2_RX,
64 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
67 .slave_id = SHDMA_SLAVE_SCIF3_TX,
69 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
72 .slave_id = SHDMA_SLAVE_SCIF3_RX,
74 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
77 .slave_id = SHDMA_SLAVE_SCIF4_TX,
79 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
82 .slave_id = SHDMA_SLAVE_SCIF4_RX,
84 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
87 .slave_id = SHDMA_SLAVE_SCIF5_TX,
89 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
92 .slave_id = SHDMA_SLAVE_SCIF5_RX,
94 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
97 .slave_id = SHDMA_SLAVE_USB0D0_TX,
99 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
102 .slave_id = SHDMA_SLAVE_USB0D0_RX,
104 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
107 .slave_id = SHDMA_SLAVE_USB0D1_TX,
109 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
112 .slave_id = SHDMA_SLAVE_USB0D1_RX,
114 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
117 .slave_id = SHDMA_SLAVE_USB1D0_TX,
119 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
122 .slave_id = SHDMA_SLAVE_USB1D0_RX,
124 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
127 .slave_id = SHDMA_SLAVE_USB1D1_TX,
129 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
132 .slave_id = SHDMA_SLAVE_USB1D1_RX,
134 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
137 .slave_id = SHDMA_SLAVE_SDHI0_TX,
139 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
142 .slave_id = SHDMA_SLAVE_SDHI0_RX,
144 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
147 .slave_id = SHDMA_SLAVE_SDHI1_TX,
149 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
152 .slave_id = SHDMA_SLAVE_SDHI1_RX,
154 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
159 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
187 static const unsigned int ts_shift[] = TS_SHIFT;
189 static struct sh_dmae_pdata dma_platform_data = {
190 .slave = sh7724_dmae_slaves,
191 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves),
192 .channel = sh7724_dmae_channels,
193 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
194 .ts_low_shift = CHCR_TS_LOW_SHIFT,
195 .ts_low_mask = CHCR_TS_LOW_MASK,
196 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
197 .ts_high_mask = CHCR_TS_HIGH_MASK,
198 .ts_shift = ts_shift,
199 .ts_shift_num = ARRAY_SIZE(ts_shift),
200 .dmaor_init = DMAOR_INIT,
203 /* Resource order important! */
204 static struct resource sh7724_dmae0_resources[] = {
206 /* Channel registers and DMAOR */
209 .flags = IORESOURCE_MEM,
215 .flags = IORESOURCE_MEM,
219 .start = evt2irq(0xbc0),
220 .end = evt2irq(0xbc0),
221 .flags = IORESOURCE_IRQ,
224 /* IRQ for channels 0-3 */
225 .start = evt2irq(0x800),
226 .end = evt2irq(0x860),
227 .flags = IORESOURCE_IRQ,
230 /* IRQ for channels 4-5 */
231 .start = evt2irq(0xb80),
232 .end = evt2irq(0xba0),
233 .flags = IORESOURCE_IRQ,
237 /* Resource order important! */
238 static struct resource sh7724_dmae1_resources[] = {
240 /* Channel registers and DMAOR */
243 .flags = IORESOURCE_MEM,
249 .flags = IORESOURCE_MEM,
253 .start = evt2irq(0xb40),
254 .end = evt2irq(0xb40),
255 .flags = IORESOURCE_IRQ,
258 /* IRQ for channels 0-3 */
259 .start = evt2irq(0x700),
260 .end = evt2irq(0x760),
261 .flags = IORESOURCE_IRQ,
264 /* IRQ for channels 4-5 */
265 .start = evt2irq(0xb00),
266 .end = evt2irq(0xb20),
267 .flags = IORESOURCE_IRQ,
271 static struct platform_device dma0_device = {
272 .name = "sh-dma-engine",
274 .resource = sh7724_dmae0_resources,
275 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
277 .platform_data = &dma_platform_data,
281 static struct platform_device dma1_device = {
282 .name = "sh-dma-engine",
284 .resource = sh7724_dmae1_resources,
285 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
287 .platform_data = &dma_platform_data,
292 static struct plat_sci_port scif0_platform_data = {
293 .mapbase = 0xffe00000,
294 .port_reg = SCIx_NOT_SUPPORTED,
295 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
297 .scbrr_algo_id = SCBRR_ALGO_2,
299 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
300 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
303 static struct platform_device scif0_device = {
307 .platform_data = &scif0_platform_data,
311 static struct plat_sci_port scif1_platform_data = {
312 .mapbase = 0xffe10000,
313 .port_reg = SCIx_NOT_SUPPORTED,
314 .flags = UPF_BOOT_AUTOCONF,
315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
316 .scbrr_algo_id = SCBRR_ALGO_2,
318 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
319 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
322 static struct platform_device scif1_device = {
326 .platform_data = &scif1_platform_data,
330 static struct plat_sci_port scif2_platform_data = {
331 .mapbase = 0xffe20000,
332 .port_reg = SCIx_NOT_SUPPORTED,
333 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2,
337 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
338 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
341 static struct platform_device scif2_device = {
345 .platform_data = &scif2_platform_data,
349 static struct plat_sci_port scif3_platform_data = {
350 .mapbase = 0xa4e30000,
351 .port_reg = SCIx_NOT_SUPPORTED,
352 .flags = UPF_BOOT_AUTOCONF,
353 .scscr = SCSCR_RE | SCSCR_TE,
354 .scbrr_algo_id = SCBRR_ALGO_3,
356 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
359 static struct platform_device scif3_device = {
363 .platform_data = &scif3_platform_data,
367 static struct plat_sci_port scif4_platform_data = {
368 .mapbase = 0xa4e40000,
369 .port_reg = SCIx_NOT_SUPPORTED,
370 .flags = UPF_BOOT_AUTOCONF,
371 .scscr = SCSCR_RE | SCSCR_TE,
372 .scbrr_algo_id = SCBRR_ALGO_3,
374 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)),
377 static struct platform_device scif4_device = {
381 .platform_data = &scif4_platform_data,
385 static struct plat_sci_port scif5_platform_data = {
386 .mapbase = 0xa4e50000,
387 .port_reg = SCIx_NOT_SUPPORTED,
388 .flags = UPF_BOOT_AUTOCONF,
389 .scscr = SCSCR_RE | SCSCR_TE,
390 .scbrr_algo_id = SCBRR_ALGO_3,
392 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)),
395 static struct platform_device scif5_device = {
399 .platform_data = &scif5_platform_data,
404 static struct resource rtc_resources[] = {
407 .end = 0xa465fec0 + 0x58 - 1,
408 .flags = IORESOURCE_IO,
412 .start = evt2irq(0xaa0),
413 .flags = IORESOURCE_IRQ,
417 .start = evt2irq(0xac0),
418 .flags = IORESOURCE_IRQ,
422 .start = evt2irq(0xa80),
423 .flags = IORESOURCE_IRQ,
427 static struct platform_device rtc_device = {
430 .num_resources = ARRAY_SIZE(rtc_resources),
431 .resource = rtc_resources,
435 static struct resource iic0_resources[] = {
439 .end = 0x04470018 - 1,
440 .flags = IORESOURCE_MEM,
443 .start = evt2irq(0xe00),
444 .end = evt2irq(0xe60),
445 .flags = IORESOURCE_IRQ,
449 static struct platform_device iic0_device = {
450 .name = "i2c-sh_mobile",
451 .id = 0, /* "i2c0" clock */
452 .num_resources = ARRAY_SIZE(iic0_resources),
453 .resource = iic0_resources,
457 static struct resource iic1_resources[] = {
461 .end = 0x04750018 - 1,
462 .flags = IORESOURCE_MEM,
465 .start = evt2irq(0xd80),
466 .end = evt2irq(0xde0),
467 .flags = IORESOURCE_IRQ,
471 static struct platform_device iic1_device = {
472 .name = "i2c-sh_mobile",
473 .id = 1, /* "i2c1" clock */
474 .num_resources = ARRAY_SIZE(iic1_resources),
475 .resource = iic1_resources,
479 static struct uio_info vpu_platform_data = {
482 .irq = evt2irq(0x980),
485 static struct resource vpu_resources[] = {
490 .flags = IORESOURCE_MEM,
493 /* place holder for contiguous memory */
497 static struct platform_device vpu_device = {
498 .name = "uio_pdrv_genirq",
501 .platform_data = &vpu_platform_data,
503 .resource = vpu_resources,
504 .num_resources = ARRAY_SIZE(vpu_resources),
508 static struct uio_info veu0_platform_data = {
511 .irq = evt2irq(0xc60),
514 static struct resource veu0_resources[] = {
519 .flags = IORESOURCE_MEM,
522 /* place holder for contiguous memory */
526 static struct platform_device veu0_device = {
527 .name = "uio_pdrv_genirq",
530 .platform_data = &veu0_platform_data,
532 .resource = veu0_resources,
533 .num_resources = ARRAY_SIZE(veu0_resources),
537 static struct uio_info veu1_platform_data = {
540 .irq = evt2irq(0x8c0),
543 static struct resource veu1_resources[] = {
548 .flags = IORESOURCE_MEM,
551 /* place holder for contiguous memory */
555 static struct platform_device veu1_device = {
556 .name = "uio_pdrv_genirq",
559 .platform_data = &veu1_platform_data,
561 .resource = veu1_resources,
562 .num_resources = ARRAY_SIZE(veu1_resources),
566 static struct uio_info beu0_platform_data = {
569 .irq = evt2irq(0x8A0),
572 static struct resource beu0_resources[] = {
577 .flags = IORESOURCE_MEM,
580 /* place holder for contiguous memory */
584 static struct platform_device beu0_device = {
585 .name = "uio_pdrv_genirq",
588 .platform_data = &beu0_platform_data,
590 .resource = beu0_resources,
591 .num_resources = ARRAY_SIZE(beu0_resources),
595 static struct uio_info beu1_platform_data = {
598 .irq = evt2irq(0xA00),
601 static struct resource beu1_resources[] = {
606 .flags = IORESOURCE_MEM,
609 /* place holder for contiguous memory */
613 static struct platform_device beu1_device = {
614 .name = "uio_pdrv_genirq",
617 .platform_data = &beu1_platform_data,
619 .resource = beu1_resources,
620 .num_resources = ARRAY_SIZE(beu1_resources),
623 static struct sh_timer_config cmt_platform_data = {
624 .channel_offset = 0x60,
626 .clockevent_rating = 125,
627 .clocksource_rating = 200,
630 static struct resource cmt_resources[] = {
634 .flags = IORESOURCE_MEM,
637 .start = evt2irq(0xf00),
638 .flags = IORESOURCE_IRQ,
642 static struct platform_device cmt_device = {
646 .platform_data = &cmt_platform_data,
648 .resource = cmt_resources,
649 .num_resources = ARRAY_SIZE(cmt_resources),
652 static struct sh_timer_config tmu0_platform_data = {
653 .channel_offset = 0x04,
655 .clockevent_rating = 200,
658 static struct resource tmu0_resources[] = {
662 .flags = IORESOURCE_MEM,
665 .start = evt2irq(0x400),
666 .flags = IORESOURCE_IRQ,
670 static struct platform_device tmu0_device = {
674 .platform_data = &tmu0_platform_data,
676 .resource = tmu0_resources,
677 .num_resources = ARRAY_SIZE(tmu0_resources),
680 static struct sh_timer_config tmu1_platform_data = {
681 .channel_offset = 0x10,
683 .clocksource_rating = 200,
686 static struct resource tmu1_resources[] = {
690 .flags = IORESOURCE_MEM,
693 .start = evt2irq(0x420),
694 .flags = IORESOURCE_IRQ,
698 static struct platform_device tmu1_device = {
702 .platform_data = &tmu1_platform_data,
704 .resource = tmu1_resources,
705 .num_resources = ARRAY_SIZE(tmu1_resources),
708 static struct sh_timer_config tmu2_platform_data = {
709 .channel_offset = 0x1c,
713 static struct resource tmu2_resources[] = {
717 .flags = IORESOURCE_MEM,
720 .start = evt2irq(0x440),
721 .flags = IORESOURCE_IRQ,
725 static struct platform_device tmu2_device = {
729 .platform_data = &tmu2_platform_data,
731 .resource = tmu2_resources,
732 .num_resources = ARRAY_SIZE(tmu2_resources),
736 static struct sh_timer_config tmu3_platform_data = {
737 .channel_offset = 0x04,
741 static struct resource tmu3_resources[] = {
745 .flags = IORESOURCE_MEM,
748 .start = evt2irq(0x920),
749 .flags = IORESOURCE_IRQ,
753 static struct platform_device tmu3_device = {
757 .platform_data = &tmu3_platform_data,
759 .resource = tmu3_resources,
760 .num_resources = ARRAY_SIZE(tmu3_resources),
763 static struct sh_timer_config tmu4_platform_data = {
764 .channel_offset = 0x10,
768 static struct resource tmu4_resources[] = {
772 .flags = IORESOURCE_MEM,
775 .start = evt2irq(0x940),
776 .flags = IORESOURCE_IRQ,
780 static struct platform_device tmu4_device = {
784 .platform_data = &tmu4_platform_data,
786 .resource = tmu4_resources,
787 .num_resources = ARRAY_SIZE(tmu4_resources),
790 static struct sh_timer_config tmu5_platform_data = {
791 .channel_offset = 0x1c,
795 static struct resource tmu5_resources[] = {
799 .flags = IORESOURCE_MEM,
802 .start = evt2irq(0x920),
803 .flags = IORESOURCE_IRQ,
807 static struct platform_device tmu5_device = {
811 .platform_data = &tmu5_platform_data,
813 .resource = tmu5_resources,
814 .num_resources = ARRAY_SIZE(tmu5_resources),
818 static struct uio_info jpu_platform_data = {
821 .irq = evt2irq(0x560),
824 static struct resource jpu_resources[] = {
829 .flags = IORESOURCE_MEM,
832 /* place holder for contiguous memory */
836 static struct platform_device jpu_device = {
837 .name = "uio_pdrv_genirq",
840 .platform_data = &jpu_platform_data,
842 .resource = jpu_resources,
843 .num_resources = ARRAY_SIZE(jpu_resources),
847 static struct uio_info spu0_platform_data = {
850 .irq = evt2irq(0xcc0),
853 static struct resource spu0_resources[] = {
858 .flags = IORESOURCE_MEM,
861 /* place holder for contiguous memory */
865 static struct platform_device spu0_device = {
866 .name = "uio_pdrv_genirq",
869 .platform_data = &spu0_platform_data,
871 .resource = spu0_resources,
872 .num_resources = ARRAY_SIZE(spu0_resources),
876 static struct uio_info spu1_platform_data = {
879 .irq = evt2irq(0xce0),
882 static struct resource spu1_resources[] = {
887 .flags = IORESOURCE_MEM,
890 /* place holder for contiguous memory */
894 static struct platform_device spu1_device = {
895 .name = "uio_pdrv_genirq",
898 .platform_data = &spu1_platform_data,
900 .resource = spu1_resources,
901 .num_resources = ARRAY_SIZE(spu1_resources),
904 static struct platform_device *sh7724_devices[] __initdata = {
933 static int __init sh7724_devices_setup(void)
935 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
936 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
937 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
938 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
939 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
940 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
942 return platform_add_devices(sh7724_devices,
943 ARRAY_SIZE(sh7724_devices));
945 arch_initcall(sh7724_devices_setup);
947 static struct platform_device *sh7724_early_devices[] __initdata = {
963 void __init plat_early_device_setup(void)
965 early_platform_add_devices(sh7724_early_devices,
966 ARRAY_SIZE(sh7724_early_devices));
969 #define RAMCR_CACHE_L2FC 0x0002
970 #define RAMCR_CACHE_L2E 0x0001
971 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
973 void l2_cache_init(void)
975 /* Enable L2 cache */
976 __raw_writel(L2_CACHE_ENABLE, RAMCR);
984 /* interrupt sources */
985 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
987 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
988 _2DG_TRI, _2DG_INI, _2DG_CEI,
989 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
990 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
998 RTC_ATI, RTC_PRI, RTC_CUI,
999 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
1000 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
1002 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
1004 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1005 SPU_SPUI0, SPU_SPUI1,
1009 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
1010 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
1015 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
1019 MMC_MMC2I, MMC_MMC3I,
1021 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
1023 /* interrupt groups */
1024 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
1025 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
1028 static struct intc_vect vectors[] __initdata = {
1029 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
1030 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
1031 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
1032 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
1034 INTC_VECT(DMAC1A_DEI0, 0x700),
1035 INTC_VECT(DMAC1A_DEI1, 0x720),
1036 INTC_VECT(DMAC1A_DEI2, 0x740),
1037 INTC_VECT(DMAC1A_DEI3, 0x760),
1039 INTC_VECT(_2DG_TRI, 0x780),
1040 INTC_VECT(_2DG_INI, 0x7A0),
1041 INTC_VECT(_2DG_CEI, 0x7C0),
1043 INTC_VECT(DMAC0A_DEI0, 0x800),
1044 INTC_VECT(DMAC0A_DEI1, 0x820),
1045 INTC_VECT(DMAC0A_DEI2, 0x840),
1046 INTC_VECT(DMAC0A_DEI3, 0x860),
1048 INTC_VECT(VIO_CEU0, 0x880),
1049 INTC_VECT(VIO_BEU0, 0x8A0),
1050 INTC_VECT(VIO_VEU1, 0x8C0),
1051 INTC_VECT(VIO_VOU, 0x8E0),
1053 INTC_VECT(SCIFA3, 0x900),
1054 INTC_VECT(VPU, 0x980),
1055 INTC_VECT(TPU, 0x9A0),
1056 INTC_VECT(CEU1, 0x9E0),
1057 INTC_VECT(BEU1, 0xA00),
1058 INTC_VECT(USB0, 0xA20),
1059 INTC_VECT(USB1, 0xA40),
1060 INTC_VECT(ATAPI, 0xA60),
1062 INTC_VECT(RTC_ATI, 0xA80),
1063 INTC_VECT(RTC_PRI, 0xAA0),
1064 INTC_VECT(RTC_CUI, 0xAC0),
1066 INTC_VECT(DMAC1B_DEI4, 0xB00),
1067 INTC_VECT(DMAC1B_DEI5, 0xB20),
1068 INTC_VECT(DMAC1B_DADERR, 0xB40),
1070 INTC_VECT(DMAC0B_DEI4, 0xB80),
1071 INTC_VECT(DMAC0B_DEI5, 0xBA0),
1072 INTC_VECT(DMAC0B_DADERR, 0xBC0),
1074 INTC_VECT(KEYSC, 0xBE0),
1075 INTC_VECT(SCIF_SCIF0, 0xC00),
1076 INTC_VECT(SCIF_SCIF1, 0xC20),
1077 INTC_VECT(SCIF_SCIF2, 0xC40),
1078 INTC_VECT(VEU0, 0xC60),
1079 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1080 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1081 INTC_VECT(SPU_SPUI0, 0xCC0),
1082 INTC_VECT(SPU_SPUI1, 0xCE0),
1083 INTC_VECT(SCIFA4, 0xD00),
1085 INTC_VECT(ICB, 0xD20),
1086 INTC_VECT(ETHI, 0xD60),
1088 INTC_VECT(I2C1_ALI, 0xD80),
1089 INTC_VECT(I2C1_TACKI, 0xDA0),
1090 INTC_VECT(I2C1_WAITI, 0xDC0),
1091 INTC_VECT(I2C1_DTEI, 0xDE0),
1093 INTC_VECT(I2C0_ALI, 0xE00),
1094 INTC_VECT(I2C0_TACKI, 0xE20),
1095 INTC_VECT(I2C0_WAITI, 0xE40),
1096 INTC_VECT(I2C0_DTEI, 0xE60),
1098 INTC_VECT(SDHI0, 0xE80),
1099 INTC_VECT(SDHI0, 0xEA0),
1100 INTC_VECT(SDHI0, 0xEC0),
1101 INTC_VECT(SDHI0, 0xEE0),
1103 INTC_VECT(CMT, 0xF00),
1104 INTC_VECT(TSIF, 0xF20),
1105 INTC_VECT(FSI, 0xF80),
1106 INTC_VECT(SCIFA5, 0xFA0),
1108 INTC_VECT(TMU0_TUNI0, 0x400),
1109 INTC_VECT(TMU0_TUNI1, 0x420),
1110 INTC_VECT(TMU0_TUNI2, 0x440),
1112 INTC_VECT(IRDA, 0x480),
1114 INTC_VECT(SDHI1, 0x4E0),
1115 INTC_VECT(SDHI1, 0x500),
1116 INTC_VECT(SDHI1, 0x520),
1118 INTC_VECT(JPU, 0x560),
1119 INTC_VECT(_2DDMAC, 0x4A0),
1121 INTC_VECT(MMC_MMC2I, 0x5A0),
1122 INTC_VECT(MMC_MMC3I, 0x5C0),
1124 INTC_VECT(LCDC, 0xF40),
1126 INTC_VECT(TMU1_TUNI0, 0x920),
1127 INTC_VECT(TMU1_TUNI1, 0x940),
1128 INTC_VECT(TMU1_TUNI2, 0x960),
1131 static struct intc_group groups[] __initdata = {
1132 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1133 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1134 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1135 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1136 INTC_GROUP(USB, USB0, USB1),
1137 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1138 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1139 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1140 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1141 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1142 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1143 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1146 static struct intc_mask_reg mask_registers[] __initdata = {
1147 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1148 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1149 0, ENABLED, ENABLED, ENABLED } },
1150 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1151 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1152 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1153 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1154 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1155 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1156 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1157 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1158 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1159 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1160 JPU, 0, 0, LCDC } },
1161 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1162 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1163 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1164 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1165 { 0, 0, ICB, SCIFA4,
1166 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1167 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1168 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1169 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1170 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1171 { DISABLED, ENABLED, ENABLED, ENABLED,
1172 0, 0, SCIFA5, FSI } },
1173 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1174 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1175 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1176 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1177 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1178 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1179 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1180 0, TPU, 0, TSIF } },
1181 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1182 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1183 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1184 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1187 static struct intc_prio_reg prio_registers[] __initdata = {
1188 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1189 TMU0_TUNI2, IRDA } },
1190 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1191 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1192 TMU1_TUNI2, SPU } },
1193 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1194 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1195 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1196 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1197 SCIF_SCIF2, VEU0 } },
1198 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1200 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1201 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1202 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1203 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1204 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1205 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1208 static struct intc_sense_reg sense_registers[] __initdata = {
1209 { 0xa414001c, 16, 2, /* ICR1 */
1210 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1213 static struct intc_mask_reg ack_registers[] __initdata = {
1214 { 0xa4140024, 0, 8, /* INTREQ00 */
1215 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1218 static struct intc_desc intc_desc __initdata = {
1220 .force_enable = ENABLED,
1221 .force_disable = DISABLED,
1222 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1223 prio_registers, sense_registers, ack_registers),
1226 void __init plat_irq_setup(void)
1228 register_intc_controller(&intc_desc);
1233 unsigned long mmselr;
1234 unsigned long cs0bcr;
1235 unsigned long cs4bcr;
1236 unsigned long cs5abcr;
1237 unsigned long cs5bbcr;
1238 unsigned long cs6abcr;
1239 unsigned long cs6bbcr;
1240 unsigned long cs4wcr;
1241 unsigned long cs5awcr;
1242 unsigned long cs5bwcr;
1243 unsigned long cs6awcr;
1244 unsigned long cs6bwcr;
1246 unsigned short ipra;
1247 unsigned short iprb;
1248 unsigned short iprc;
1249 unsigned short iprd;
1250 unsigned short ipre;
1251 unsigned short iprf;
1252 unsigned short iprg;
1253 unsigned short iprh;
1254 unsigned short ipri;
1255 unsigned short iprj;
1256 unsigned short iprk;
1257 unsigned short iprl;
1268 unsigned char imr10;
1269 unsigned char imr11;
1270 unsigned char imr12;
1272 unsigned short rwtcnt;
1273 unsigned short rwtcsr;
1275 unsigned long irdaclk;
1276 unsigned long spuclk;
1277 } sh7724_rstandby_state;
1279 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1280 unsigned long flags, void *unused)
1282 if (!(flags & SUSP_SH_RSTANDBY))
1286 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1287 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1288 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1289 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1290 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1291 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1292 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1293 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1294 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1295 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1296 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1297 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1298 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1301 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1302 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1303 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1304 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1305 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1306 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1307 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1308 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1309 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1310 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1311 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1312 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1313 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1314 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1315 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1316 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1317 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1318 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1319 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1320 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1321 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1322 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1323 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1324 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1325 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1328 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1329 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1330 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1331 sh7724_rstandby_state.rwtcsr |= 0xa500;
1332 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1335 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1336 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1341 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1342 unsigned long flags, void *unused)
1344 if (!(flags & SUSP_SH_RSTANDBY))
1348 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1349 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1350 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1351 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1352 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1353 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1354 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1355 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1356 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1357 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1358 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1359 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1362 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1363 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1364 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1365 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1366 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1367 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1368 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1369 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1370 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1371 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1372 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1373 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1374 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1375 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1376 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1377 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1378 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1379 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1380 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1381 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1382 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1383 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1384 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1385 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1386 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1389 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1390 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1393 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1394 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1399 static struct notifier_block sh7724_pre_sleep_notifier = {
1400 .notifier_call = sh7724_pre_sleep_notifier_call,
1401 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1404 static struct notifier_block sh7724_post_sleep_notifier = {
1405 .notifier_call = sh7724_post_sleep_notifier_call,
1406 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1409 static int __init sh7724_sleep_setup(void)
1411 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1412 &sh7724_pre_sleep_notifier);
1414 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1415 &sh7724_post_sleep_notifier);
1418 arch_initcall(sh7724_sleep_setup);