2 * arch/sh/kernel/cpu/sh4a/clock-sh7343.c
4 * SH7343 clock framework support
6 * Copyright (C) 2009 Magnus Damm
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/kernel.h>
24 #include <asm/clkdev.h>
25 #include <asm/clock.h>
27 /* SH7343 registers */
28 #define FRQCR 0xa4150000
29 #define VCLKCR 0xa4150004
30 #define SCLKACR 0xa4150008
31 #define SCLKBCR 0xa415000c
32 #define PLLCR 0xa4150024
33 #define MSTPCR0 0xa4150030
34 #define MSTPCR1 0xa4150034
35 #define MSTPCR2 0xa4150038
36 #define DLLFRQ 0xa4150050
38 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
39 static struct clk r_clk = {
46 * Default rate for the root input clock, reset this with clk_set_rate()
47 * from the platform code.
49 struct clk extal_clk = {
55 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
56 static unsigned long dll_recalc(struct clk *clk)
60 if (__raw_readl(PLLCR) & 0x1000)
61 mult = __raw_readl(DLLFRQ);
65 return clk->parent->rate * mult;
68 static struct clk_ops dll_clk_ops = {
72 static struct clk dll_clk = {
77 .flags = CLK_ENABLE_ON_INIT,
80 static unsigned long pll_recalc(struct clk *clk)
82 unsigned long mult = 1;
84 if (__raw_readl(PLLCR) & 0x4000)
85 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
87 return clk->parent->rate * mult;
90 static struct clk_ops pll_clk_ops = {
94 static struct clk pll_clk = {
98 .flags = CLK_ENABLE_ON_INIT,
101 struct clk *main_clks[] = {
108 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
109 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
111 static struct clk_div_mult_table div4_div_mult_table = {
112 .divisors = divisors,
113 .nr_divisors = ARRAY_SIZE(divisors),
114 .multipliers = multipliers,
115 .nr_multipliers = ARRAY_SIZE(multipliers),
118 static struct clk_div4_table div4_table = {
119 .div_mult_table = &div4_div_mult_table,
122 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
123 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
125 #define DIV4(_str, _reg, _bit, _mask, _flags) \
126 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
128 struct clk div4_clks[DIV4_NR] = {
129 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
135 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
136 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
139 enum { DIV6_V, DIV6_NR };
141 struct clk div6_clks[DIV6_NR] = {
142 [DIV6_V] = SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
145 #define MSTP(_str, _parent, _reg, _bit, _flags) \
146 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
148 static struct clk mstp_clks[] = {
149 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
150 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
151 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
152 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
153 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
154 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
155 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
156 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
157 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
158 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
159 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
160 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
161 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
162 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
163 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
164 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
165 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
166 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
167 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
168 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
169 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
170 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
171 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
173 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
174 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
176 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
177 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
178 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
179 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
180 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
181 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
182 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
183 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
184 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
185 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
186 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
187 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
188 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
189 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
190 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
191 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
192 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
195 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
197 static struct clk_lookup lookups[] = {
199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
202 int __init arch_clk_init(void)
206 /* autodetect extal or dll configuration */
207 if (__raw_readl(PLLCR) & 0x1000)
208 pll_clk.parent = &dll_clk;
210 pll_clk.parent = &extal_clk;
212 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
213 ret = clk_register(main_clks[k]);
215 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
218 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
221 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
224 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));