1 #ifndef __ASM_SH_CLOCK_H
2 #define __ASM_SH_CLOCK_H
4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
13 void (*init)(struct clk *clk);
14 int (*enable)(struct clk *clk);
15 void (*disable)(struct clk *clk);
16 unsigned long (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent);
19 long (*round_rate)(struct clk *clk, unsigned long rate);
23 struct list_head node;
31 struct list_head children;
32 struct list_head sibling; /* node for children */
39 void __iomem *enable_reg;
40 unsigned int enable_bit;
42 unsigned long arch_flags;
44 struct dentry *dentry;
45 struct cpufreq_frequency_table *freq_table;
48 #define CLK_ENABLE_ON_INIT (1 << 0)
50 /* Should be defined by processor-specific code */
51 void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
52 int __init arch_clk_init(void);
54 /* arch/sh/kernel/cpu/clock.c */
56 unsigned long followparent_recalc(struct clk *);
57 void recalculate_root_clocks(void);
58 void propagate_rate(struct clk *);
59 int clk_reparent(struct clk *child, struct clk *parent);
60 int clk_register(struct clk *);
61 void clk_unregister(struct clk *);
63 /* arch/sh/kernel/cpu/clock-cpg.c */
64 int __init __deprecated cpg_clk_init(void);
66 /* the exported API, in addition to clk_set_rate */
68 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
70 * @rate: desired clock rate in Hz
71 * @algo_id: algorithm id to be passed down to ops->set_rate
73 * Returns success (0) or negative errno.
75 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
97 struct clk_div_mult_table {
98 unsigned int *divisors;
99 unsigned int nr_divisors;
100 unsigned int *multipliers;
101 unsigned int nr_multipliers;
104 struct cpufreq_frequency_table;
105 void clk_rate_table_build(struct clk *clk,
106 struct cpufreq_frequency_table *freq_table,
108 struct clk_div_mult_table *src_table,
109 unsigned long *bitmap);
111 long clk_rate_table_round(struct clk *clk,
112 struct cpufreq_frequency_table *freq_table,
115 int clk_rate_table_find(struct clk *clk,
116 struct cpufreq_frequency_table *freq_table,
119 #define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \
120 _enable_bit, _flags) \
125 .enable_reg = (void __iomem *)_enable_reg, \
126 .enable_bit = _enable_bit, \
130 int sh_clk_mstp32_register(struct clk *clks, int nr);
132 #define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \
136 .enable_reg = (void __iomem *)_reg, \
137 .enable_bit = _shift, \
138 .arch_flags = _div_bitmap, \
142 struct clk_div4_table {
143 struct clk_div_mult_table *div_mult_table;
144 void (*kick)(struct clk *clk);
147 int sh_clk_div4_register(struct clk *clks, int nr,
148 struct clk_div4_table *table);
149 int sh_clk_div4_enable_register(struct clk *clks, int nr,
150 struct clk_div4_table *table);
151 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
152 struct clk_div4_table *table);
154 #define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
158 .enable_reg = (void __iomem *)_reg, \
162 int sh_clk_div6_register(struct clk *clks, int nr);
164 #endif /* __ASM_SH_CLOCK_H */